DS34S132GNA2+ [MAXIM]
Framer,;
| 型号： | DS34S132GNA2+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Framer, 电信 电信集成电路 |
| 文件： | 总194页 (文件大小：3415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4750; Rev 1; 7/11
DS34S132
32-Port TDM-over-Packet IC
General Description
Features
♦
32 Independent TDM Ports with Serial Data,
Clock, and Sync (Data = 64Kbps to 2.048Mbps)
The IETF PWE3 SAToP/CESoPSN/HDLC-compliant
DS34S132 provides the interworking functions that
are required for translating TDM data streams into
and out of TDM-over-Packet (TDMoP) data streams
for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro
Ethernet (MEF-8) networks while meeting the jitter
and wander timing performance that is required by
the public network (ITU G.823, G.824, and G.8261).
Up to 32 TDM ports can be translated into as many
as 256 individually configurable pseudowires (PWs)
for transmission over a 100/1000Mbps Ethernet port.
Each TDM port’s bit rate can vary from 64Kbps to
2.048Mbps to support T1/E1 or slower TDM rates.
PW interworking for TDM-based serial HDLC data is
also supported. A built-in time-slot assignment (TSA)
circuit provides the ability to combine any group of
time slots (TS) from a single TDM port into a single
PW. The high level of integration provides the perfect
solution for high-density applications to minimize
cost, board space, and time to market.
♦
♦
One 100/1000Mbps (MII/GMII) Ethernet MAC
256 Total PWs, 32 PW per TDM Port, with Any
Combination of TDMoP and/or HDLC PWs
♦
PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or
IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8)
♦
♦
0, 1, or 2 VLAN Tags (IEEE 802.1Q)
Synchronous or Asynchronous TDM Port
Timing
One Clock Recovery Engine per TDM Port with
One Assignable as a Global Reference
Supported Clock Recovery Techniques
Adaptive Clock Recovery
Differential Clock Recovery
Absolute and Differential Timestamps
Independent Receive and Transmit Interfaces
Two Clock Inputs for Direct Transmit Timing
♦
♦
For Structured T1/E1, Each TDM Port Includes
DS0 TSA Block for any Time Slot to Any PW
32 HDLC/CES Engines (256 Total)
Applications
With or Without CAS Signaling
TDM Circuit Emulation Over PSN
TDM Leased-Line Services Over PSN
TDM Over BPON/GPON/EPON
TDM Over Cable
TDM Over Wireless
Cellular Backhaul
Multiservice Over Unified PSN
HDLC-Encapsulated Data Over PSN
For Unstructured, each TDM Port Includes
One HDLC/SAT Engine (32 Total)
Any data rate from 64Kbps to 2.048Mbps
♦
♦
32-Bit or 16-Bit CPU Processor Bus
CPU-Based OAM and Signaling
UDP-specific
Inband VCCV
MEF OAM
“Special” Ethernet Type
ARP
NDP/IPv6
Broadcast DA
Functional Diagram
CPU Interface
♦
♦
DDR SDRAM Interface
Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM
DS34S1328
32 TDM Ports
Packet
Circuit
Emulation
& HDLC
Engines
100/1000
Ethernet
Ordering Information
PORTS TEMP RANGE PIN-PACKAGE
32 Serial
Clock &
Data
Generator
MII/
GMII
T1/E1
TSA
Packet
PART
MAC
Interfaces
Classifier
DS34S132GNA2
DS34S132GNA2+
32
32
676 BGA
676 BGA
-40°C to +85°C
-40°C to +85°C
BERT, CAS &
Conditioning
Buffer
Clock
Adapter
Manager
+Denotes a lead(Pb)-free/RoHS-compliant package.
Clock Inputs
& Outputs
DDR SDRAM
Interface
Maxim Integrated Products
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
DS34S132 DATA SHEET
TABLE OF CONTENTS
1
2
3
4
5
6
7
8
Introduction....................................................................................................................................................8
Acronyms and Glossary .................................................................................................................................9
Applicable Standards ................................................................................................................................... 10
High Level Description ................................................................................................................................. 11
Application Examples................................................................................................................................... 13
Block Diagram ............................................................................................................................................. 15
Features ...................................................................................................................................................... 16
Pin Descriptions........................................................................................................................................... 20
8.1 Short Pin Descriptions ........................................................................................................................... 20
8.2 Detailed Pin Descriptions....................................................................................................................... 22
Functional Description.................................................................................................................................. 27
9.1 Connection Types.................................................................................................................................. 29
9.1.1 SAT/CES Payload Connections ..................................................................................................... 29
9.1.2 HDLC Connections ........................................................................................................................ 29
9.1.3 SAT/CES PW-Timing Connections................................................................................................. 30
9.1.4 CPU Connections .......................................................................................................................... 31
9.2 TDM Port Functions............................................................................................................................... 32
9.2.1 TDM Port Related Input and Output Clocks.................................................................................... 32
9.2.1.1 PW-Timing............................................................................................................................. 33
9.2.1.1.1 RXP Clock Recovery (RXP PW-Timing) ......................................................................... 34
9.2.1.1.2 TXP PW-Timing ............................................................................................................. 34
9.2.1.2 TDM Port - One Clock and Two Clock Modes......................................................................... 35
9.2.2 TDM Port Interface......................................................................................................................... 35
9.2.2.1 TDM Port Transmit Interface .................................................................................................. 36
9.2.2.2 TDM Port Receive Interface ................................................................................................... 37
9.2.3 TDM Port Structure & Frame Formats............................................................................................ 37
9.2.4 Timeslot Assignment Block ............................................................................................................ 38
9.2.4.1 TDM CAS to Packet CAS Translation..................................................................................... 40
9.2.4.2 TSA Block Loopbacks ............................................................................................................ 42
9.2.5 TDM Port Data Processing Engines............................................................................................... 42
9.2.5.1 HDLC Engine......................................................................................................................... 43
9.2.5.1.1 SAT/CES Engine............................................................................................................ 44
9.2.5.2 TDM Port Priority.................................................................................................................... 45
9.2.5.3 Jitter Buffer Settings............................................................................................................... 45
9.2.6 TDM Diagnostic Functions ............................................................................................................. 50
9.2.6.1 TDM Loopback....................................................................................................................... 50
9.2.6.2 TDM BERT ............................................................................................................................ 51
9.3 Packet Processing Functions................................................................................................................. 53
9.3.1 Ethernet MAC................................................................................................................................ 53
9.3.1.1 Ethernet Port Diagnostic Functions ........................................................................................ 54
9.3.1.1.1 Ethernet Loopback ......................................................................................................... 54
9.3.1.1.2 Packet BERT ................................................................................................................. 54
9.3.2 RXP Packet Classification.............................................................................................................. 56
9.3.2.1 Generalized Packet Classification .......................................................................................... 56
9.3.2.2 PW (BID and OAM BID) Packet Classification........................................................................ 57
9.3.2.2.1 UDP Settings ................................................................................................................. 58
9.3.2.2.2 Handling of Packets with a Matching BID or OAM BID.................................................... 58
9.3.2.2.3 L-bit Signaling for RXP PWs........................................................................................... 59
9.3.2.3 CPU Packet Classification...................................................................................................... 59
9.3.2.3.1 Packets with Broadcast Ethernet DA (DPC.CR1.DPBTP and DPC.CR1.DPBCP) ........... 60
9.3.2.3.2 Packets with Unknown Ethernet DA (PC.CR7 – PC.CR19 and DPC.CR1.DPS9)............ 60
9.3.2.3.3 PW Packets with Unknown PW-ID (DPS6) ..................................................................... 60
9.3.2.3.4 MEF OAM Ethernet Type Packets (MOET)..................................................................... 60
9.3.2.3.5 CPU Destination Ethernet Type Packets (CDET and DPS8)........................................... 60
9.3.2.3.6 ARP Packet with Known IP Destination Address (PC.CR6 – PC.CR8 and DPS3) ........... 60
9.3.2.3.7 ARP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR8 and DPS0) ....... 60
9.3.2.3.8 Packet with Unknown Ethernet Type (DPS2).................................................................. 60
9
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DS34S132 DATA SHEET
9.3.2.3.9 IP Packets with Unknown IP Protocol (DPS4)................................................................. 60
9.3.2.3.10 IP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR16 and DPS1) ......... 60
9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS)............................................................ 61
9.3.2.3.12 PW Bundle with Unknown UDP Protocol Type (UPVCE and DPS5)................................ 61
9.3.2.3.13 PW Bundle In-band VCCV OAM (RXOICWE and DPS7)................................................ 61
9.3.2.3.14 PW Bundle with Too Many MPLS Labels (DPS10).......................................................... 61
9.3.2.3.15 PW OAM Bundle - Out-band VCCV OAM Packets (DPS7) ............................................. 61
9.3.3 TXP Packet Generation ................................................................................................................. 61
9.3.3.1 TXP SAT/CES/HDLC/Clock Only PW Packet Generation....................................................... 62
9.3.3.1.1 L-bit Signaling ................................................................................................................ 63
9.3.3.2 TXP CPU Packet Generation ................................................................................................. 63
9.3.3.3 TXP Packet Scheduling.......................................................................................................... 63
9.3.3.4 TXP Packet Queue Monitoring ............................................................................................... 63
9.4 CPU Packet Interface ............................................................................................................................ 63
9.4.1 RXP CPU Packet Interface ............................................................................................................ 63
9.4.2 TXP CPU Packet Interface............................................................................................................. 66
9.5 Clock Recovery Functions ..................................................................................................................... 68
9.6 Miscellaneous Global Functions............................................................................................................. 68
9.6.1 Global Resets................................................................................................................................ 68
9.6.2 Latched Status and Counter Register Reset................................................................................... 68
9.6.3 Buffer Manager.............................................................................................................................. 68
9.6.3.1 SDRAM Interface................................................................................................................... 69
9.6.4 CPU Electrical Interconnect ........................................................................................................... 69
9.6.5 Interrupt Hierarchy......................................................................................................................... 71
10 Device Registers.......................................................................................................................................... 74
10.1 Register Block Address Ranges............................................................................................................. 74
10.2 Register Address Reference List............................................................................................................ 75
10.3 Register Definitions................................................................................................................................ 83
10.3.1 Global Registers (G.) ..................................................................................................................... 83
10.3.1.1 Global Configuration Registers (G.)........................................................................................ 83
10.3.1.2 Global Status Registers (G.)................................................................................................... 86
10.3.1.3 Global Status Register Interrupt Enables (G.)......................................................................... 88
10.3.2 Bundle Registers (B.)..................................................................................................................... 89
10.3.2.1 Bundle Reset Registers (B.)................................................................................................... 89
10.3.2.2 Bundle Data Control Registers (B.)......................................................................................... 90
10.3.2.3 Bundle Data Registers (B.)..................................................................................................... 91
10.3.2.4 Bundle Status Latch Registers (B.)......................................................................................... 97
10.3.2.5 Bundle Status Register Interrupt Enables (B.)....................................................................... 100
10.3.3 Jitter Buffer Registers (JB.).......................................................................................................... 104
10.3.3.1 Jitter Buffer Status Registers (JB.)........................................................................................ 104
10.3.3.2 Jitter Buffer Status Register Interrupt Enables (JB.).............................................................. 107
10.3.4 Packet Classifier Registers (PC.) ................................................................................................. 110
10.3.4.1 Packet Classifier Configuration Registers (PC.).................................................................... 110
10.3.4.2 Packet Classifier Status Register Latches (PC.) ................................................................... 113
10.3.4.3 Packet Classifier Status Register Interrupt Enables (PC.)..................................................... 114
10.3.4.4 Packet Classifier Counter Registers (PC.) ............................................................................ 115
10.3.5 External Memory Interface Registers (EMI.)................................................................................. 115
10.3.5.1 External Memory Interface Configuration Registers (EMI.).................................................... 115
10.3.5.2 External Memory Interface Status Registers (EMI.)............................................................... 116
10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.)..................................... 117
10.3.5.4 External Memory DLL/PLL Test Registers (EMI.).................................................................. 118
10.3.6 External Memory Access Registers (EMA.).................................................................................. 118
10.3.6.1 Write Registers (EMA.)......................................................................................................... 118
10.3.6.2 Read Registers (EMA.) ........................................................................................................ 120
10.3.7 Encap BERT Registers (EB.) ....................................................................................................... 122
10.3.8 Decap BERT Registers (DB.)....................................................................................................... 124
10.3.9 Miscellaneous Diagnostic Registers (MD.) ................................................................................... 126
10.3.10 Test Registers (TST.)................................................................................................................... 127
10.3.11 Clock Recovery Registers (CR.)................................................................................................... 129
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DS34S132 DATA SHEET
10.3.12 MAC Registers (M.) ..................................................................................................................... 129
10.3.13 TXP SW CAS Registers (TXSCn.) ............................................................................................... 138
10.3.14 Xmt (RXP) SW CAS Registers (RXSCn.) ..................................................................................... 139
10.3.15 TDM Port n Registers (Pn.; n = 0 to 31)........................................................................................ 140
10.3.15.1 Port n Transmit Configuration Registers (Pn.)....................................................................... 140
10.3.15.2 Port n Transmit Status Registers (Pn.) ................................................................................. 142
10.3.15.3 Port n Transmit Status Register Latches (Pn.)...................................................................... 143
10.3.15.4 Port n Transmit Status Register Interrupt Enables (Pn.)........................................................ 143
10.3.15.5 Port n Receive Configuration Registers (Pn.)........................................................................ 144
10.3.15.6 Port n Receive Status Registers (Pn.) .................................................................................. 146
10.3.15.7 Port n Receive Status Register Latches (Pn.)....................................................................... 147
10.3.15.8 Port n Receive Status Register Interrupt Enables (Pn.)......................................................... 147
10.3.16 Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m) ........................... 147
10.4 Register Guide..................................................................................................................................... 148
10.4.1 Global Packet Settings................................................................................................................. 149
10.4.2 Bundle and OAM Bundle Settings ................................................................................................ 151
10.4.2.1 SAT Bundle Settings............................................................................................................ 152
10.4.2.2 CES without CAS Bundle Settings........................................................................................ 153
10.4.2.3 CES with CAS Bundle Settings ............................................................................................ 154
10.4.2.4 Unstructured HDLC Bundle (any Line Rate) Settings............................................................ 155
10.4.2.5 Structured Nx64 Kb/s HDLC Bundle Settings ....................................................................... 156
10.4.2.6 Structured 16 Kb/s or 56 Kb/s HDLC Bundle Settings........................................................... 157
10.4.2.7 Clock Only Bundle Settings.................................................................................................. 158
10.4.2.7.1 Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings............................. 158
10.4.2.7.2 RXP (Unidirectional) Clock Only Bundle Settings.......................................................... 159
10.4.2.7.3 TXP (Unidirectional) Clock Only Bundle Settings .......................................................... 160
10.4.2.8 “CPU RXP PW Debug” Bundle Settings ............................................................................... 161
10.4.2.9 In-band VCCV OAM Connection Settings............................................................................. 162
10.4.2.10 OAM Bundle (Out-band VCCV OAM) Settings...................................................................... 162
10.4.3 Send to CPU Settings.................................................................................................................. 163
10.4.4 TDM Port Settings........................................................................................................................ 163
10.4.5 Status Monitoring......................................................................................................................... 167
10.4.5.1 Ethernet Port Monitoring....................................................................................................... 167
10.4.5.2 Global Packet Classifier Monitoring Control.......................................................................... 168
10.4.5.3 Global RXP Bundle Monitoring Control................................................................................. 168
10.4.5.4 Global TXP Packet Queue Monitoring .................................................................................. 168
10.4.5.5 PW Bundle Monitoring.......................................................................................................... 168
10.4.6 SDRAM Settings.......................................................................................................................... 169
11 JTAG Information....................................................................................................................................... 171
12 DC Electrical Characteristics...................................................................................................................... 172
13 AC Timing Characteristics.......................................................................................................................... 173
13.1 CPU Interface...................................................................................................................................... 173
13.2 TDM Interface...................................................................................................................................... 175
13.3 MAC Interface...................................................................................................................................... 177
13.3.1 GMII Interface.............................................................................................................................. 177
13.3.2 MII Interface................................................................................................................................. 177
13.4 DDR SDRAM Timing ........................................................................................................................... 178
14 Pin Assignment.......................................................................................................................................... 180
15 Package Information.................................................................................................................................. 192
16 Thermal Information................................................................................................................................... 193
17 Data sheet Revision History....................................................................................................................... 194
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DS34S132 DATA SHEET
LIST OF FIGURES
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network ........................................................................... 13
Figure 5-2. TDMoP in Cellular Backhaul............................................................................................................... 14
Figure 6-1. DS34S132 Functional Block Diagram................................................................................................. 15
Figure 9-1. S132 Block Diagram .......................................................................................................................... 28
Figure 9-2. RXP/TXP Data Path Directions .......................................................................................................... 28
Figure 9-3. SAT/CES Payload Connection........................................................................................................... 29
Figure 9-4. Bundle HDLC Connection .................................................................................................................. 29
Figure 9-5. Bundle PW-Timing Connections......................................................................................................... 30
Figure 9-6. CPU Connections .............................................................................................................................. 31
Figure 9-7. TDM Port Input and Output Clock Overview ....................................................................................... 32
Figure 9-8. Clock Recovery Engine Environment.................................................................................................. 34
Figure 9-9. TXP PW-Timing Environment............................................................................................................. 34
Figure 9-10. TDM Port #1 Environment................................................................................................................ 35
Figure 9-11. Logic Detail for a Single TDM Port Interface ..................................................................................... 36
Figure 9-12. T1 ESF CAS to SF CAS Translation Example .................................................................................. 37
Figure 9-13. TSA Block Environment ................................................................................................................... 39
Figure 9-14. HDLC Engine Environment .............................................................................................................. 43
Figure 9-15. SAT/CES Engine Environment......................................................................................................... 44
Figure 9-16. Bundle Jitter Buffer FIFO.................................................................................................................. 48
Figure 9-17. T1/E1 Port Line Loopback and TDM Port Timeslot Loopback Diagram ............................................. 51
Figure 9-18. T1/E1 Port Bundle Loopback Diagram.............................................................................................. 51
Figure 9-19. TDM Port BERT Diagram................................................................................................................. 51
Figure 9-20. Ethernet MAC Environment.............................................................................................................. 53
Figure 9-21. Ethernet Port Local Loopback .......................................................................................................... 54
Figure 9-22. Ethernet Port BERT Diagram ........................................................................................................... 55
Figure 9-23. RXP Packet Classifier Environment.................................................................................................. 56
Figure 9-24. TXP Packet Generation Environment ............................................................................................... 61
Figure 9-25. SAT/CES/HDLC/Clock Only PW TXP Header Descriptor.................................................................. 62
Figure 9-26. Stored RXP CPU Packet.................................................................................................................. 64
Figure 9-27. Stored TXP CPU Packet and Header Descriptor .............................................................................. 66
Figure 9-28. Buffer Manager Environment............................................................................................................ 68
Figure 9-29. MPC870 32-bit Bus Interface............................................................................................................ 70
Figure 9-30. MPC8313, Non-multiplexed Bus Interface ........................................................................................ 71
Figure 9-31. MPC8313, Multiplexed Bus Interface................................................................................................ 71
Figure 9-32. Interrupt Hierarchy Diagram ............................................................................................................. 73
Figure 10-1. Register Guide High Level Diagram................................................................................................ 148
Figure 13-1. MPC870-like processor CPU Interface Write Cycle......................................................................... 174
Figure 13-2. MPC870-like processor CPU Interface Read Cycle ........................................................................ 174
Figure 13-3. MPC8313-like processor CPU Interface Write Cycle....................................................................... 174
Figure 13-4. MPC8313-like processor CPU Interface Read Cycle ...................................................................... 175
Figure 13-5. TDM Port using Single Clock (TCLKO), positive edge timing (RSS = 1, TIES = RIES = 0) .............. 176
Figure 13-6. TDM Port using Two Clock, negative edge timing (RSS = 0, TIES = RIES = 1)............................... 176
Figure 13-7. GMII Transmit Timing.................................................................................................................... 177
Figure 13-8. GMII Receive Timing..................................................................................................................... 177
Figure 13-9. MII Transmit Timing ...................................................................................................................... 178
Figure 13-10. MII Receive Timing...................................................................................................................... 178
Figure 13-11. DDR SDRAM Timing.................................................................................................................... 179
Figure 15-1. 676-Ball TEPBGA (56-G6029-001)................................................................................................. 192
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DS34S132 DATA SHEET
LIST OF TABLES
Table 3-1. Applicable Standards ......................................................................................................................... 10
Table 8-2. Detailed Pin Descriptions .................................................................................................................... 22
Table 9-2. TDM Port TCLKOn Clock Source Selection......................................................................................... 36
Table 9-3. TDM Port BFD Settings....................................................................................................................... 38
Table 9-4. CAS Translation using RSIG and TSIG ............................................................................................... 41
Table 9-5. CAS Translation using RDAT and TDAT ............................................................................................. 42
Table 9-6. PDV Parameters that affect the latency of a PW packet....................................................................... 46
Table 9-7. Maximum S132 Ethernet Media PDV .................................................................................................. 47
Table 9-8. Recognized PW Ethernet Types.......................................................................................................... 57
Table 9-9. Malformed PW Header Handling (not including the UDP specific settings)........................................... 59
Table 9-10. Bundle Forwarding Options ............................................................................................................... 59
Table 9-11. TXP SAT/CES/HDLC/Clock Only PW Header Control ....................................................................... 62
Table 9-12. RXP CPU Header Descriptor – 1st Dword .......................................................................................... 64
Table 9-13. RXP CPU Header Descriptor – 2nd Dword ......................................................................................... 65
Table 9-14. RXP CPU Header Descriptor – 3rd Dword.......................................................................................... 65
Table 9-15. TXP CPU Header Control.................................................................................................................. 66
Table 9-16. Modify FCS and Add TXP OAM Timestamp Functions....................................................................... 67
Table 9-17. SDRAM Device Selection Table ........................................................................................................ 69
Table 9-18. Interrupt Hierarchy............................................................................................................................. 72
Table 10-1. Register Block Address Ranges ........................................................................................................ 74
Table 10-3. Global Configuration Registers.......................................................................................................... 83
Table 10-4. Global Status Registers (G.).............................................................................................................. 86
Table 10-5. Global Status Register Interrupt Enables (G.) .................................................................................... 88
Table 10-6. Bundle Reset Registers (G.).............................................................................................................. 89
Table 10-7. Bundle Data Control Registers (B.).................................................................................................... 90
Table 10-8. Bundle Data Registers (B.)................................................................................................................ 91
Table 10-9. Bundle Status Latch Registers (B.).................................................................................................... 97
Table 10-10. Bundle Status Register Interrupt Enables (B.)................................................................................ 100
Table 10-11. Jitter Buffer Status Registers (JB.)................................................................................................. 104
Table 10-12. Jitter Buffer Status Register Interrupt Enables (JB.)....................................................................... 107
Table 10-13. Packet Classifier Configuration Registers (PC.) ............................................................................. 110
Table 10-14. Packet Classifier Register Latches (PC.) ....................................................................................... 113
Table 10-15. Packet Classifier Status Register Interrupt Enables (PC.) .............................................................. 114
Table 10-16. Packet Classifier Counter Registers (PC.) ..................................................................................... 115
Table 10-17. External Memory Interface Configuration Registers (EMI.)............................................................. 115
Table 10-18. External Memory Interface Status Registers (EMI.)........................................................................ 116
Table 10-19. External Memory Interface Status Register Interrupt Enables (EMI.).............................................. 117
Table 10-20. External Memory DLL/PLL Test Registers (EMI.)........................................................................... 118
Table 10-21. Write Registers (EMA.).................................................................................................................. 118
Table 10-22. Read Registers (EMA.).................................................................................................................. 120
Table 10-23. Encap BERT Registers (EB.)......................................................................................................... 122
Table 10-24. Decap BERT Registers (DB.) ........................................................................................................ 124
Table 10-25. Miscellaneous Diagnostic Registers (MD.)..................................................................................... 126
Table 10-26. Test Registers (TST.).................................................................................................................... 127
Table 10-27. MAC Registers (M.)....................................................................................................................... 129
Table 10-28. TXP SW CAS Registers (TXSCn.)................................................................................................. 138
Table 10-29. Xmt (RXP) SW CAS Registers (RXSCn.)....................................................................................... 139
Table 10-30. Port n Transmit Configuration Registers (Pn.)................................................................................ 140
Table 10-31. Port n Transmit Status Registers (Pn.)........................................................................................... 142
Table 10-32. Port n Transmit Status Register Latches (Pn.) ............................................................................... 143
Table 10-33. Port n Transmit Status Register Interrupt Enables (Pn.)................................................................. 143
Table 10-34. Port n Receive Configuration Registers (Pn.)................................................................................. 144
Table 10-35. Port n Receive Status Registers (Pn.)............................................................................................ 146
Table 10-36. Port n Receive Status Register Latches (Pn.) ................................................................................ 147
Table 10-37. Port n Receive Status Register Interrupt Enables (Pn.).................................................................. 147
Table 10-38. Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m)............................. 147
Table 10-39. Global Ethernet MAC (M.) Control Register Settings (Values are in hex)........................................ 149
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DS34S132 DATA SHEET
Table 10-40. Global Ethernet Packet Classification (PC.) Settings...................................................................... 150
Table 10-41. Valid UDP BID Location and UDP Protocol Type Settings.............................................................. 151
Table 10-42. Bundle and OAM Bundle Control Registers (B.)............................................................................. 151
Table 10-43. SAT Bundle Settings ..................................................................................................................... 152
Table 10-44. PMS/PDVT/MJBS for SAT with various PCT, PDV and BFD values............................................... 152
Table 10-45. CES without CAS Bundle Settings................................................................................................. 153
Table 10-46. PMS/PDVT/MJBS for T1/E1 CES without CAS for various PCT, PDV and BFD values .................. 153
Table 10-47. CES with CAS Bundle Settings...................................................................................................... 154
Table 10-48. PMS/PDVT/MJBS for T1/E1 CES with CAS for various PCT, PDV and BFD values....................... 154
Table 10-49. Unstructured HDLC Bundle (any Line Rate) Settings..................................................................... 155
Table 10-50. Structured Nx64 Kb/s HDLC Bundle Settings................................................................................. 156
Table 10-51. Structured 16 Kb/s or 56 Kb/s HDLC Bundle Settings.................................................................... 157
Table 10-52. Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings.............................................. 158
Table 10-53. RXP (Unidirectional) Clock Only Bundle Settings........................................................................... 159
Table 10-54. TXP (Unidirectional) Clock Only Bundle Settings ........................................................................... 160
Table 10-55. “CPU RXP PW Debug” Bundle Settings......................................................................................... 161
Table 10-56. In-band VCCV OAM Connection Settings...................................................................................... 162
Table 10-57. OAM Bundle PWID and Activation Control Registers (B.)............................................................... 162
Table 10-58. “Send to CPU” Quick Reference Settings ...................................................................................... 163
Table 10-59. Global TDM Port Settings.............................................................................................................. 163
Table 10-60. TDM Port “n” Register Settings for T1 Applications (Pn.; n = 0 to 31) ............................................. 164
Table 10-61. TDM Port “n” Register Settings for E1 Applications (Pn.; n = 0 to 31)............................................. 165
Table 10-62. TDM Port “n” Register Settings for non-T1/E1 Applications (Pn.; n = 0 to 31)................................. 166
Table 10-63. Ethernet MAC Status Registers (M.).............................................................................................. 167
Table 10-64. Ethernet RMON Count Registers (M.; all are Read Only)............................................................... 167
Table 10-65. Global Packet Classifier Monitoring Settings (PC.)......................................................................... 168
Table 10-66. Global RXP Bundle Control Word Change Monitor Settings(G.)..................................................... 168
Table 10-67. Global TXP Output Queue Status Registers (G.) ........................................................................... 168
Table 10-68. TXP Bundle Status/Statistics Registers.......................................................................................... 168
Table 10-69. RXP Bundle Status/Statistics Registers3 ........................................................................................ 169
Table 10-70. SDRAM Settings (EMI.)................................................................................................................. 169
Table 10-71. SDRAM Starting Address Assignments (EMI.; all SDRAM sizes) ................................................... 169
Table 10-72. Example Max PDV (ms) for various PCT, JBMD and # of TS Combinations................................... 169
Table 11-1. JTAG ID Code................................................................................................................................. 171
Table 12-1. Recommended DC Operating Conditions (Tj = -40°C to +85°C.)...................................................... 172
Table 12-2. DC Electrical Characteristics (Tj = -40°C to +85°C.)......................................................................... 173
Table 13-1. CPU Interface Timing (VDD = 3.3V ±5%, Tj = -40°C to 125°C.) ....................................................... 173
Table 13-2. TDM Ports....................................................................................................................................... 175
Table 13-3. GMII Transmit Timing...................................................................................................................... 177
Table 13-4. GMII Receive Timing....................................................................................................................... 177
Table 13-5. MII Transmit Timing......................................................................................................................... 177
Table 13-6. MII Receive Timing.......................................................................................................................... 178
Table 13-7. DDR SDRAM Interface Timing ........................................................................................................ 178
Table 14-1. Pins Sorted by Signal Name............................................................................................................ 180
Table 14-2. Pins Sorted by Ball Grid Array - Ball Number................................................................................... 184
Table 14-3. Pin Assignments according to Device Outline.................................................................................. 188
Table 16-1. Thermal Package Information.......................................................................................................... 193
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1
INTRODUCTION
The public network is in transition from a TDM Switched Network to a Packet Switched Network. A number of
Pseudowire (PW) packet protocols have been standardized to enable legacy TDM services (e.g. TDM voice, TDM
Leased-line and HDLC encapsulated data) to be transported and switched/routed over a single, unified PSN. The
legacy service is encapsulated into a PW protocol and then transported or tunneled through the unified PSN. The
PW protocols provide the addressing mechanisms that enable a PSN to switch/route the service without
understanding or directly regarding the specific characteristics of the services (e.g. the PSN does not have to
directly understand the timing requirements of a TDM voice service). The PW protocols have been developed for
use over PSNs that utilize the L2TPv3/IP, UDP/IP, MPLS (MFA-8) or Metro Ethernet (MEF-8) protocols.
PW protocols that are used for TDM services can be categorized as TDM-over-Packet (TDMoP) PW protocols. The
TDMoP protocols support all of the aspects of the TDM services (data, timing, signaling and OAM). This enables
Public (WAN) and Enterprise (LAN) networks to migrate to next generation PSNs and continue supporting legacy
voice and leased-line services without replacing the legacy termination equipment.
Legacy TDM services depend on constant bit rate data streams with highly accurate frequency, jitter and wander
timing requirements that up until recently have not been well supported by most packet switching equipment. For
public network applications the timing recovery mechanisms must achieve the jitter and wander performance that is
required by the ITU-T G.823/824/8261 standards. To accomplish this, a TDMoP terminating device must
incorporate innovative and complex mechanisms to recovery the TDM timing from a stream of packets.
Legacy TDM services also have numerous special features that include voice signaling and OAM systems that
have been developed over many years through a long list of standardization literature to provide carrier-grade
reliability and maintainability. The list of legacy functions and features is so long that today’s VoIP equipment only
supports a subset of what is used in the legacy TDM network. This, in part, has slowed the transition from a TDM to
Packet-based network. With TDMoP technology all features and services can be supported.
The TDMoP technology is similar to VoIP technology in that both provide a means of communicating a time
oriented service (e.g. voice) over a non-time oriented, packet network. TDMoP technology can be added
incrementally to the network (as needed) to supplement VoIP technology to provide an alternative solution when
VoIP price/performance is not optimal (e.g. where the number of supported lines does not warrant the infrastructure
required of a VoIP network) and where some function/features are not supported by the VoIP protocols.
The Legacy PSTN network also supports HDLC encapsulated data that is transported over TDM lines. PWs can
also be used to transport HDLC data. This form of PW could also be categorized as a TDM service since the
legacy service is carried over TDM lines. However, the fundamental aspects of an HDLC service do not depend as
much on TDM timing and the nature of the data can be described as “packetized” as with Ethernet, Frame Relay
and ATM services. For clarity the HDLC service is categorized as “HDLC over PW”. One example Legacy HDLC
service is SS7 Signaling which is used to communicate voice signaling information from one TDM switch to
another.
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2
ACRONYMS AND GLOSSARY
•
•
•
•
•
•
•
•
# – Number
ACR – Adaptive Clock Recovery
AT – Absolute Timestamps
ATM – Asynchronous Transfer Mode
BERT – Bit Error Rate Test
BGA – Ball Grid Array
BITS - Building Integrated Timing System
Bundle – a PW with an ID that is recognized by the
DS34S132
BW – Bandwidth
CR – Clock Recovery
CAS – Channel Associated Signaling
CCS – Common Channel Signaling
CES – abbreviation for CESoPSN
CESoPSN – Circuit Emulation Service over PSN
CLAD – Clock Rate Adapter
CRE – Clock Recovery Engine
DA – Destination Address
DCR – Differential Clock Recovery
DCR-DT – DCR with Differential Timestamps
DDR – Double Data Rate
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MPLS – Multi-Protocol Label Switching
OAM – Operations, Administration & Maintenance
OCXO – Oven Controlled Crystal Oscillator
OLT – Optical Line Termination
ONU – Optical Network Unit
PBX – Private Branch Exchange
PDV – Packet Delay Variation
PDVT – PDV Tolerance
PON – Passive Optical Network
PRBS – Pseudo-Random Bit Sequence
PSN – Packet Switched Network
PSTN – Public Switched Telephone Network
PWE3 – Pseudo-Wire Edge-to-Edge Emulation
PW – Pseudo Wire
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
QoS – Quality of Service
QRBS – Quasi-Random Bit Sequence
RAM – Random Access Memory
Rcv – Receive
RXP – Receive Packet direction “from Ethernet
Port to TDM Port”
SAT – abbreviation for SAToP
SAToP – Structure-Agnostic TDM over Packet
SDH – Synchronous Digital Hierarchy
SDRAM – Synchronous Dynamic RAM
SN – Sequence Number
SONET –Synchronous Optical Network
SS7 – Signaling System 7
T1 – commonly used term for DS1
T1-ESF – T1 Extended Super-frame
T1-SF – T1 Super-frame
T1/E1 – T1 or E1
TCXO – Temperature Compensated Crystal
Oscillator
TDM – Time Division Multiplexing
TDMoIP – TDM over IP
TDMoP – TDM over Packet
Timeslot – 64 Kb/s channel within an E1 or T1
TS – Timeslot
TXP – Transmit Packet direction “from TDM Port to
Ethernet Port”
UDP – User Datagram Protocol
VCCV – Virtual Circuit Connectivity Verification
VoIP – Voice over IP
WAN – Wide Area Network
Xmt - Transmit
•
•
•
•
•
•
•
•
•
•
•
•
Decap –De-encapsulate
DS0 – 64 Kb/s Timeslot within a T1 or E1 signal
DS1 – 1.544 Mb/s TDM data stream
E1 – 2.048 Mb/s TDM data stream
Encap –Encapsulate
EPON – Ethernet PON (IEEE 802.3ah)
FCS – Frame Check Sequence
GMII – Gigabit MII (IEEE 802.3)
GPON – Gigabit PON (ITU-T G.984)
GPS - Global Positioning System
HDLC – High-level Data Link Control
IEEE – Institute of Electrical & Electronic Engineers
IETF – Internet Engineering Task Force
IP – Internet Protocol
ISDN – Integrated Services Digital Network
ITU – International Telecommunication Union
JB – Jitter Buffer
L2TPv3 – Layer 2 Tunneling Protocol Version 3
LAN – Local Area Network
MAC – Media Access Control
MAN – Metropolitan Area Network
MEF – Metro Ethernet Forum
•
•
•
•
•
•
•
•
•
•
•
MFA – MPLS/Frame Relay Alliance (Now called
IP/MPLS Forum)
•
MII – Medium Independent Interface (IEEE 802.3)
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3
APPLICABLE STANDARDS
Table 3-1. Applicable Standards
SPECIFICATION
SPECIFICATION TITLE
ANSI
Digital Hierarchy—Electrical Interfaces, 1993
Digital Hierarchy—Formats Specification, 1995
T1.102
T1.107
Network and Customer Installation Interfaces—DS1 Electrical Interface, 1999
T1.403
ETSI
ISDN Primary Rate User Network Interface (UNI); Part 1: Layer 1 Spec. V1.2.2 (2000-05)
ETS 300 011
IEEE
Virtual Bridged Local Area Networks (2003)
IEEE 802.1Q
Carrier Sense Multiple Access with Collision Detection Access Method and Physical Layer
Spec. (2005)
IEEE 802.3
Standard Test Access Port and Boundary-Scan Architecture, 1990
IEEE 1149.1
IETF
Structure-Agnostic Time Division Multiplexing (TDM) over Packet (SAToP) (06/2006)
Encapsulation Methods for Transport of PPP/High-Level Data Link Control (HDLC) over MPLS
Networks (09/2006)
RFC 4553
RFC 4618
Structure-Aware Time Division Multiplexed (TDM) Circuit Emulation Service over Packet
Switched Network (CESoPSN) (12/2007)
RFC 5086
Time Division Multiplexing over IP (TDMoIP) (12/2007)
RFC 5087
ITU-T
Synchronous Frame Structures at 1544, 6312, 2048, 8448 and 44736 kbit/s Levels (10/1998)
Characteristics of Primary PCM Multiplex Equipment Operating at 2048Kbit/s (11/1988)
Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048Kbit/s (03/1993)
The Control of Jitter and Wander in Digital Networks Based on 2048kbps Hierarchy (03/2000)
The Control of Jitter and Wander in Digital Networks Based on 1544kbps Hierarchy (03/2000)
Timing and Synchronization Aspects in Packet Networks (05/2006)
G.704
G.732
G.736
G.823
G.824
G.8261/Y.1361
G.8261/Y.1361
I.431
Timing and Synchronization Aspects in Packet Networks (12/2006). Corrigendum 1.
Primary Rate User-Network Interface - Layer 1 Specification (03/1993)
Error Performance Measuring Equipment Operating at the Primary Rate and Above (1992)
TDM-MPLS Network Interworking – User Plane Interworking (03/2004)
O.151
Y.1413
Y.1413
Y.1414
Y.1453
MEF
TDM-MPLS Network Interworking – User Plane Interworking (10/2005). Corrigendum 1.
Voice Services–MPLS Network Interworking (07/2004)
TDM-IP Interworking – User Plane Networking (03/2006)
Implementation Agree. for Emulation of PDH Circuits over Metro Ethernet Networks (10/2004)
Emulation of TDM Circuits over MPLS Using Raw Encapsulation – Implement. Agree. (11/2004)
MEF 8
MFA
MFA 8.0.0
Note:
Only those sections of these standards that are affected by the DS34S132 functions are considered applicable. For
example, several of the standards specify T1/E1 Framer/LIU functions (e.g. pulse shape) that are not included in the
DS34S132 but also specify jitter/wander functions that are applicable.
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4
HIGH LEVEL DESCRIPTION
To implement a PW (tunnel) across a PSN requires a PW termination point at each end of the PW (tunnel). Each
terminating point provides the PW encapsulation functions that are required to enter the PSN (for one direction of
data) and the PW de-encapsulation functions to restore the data to its original (non-PW) format (for the opposite
direction). The two data directions at each termination point can be can be described as the “transmit PW packet
direction” (TXP) and the “receive PW packet direction” (RXP).
The DS34S132 TDMoP device implements the complete, bi-directional PW termination point encapsulation
functions for TDMoP and HDLC PWs. The DS34S132 is a high density solution that can terminate up to 256 PWs
that are associated with up to 32 T1/E1 data streams and aggregate that traffic for transmission over a single
100/1000 Mb/s Ethernet data stream. The DS34S132 can encap/decap TDMoP and HDLC PWs into the following
PSN protocols: L2TPv3/IPv4, L2TPv3/IPv6, UDP/IPv4, UDP/IPv6, Metro Ethernet (MEF-8) and MPLS (MFA-8).
For TDMoP PWs the DS34S132 supports the SAToP and CESoPSN payload formats. SAToP is used for
Unstructured TDM transport, where an entire T1/E1 including the framing pattern (if it exists) is transferred
transparently as a series of unformatted bytes of data in the PW payload without regard to any bit, byte and/or
frame alignment that may exist in the TDM data stream. The DS34S132 can support Unstructured T1, E1 or
slower TDM data streams (any bit rate less than or equal to 2.048 Mb/s).
CESoPSN is used for Structured TDM transport where the PW packet payload is synchronized to the T1/E1
framing. With CESoPSN the T1/E1 framing pattern is commonly not passed across the PW (removed) because the
structured PW format enables the framing information to be conveyed through the PW mechanisms. The opposite
end generates the T1/E1 framing pattern from the PWs payload structure. This payload format can be used when
the TDM service (e.g. voice) requires the ability to interpret, and/or terminate some functional aspects of the T1/E1
signal (e.g. identify DS0s within the T1/E1). PWs with the Structured payload format can support Nx64 Kb/s,
fractional T1/E1 (T1: N = 1 – 24; E1: N = 1 – 32). In some applications, a T1/E1 can be divided into multiple Nx64
blocks (M x N x 64; M = the number of fractional blocks) and the PSN can be used as a “distributed cross-connect”
to implement a point to multi-point topology forwarding some Nx64 blocks to one end point and other Nx64 blocks
to other end points (T1: M = 1 – 24; E1: M = 1 – 32; e.g. for E1: 32 x 1 x 64).
The CESoPSN Structured format can also convey CAS Signaling across a PW through the use of a sub-channel
within the CESoPSN PW packets. The DS34S132 enables the CAS Signaling to be transparently passed,
monitored by an external CPU, and/or terminated by an external CPU, all on a per Timeslot and per direction basis.
The DS34S132 allows each TDM Port to independently support asynchronous or synchronous TDM data streams.
Each TDM Port has a Clock Recovery Engine to regenerate the timing from a TDMoP PW packet data stream. For
applications that do not require clock recovery the DS34S132 also provides several external clocking options.
The Clock Recovery Engines support Differential Clock Recovery (DCR) and Adaptive Clock Recovery (ACR).
DCR can be used when a common clock is available at both ends of the PW (e.g. BITS clock for the public network
or GPS for the mobile cellular network) and requires that the PW use RTP Timestamps to convey the TDM timing
information. Adaptive Clock Recovery does not use Timestamps but instead regenerates the timing based on the
TDMoP PW packet transmission rate. The DS34S132 high performance clock recovery circuits enable the use of
PWs in the public network by achieving the stringent jitter and wander performance requirements of ITU-T
G.823/824/8261, even for networks that impose large packet delay variation (PDV) and packet loss. For far end
clock recovery, the DS34S132 can generate two Timestamp formats - Absolute and Differential Timestamps.
PWs can be used to transport HDLC packet data. The DS34S132 can forward HDLC encapsulated data
transparently using a TDMoP PW (as described above; idle HDLC Flags are forwarded with the data) or by first
extracting the data from the HDLC coding and then only forwarding the non-idle data in an HDLC PW. The HDLC
PW is useful for HDLC data streams where a significant portion of the data stream is filled with HDLC Idle Flags.
For example, if a 64 Kb/s TDM Timeslot is used to carry 4 Kb/s of HDLC data then it may be more bandwidth
efficient to extract the payload data from the HDLC encoding and forward the data over an HDLC PW. The
DS34S132 incorporates 256 HDLC Engines so that any PW can be assigned as a TDMoP PW or an HDLC PW.
PW Termination points often must also terminate OAM and Signaling packet data streams. To support this need
the DS34S132 enables an external CPU to terminate several OAM and Signaling types including: PW In-band
VCCV OAM, PW UDP-specific (Out-band VCCV) OAM, MEF OAM, Ethernet Broadcast frames, ARP, IPv6 NDP
and includes a user specified CPU-destination Ethernet Type. The DS34S132 can also be programmed to forward
packets to the CPU that match specialized conditions for debug or other purposes (e.g. wrong IP DA).
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DS34S132 DATA SHEET
The DS34S132 uses an external DDR SDRAM device to buffer data. The large memory supplies sufficient buffer
space to support a 256 ms PDV for each of the 256 PW/Bundles and to enable packet re-ordering for packets that
are received out of order (the PSN may mis-order the packets). This large memory is also used to buffer the HDLC
data streams and the CPU terminated OAM and Signaling packets.
TDMoP provides the perfect transition technology for next generation packet networks enabling the continued use
of the vast Legacy network and at the same time supplementing new packet based technologies.
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5
APPLICATION EXAMPLES
In Figure 5-1, TDMoP devices are used in gateway nodes to transport TDM services through a metropolitan PSN.
The Maxim TDMoP family of devices offers a range of density solutions so that lower density solutions like the
DS34T101 can be used in Service Provider Edge applications, to support a small number of T1/E1 lines, and
higher density solutions like the DS34S132 can be used in Central Office applications, to terminate several Service
Provider Edge nodes. PWs can be carried over fiber, wireless, SONET/SDH, G/EPON, coax, etc.
Figure 5-1. TDMoP in a Metropolitan Packet Switched Network
In Figure 5-2, DS34S132 devices are used in TDMoP gateways to enable TDM services to be transported through
a Cellular Backhaul PSN.
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DS34S132 DATA SHEET
Figure 5-2. TDMoP in Cellular Backhaul
Other Possible Applications
Using a Packet Backplane for Multiservice Concentrators
Communications platforms with all/any of the above-mentioned capabilities can replace obsolete, low bandwidth
TDM buses with low cost, high bandwidth Ethernet buses. The DS34S132 provides the interworking functions that
are needed to packetize TDM services so that they can be multiplexed together with bursty services for
transmission over a unified backplane bus. This enables a cost-effective, future-proof design with full support for
both legacy and next-generation services.
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DS34S132 DATA SHEET
6
BLOCK DIAGRAM
Figure 6-1. DS34S132 Functional Block Diagram
DDR SDRAM
Controller
CLAD
LIUCLK
Clock Recovery
Engines
TCLKO[31:0]
EXTCLK[1:0]
Ethernet
De-encapsulation
Engines
TDM
Port
ETHCLK
TSYNC[31:0]
TDAT[31:0]
TSIG[31:0]
&
CESoPSN
TSA
GTXCLK
TXER
TXEN
32
1
SAToP
Packet
Classifier
HDLC
TXD[7:0]
TXCLK
Ethernet
100/1000
MAC
Buffer Manager
CRS
COL
RCLK[31:0]
Ethernet
Encapsulation
Engines
RXER
RXDV
RXD[7:0]
RXCLK
Packet
Generator
TDM
Port
RSYNC[31:0]
RDAT[31:0]
RSIG[31:0]
CESoPSN
&
TSA
SAToP
32
1
MDIO
HDLC
MDC
EXTINT
EPHYRST_N
CPU
Interface
JTAG
MISC/MBIST
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7
FEATURES
TDM Port Features
• TDM Ports
•
32 TDM Ports, each with independently configured Framing Format
•
T1/E1 Structured (with T1/E1 Framing)
•
•
T1-SF, T1-ESF and E1 CAS Multi-frame formats
With and Without CAS Signaling
CAS embedded in data bus using RDAT/TDAT pins
Parallel CAS Interface using RSIG/TSIG pins
•
Unstructured (without Framing) - T1, E1 and slower TDM line rates (any line rate ≤ 2.048 Mb/s)
• TDM Port Timing References
•
TDM Port Clocks
•
•
•
Asynchronous or Synchronous TDM Port Timing
Independent Receive and Transmit Clocks
Transmit TDM Port Timing
•
RXP packet stream Clock Recovery
One Clock Recovery Engine per TDM Port
Global Clock Recovery Engine
•
•
EXTCLK0 or EXTCLK1 External clock reference
External RCLK signal (Loop timed)
•
Receive TDM Port Timing
•
•
External RCLK signal
Internally generated Transmit timing (for synchronous systems)
•
TDM Multi-frame Synchronization for CAS Signaling
•
•
•
Independent Receive and Transmit Multi-frame Synchronization for each TDM Port
E1, T1-SF and T1-ESF Multi-frame Synchronization
External input or internally generated Multi-frame synchronization
• TDM Port Clock Recovery Engines
•
•
Adaptive Clock Recovery or
Differential Clock Recovery
•
•
Common Clock (CMNCLK) frequency = 1MHz to 25MHz (in 8kHz increments)
RTP Differential Timestamp
•
•
•
•
•
•
Generation of Absolute Timestamps and Differential Timestamps
External 5.0 MHz – 155.52 MHz clock input (REFCLK) for internal Clock Recovery synthesizer
Fast Frequency Acquisition and Highly Accurate Phase Tracking
Recovered Clock Jitter and Wander per ITU-T G.823/G.824/G.8261 with Stratum 3 clock reference
High resilience to Packet Loss and Robust to Sudden Significant Constant Delay Changes
Automatic transition to hold-over during alarm/event impairments
• TDM Port Timeslot Assignment (TSA), CAS and Conditioning
•
•
Nx64 Kb/s – any combination of T1/E1 Timeslots from one TDM Port can be assigned to a PW/Bundle
T1/E1 CAS Signaling (Channel Associated Signaling)
•
•
•
Transparent CAS (forwarded from TDM to Ethernet Port and from Ethernet to TDM Port)
Per Timeslot CPU Controlled CAS (CPU inserts CAS; in TXP and/or RXP directions)
CAS Status and Change of Status for CPU Monitoring (in RXP and TXP directions)
•
Data Conditioning – can force any 8-bit pattern on any number of Timeslots (in RXP and TXP directions)
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DS34S132 DATA SHEET
Ethernet Port Features
• Ethernet MAC Interface
•
•
•
•
100/1000 Mb/s Operation using MII/GMII Interface
2 programmable receive Ethernet Destination Addresses
Mixed Ethernet II (DIX) and IEEE 802.2 LLC/SNAP formats
Mixed data streams with 0, 1, or 2 VLAN Tags
•
Programmable VLAN TPID
•
Ethernet Frame Length 64 bytes to 2000 bytes
PW/Bundle Features
• RXP PW/Bundle Header
•
•
Up to 256 programmed PW/Bundles (32 per TDM Port)
PW Header Types
•
•
L2TPv3 / IPv6
L2TPv3 / IPv4
•
•
UDP / IPv4
UDP / IPv6
•
•
MEF (MEF-8)
MPLS (MFA-8)
•
•
•
Mixed MPLS data streams with 0, 1 or 2 MPLS Outer Labels
Mixed L2TPv3 data streams with 0, 1, or 2 L2TPv3 Cookies
Flexible UDP settings
•
•
•
•
16-bit (standard) or 32-bit (extended) UDP PW-ID bit width
16-bit UDP PW-ID selectable to be verified against UDP Source or Destination Port
Optional 16-bit PW-ID Mask
Ignore UDP Payload Protocol or verify against 2 programmable UDP Payload Protocol Values
•
Optional PW Control Word
Optional “In-band VCCV” Monitoring
Programmable 16-bit In-band VCCV value with programmable 16-bit In-band VCCV mask
Optional RTP Header
One PW/Bundle per TDM Port can be assigned to provide RTP Timestamp for Clock Recovery
Sequence Number
•
•
•
•
•
•
•
•
Selectable between Control Word or RTP Sequence Number
Used to initiate conditioning data when packets are missing
Optional re-ordering of mis-ordered packets up to the Size of the Jitter Buffer depth
•
•
Up to 32 UDP-Specific (Out-band VCCV) OAM PW-IDs
Debug settings to forward PW/Bundles with special conditions to CPU for analysis (e.g. wrong IP DA)
• TXP PW/Bundle Header
•
Store up to 256 CPU generated PW/Bundle Headers (one per PW/Bundle)
Maximum 122 byte header with any CPU-specified content (Layer 2/3/4 content)
•
•
•
Auto generate and insert Length and FCS functions for IP and UDP Headers
Optional RTP Timestamp Insertion
Any number of TXP PW/Bundles can be assigned to include Timestamp in RTP Header
Optional RTP and Control Word Sequence Number Insertion
3 HDLC Sequence Number generation modes
•
•
•
•
Sequence Numbers with “fixed at zero” value
Sequence Numbers with incremented counting using “skip zero at Rollover”
Sequence Numbers with incremented counting using “include zero at Rollover”
• PW/Bundle Payload Types
•
TDMoP PW/Bundles (non-HDLC) - Constant Bit Rate Services (e.g. PCM voice)
•
•
Unstructured PW Payload (without framing; SAToP): E1, T1 and slower TDM bit rate (≤ 2.048 Mb/s)
Structured PW Payload (with framing; CESoPSN)
•
E1, T1-SF and T1-ESF formats
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DS34S132 DATA SHEET
•
•
Any Nx64 Kb/s bit rate from a single T1 or E1 TDM Port
With or without CAS Signaling
•
HDLC PW/Bundles (e.g. SS7 Signaling)
•
•
Unstructured PW Payload: E1, T1 and slower TDM bit rate (≤ 2.048 Mb/s)
Structured PW Payload: Any Nx64 Kb/s bit rate from a single T1 or E1 TDM Port (for 8-bit HDLC)
• CES/SAT Processing
•
•
256 CES/SAT Engines (one per PW/Bundle)
Per PW/Bundle Settings
•
•
•
Any Payload Size (up to maximum 2000 byte Ethernet Packet length)
Optional “zero” payload size for PW/Bundles that are only used for Clock Recovery
RXP Jitter Buffer (to compensate for PDV and for packet re-ordering; up to 500 ms)
Programmable “Begin Play-out Watermark” (for PDVT)
TXP high or low priority queue scheduling
•
•
• HDLC Processing
•
•
•
256 HDLC Engines (one per PW/Bundle)
Configurable Transmit TDM Port minimum number of Intra-frame Flags (1 to 8)
Per Engine Settings
•
•
•
•
2-bit, 7-bit or 8-bit HDLC coding
16-bit, 32-bit or “no” Trailing HDLC FCS
Intra-frame Flag Value (0xFF or 0x7E)
HDLC Transmission Bit Order using MSB first or LSB first
CPU Interface Features
• CPU Packet Interface (for CPU-based OAM and Signaling)
•
•
Stores up to 512 Transmit and 512 Receive Packets that can be 64 byte to 2000 byte in length
RXP direction
•
Provides detected packet type with each received RXP CPU packet
•
•
•
•
•
•
•
In-band VCCV OAM
UDP-specific (Out-band VCCV) OAM
MEF OAM Ethernet Type
Configured “CPU Ethernet Type”
ARP
Broadcast Ethernet DA
Several Packet Header Conditions (e.g. NDP/IPv6 & unknown IP DA)
•
Provides Local Timestamp indicating the time the packet was received (in 1 us or 100 us units)
•
TXP direction
Any CPU generated Header and Payload (any Layer 2/3/4 content)
•
•
•
Support for IP FCS and UDP FCS Generation
Optionally inserts TXP OAM Timestamps (in 1 us or 100 us units)
• DS34S132 Control Interface
•
MPC8xx or MPC83xx synchronous interface using a 50 to 80 MHz clock rate (the MPC8xx and MPC83xx
are processor product families of Freescale Semiconductor, Inc.)
Selectable 16-bit or 32-bit data bus
DS34S132 device Control & Sense Registers
Mask-able Interrupt Hierarchy for Change of Status, Alarms and Events
Ethernet Port RMON Statistics
•
•
•
•
Miscellaneous
•
Loopbacks
•
•
PW/Bundle Loopback (payload from RXP PW packets are transmitted in TXP PW packets)
TDM Port Line Loopback (all data from Receive TDM Port sent to Transmit TDM Port using RCLK)
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DS34S132 DATA SHEET
•
TDM Port Timeslot Loopback (from Receive to Transmit TDM Port Timeslot using RCLK)
•
TDM Port and/or Ethernet Port BERT Testing
•
•
Half Channel (one-way) or Full Channel (round-trip) Testing
Flexible PRBS, QRBS or Fixed Pattern Testing
•
•
•
•
•
16-bit DDR SDRAM Interface that does not require any glue-logic
IEEE 1149.1 JTAG support
MBIST (memory built-in self test)
1.8V Core, 2.5V DDR SDRAM and 3.3V I/O that are 5V tolerant
27 x 27 mm, 676-pin BGA package (1mm pitch)
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DS34S132 DATA SHEET
8
PIN DESCRIPTIONS
8.1 Short Pin Descriptions
Table 8-1. DS34S132 Short Pin Descriptions
Name
TDM Port n = 0 through 31 Ports
Type* Function
TCLKOn
TSYNCn
TDATn
TSIGn
RCLKn
RSYNCn
RDATn
RSIGn
Oz
IO
Oz
Oz
I
IO
I
I
Transmit TDM Clock Output
Transmit Frame (Frame or Multi-frame Sync Pulse)
Transmit NRZ Data
Transmit Signaling
Receive Clock Input
Receive Frame (Frame or Multi-frame Sync Pulse)
Receive NRZ Data
Receive Signaling
100/1000 Mbps Ethernet MAC Interface (GMII/MII)
TXCLK
GTXCLK
TXD[7:0]
TXEN
Ipu
Oz
Oz
Oz
Oz
Ipu
I
MII Transmit clock (25 MHz)
GMII Transmit clock (125 MHz)
GMII/MII Transmit data
GMII/MII Transmit data enable
GMII/MII Transmit packet frame invalid
GMII/MII Receive clock (25 MHz or 125 MHz)
GMII/MII Receive data
TXER
RXCLK
RXD[7:0]
RXDV
I
I
GMII/MII Receive data valid
GMII/MII Receive error
RXER
COL
CRS
MDC
MDIO
I
I
MII Collision Detection (not used)
Carrier Sense Detection (not used)
Management Data Clock
Oz
IO
Management Data Input/Output
CPU Interface
PD[31:0]
PA[13:1]
PALE
PCS_N
PRW
IO
I
I
I
I
Data [31:0]
Address [13:1]
Address Latch Enable
Chip Select (active low)
Read/Write
PRWCTRL
PTA_N
PWIDTH
PINT_N
I
Read/Write Control
Transfer Acknowledge (active low)
Processor Bus Width
Interrupt Out (active low)
Oz
I
Oz
External Memory Interface – DDR SDRAM
SDCLK, SDCLK_N
SDCLKEN
SDCS_N
SDRAS_N
SDCAS_N
SDWE_N
SDBA[1:0]
SDA[13:0]
SDDQ[15:0]
SDLDM
Oz
Oz
Oz
Oz
Oz
Oz
Oz
Oz
IO
SDRAM Clock
Clock Enable
Chip Select (active low)
RAS (active low)
CAS (active low)
Write Enable (active low)
Bank Address Select
Address
Bi-directional Data Bus
Lower Byte Data Mask
Upper Byte Data Mask
Oz
Oz
SDUDM
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DS34S132 DATA SHEET
Name
Type* Function
SDLDQS
SDUDQS
Oz
Oz
Lower Byte Data Strobe
Upper Byte Data Strobe
Clocks, Resets , JTAG & Miscellaneous
CMNCLK
EXTCLK[1:0]
SYSCLK
LIUCLK
REFCLK
DDRCLK
ETHCLK
EXTINT
EPHYRST_N
RST_N
I
I
I
Optional Differential Clock Recovery Common Clock (8kHz to 25MHz)
2 Independent Optional External Clocks for TDM Port Transmit Timing
System Clock for CPU Interface (50 MHz to 80MHz)
1.544MHz or 2.048MHz
Optional Oscillator Reference for Clock Recovery (5 MHz to 155.52 MHz)
DDR SDRAM clock (125MHz)
Optional Clock for GMII operation & OAM Timestamps (25MHz or 125MHz)
Ethernet Phy Interrupt (if MDIO/MDC are not used)
Ethernet Phy Reset signal
Oz
I
I
I
I
Oz
I
Global Reset
JTCLK
I
JTAG Clock
JTMS
JTDI
JTDO
JTRST_N
HIZ_N
TEST_N
MT[15:0]
SMTI
Ipu
Ipu
Oz
Ipu
I
JTAG Mode Select
JTAG Data Input
JTAG Data Output
JTAG Reset (active low)
High impedance test enable (active low)
Test enable (active low)
Manufacturing Test
Manufacturing Test Input, Must be tied to VCC33.
Manufacturing Test Output, Must be left unconnected (floating).
I
IO
Ipu
O
SMTO
Power Supply Signals
VDD33
VDD18
VSS
pwr
Core Digital 3.3 Volt Power Supply Input
Core Digital 1.8 Volt Power Supply Input
pwr
pwr
pwr
pwr
pwr
pwr
pwr
pwr
pwr
pwr
Ground for 3.3V and 1.8V supplies. Connect to Common Supply Ground
SDRAM 1.8 Volt PLL Power (may be connected CVDD)
AVDD Ground (may be connected to CVSS)
CLAD 1.8 Volt Power (may be connected to AVDD)
CVDD Ground (may be connected to AVSS)
SDRAM Digital Core 2.5 Volt Power Supply Input
SDRAM DQ 2.5 Volt Power Supply Input
SDRAM Digital Ground for VDDP and VDDQ
SDRAM SSTL_2 Reference Voltage (one-half VDDQ)
AVDD
AVSS
CVDD
CVSS
VDDP
VDDQ
VSSQ
VREF
1
Note:
n = 0 to 31 (port number), Ipu = input with pullup, Oz = output tri-stateable, IO = Bi-directional input/output
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DS34S132 DATA SHEET
8.2 Detailed Pin Descriptions
Table 8-2. Detailed Pin Descriptions
Pin Name
Type Pin Description
TDM Port n = 0 through 31 Ports
Transmit Clock Output. TCLKOn is derived from the clock recovery engine or from
RCLKn when in loop-timed mode or from the EXTCLK signal.
TCLKOn
TSYNCn
Oz
IO
Transmit Sync. TSYNCn may be a frame or multi-frame input or output signal. Each
frame is a 125 us time period. The frame count for each multi-frame type is: T1-SF =
12; T1-ESF = 24; E1 = 16. If configured as an input, it is sampled by TCLKOn. If
configured as an output, it is output with respect to TCLKOn.
Transmit Data Output. TDATn is the TDM datastream recovered from the PSN,
output with respect to TCLKOn.
TDATn
TSIGn
Oz
Oz
Transmit Signaling. TSIGn is the transmit signaling recovered from the PSN, output
with respect to TCLKOn. The CAS values are updated once every TSYNC period.
Receive Clock. RCLKn is input clock typically derived from a T1/E1 framer or LIU.
RCLKn
I
I
Receive Sync. RSYNCn indicates the frame or multi-frame boundary for the T1/E1
datastream, typically derived from a T1/E1 framer or LIU and sampled by RCLKn.
Each frame is a 125 us period. The frame count for each multi-frame type is: T1-SF =
12; T1-ESF = 24; E1 = 16.
RSYNCn
Receive Data. RDATn is the receive TDM datastream typically derived from a T1/E1
framer or LIU, sampled by RCLKn.
RDATn
RSIGn
I
I
Receive Signaling. RSIGn is the receive signaling typically derived from a T1/E1
framer, sampled by RCLKn. The CAS values are updated once every RSYNC period.
100/1000 Mbps Ethernet MAC Interface (GMII/MII)
Transmit Clock (MII). Timing reference for TXEN and TXD[0:3]. The TXCLK
frequency is 25 MHz for 100 Mbit/s operation.
TXCLK
Ipu
Oz
Oz
GMII Transmit Clock Output. 125MHz clock output available for GMII operation.
This clock is synchronous to ETHCLK input.
GTXCLK
TXD[0:7]
Transmit Data 0 through 7(GMII Mode – TXD[0:7]). TXD[0:7] is presented
synchronously with the rising edge of TXCLK. TXD[0] is the least significant bit of the
data. When TXEN is low the data on TXD should be ignored.
Transmit Data 0 through 3(MII Mode – TXD[0:3]). Four bits of data TXD[0:3]
presented synchronously with the rising edge of TXCLK. When MII mode is selected,
TXD[4:7] pins are not used.
Transmit Enable (GMII). When this signal is asserted, the data on TXD[0:7] is valid;
TXEN
Oz
synchronous with GTXCLK.
Transmit Enable (MII). In MII mode, this pin is asserted high when data TXD[0:3] is
being provided by the device. This signal is synchronous with the rising edge TXCLK.
It is asserted with the first bit of the preamble. Synchronous with TXCLK.
Transmit Error (GMII, MII). When this signal is asserted, the PHY will respond by
sending one or more code groups in error.
TXER
Oz
Ipu
Receive Clock (GMII). 125 MHz clock. This clock is used to sample the RXD[0:7]
RXCLK
data.
Receive Clock (MII). Timing reference for RXDV, RXER and RXD[0:3], which are
clocked on the rising edge. RXCLK frequency is 25 MHz for 100 Mbit/s operation.
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DS34S132 DATA SHEET
Pin Name
Type Pin Description
Receive Data 0 through 7(GMII Mode – RXD[0:7]). Eight bits of received data,
sampled synchronously with the rising edge of RXCLK. For every clock cycle, the
RXD[7:0]
I
PHY transfers 8 bits to the device. RXD[0] is the least significant bit of the data. Data
is not considered valid when RXDV is low.
Receive Data 0 through 3(MII Mode – RXD[0:3]). Four bits of received data,
sampled synchronously with RXCLK. Accepted when CRS is asserted. When MII
mode is selected, RXD[4:7] pins are not used.
Receive Data Valid (GMII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In GMII mode the data RXD[0:7] is ignored if RXDV is not
asserted high.
RXDV
RXER
I
I
Receive Data Valid (MII). This active high signal, synchronous to RXCLK, indicates
valid data from the PHY. In MII mode the data RXD[0:3] is ignored if RXDV is not
asserted high.
Receive Error (GMII). This signal indicates a receive error or a carrier extension in
the GMII Mode.
Receive Error (MII). Asserted by the PHY for one or more RXCLK periods indicating
that an error has occurred. Active high indicates receive packet is invalid.
MII and GMII modes: This is synchronous with RXCLK.
Collision Detect (MII). Asserted by the Ethernet PHY to indicate that a collision is
occurring. This signal is only valid in half duplex mode, and is ignored in full duplex
mode.
COL
I
Receive Carrier Sense. This signal is asserted by the PHY when either transmit or
CRS
I
receive medium is active. This signal is not synchronous to any of the clocks.
Management Data Clock. A divided down SYSCLK that clocks management data to
and from the PHY.
MDC
MDIO
Oz
IO
Management Data IO. Data path for control information between the device and the
PHY. Pull to logic high externally through a 1.5K ohm resistor. The MDC and MDIO
pins are used to write or read up to 32 Control and Status Registers in PHY
Controllers. This port can also be used to initiate Auto-Negotiation for the PHY.
CPU Interface
32-bit Processor Data Bus. PD[31] is the MSB which should be mapped to D[0] of a
PD[31:0]
IO
MPC8xxx processor.
16-bit Processor Data Bus. PD[15] is the MSB which should be mapped to D[0] of a
MPC8xxx processor. PD[31:16] is not used and should be tied low.
32-bit & 16-bit Processor Data Bus. Input signals on this bus are captured by the
rising edge of SYSCLK. Output signals are updated on the rising edge of SYSCLK.
Processor Address Bus. The signals on this bus are captured by the rising edge of
SYSCLK.
PA[13:2]
PA[1]
I
I
32-bit Processor Address Bus Bit 1. PA[1] is not used and should be tied low.
32-bit Processor Address Bus Bit 1. When PA[1] = 0, PD[15:0] carries the upper 16
bits of the 32-bit word. When PA[1] = 1, PD[15:0] carries the lower 16 bits of the 32-bit
word.
Processor Address Latch. PALE latches PA[13:1] on its falling edge. In non-muxed
PALE
I
mode, tie high.
Processor Chip Select. Processor chip select active low. Synchronous to SYSCLK.
PCS_N
PRW
I
I
Processor Read/Write. The behavior of this signal is described by PRWCTRL. This
signal is synchronous to SYSCLK.
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DS34S132 DATA SHEET
Pin Name
Type Pin Description
Processor Read/Write Control.
PRWCTRL
I
0 = PRW is high for a write, low for a read (PQ II Pro mode)
1 = PRW is low for a write, high for a read (PQ I mode)
Processor Transfer Acknowledge. This signal indicates to the processor on a read
that data is valid on the data bus. On a write, it indicates that the DS34S132 is ready
for a new transaction. This signal is synchronous to SYSCLK since the PowerQuicc I
requires it. This signal requires an external pull-up. On the PowerQuicc I, the PTA_N
is used as a data valid signal and therefore must be coincident with the data on read
accesses (i.e. it may not be early.)
PTA_N
Oz
Processor Bus Width
0 = 16-bit mode
1 = 32-bit mode
Processor Interrupt. When the bit configurable Interrupt Inactive Mode is ‘0’, this pin
is active low, asynchronous to SYSCLK and is high impedance when not active.
When the bit configurable Interrupt Inactive Mode is ‘1’, this pin is active low,
asynchronous to SYSCLK and drives high when no interrupts are active.
PWIDTH
PINT_N
I
Oz
External Memory Interface – DDR SDRAM
SDRAM Clock. SDCLK and SDCLK_N are differential clock outputs. (Both pins are
referenced collectively as SDCLK.) All address and control input signals are sampled
on the positive edge of SDCLK and negative edge of SDCLK. Output (write) data is
referenced to the rising edge and falling edge of SDCLK.
SDCLK,
SDCLK_N
Oz
SDRAM Clock Enable. Active High. SDCLKEN must be active throughout DDR
SDRAM READ and WRITE accesses.
SDCLKEN
SDCS_N
Oz
Oz
SDRAM Chip Select. All commands are masked when SDCS_N is registered high.
SDCS_N provides for external bank selection on systems with multiple banks. SDCS-
_N is considered part of the command code.
SDRAM Row Address Strobe. Active low output, used to latch the row address on
rising edge of SDCLK. It is used with commands for Bank Activate, Precharge, and
Mode Register Write.
SDRAS_N
SDCAS_N
Oz
Oz
SDRAM Column Address Strobe. Active low output, used to latch the column
address on the rising edge of SDCLK. It is used with commands for Bank Activate,
Precharge, and Mode Register Write.
SDRAM Write Enable. This active low output enables write operation and auto
precharge.
SDWE_N
SDBA[1:0]
SDA[13:0]
Oz
Oz
Oz
SDRAM Bank Select. These 2 bits select 1 of 4 banks for the read/write/precharge
operations.
SDRAM Address. The 14 pins of the SDRAM address bus output the row address
first, followed by the column address. The row address is determined by SDA[0] to
SDA[13] at the rising edge of clock. Column address is determined by SDA[0]-SDA[9]
at the rising edge of the clock. SDA[10] is used as an auto-precharge signal.
SDRAM Data Bus. The 16 pins of the SDRAM data bus are inputs for read
operations and outputs for write operations. At all other times, these pins are high-
impedance.
SDDQ[15:0]
SDLDM
IO
Oz
Oz
SDRAM Lower Data Mask. SDLDM is an active high output mask signal for write
data. SDLDM is updated on both edges of SDLDQS. SD_LDM corresponds to data
on SDATA7-SDATA0.
SDRAM Upper Data Mask. SDUDM is an active high output mask signal for write
data. SDUDM is updated on both edges of SDUDQS. SDUDM corresponds to data
on SDATA15-SDATA8.
SDUDM
SDRAM Lower Data Strobe. Output with write data, input with read data. SDLDQS
corresponds to data on SDATA7-SDATA0.
SDLDQS
Oz
Oz
SDRAM Upper Data Strobe. Output with write data, input with read data. SDUDQS
SDUDQS
corresponds to data on SDATA15-SDATA8.
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DS34S132 DATA SHEET
Pin Name
Type Pin Description
Clocks, Resets , JTAG & Miscellaneous
Common Clock. This clock is used for Differential Clock Recovery. Common clock
has to be a multiple of 8 kHz and in the range of 8 kHz to 25 MHz. The frequency
input should not be too close to an integer multiple of the service clock frequency.
Based on these criteria, the following frequencies are suggested:
CMNCLK
I
SONET/SDH systems: 19.44 MHz
GPS systems: 8.184 MHz
ATM systems: 9.72 MHz or 19.44 MHz
Synchronous Ethernet systems: 25 MHz
CMNCLK may also be used in lieu of REFCLK if the CMNCLK frequency matches
one of the frequencies used for REFCLK and if CMNCLK is a high quality clock
(Stratum 3). When CMNCLK is not used tie to ground or VDD(3.3V).
External Clock. This clock is used as an E1 or T1 Station Clock. In this mode, is
used for TDATn. When this clock is not used tie to ground or VDD(3.3V).
EXTCLK[1:0]
SYSCLK
I
I
System Clock. This clock shall be in the range of 50 – 85 MHz and also synchronous
with the CPU’s bus clock.
LIU Clock. This clock is generated by the CLAD based on either REFCLK or
CMNCLK and can be selected to be 1.544 MHz or 2.048 MHz. By default, this clock
drives low.
LIUCLK
O
Reference Clock. This clock must be one of the following frequencies: 5 MHz, 5.12
MHz, 10 MHz, 10.24 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 25 MHz, 30.72
MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz. This input shall be a stratum 3 quality
or better. This clock is selectable by the CLAD to derive the synthesis clock for the
clock recovery engine. CMNCLK can be used in lieu of REFCLK.
REFCLK
ETHCLK
I
I
Ethernet Clock. This clock is used as the source for the GTXCLK in GMII mode and
is used as a constant reference for several internal clocks. This signal must always be
provided with 125MHz clock +/- 100ppm. It may use the same oscillator as DDRCLK.
DDR Clock. This clock is used as the source for SD0CLK and SDCLK. The clock
frequency should be 125 MHz. It may use the same oscillator as ETHCLK.
DDRCLK
RST_N
I
I
Reset. An active low signal on this pin resets the internal registers and logic. While
this pin is held low, the microprocessor interface is kept in a high-impedance state.
This pin should remain low until power is stable and then set high for normal
operation.
JTAG Clock. This signal is used to shift data into JTDI on the rising edge and out of
JTDO on the falling edge.
JTCLK
JTMS
I
JTAG Mode Select. This pin is sampled on the rising edge of JTCLK and is used to
place the test access port into the various defined IEEE 1149.1 states. This pin has a
10k pull up resistor.
Ipu
JTAG Data In. Test instructions and data are clocked into this pin on the rising edge
of JTCLK. This pin has a 10k pull up resistor.
JTDI
Ipu
Oz
Ipu
JTAG Data Out. Test instructions and data are clocked out of this pin on the falling
edge of JTCLK. If not used, this pin should be left unconnected.
JTDO
JTAG Reset. JTRST is used to asynchronously reset the test access port controller.
After power up, a rising edge on JTRST will reset the test port and cause the device
I/O to enter the JTAG DEVICE ID mode. Pulling JTRST low restores normal device
operation. JTRST is pulled HIGH internally via a 10k resistor operation. If boundary
scan is not used, this pin should be held low.
JTRST_N
Test Enable. (active low)
TEST_N
HIZ_N
I
I
High Impedance test enable. This signal puts all digital output and bi-directional pins
in the high impedance state when it is low and JTRST is low. For normal operation tie
high. This is an asynchronous input.
External PHY Interrupt. PHY Interrupt to MAC, if MDIO and MDC are not used.
Manufacturing Test. For normal operation leave these pins unconnected.
Manufacturing Test Input, Must be tied to VCC33.
EXTINT
MT[15:0]
SMTI
I
IO
Ipu
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DS34S132 DATA SHEET
Pin Name
SMTO
Type Pin Description
Manufacturing Test Output, Must be left unconnected (floating).
O
Power Supply Signals
VDD33. Connect to 3.3 Volt Power Supply
VDD18. Connect to 1.8 Volt Power Supply
VDD33
VDD18
VSS
pwr
pwr
pwr
VSS. Ground connection for 3.3V and 1.8V supplies. Connect to the Common Supply
Ground
Analog PLL Power 1. Connect to a 1.8 Volt Power Supply
Analog PLL Power 2. Connect to a 1.8 Volt Power Supply
Analog PLL Ground.
AVDD1
AVDD2
AVSS
pwr
pwr
pwr
pwr
pwr
pwr
ref
SDRAM Digital Power. Connect to a 2.5 Volt Power Supply
SDRAM Digital DQ Power. Connect to a 2.5 Volt Power Supply
SDRAM Digital Ground.
VDD25
VDDQ
VSSQ
VREF
Voltage Reference. SDRAM SSTL_2 Reference Voltage
Notes: n=0 to 31 (port number), Ipu (input with pullup), Oz (output tri-stateable), & IO (Bi-directional input/output).
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DS34S132 DATA SHEET
9
FUNCTIONAL DESCRIPTION
This section provides a high level, functional view of the S132. Because of the high level of integration and
complexity that has been included in the S132, it is necessary to first explain the terminology and conventions that
are used. This Functional Description section is further supported by the Register Guide section, which identifies
common settings for specific applications, and the Register Definition section which provides a definition for each
register, but without as much regard for application information.
The industry term “Pseudowire” (PW) includes the idea of a “virtual connection” (pseudo ≅ virtual; wire ≅
connection). PW data is carried in packets. The connection is not a “hardwired” connection but “virtual” in nature
where the “virtual connection” is recognized by interpreting the PW packet header (e.g. the PW-ID provides the PW
destination address).
There are multiple PW protocols to carry different types of data. Each is designed to support a particular service
type, for example PCM, HDLC, ATM and Frame Relay. The PW protocols enable a Service Provider to transport
and switch all of its services using a single unified switching/routing/forwarding technique (e.g. IPv4).
Enterprise and CPE equipment can similarly use the PW protocols. PWs can enable LAN
switching/routing/forwarding using a single protocol/equipment type (e.g. Ethernet switch) to support both packet
encapsulated-TDM and bursty packet data. PWs can also be used to enable the use of a single WAN interface to
carry aggregated Enterprise data across the WAN/PSN. For example, if the WAN service/interface is Ethernet, then
a single WAN-Ethernet interface can be used to carry “bursty” Ethernet data and packet encapsulated TDM data
across the WAN. This prevents the need to pay for independent Ethernet WAN and TDM WAN services.
The DS34S132 supports three PW types. The term “TDMoP PW” is used to refer to a PW that is used to transport
a constant-bit-rate TDM service. The S132 supports two types of TDMoP PWs: SAToP (SAT) and CESoPSN
(CES). The term “HDLC PW” is used to refer to a PW that is used to transport the non-idle payload data from an
HDLC data stream. The S132 includes the necessary functions to translate TDM constant bit rate data streams
to/from TDMoP PWs and HDLC data streams to/from HDLC PWs for PSNs using the UDP/IP, L2TPv3/IP, MEF-8
or MFA-8 protocol.
PWs that are recognized by the S132 are described using the terms “Connection”, ”Packet”, “Bundle” and “Bundle
ID” (BID). Each term emphasizes a different aspect of the PW. The S132 supports up to 256 programmed Bundles
(numbered Bundle 0 through Bundle 255). The term “Bundle” emphasizes the recognized/programmed parameters
associated with a PW (the programmed header format, payload format, PW-ID value, etc.). If a PW packet is
received by an S132, but the packet format or PW-ID of the packet does not equal that of a programmed Bundle,
then the packet is not recognized. The term “BID” equates to a “recognized/programmed PW-ID” (part of a Bundle).
The term “Connection” emphasizes the type of data carried by a packet (e.g. timing) and emphasizes where the
data is forwarded inside the S132 (e.g. to a Clock Recovery Engine). The S132 Bundle Connection types include
SAT/CES Payload, HDLC Payload, SAT/CES PW-Timing and CPU. SAT, CES and HDLC Payload Connections
are used to forward the data between a TDM Port and the payload of a TDMoP PW. A SAT or CES PW-Timing
Connection is used to forward the timing information between a TDM Port and the TDMoP PW. A CPU Connection
is used to forward packets between the CPU and the Ethernet Port. CPU packets can be PW packets or non-PW
packets. A “connection” is commonly “established” by enabling an internal S132 function. For example enabling the
Clock Recovery Engine for a particular Bundle “establishes” a PW-Timing Connection for that Bundle.
The term “Bundle” can be thought of as a “small set of connections and parameters”. The packets for a Bundle can
contain data/information for multiple connections, e.g. the packet for a SAT Bundle can contain data/information for
a SAT Payload Connection and a SAT PW-Timing Connection.
The S132 supports a number of CPU packet types that are not Bundle/PWs. The term “CPU Connection” indicates
that the data stream carries data that is forwarded to the CPU. The S132 supports specialized header field values
and conditions that identify CPU Connections (e.g. the MEF OAM header).
The terms “OAM Bundle” and “OAM BID” are similar in meaning to “Bundle” and “BID” except that they are only
used for CPU Connections. The S132 supports up to 32 “OAM Bundles” that are programmed independent of the
256 Bundles. “OAM Bundles” are used to support Out-band VCCV (also known as UDP-specific OAM).
The term “Packet”, when used in combination with one of the Connection/data types emphasizes that the packet
contains data/information for a particular type of connection (e.g. CES, SAT, HDLC, PW-Timing and/or CPU
Packet). The terms “packet” and “frame” are loosely used interchangeably to identify a “datagram/unit” of data that
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DS34S132 DATA SHEET
is carried inside an encapsulation protocol. The term “frame” is also used to mean a “125 us TDM time period” but
then can be understood to use this meaning from the TDM context of the surrounding text.
The term “HDLC” is used to mean “HDLC-encoded data that is processed by the S132 for a TDM Port that is
translated to/from an HDLC PW packet stream”. The terms “CES Payload” and “SAT Payload” are used to mean
“data that is processed as constant bit rate data (e.g. PCM) without HDLC encoding and translated into the payload
of a TDMoP PW”. In the case of “CES Payload”, CAS Signaling may also be included through CAS timing rules.
“TDM”, by itself, is used to mean any of these 3 data types (CES, SAT or HDLC; “coming from a TDM Port”).
”PW-Timing” is used to mean “the timing of a TDM Port that is communicated in a PW” and is only associated with
a SAT/CES Bundles. The terms “Clock Recovery” and “RTP Timestamps” are “PW-Timing” functions.
Figure 9-1 provides a high level view of the basic functional areas within the S132 device.
Figure 9-1. S132 Block Diagram
DDR
SDRAM
CPU
Reference Clocks
CLAD
SAT/CES/HDLC
Connection
TXP Pkt
Generator
HDLC
Engines
HDLC
Connection
TXP RTP T-stamp
Buffer
SAT/CES
Engines
TXP RTP
T-Stamp Gen
Manager
SAT/CES/HDLC
Connection
SAT/CES
Connection
RXP Pkt
Classifier
TXP RTP
T-stamp
Rcv TDM Timing
Xmt TDM Timing
RXP Clock
Recovery Engines
RXP Clock Recovery Timing Connection
S132
The term “RXP” is used to denote “data that is received at the Ethernet port and forwarded to a transmit TDM Port,
the CPU or an RXP Clock Recovery Engine. “TXP” is used to denote “data received from a TDM Port or the CPU
that is transmitted at the transmit Ethernet port”. The RXP and TXP directions are depicted in the simplified diagram
in Figure 9-2. Bold lines are used to depict the “payload” connection paths (SAT/CES and HDLC). Thin lines depict
the PW-Timing and CPU connection paths.
Figure 9-2. RXP/TXP Data Path Directions
S132
TXP RTP T-stamp Gen
TXP
TXP SAT/CES Engines
TXP HDLC Engines
TXP
TSA
Clock Recovery Engines
RXP SAT/CES Engines
RXP
TSA
RXP
RXP HDLC Engines
CPU
The term “Port” is used with two meanings. The UDP standard uses “Port” to mean “virtual port” (e.g. UDP Source
Port ID). Otherwise the term “Port” is used to mean an electrical S132 port with external pins (e.g. TDM Port).
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9.1 Connection Types
The following subsections describe the different connection types in more detail.
9.1.1 SAT/CES Payload Connections
The S132 can support up to 256 SAT/CES Payload Connections spread across 32 TDM Ports. Each SAT/CES
Payload Connection carries constant bit rate data and is programmed as part of a Bundle. In the RXP direction, the
Classifier identifies a packet for a SAT/CES Payload Connection when the received Header and PW-ID match that
of a Bundle and that Bundle is programmed to forward payload data to a SAT/CES Engine. The SAT/CES Payload
Connection is diagramed in Figure 9-3.
Figure 9-3. SAT/CES Payload Connection
S132
TXP
TSA
TXP Bundle
Buffer
TXP Pkt
Generator
SAT/
CES
Engine
RXP
TSA
RXP Bundle
Jitter Buffer
RXP Pkt
Classifier
Each Bundle can be configured to support any number of DS0s up to an entire TDM Port line rate. In the RXP
direction the PW Header is stripped off of the packets and the payload is stored in a Jitter Buffer to smooth the
bursty transmission of the PSN. In the TXP direction, when sufficient SAT/CES Payload has been received the
S132 appends a configured TXP Bundle Header to generate a PW packet. A Timeslot Assignment block provides a
DS0 cross-connect function to interconnect the payload of any SAT/CES Bundle to any set of DS0 positions on a
single TDM Port and to allow control and monitoring of Sub-channel CAS Signaling and Data Conditioning.
A Bundle that includes a SAT/CES Payload Connection can also include a PW-Timing Connection and an In-band
VCCV (CPU) Connection (the PW-Timing and CPU Connections are described in the sections that follow).
9.1.2 HDLC Connections
The S132 supports up to 256 HDLC Connections. This connection type can be used to support T1/E1 CCS
Signaling or other HDLC encoded packet streams. Each HDLC Connection is programmed as part of a Bundle. In
the RXP direction, the Classifier identifies a packet for an HDLC Connection when the header and PW-ID of a
received packet matches the Header protocol and BID of a Bundle and that Bundle is programmed to forward data
to an HDLC Engine. The HDLC Connection is diagramed in Figure 9-4.
Figure 9-4. Bundle HDLC Connection
S132
TXP Bundle
TXP
TSA
TXP Pkt
Generator
Buffer
HDLC
Engine
RXP Bundle
(Jitter) Buffer
RXP Pkt
Classifier
RXP
TSA
At the TDM Port the HDLC data appears as constant bit rate data because the HDLC packet stream, at the TDM
Port, is supplemented with Idle HDLC Flags (Idle Flags are used during time periods when there are no HDLC
packets). On the Ethernet/PW side the HDLC encoding does not exist. The HDLC data no longer appears as
constant bit rate data since the HDLC Idle Flags are not carried by the HDLC PWs (only non-idle packet data is
carried by an HDLC PW).
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Each HDLC Bundle can be configured to support any number of DS0s up to the entire TDM Port line rate. In the
RXP direction the PW Header is stripped off and a Buffer is used to store the complete packet so that the packet’s
Ethernet FCS can be verified before transmitting the payload data at the TDM Port. In the TXP direction the HDLC
encoding is stripped off. When a complete HDLC frame has been received and the HDLC FCS has been verified,
the S132 appends a programmed TXP Bundle Header and generates a PW packet. A Timeslot Assignment block
provides a DS0 cross-connect function to interconnect the payload of any HDLC Bundle to any set of DS0 positions
on a single TDM Port.
9.1.3 SAT/CES PW-Timing Connections
SAT/CES TDMoP PW packets intrinsically always carry timing information by the constant periodic transmission
rate of the PW packets. The Adaptive Clock Recovery (ACR) technique takes advantage of this fact and does not
require that a TDMoP PW packet include a Timestamp header field. The Differential Clock Recovery (DCR)
Technique does not directly utilize the periodic transmission rate, but instead utilizes RTP Timestamps to indicate
the time differences between each successive PW packet. Every TDMoP PW packet includes ACR timing
information and can optionally include Timestamps.
When more than one TDMoP PWs are associated with a single TDM Port and the timing for that TDM Port uses
clock recovered timing, only one Bundle/PW can be programmed to include a PW-Timing Connection (to supply the
timing) and the frequency (data rate) for all of the other Bundle/PW streams assigned to that TDM Port must be
identical (synchronized). Otherwise the data, at the transmit TDM Port, for a non-synchronous PW would be
corrupted (the TDM Port can only transmit at one line rate). When timing information is included in PW packets, but
the Bundle does not include a PW-Timing Connection, the timing information is ignored by the S132.
The DS34S132 internal PW-Timing Connections are used by the RXP Clock Recovery Engines and the TXP RTP
Timestamp Generator. PW-Timing Connections can be set up in either direction or in both directions. The RXP and
TXP PW-Timing Connections are diagramed in Figure 9-5.
Figure 9-5. Bundle PW-Timing Connections
DS34S132
Rcv TDM Timing
Xmt TDM Timing
TXP Timing
RXP Timing
TXP Pkt
Generator
RTP Timestamp Generator
TXP SAT/CES Engine Timing
RXP Pkt
Classifier
Clock Recovery Engine
RXP SAT/CES Engine Timing
The S132 supports up to 32 RXP Clock Recovery PW-Timing Connections (one for each transmit TDM Port) and
up to 256 TXP, RTP Timestamp, PW-Timing Connections (one for each TXP Bundle). Each RXP PW-Timing
Connection is programmed as part of the RXP Bundle parameters. Each TXP PW-Timing Connection is enabled by
programming the TXP Header Descriptor to include an RTP Header.
In the RXP direction the Classifier identifies the packets for an RXP PW-Timing Connection when a received packet
matches the Header protocol and BID of a Bundle and that Bundle is programmed for “Clock Recovery”. The PW-
Timing information from the packet is forwarded to the appropriate Clock Recovery Engine which in turn is used to
drive the timing of a transmit TDM Port. The clock recovery timing information can be derived from the RXP packet
rate (ACR) or RTP Differential Timestamps (DCR-DT).
In the TXP direction, the PW timing information is derived from the receive TDM Port. A TXP packet is periodically
generated when the prescribed amount of SAT/CES Payload has been received from the TDM Port. The TXP PW-
Timing information is conveyed through the rate at which TXP packets are transmitted (ACR) but can also be
supplemented by inserting an optional TXP RTP Timestamp. The TXP PW-Timing Connection (when
included/enabled in a TXP Bundle) inserts the optional TXP RTP Timestamp. The TXP PW-Timing Connection is
not required if the far end clock recovery uses the ACR technique.
A Bundle that includes a PW-Timing Connection (RXP and/or TXP direction) can also include a SAT/CES Payload
Connection. If the Bundle does not include a SAT/CES Connection, the Bundle/PW is called a “Clock Only”
Bundle/PW. Clock Only packets do not include payload data, but instead only carry the timing information
(conveyed through the packet transmission rate and/or RTP Timestamps).
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The most generalized TDMoP PW application recovers TDM timing from a TDMoP PW packet stream. However,
for some applications the timing/rate of the TDMoP PW payload data is synchronized to a distributed, common
clock reference at both ends of the PW and clock recovery is not required (e.g. for synchronous T1/E1 data
streams). For these cases the Transmit TDM Port can use an external clock signal instead of a Clock Recovery
Engine (none of the Bundles associated with that TDM Port include an RXP PW-Timing Connection). This special
application (synchronous T1/E1 data streams) should not be confused with the DCR mode that uses a Common
Clock to drive a Clock Recovery Engine that recovers the timing of a T1/E1 data stream that may be asynchronous.
Only SAT/CES Bundle/PWs can include PW-Timing. HDLC and CPU packet streams (including those for OAM
Bundles) should not be used for PW-Timing since these packet types do not provide a constant bit rate.
9.1.4 CPU Connections
CPU Connections provide the CPU with the ability to send and receive Ethernet packets. CPU Connections can be
used for VCCV connections that are used to establish and monitor PWs, for Ethernet OAM (e.g. MEF OAM), for
specialized Ethernet protocols (e.g. ARP) and for detecting unexpected or invalid packet types. The different types
of CPU Connections that are supported are listed below. The CPU Connections are described in more detail in the
“CPU Packet Classification” and “TXP CPU Packet Generation” sections.
Debug “Normal” Bundle
OAM Bundle
CPU Destination Ethernet Type
MEF OAM Ethernet Type
In-band VCCV OAM
Too many MPLS Labels
Unknown Ethernet DA
Unknown PW-ID
Unknown UDP Protocol
Unknown IP Protocol
ARP with known IP DA
ARP with unknown IP DA
Unknown Ethernet Type
Unknown IP DA
Ethernet Broadcast DA
The CPU Connection is diagramed in Figure 9-6.
Figure 9-6. CPU Connections
S132
TXP OAM T-stamp Gen
TXP CPU Queue
TXP Pkt Generator
RXP Local T-stamp Gen
RXP CPU Queue
RXP Pkt Classifier
CPU
The S132 supports optional OAM Timestamps. The OAM Timestamps are independent of the RTP header
Timestamps (PW-Timing Connections). In the RXP direction the S132 records when each RXP CPU packet is
received and forwards an RXP Local Timestamp with each packet that is forwarded to the CPU. This RXP Local
Timestamp is always enabled for all CPU packet types (the CPU can ignore the RXP Local Timestamp if the
information is not relevant). In the TXP direction, the S132 can be programmed to add a TXP OAM Timestamp to
any outgoing CPU packet (e.g. for TDMoIP-VCCV-OAM header according to RFC5087 Appendix D).
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DS34S132 DATA SHEET
9.2 TDM Port Functions
The S132 includes 32 TDM Ports. Each TDM Port can be used to support a T1, E1 or any slower TDM data
stream. Each TDM Port uses a serial clock and data interface. The high level functions include:
•
•
•
•
•
•
•
Structured & Unstructured Formats
T1, E1 and slower TDM Port Line Rates
T1SF, T1ESF and E1 Multi-frame Formats
N x 64 Kb/s PW Packet Payload Rates
With & without CAS Signaling
•
•
CPU Control for Data Conditioning
TDM Port Timing
•
•
•
From Recovered or External Time References
Adaptive & Differential Clock Recovery
Generates Differential & Absolute Timestamps
DS0 Timeslot Assignment
CPU Monitor and Control of CAS Signaling
•
•
TDM Port, Timeslot and PW Loopbacks
BERT Diagnostics
9.2.1 TDM Port Related Input and Output Clocks
The TDM Port Input and Output Clocks are identified in Figure 9-7.
Figure 9-7. TDM Port Input and Output Clock Overview
LCS
DS34S132
LCE
Freq Select
FS[3:0]
1.544 MHz
Ck
Select
LIUCLK
2.048 MHz
High Quality
Reference
(e.g. OCXO)
synclk
EXTCLK0
EXTCLK1
REFCLK
CMNCLK
CLAD
Clock
Select
_ref_in
GRCSS
synclk
32
32
grclk
RCLKn
32 Clock
Recovery
Engines
TDM
Port n
(n = 1 - 32)
CLAD
TCLKOn
SCS
aclk_n
DCR
Common
Clock
The S132 Clock Recovery Engines support “Adaptive Clock Recovery” (ACR) and “Differential Clock Recovery”
(DCR). The ACR technique measures the timing of each successive RXP Packet to determine the recovered clock
frequency. The DCR technique uses RTP timestamps to determine the recovered clock frequency. Two external
clock recovery reference inputs (REFCLK and CMNCLK) are used to supply 1) a Frequency Synthesizer reference
input and 2) to provide a DCR common clock reference.
The Frequency Synthesizer reference input (synclk_ref_in) is required to generate an internal “synclk” signal. To
achieve the jitter/wander performance of ITU G.823/824/8261 the reference should be at least equal to that of a
Stratum 3 clock. The reference can be input on either REFCLK or CMNCLK (selected with G.CCR.SCS). For PSTN
and Cellular Mobile Phone applications, the BITS or GPS Network Timing commonly provide at least a Stratum 3
reference. For applications where a Network Timing reference is not available, then an OCXO may be used. Some
specialized TCXOs can also meet these stringent requirements. Otherwise, if the jitter/wander requirements can be
relaxed then the synclk reference input signal requirements can be equally relaxed.
To support the DCR mode, both ends of the PW must share a common clock reference that is derived from a single
timing source so that the frequency of the common clock reference at both ends of the PW are locked to each
other. The CMNCLK input is used to provide the DCR common clock reference.
In public network applications that use the DCR mode, the public network broadcast Network Timing, that provides
a Stratum 3 or better reference (e.g. BITS or GPS), can be used for the DCR common clock (CMNCLK) input and
the synclk reference input; and the REFCLK input can be tied low to save power.
In applications that use the DCR mode, but the DCR common clock reference is not a Stratum 3 reference (e.g.
private networks), the DCR common clock is connected to the CMNCLK input and a high quality reference (e.g.
OCXO) is connected to the REFCLK input.
In applications that do not use the DCR mode, only a high quality reference is required that can be connected to
CMNCLK or REFCLK and the unused input pin can be tied low to save power.
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In general, the DCR technique provides better clock recovery performance than the ACR technique (when
compared using an equal quality synclk reference input for both techniques).
For DCR applications the PW standards assume both ends of the PW use the same frequency for a DCR common
clock reference. The S132 however also allows the DCR common clock frequency to differ from one end to the
other (e.g. 2.5 MHz at one end and 25 MHz at the other), but with the requirement that the two are frequency
locked to the same source (e.g. BITS) and the S132 is programmed to compensate for the frequencies that are
used (Pn.PRCR4 and Pn.PRCR5).
To function well the DCR common clock (CMNCLK) frequency must be an integer multiple of 8 KHz and in the
range of 1 MHz to 25 MHz, but not close to the T1/E1 clock frequency (1.544 MHz or 2.048 MHz). The CMNCLK
frequency can be in the range from 8 KHz to 1 MHz, but with degraded MTIE (Maximum Time Interval Error)
performance. The following frequencies are recommended according to equipment type. The RTP Timestamp
coefficient registers (Pn.PRCR4 and Pn.PRCR5) must be set according to the CMNCLK frequency that is used.
SONET/SDH based equipment – 19.44 MHz
ATM network equipment – 9.72 MHz or 19.44 MHz
GPS based equipment – 8.184 MHz
Ethernet Equipment – 25 MHz
An internal CLAD generates the internal synclk signal from REFCLK or CMNCLK (selected with G.CCR.SCS). Any
of the input frequencies listed below can be used. The input frequency is selected using G.CCR.FS.
5.000 MHz
5.120 MHz
10.00 MHz
10.24 MHz
12.80 MHz
13.00 MHz
19.44 MHz
20.00 MHz
25.00 MHz
30.72 MHz
38.80 MHz
77.76 MHz
155.52 MHz
The S132 includes 32 Clock Recovery Engines that are each hardwired to one of the 32 TDM Ports. One of the 32
TDM Port recovered clocks (aclk_n; n = 0 to 31) can be assigned as a Global Clock Recovery reference (grclk)
using G.GCR.GRCSS. This allows the Clock Recovery Engine for one TDM Port to act as the “master timing” for
other “slave timed” TDM Ports.
An LIUCLK output is generated by the CLAD to provide an optional T1/E1 clock reference for external circuits. The
output is enabled with G.CCR.LCE and the frequency is set using G.CCR.LCS (1.544 MHz or 2.048 MHz).
In the TXP direction, the rate at which TXP Packets are transmitted is always directly related to the rate at which
data is received at the TDM Port. In the RXP direction, there are several methods that can be used to reconstruct
the transmit T1/E1 timing. The multiple timing sources provide the ability to support several different timing
applications and to provide primary and secondary (backup) timing.
In the RXP direction, the TCLKOn signal can derive its timing from RCLKn (the TDM Port receive clock input),
EXTCLK0, EXTCLK1, the internal aclk_n signal (the recovered clock from the Port “n” Clock Recovery Engine) or
the internal grclk signal (Global Recovered Clock that is selected by G.GCR.GRCSS). Only aclk_n and grclk derive
their timing from received RXP Packets. The selected timing source for a TDM Port must be equal to the payload
bit rate of each of the RXP Bundles assigned to that TDM Port. If the timing of the selected clock source differs
from one of its Bundles, then the internal RXP Jitter Buffer for that Bundle will overflow or underrun.
A TDM Port can be timed to an external T1/E1 reference that is input at EXTCLK0 or EXTCLK1 (e.g. for a Network
Timed T1/E1). If the synclk reference input (at REFCLK or CMNCLK) is from a Network Timing source (e.g. BITS 8
KHz), then the LIUCLK output can be tied to EXTCLK0 or EXTCLK1 to provide Network Timing to the TDM Port.
RCLKn can be used as the TCLKOn timing source in applications where the TDM Port must use “Loop Timing”.
“Loop Timing” can be used when the TXP data stream at any node within the network returns the TXP data back in
the RXP direction (loopback). Or it can be used in applications where the local transmit T1/E1 line rate is required
to use the local receive T1/E1 line rate (e.g. RCLKn provides Network Timing).
9.2.1.1 PW-Timing
The TDMoP PW standards define two PW Timing techniques: “Adaptive Clock Recovery” (ACR) and “Differential
Clock Recovery using Differential Timestamps” (DCR-DT). A third technique, using “Absolute Timestamps” (AT), is
supported by some companies, but is not prescribed by the TDMoP standards. The S132 is compatible with each
of these PW-Timing techniques.
The ACR technique uses the (intrinsic) packet transmission rate to convey the PW-Timing (e.g. 1 packet received
every 1 ms). The DCR technique uses RTP Timestamps to convey the PW-Timing information from the originating
side. Differential RTP Timestamps (DCR-DT) provide a means to monitor the time period between successive
packets using time units that are equalized at both ends of the PW through the use of a common clock reference
signal (e.g. Timestamp = 125 might equate to 125 us). The “Absolute RTP Timestamp” (AT) indicates the amount
of data that has been received at the TDM Port (e.g. 1000 bits) making the Absolute Timestamp an integer multiple
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DS34S132 DATA SHEET
of the Sequence Number. Both Timestamp types provide a measure of time, one referenced to a common clock,
the other referenced to the receive TDM Port line rate.
In the TXP direction the S132 supports all 3 techniques. The ACR technique is implicit in the packet transmit rate.
The DCR-DT and AT techniques are supported by transmitting Differential or Absolute Timestamps (respectively).
In the RXP direction the S132 directly supports the ACR and DCR-DT techniques. With the ACR technique the
Clock Recovery Engine recovers timing from the rate at which packets are received. With DCR-DT the Clock
Recovery Engine recovers timing from the received RTP Differential Timestamps.
In the RXP direction the S132 is compatible with (supports) the AT technique, but does not utilize the RTP Absolute
Timestamps. To provide compatibility with the AT technique the Clock Recovery Engine instead recovers timing
using the ACR technique (derived from the rate at which packets are received).
9.2.1.1.1 RXP Clock Recovery (RXP PW-Timing)
There are 32 RXP Clock Recovery Engines, one hardwired to each of the 32 TDM Ports. Each can be programmed
to support the ACR or DCR-DT technique.
Figure 9-8. Clock Recovery Engine Environment
DS34S132
Clock Recovery Engines
TDM
Xmt Port
RXP Pkt
Classifier
Xmt TDM Timing
RXP Timing
RXP SAT/CES Engine Timing
When a Transmit TDM Port is programmed to derive its timing from a Clock Recovery Engine, one TDMoP
PW/Bundle must be programmed to include an RXP PW-Timing Connection (B.BCDR4.PCRE). No more than one
PW/Bundle can be assigned to provide the RXP PW-Timing Connection for a TDM Port.
The RXP Clock Recovery technique (ACR or DCR-DT) is selected by properly programming the S132 Clock
Recovery Engine DSP firmware revision (not included in this Datasheet).
9.2.1.1.2 TXP PW-Timing
In the TXP direction the TDMoP PWs communicate timing information through the transmission rate of the TXP
Packets (ACR) and can optionally include an RTP Timestamp with each TXP Packet. TXP Packets are
automatically transmitted when sufficient T1/E1 data has been received to fill the TXP Packet payload. A TXP PW-
Timing Connection is only required if a TXP RTP Timestamp is included in the TXP packets.
The S132 appends a header to the payload of each TXP TDMoP Packet as it is transmitted. The header is
programmed using a TXP Header Descriptor that is stored in a block of memory at EMI.BMCR1.TXHSO (1 TXP
Header Descriptor per Bundle). A TXP PW-Timing Connection is enabled when the TXP Header Descriptor for a
Bundle is programmed to insert a TXP RTP Timestamp (TXRE field = 1; see “TXP SAT/CES and HDLC PW Packet
Generation” section). Any number of TXP Bundles can be programmed to include an RTP Header.
Figure 9-9. TXP PW-Timing Environment
DS34S132
RTP Timestamp Generator
TDM
Rcv Port
TXP Pkt
Generator
Rcv TDM Timing
TXP Timing
TXP SAT/CES Engine Timing
In the TXP direction, to conform to the Clock Recovery technique that is used at the far end PW end point, the
S132 allows the RTP Header to be optionally enabled with a Differential Timestamp or Absolute Timestamp,
independent of the RXP RTP settings. Pn.PRCR4.TSGMS selects whether Differential or Absolute Timestamps are
inserted when the RTP Header has been enabled in the TXP Header Descriptor.
RTP Differential Timestamp values are generated using the CMNCLK input and 3 coefficients that are programmed
in the Pn.PRCR4.TSGMC, Pn.PRCR5.TSGN1C and Pn.PRCR5.TSGN0C registers (programmed per TDM Port).
When the RTP Absolute Timestamp is enabled, the Absolute Timestamp values are incremented according to the
receive TDM Port timing (Pn.PRCR2.RSS selects the receive TDM Port timing as either RCLKn or TCLKOn).
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9.2.1.2 TDM Port - One Clock and Two Clock Modes
Each TDM Port can be independently programmed to support “One Clock” or “Two Clock” operation. In the “One
Clock” mode, the transmit and receive directions are both timed relative to either TCLKOn for TDM Ports that have
line rates that are synchronized to a local system clock (System Timed) or relative to RCLKn for TDM Ports that are
programmed to be “Loop Timed”.
In the “Two Clock” mode RCLK is used to time receive data and TCLKO is used to time transmit data allowing the
line rates and/or clock phases of the TXP and RXP directions to be different. This supports the most generalized
case for asynchronous transmit and receive timing. Table 9-1 identifies how to select between these modes.
Table 9-1. One-Clock and Two-Clock Mode settings
Mode
Pn.PTCR2.TSS
0
Pn.PRCR2.RSS
One Clock Mode using RCLK (Loop Timed)
One Clock Mode using TCLKO (System Timed)
Two Clock Mode (independent receive and transmit timing)
0
1
0
1, 2, 4 or 5
1, 2, 4 or 5
9.2.2 TDM Port Interface
Each TDM Port supports independent transmit and receive NRZ data, clock, sync pulse and signaling pins. Figure
9-10 provides a high level view of the interconnections to TDM Port “n”.
Figure 9-10. TDM Port #1 Environment
DS34S132
TDM Rcv
Port n
TXP
TSA
RDATn, RSIGn,
RSYNCn, RCLKn
EXTCLK0
EXTCLK1
RCLKn
RCLKn
T1/E1
LIU &
Framer
grclk
Global Clock Recovery Select
TCLKOn
TCLKOn
Port 31 Ck Recov Engine
aclk_n
Port n Clock
Recovery Engine
RXP
TSA
TDM Xmt
Port n
TDATn, TSIGn,
TSYNCn, TCLKOn
Port 0 Ck Recov Engine
When configured for Structured (CES), the RSYNCn/TSYNCn signals are used to identify the T1/E1 frame
synchronization, CAS and Timeslot positions. For Unstructured (SAT), the RSYNCn/TSYNCn signals are ignored
and the entire TDM Port bandwidth is transported in the TDM-over-Packet payload without regard to framing.
The TSYNC and RSYNC signals can be programmed to be input or output signals, although they are portrayed in
this diagram as unidirectional. Figure 9-11 provides a more detailed view of the TDM Port Interface.
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DS34S132 DATA SHEET
Figure 9-11. Logic Detail for a Single TDM Port Interface
EXTCLK0
S132
EXTCLK1
TCLKOn
TSS
aclk_n
(Port n Recov Ck)
TOES
TCE
TIOE
grclk
(Global Recov Ck)
TDATn
tdat_n
tsig_n
Q
Q
Q
Q
D
D
D
TSIGn
TDS
TSYNCn
tsync_n
Q
Q
TIES
TSRS
Q
Q
D
RIES
RSS
FFS MFS
RDATn
RSIGn
rdat_n
rsig_n
D
D
Q
Q
Q
Q
RDS
RSTS
rsync_n
D
Q
Q
RSYNCn
RCLKn
9.2.2.1 TDM Port Transmit Interface
The T1/E1 Transmit interface is controlled using the Pn.PTCR2 register to program the following functions:
TIOE:
TCE:
Enable/disable the TDATn, TSIGn and TSYNCn signals
Enable/disable TCLKOn
TSRS:
TDS:
Select the transmit framing to be synchronized to TSYNCn or RSYNCn
Select TSYNCn direction to be input or output
TOES:
TSS:
Select TDATn, TSIGn and TSYNCn timed to the positive or negative TCLKOn edge
Select TCLKOn clock source
DOSOT: Enable CAS Signaling to be overwritten in the CAS “robbed-bit” positions on TDAT
Table 9-2. TDM Port TCLKOn Clock Source Selection
TSS TCLKOn Clock Source Description
Notes
0
1
2
4
5
RCLKn
Loop timed
Received Clock from LIU/Framer for TDM Port n
Recovered clock from RXP PW packet stream
aclk_n
Port n Recovered Clock
grclk
Global Recovered Clock Selects 1 of 32 aclk_n using G.GCR.GRCSS
EXTCLK[1]
EXTCLK[0]
2nd External Clock Input
1st External Clock Input
E.g. 2.048 MHz reference (or 1.544 MHz)
E.g. 1.544 MHz reference (or 2.048 MHz)
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9.2.2.2 TDM Port Receive Interface
The T1/E1 Receive interface is controlled using the Pn.PRCR1 and Pn.PRCR2 registers to program the following
functions (more of the PRCR1 functions are described in the sub-sections that follow):
RSTS:
RDS:
RIES:
RSS:
CS:
Select the receive framing to be synchronized to RSYNCn or internal transmit framing
Select RSYNCn direction to be input or output
Select RDATn, RSIGn and RSYNCn timed to the positive or negative RCLKn edge
Select clock source to be RCLKn or TCLKOn
Select RDAT or RSIG for TXP direction CAS Signaling interface
9.2.3 TDM Port Structure & Frame Formats
The TDM Ports support the Structured (with Framing) and Unstructured (without Framing) Formats. The Structured
Format is used by T1/E1 CES applications. The Unstructured Format is used by T1/E1 SAT and non-T1/E1 SAT
applications. The SAT/CES Format for each TDM Port is programmed using Pn.PTCR1.SFS and Pn.PRCR1.SFS.
The programmed SAT/CES Format for all RXP and TXP Bundles (B.BCDR4.RXBTS and B.BCDR3.TXBTS) must
be the same as the programmed SAT/CES Format for the TDM Port that they are assigned to.
The Structured Format (CES) is programmed to T1 or E1 Framing using Pn.PRCR1.FFS and Pn.PTCR1.FFS. The
Multi-frame formats that are supported in the Structured Format (CES) are: no multi-frame, T1 SF, T1 ESF and E1
(selected using Pn.PRCR1.MFS and Pn.PTCR1.MFS). For CES with MFS = “no multi-frame” the RSYNC/TSYNC
pulse period is ~125 us (“193 bits/frame” for T1 or “256 bits/frame” period for E1) and CAS is not supported. For the
remaining CES settings the RSYNC/TSYNC periods are based on a “12 x 193 bit”, “24 x 193 bit” or “16 x 256 bit”
period (for SF, ESF or E1 respectively) and CAS Signaling is included.
SFS and MFS should be set to be the same as that of the “local” external transceiver (e.g. T1/E1 Framer). The
MFS setting is a multi-frame setting to enable the CAS functions of the S132. The MFS setting may differ from the
external transceiver where the multi-frame format setting determines both the T1/E1 framing pattern and the CAS
Signaling format. For multi-frame, non-CAS applications the S132 MFS should be set for MFS = “no multi-frame”
(meaning no CAS multi-frame) and the external transceiver should be set to T1-SF, T1-ESF or E1. This will disable
the S132 CAS Signaling functions and the frame synchronization will only be used to frame align the Timeslots.
In most applications the T1/E1 format at both ends of a PW are the same (e.g. T1 SF to T1 SF). Some unusual T1
CAS applications may prefer to translate one T1 CAS format to the other (e.g. translate T1 SF CAS to T1 ESF
CAS). This function is a unidirectional S132 function that is implemented in the TXP direction using the TXP Bundle
Payload Multi-frame Format setting (B.BCDR1.SCTXDFSE; the RXP direction does not support translation). The
SCTXDFSE setting should always match the T1 CAS Format of the far end T1 PW termination end point (this
setting is not used for E1 and T1 non-CAS applications). For T1 CAS applications the SCTXDFSE setting can differ
from the MFS settings to provide a T1 CAS Multi-frame Format translation (or be the same for no translation). An
example T1 ESF CAS to SF CAS Translation is depicted in Figure 9-12. More CAS translation information is
provided in the “TDM CAS to Packet CAS Translation” section.
Figure 9-12. T1 ESF CAS to SF CAS Translation Example
SCTXDFSE = SF
TXP
PTCR1.FFS & MFS = ESF
PRCR1.FFS & MFS = ESF
RXP
Direction
Direction
TDM
Xmt
Port
TDM
Rcv
Port
RXP
Bundle
TXP
Bundle
T1
ESF
T1
SF
S132
S132
PSN
TDM
Rcv
Port
TDM
Xmt
Port
TXP
Bundle
RXP
Bundle
TXP
RXP
Direction
Direction
PRCR1.FFS & MFS = ESF
SCTXDFSE = SF
PTCR1.FFS & MFS = ESF
Internally, the data for SAT/CES Bundles is processed using data that is stored in short term, Staging Buffers. The
buffers are filled and then forwarded. Each Staging Buffer is divided into fragments (blocks) of data. One Fragment
stores the SAT/CES data for a 125 us period (TDAT or RDAT data). Pn.PRCR1.BPF and Pn.PTCR1.BPF specify
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the Fragment byte depth (e.g. 24 bytes for T1). Pn.PRCR1.BFD and Pn.PTCR1.BFD specify how many Fragments
are used by each Staging Buffer (4 Fragments will store data for a 4 x 125 us = 500 us period).
BPF should be set to the number of bytes exchanged on the TDAT/RDAT interface in a 125 us period (e.g. for T1:
17 hex for “24 bytes”; for E1: 1F hex for “32 bytes”). For applications where TDAT and RDAT are used to support a
slower, non-T1/E1 interface, the BPF can be set to any integer value to represent the TDM Port data rate (data
received in a 125 us period; e.g. BPF = 1 for 64 Kb/s).
The BFD setting enables a compromise between the processing latency and the total number of Bundles supported
by an S132. Smaller BFD settings enable a smaller processing latency (smaller wait period to fill the Staging
Buffer), but with a smaller maximum number of Bundles. To function properly, the BFD value must also be set so
that the data stored in the Staging Buffer cannot exceed the smallest Bundle payload size associated with that TDM
Port (i.e. the number of bytes represented by BPF * BFD must be ≤ the number of bytes represented by
B.BCDR1.PMS for all Bundles assigned to that TDM Port). Table 9-3 describes the BFD settings.
Table 9-3. TDM Port BFD Settings
BFD value Staging Buffer Depth
Staging Buffer Latency
Maximum # of Bundles
0
1
2
3
TDM Port data path disabled
-
-
1 Fragment
2 Fragment
4 Fragment
125 us
250 us
500 us
64
128
256
For CES applications, the BFD and PMS settings can be directly compared since both are essentially specified in
frames (BFD ≤ PMS; for CES applications the number of bytes stored by the Staging Buffer Fragment is equal to
the number of bytes in one CES Frame, or 1 Fragment = 1 Frame). As an example, if PMS = 3 (3 frames per
packet payload), then BFD should be set to 10b or 01b (1 or 2 fragments). For SAT applications the PMS setting is
specified in bytes (instead of frames) and the TXP/RXP Bundle packets are programmed to carry a payload size
that is not related to a frame size (“frames” are not applicable to the SAT/Unstructured application). For SAT
applications the following “BFD to PMS” comparison can be used:
BFD (in Fragments) x BPF (in bytes per Fragment) ≤ PMS (in bytes)
In SAT applications, the S132 supports T1/E1 line rates and slower, non-T1/E1 rates. For all SAT applications, the
Pn.PRCR1.SPL register be programmed to indicate how many bytes are included in each RXP/TXP Bundle
payload. The TDM Port SPL value should be set to the same value as the Bundle PMS.
For SAT (Unstructured), non-T1/E1 applications (e.g. V.35), the TDM Port should use a line rate that is
approximately equal to an integer multiple of 64 Kb/s. This might be referred to as an “Unstructured Nx64” signal. In
this document it is called a “non-T1/E1” signal. Unstructured (SAT) signals usually are asynchronous signals. The
term “Nx64” can also refer to a “Structured Nx64” signal that is synchronized to the public network and can be
carried by a T1/E1 for transporting and switching in the public network (e.g. “Fractional T1/E1” and ISDN signals). A
“Structured Nx64” signal is carried by a CES PW (the S132 only supports “Structured Nx64” with T1/E1 line rate
TDM Ports).
For the best latency performance, each TDM Port BFD should be set to the lowest possible value allowed for the
maximum number of Bundles that will be supported by the S132. With a selected BFD value, all Bundle PMS
values associated with that TDM Port cannot be smaller than BFD. As an example, if it is necessary to support a
Bundle with a PMS = 1 (1 frame per packet or one packet every 125 us) then no more than 64 Bundles can be
supported by the S132 (the standards only require a maximum packet rate of one packet every 1 ms).
9.2.4 Timeslot Assignment Block
For T1/E1 applications, the S132 includes a Timeslot Assignment Block with the ability to monitor outgoing CAS
and control outgoing SW CAS Conditioning, Data Conditioning, and Loopback functions (depicted in Figure 9-13).
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DS34S132 DATA SHEET
Figure 9-13. TSA Block Environment
DS34S132
TXP Cond TXP SW TXP CAS
TXP HDLC Engines
Data
CAS
Monitor
Rcv TDM
Port
TXP SAT/CES Engines
TXP TSA
RXP TSA
TDM Port Line &
Timeslot Loopbacks
Bundle Loopback
Xmt TDM
Port
RXP HDLC Engines
Xmt CAS Xmt SW
Monitor CAS
Xmt Cond
Data
RXP SAT/CES Engines
One Timeslot Assigner circuit is provided for each TDM Port and in each direction so that any combination of
timeslots from a TDM Port can be assigned to a Bundle. The ordering of the data within a packet always follows the
“chronological” order on the T1/E1 line. For example if Timeslots 0, 7, 13 and 17 are assigned to Bundle A, the data
in the packet payload section will be 0, 7, 13, 17, 0, 7, 13, 17 and so on. The timeslot order cannot be programmed
to provide an ordering like 7, 0, 17, 13.
For Structured TDM data streams, the association between a Bundle to its TDM Port number and T1/E1 Timeslot
positions is programmed using B.BCDR4.PNS, B.BCDR2.ATSS and TSAn.m. To function properly, every Bundle
must be assigned at least one TDM Port Timeslot and each TDM Port Timeslot cannot be assigned to more than
one Bundle. Timeslots can be ignored by not assigning them to Bundles.
Unstructured TDM data streams do not provide a means to byte-align to the data stream. The Timeslots are viewed
by the S132 as 8–bit time periods that are not synchronized to a framing pattern, but timed to a 125 us time period.
Unstructured Bundles use the entire TDM Port bandwidth. The first Timeslot (TS0) of the TDM Port must be
assigned to the Unstructured Bundle using the B.BCDR4.PNS, B.BCDR2.ATSS and TSAn.m registers. The first
Timeslot is the only Timeslot that is assigned to that Bundle and no other Timeslots on that TDM Port should be
assigned/enabled. Although the T1 line rate includes a non-integer number of bytes within a 125 us period (193
bits), there are no register settings to include/assign the 193rd bit. An Unstructured TDM Port that is programmed
with Pn.PTCR1.BPF = Pn.PRCR1.BPF = 0x17 can support both 192 and 193 bits per 125 us time period.
Although the packets for Clock Only Bundles do not include packet payload (no Timeslot data), the S132 requires
that Clock Only Bundles must also be assigned a fraction/portion of the TDM Port bandwidth (assigned 1 or more
Timeslots). Assigning one Timeslot to a Clock Only Bundle allocates enough processing time (from the TDM Port)
for the S132 to perform the Clock Only Bundle functions. A Timeslot that is assigned to a Clock Only Bundle cannot
be assigned to any other Bundle even though the payload data is not used (the Timeslot processing time period
can only be used by one Bundle). For E1-CES Timeslot 0 can be used for a Clock Only Bundle since the Framing
Timeslot is not normally carried in the PW packets. For T1-CES, T1-SAT and E1-SAT, two TDM Ports (out of the
32 TDM Ports) can be connected in “parallel” so that one TDM Port is used for the Clock Only Bundles and the
other TDM Port is used for the Bundle with payload data. The use of Clock Only Bundles is optional to provide a
technique to reduce the packet latency through the use of smaller packets with high priority scheduling.
The outgoing CAS codes can be monitored in both directions. The Xmt CAS codes (RXP direction) can be read
using Pn.PRSR1 – Pn.PRSR4. The TXP CAS codes can be read using Pn.PTSR1 – Pn.PTSR4. The receive TDM
Port CAS codes can be sourced from RSIG or RDAT (Pn.PRCR1.CS). The CAS codes can be monitored by polling
the Monitor registers (PRSRx and PTSRx) or by using an interrupt hierarchy that reports when a CAS change has
been detected (G.GSR2 and G.GSR3). The interrupt method is also described in the “Interrupt Hierarchy” section.
In the RXP direction, when CAS Signaling is enabled on a Bundle (B.BCDR4.RXBTS = 2), the CAS codes received
from RXP packets are forwarded to the TDM Port and transmitted in the proper Timeslot CAS code positions.
When RXP CAS codes are received they are first stored in a Jitter Buffer along with the CES Bundle payload data
to smooth out the irregular (bursty) receive packet rate. If the RXP packet stream is blocked (e.g. for a fault), the
S132 will continue to send CAS codes until the Jitter Buffer is empty. When the Jitter Buffer empties, the S132 can
be programmed to continue sending the last stored CAS code or to send the programmed Xmt SW CAS
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(B.BCDR1.SCRXBCSS; Xmt SW CAS will only be sent when the Jitter Buffer is empty). These two functions are
programmed on a per-Bundle basis. The Xmt SW CAS codes are programmed using RXSCn.CR1 - RXSCn.CR4
(programmed on a per-Timeslot basis).
In the TXP direction, when CAS Signaling is enabled on a Bundle (B.BCDR3.TXBTS = 2), the S132 can be
programmed to “pass through” the incoming receive TDM Port CAS Signaling or to insert a programmed TXP SW
CAS code (B.BCDR1.SCTXBCSS). The forced TXP SW CAS codes can be used during fault conditions (e.g. “Loss
of Signal”) or to force a known CAS code for idle timeslots. These two functions are programmed on a per-Bundle
basis. The TXP SW CAS codes (transmitted at the Ethernet Port) are programmed using TXSCn.CR1 -
TXSCn.CR4 (programmed on a per-Timeslot basis).
The S132 provides the ability to force Xmt Conditioning Data in the outgoing data stream at the transmit TDM Port
(programmed on a per Bundle basis). For SAT/CES Bundles, RXP Payload that is received from the Ethernet Port
is stored in a Jitter Buffer and later transmitted at the TDM Port as data is needed. For CES Payload Connections,
if the Jitter Buffer runs out of data the S132 continues transmitting data at the TDM Port using either the “Last
Value” or using one of eight programmed Xmt Conditioning Data values (B.BCDR4.SCLVI). For SAT Payload
Bundles, the Unstructured format does not identify byte boundaries and the TDM Port should be programmed to
immediately transmit Data Conditioning (SCLVI = 0). For HDLC Bundles, when the S132 runs out of HDLC data,
the TDM Port transmits the selected Xmt Conditioning Data (e.g. HDLC Idle Flags). The eight Xmt Conditioning
Data values are programmed using G.TCCR1 and G.TCCR2. The Conditioning Data is independently selected for
each Bundle using the B.BCDR4.RXCOS register.
For SAT/CES Bundles, the S132 can force TXP Conditioning Data in the outgoing TXP Packets. This may used
during incoming T1/E1 fault conditions or to send a forced PCM value like “Idle”. TXP Conditioning Data can be
enabled on a per Bundle basis using one of eight programmed TXP Conditioning Data values. Eight TXP
Conditioning Data values can be programmed using G.ECCR1 and G.ECCR2. The Conditioning Data value is
independently selected for each Bundle using BCDR1.SCTXCOS and independently enabled using
BCDR1.SCTXCE. For HDLC Bundles, when the S132 runs out of received/stored HDLC packets the S132 stops
transmitting TXP packets (TXP Conditioning Data is not used for HDLC Bundles).
Special considerations:
For systems that require the legacy CAS “Freeze Signaling” function (TXP and RXP directions), the Framer that
interfaces to the S132 TDM Port should implement the “Freeze Signaling” function so that proper CAS codes are
forwarded during fault conditions. The legacy “Freeze Signaling” function includes a CAS code de-bounce function
that is not implemented in the S132 (new CAS codes are not forwarded until the CAS code is received 3 times).
For systems that need to dynamically insert the transmit TDM Port CAS codes (e.g. to continuously translate
incoming RXP CAS codes into different outgoing CAS codes) the “dynamic insertion” should be implemented in the
external T1/E1 Framer. The S132 CAS functions do not allow the CPU to both monitor the incoming CAS codes
from RXP packets and replace the received CAS codes with Xmt SW CAS codes (the S132 function monitors the
CAS output, not the input).
In the transmit TDM Port (RXP) direction, when a Timeslot and/or its CAS code is “unspecified” (e.g. for unassigned
Timeslots), the data that is transmitted toward the T1/E1 Framer uses default values. The G.TCCR1.TCOA register
value is transmitted for “Unspecified” Timeslot data. “Unspecified” Timeslot CAS positions are filled with the
RXSCn.CTSx register value (“x” is equal to the Timeslot number).
In the transmit TDM Port (RXP) direction, when CAS is enabled on a TDM Port, CAS data is inserted in all
Timeslots (24 for T1, 30 for E1) regardless of whether all Timeslots are intended to include CAS. For T1
applications that use CAS in some Timeslots and “no CAS” in other Timeslots, TSIG should be used to transmit the
CAS codes to the external Framer, the S132 “Overwrite TDAT with CAS” function should be disabled
(Pn.PTCR2.DOSOT) and the external Framer should be programmed to insert the CAS codes (from TSIG) in the
appropriate Timeslots (the “Overwrite TDAT with CAS” function overwrites “with CAS” and “no CAS” Timeslots).
When the “CAS Change Interrupt” function for a TDM Port is enabled (G.GSR2 and G.GSR3), even non-CAS
Timeslots can generate an interrupt since all Timeslots are monitored. If the T1/E1 includes non-CAS Timeslots,
frequent interrupts may occur (once per multi-frame) because the data in the 8th bit position (CAS position) may be
constantly changing.
9.2.4.1 TDM CAS to Packet CAS Translation
When “pass through” CAS Signaling is enabled, the S132 translates the T1/E1 CAS timing at the TDM Port into PW
CAS Sub-channel signaling used by the Bundles. In the TXP and RXP directions the S132 stores and forwards 16
frames of received CAS Signaling for the E1 format and 24 frames of received CAS Signaling for the T1 SF and T1
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ESF formats. For the T1 SF format this means that two successive 2-bit CAS Codes from 2 consecutive SF frames
are stored.
For T1 ESF and E1, the 4-bit ABCD CAS-codes received at a T1/E1 Port are stored and forwarded unmodified.
When the T1 SF format is used the S132 “extends” the T1-SF, 2-bit AB CAS-codes into a 4-bit CAS field since the
PW Sub-channel CAS Signaling requires a 4-bit field (regardless of whether it is T1-ESF, T1-SF or E1). Two
dummy bits are appended to and removed from the T1-SF, AB CAS-code to fill the packet’s 4-bit CAS field.
Most applications will use the same T1/E1 framing on both ends of the PW (e.g. T1-ESF to T1-ESF). For T1
applications, the S132 can be programmed to provide a translation between the 2-bit SF CAS Codes and 4-bit ESF
CAS Codes. This is a unidirectional function that can be enabled in the TXP direction (see Figure 9-12, “ESF to SF
Translation Example”). When translating 4-bit, ESF, “ABCD” CAS into 2-bit, SF, “AB” CAS the “CD” bits are
discarded. When translating 2-bit, SF, “AB” CAS into 4-bit, ESF, “ABCD” CAS the S132 generates an ABCD code
by appending a programmed, 2-bit “CD” value to the received, 2-bit “AB” code (the “CD” insertion bits are
programmed using Pn.PRCR1.CBVSE and Pn.PRCR1.DBVSE).
Table 9-4 describes how to program each of the various translation functions and how the 4-bit fields are
interpreted when using RSIG and TSIG. The table should be read from left to right. The “TXP Direction”,
“SCTXDFSE & PRCR1.MFS Format” column identifies each programmed translation function (e.g. ESF to SF). For
example, for “ESF to SF”, Pn.PRCR1.FFS and Pn.PRCR1.MFS are programmed for ESF; B.BCDR1.SCTXDFSE is
programmed for SF; Pn.PTCR1.FFS and Pn.PTCR1.MFS are programmed for SF.
The RSIG column includes two sub-columns that provide an example of CAS data that might be received in frames
1 - 24. The “TXP Packet Out” columns indicate how the CAS codes received from the RSIG pin would be
transmitted in the TXP Packets. The “RXP Packet In” column is identical to the “TXP Packet Out” column to
represent the process on the opposite end of the PW (as though the TXP Out is connected to the RXP In). The
TSIG column indicates how the CAS code (received from the RXP Packet) would be transmitted on the TSIG pin.
The “Format” settings determine whether CAS is sent once every 12 T1 frames or once every 24 T1 frames.
SCTXDFSE specifies the RSIG frame rate. PRCR1.MFS specifies the “TXP Packet Out” frame rate. PTCR1.MFS
specifies the TSIG frame rate.
The protocols for the RSIG and TSIG pins always include a 4-bit field for the CAS Code (even for the SF format). In
the SF format only 2-bits of the 4-bit field are regarded as valid by the protocol. In the “RSIG” column, “XY” is used
to indicate that the values of the two “extra” bits are unknown. An external T1 SF Framer will ignore the last two
TSIG dummy bits. The “SF to SF”, “ESF to ESF” and “E1 to E1” translation functions are included in the table to
show how the CAS codes are handled for all combinations.
Table 9-4. CAS Translation using RSIG and TSIG
TXP Direction
TDM Port RSIG
RXP Direction
TDM Port TSIG
SCTXDFSE to
PRCR1.MFS
PTCR1.MFS
TXP Packet Out
RXP Packet In
Format
Frm 1-12
Frm 13-24
Frm 1-24
Frm 1-24
Frm 1-12
Frm 13-24
Format
SF
ESF to SF
SF to ESF
SF to SF
ESF to ESF
E1 to E1
A1B1C1D1
A1B1A1B1
A1B1A1B1
A1B1CD
A1B1A1B1 A1B1A1B1
A1B1CD
ESF
SF
A1B1X1Y1 A2B2X2Y2 A1B1CD
A1B1X1Y1 A2B2X2Y2 A1B1A2B2
A1B1A2B2
A1B1C1D1
A1B1C1D1
A1B1A1B1 A2B2A2B2
A1B1C1D1
ESF
E1
A1B1C1D1
A1B1C1D1
A1B1C1D1
A1B1C1D1
A1B1C1D1
Notes: The “X” and “Y” values mean ”any value”, these values doesn’t matter since these bit positions are ignored.”
Table 9-5 describes the same information for applications that use RDAT and TDAT instead of RSIG and TSIG. For
T1-SF, TDAT and RDAT only exchange a 2-bit CAS field for each 12- frame, SF multi-frame.
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DS34S132 DATA SHEET
Table 9-5. CAS Translation using RDAT and TDAT
TXP Direction
RXP Direction
TDM Port TDAT
SCTXDFSE to
PTCR1.MFS
TDM Port RDAT
TXP Packet Out
RXP Packet In
PRCR1.MFS
Format
Frm 1-12
Frm 13-24
Frm 1-12
Frm 1-12
Frm 1-12
Frm 13-24
Format
SF
ESF to SF
SF to ESF
SF to SF
A1B1C1D1
A1B1
A1B1A1B1
A1B1CD
A1B1A1B1
A1B1CD
A1B1
A1B1
ESF
SF
A2B2
A2B2
A1B1CD
A1B1
A1B1
A1B1A2B2
A1B1C1D1
A1B1C1D1
A1B1A2B2
A1B1C1D1
A1B1C1D1
A2B2
ESF to ESF
E1 to E1
ESF
E1
A1B1C1D1
A1B1C1D1
A1B1C1D1
A1B1C1D1
Special considerations:
Each system should be analyzed to determine whether the 2-bit to 4-bit translation function is appropriate. The
method of appending a fixed, programmed “CD” value in one direction (SF to ESF) and discarding the “CD” bits in
the other direction (ESF to SF) may not be valid.
In applications where T1-SF CAS Signaling is carried in RXP packets, because the S132 stores 24 frames of T1-
SF CAS Signaling, it is possible (during a loss of RXP packet condition) that a constantly alternating 2-bit CAS code
(A1B1 ≠ A2B2) is transmitted at the TDM Port if the last 2 received AB CAS-codes are 2 different values, the Jitter
Buffer underruns (e.g. RXP packet fault) and the CAS “Last Value” function is enabled (B.BCDR1.SCRXBCSS).
This can occur, for example, if the far end of the PW transmitted an On-hook to Off-hook CAS Code transition in the
last received RXP packet. If this condition occurs (A1B1 ≠ A2B2), the TDM Port transmitted CAS codes will alternate
between these two values every 12 frames. Each system should be evaluated to determine whether this condition
is acceptable (an external T1 Framer with CAS debounce function should filter out the alternating pattern).
The support of CAS Signaling in a system that allows the use of multiple Nx64 PWs with a single T1/E1 may
require the system to be compliant with the defect and alarm requirements of a Digital Cross-Connect. When a
T1/E1 is divided into multiple segment/paths, the segments are unable to use the T1/E1 framing as an indication of
the state of the connection. For example if 2 PWs are merged into a single T1/E1, a far end T1/E1 fault in the RXP
direction of PW #1 (e.g. LOS) cannot be directly communicated over the local, T1/E1 transmit port since that would
imply that PW #2 is experiencing the same fault (i.e. the local T1/E1 transmit Port cannot forward the T1/E1-AIS,
Alarm Indication Signal, for PW #1 without indicating the same for PW #2; some systems allow DS0-AIS). Each
system should be analyzed to determine whether Digital Cross-Connect defect and alarm conditioning is required.
If these functions are required, they should be implemented external to the S132 (e.g. in the T1/E1 Framer).
9.2.4.2 TSA Block Loopbacks
The TSA Timeslots can be programmed to loopback data using a Bundle Loopback, TDM Port Line Loopback or
TDM Port Timeslot Loopback (see Figure 9-13). Any number of Timeslots, Bundles and/or TDM Ports can be in
Loopback at the same time.
The Bundle Loopback sends packet payload data that has been received for an RXP Bundle back toward the
Ethernet Port in TXP packets for the same Bundle. When the Bundle Loopback is enabled (Pn.PTCR3.RXTXTSL),
the RXP packet payload data is processed as though it will be transmitted at a TDM Port. But when the payload
data reaches the TSA block the data is looped back in the TXP direction and processed as though the data was
received from the TDM port. To work properly all Timeslots associated with the Bundle should be programmed into
the Bundle Loopback state.
The TDM Port Line Loopback and TDM Port Timeslot Loopback send payload data from the receive TDM Port back
toward the transmit TDM Port without any packet processing functions. The TDM Port Timeslot Loopback
(Pn.PTCR3.PRPTTSL) allows loopback selection on a per-Timeslot basis while the TDM Port Line Loopback
(Pn.PTCR2.PRPTLL) provides a loopback of all Receive TDM Port Data.
9.2.5 TDM Port Data Processing Engines
A TDM Port is assigned to a Bundle using B.BCDR4.PNS. The format of the TDM Port data streams can be
Unstructured, Structured T1/E1 without CAS or Structured T1/E1 with CAS and are processed using 3 engine
types: HDLC, SAT/CES and Clock Recovery. The combination of B.BCDR1.PMT (Payload Engine Type),
B.BCDR3.TXBTS (TXP Bundle Structure), B.BCDR4.RXBTS (RXP Bundle Structure) and B.BCDR4.PCRE (Clock
Recovery Enable) select the payload format and engine type for each Bundle. Enabling a particular Engine Type for
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a Bundle is equivalent to enabling a “Connection” for that Engine (e.g. enabling SAT/CES Engine = enable
SAT/CES Connection). B.BCDR1.RXBDS further supplements these selections by providing the ability to instead
forward the packets for a Bundle to the CPU (for debug; CPU Debug RXP PW Bundle) or to discard the packet
payload for Clock Only Bundles (to reduce the S132 payload processing functions). The following types of Bundles
can be programmed using these registers. The “Register Definition” and the “Register Guide” sections provide
more information on how to set these registers for each Bundle type.
SAT
HDLC for Unstructured TDM Port
Structured Nx64 HDLC
Structured 56 Kb/s or 16 Kb/s HDLC
SAT Clock Only
CES Clock Only
Nx64 CES without CAS
Nx64 CES with CAS
The SAT and CES Bundles can include an RXP PW-Timing Connection by enabling B.BCDR4.PCRE and/or a TXP
PW-Timing Connection by including the RTP Timestamp in the TXP Header Descriptor for that Bundle (see the
“TXP SAT/CES and HDLC PW Packet Generation” section). The Clock Recovery functions are described in more
detail in the “PW-Timing” section.
All of the Bundle types can include support for In-band VCCV (In-band VCCV CPU Connection). When a packet is
received for a recognized Bundle, the received packet header matches the In-band VCCV Control Word
(PC.CR5.VOV and PC.CR5.VOM) and In-band VCCV has been enabled for that Bundle (B.BCDR4.RXCWE and
B.BCDR4.RXOICWE) the S132 forwards the In-band VCCV packet to the CPU or discards the packet according to
the PC.CR1.DPS7 setting (OAM Packet Discard switch; this switch also affects other OAM types).
In the TXP direction, Receive TDM Port data that is ready for transmission is buffered in one of two priority queues
so that the packets can be scheduled according to their importance when congestion occurs. TXP Packets that are
buffered in the higher priority queue are processed before TXP Packets in the lower priority queue. For example,
Bundles with PW-Timing Connections can be assigned to the higher priority queue. The TXP priority is selected for
each TXP Bundle using B.BCDR3.TXBPS.
9.2.5.1 HDLC Engine
The S132 includes 256 HDLC Engines, one each for up to 256 Bundles. Several HDLC Bundle types are supported
including Unstructured HDLC (full TDM Port bandwidth), Structured Nx64 Kb/s HDLC, Structured 56 Kb/s or
Structured 16 Kb/s. With HDLC Bundles the terms “Unstructured” and “Structured” refer to the format of the TDM
Port. These terms do not have any direct relevance to the packet format of an HDLC Bundle. A single Structured
TDM Port can support any combination of Structured HDLC Bundles and CES Bundles since each Bundle can be
assigned to independent Timeslots on a Structured TDM Port.
Figure 9-14. HDLC Engine Environment
DS34S132
TXP
TXP HDLC Engine
TSA
HDLC
Connection
Buffer
Manager
RXP
RXP HDLC Engine
TSA
An Unstructured HDLC Bundle uses the entire bandwidth of its assigned TDM Port. The HDLC coding/decoding is
performed using the entire data stream without regard for T1/E1 framing or Timeslot positions.
Structured HDLC Bundles can be programmed to use 2-bit, 7-bit or 8-bit HDLC coding (for 16 Kb/s, 56 Kb/s and
“Nx64 Kb/s” channels respectively; B.BCDR1.SCTXCOS). The bit-width setting identifies how many bits are used in
the assigned Timeslot. For 8-bit, all 8 bits of the timeslot are HDLC coded. For 7-bit coding, only the 7 MSbits are
HDLC coded (the LSbit is unused). For 2-bit coding, the two MSbits or two LSbits can be selected for HDLC coding
(the remaining 6-bits are unused). Unstructured HDLC Bundles always use 8-bit coding.
The “8-bit” format allows an HDLC Bundle to combine the data from multiple 8-bit Timeslots of a single Structured
T1/E1 to support bandwidths like 384 Kb/s (using six 8-bit Timeslots). Any number of 8-bit Timeslots can be
combined (up to 24 for Structured T1 or 31 for Structured E1).
Only one 2-bit or 7-bit HDLC coded Timeslot from a Structured T1/E1 can be assigned to an HDLC Bundle.
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Each HDLC Engine can be programmed to use MSbit or LSbit first transmission (BCDR1.SCSNRE). This function
does not specify which bits of the Timeslot are used (previous paragraphs), but instead specifies whether the MSbit
or LSbit of each HDLC coded byte is transmitted first (the byte order is always MSByte first). For example, if LSbit
transmission and 8-bit coding are selected, then the LSbit of each byte is transmitted first (in the “bit 8” position of
the Timeslot). If instead MSbit transmission and 8-bit coding are selected then the MSbit of each byte is transmitted
first (in “bit 8”). Most T1/E1 applications use MSbit first.
Each HDLC Bundle can be programmed to include a 16-bit, 32-bit or “no” FCS (B.BCDR1SCRXBCSS and
SCTXBCSS).
In the TXP direction the HDLC Engine receives data from a TDM Port and removes the HDLC encoding (HDLC
Flags and HDLC Control Characters). The de-encoded packet data is buffered until a complete packet has been
received. After the HDLC FCS has been verified to be correct, the packet is queued for transmission as the payload
of a TXP HDLC Bundle packet.
TXP HDLC Bundles can optionally include RTP and Control Word Headers (enabled using the TXP Header
Descriptor). For RTP and/or Control Word headers can use Sequence Numbers that are always “zero”, or are
constantly incremented by one with each successive packet (B.BCDR4.SCTXCE and B.BCDR1.SCTXDFSE).
When incremented Sequence Numbers are used the S132 can be programmed to skip or include the Sequence
Number = “zero” value when the Sequence Number reaches roll-over.
In the RXP direction, when the RXP Classifier identifies an error-free packet for an HDLC Bundle, the PW packet
header and FCS are removed and the PW packet payload is stored for later processing by the RXP HDLC Engine.
The HDLC Engine inserts a Flag (Packet Delimiter = 0x7E) in between each successive RXP Packet to identify the
start and stop of each packet. The G.GCR.RXHMFIS register specifies the minimum number of Flags that are
inserted in between 2 HDLC packets where RXHMFIS + 1 = minimum number of flags (e.g. RXHMFIS = 0 for 1
flag). When the HDLC Engine no longer has a packet to forward and the minimum number of flags have been
transmitted the HDLC engine inserts “Inter-frame Fill” into the outgoing HDLC data stream. The Inter-frame Fill
value can be programmed to 0x7E or 0xFF (B.BCDR4.SCLVI).
In the RXP direction the S132 does not provide re-ordering of mis-ordered HDLC packets, so the optional RTP
and/or Control Word Sequence Numbers received in packets for RXP HDLC Bundles are ignored.
The B.BCDR1.PMS register is used to define the largest Ethernet packet that is accepted for an RXP HDLC
Bundle. Packets with a size greater than PMS are discarded.
Special Considerations
The S132 does not provide special handling for CAS Signaling when a T1/E1 Port includes an RXP HDLC Bundle.
If CAS Signaling is enabled for the T1/E1 Port and if the “overwrite CAS on TDAT” is enabled, CAS values will be
written in Timeslot positions assigned to HDLC Bundles. To prevent this, the HDLC 7-bit Sampling format can be
used, or else TSIG can be used to provide the CAS values (disable the “Overwrite CAS on TDAT”). In the TXP
direction, the RSIG value and the SW TXP CAS functions are ignored by TXP HDLC Bundles.
9.2.5.1.1 SAT/CES Engine
The S132 includes 256 SAT/CES Engines, one for each of the 256 possible SAT/CES Bundles.
Figure 9-15. SAT/CES Engine Environment
DS34S132
TXP
TXP SAT/CES Engine
TSA
TDM
Connection
Buffer
Manager
RXP
RXP SAT/CES Engine
TSA
In the RXP direction, B.BCDR1.PMS specifies the expected packet payload size for each RXP Bundle (not
including the optional CAS bytes). For SAT applications, PMS specifies how many bytes; for CES applications, how
many frames. In the TXP direction, the PMS setting determines the amount of data that is included in the payload
of each TXP Bundle packet.
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For RXP Bundles, the S132 monitors the received Control Word L-bit field. If the RXP Bundle is programmed with
B.BCDR1.SCSCFPD = 1 (verify packet size) and the received L-bit = “0” (“PW payload is valid”), the S132 discards
the packet if the PW packet payload size does not match the PMS setting. If SCSCFPD = 1, the received L-bit = 1
(packet payload invalid) and B.BCDR1.LBCAI = 1 (conditioning for L-bit = 1) the PMS setting is ignored.
B.BCDR1.SCSNRE selects whether the packets for RXP SAT/CES Bundles are re-ordered when they are received
out of order. B.BCDR1.RSNS is used to specify whether the Sequence Number in the Control Word or RTP header
is used by this re-ordering function.
A packet is only accepted as a SAT/CES Bundle if the first 4 bits of the Control Word equal 0h. Packet payload
data for RXP SAT/CES Bundles is stored in a Jitter Buffer according to its Sequence Number. When a packet for a
Bundle is “missing” (Sequence Number not received) or the Jitter Buffer underruns, the S132 replaces the missing
data at the transmit TDM Port according to the B.BCDR4.SCLVI setting.
For CES Bundles when B.BCDR4.SCLVI is enabled, the S132 uses the last received byte (Last Value) for each
Timeslot of the Bundle to replace the missing data for up to 375 us. After 375 us, the Conditioning Data selected by
B.BCDR4.RXCOS is inserted. If SCLVI is disabled, the missing data is immediately replaced by Conditioning Data.
For SAT Bundles, the Unstructured format does not identify byte boundaries so the SCLVI function must be
disabled so that Conditioning Data is always used to replace SAT missing data.
9.2.5.2 TDM Port Priority
Each Port can be assigned as “high” or “low” priority, using Pn.PTCR1.DP (TXP direction) and Pn.PRCR1.EP (RXP
direction) so that the SAT/CES/HDLC Engines process some TDM Ports before others. In most applications all
TDM Ports should be assigned the same priority level.
9.2.5.3 Jitter Buffer Settings
The Jitter Buffer provides a means of transitioning TDM data between the PW and TDM domains (RXP direction).
There are 3 fundamental issues when reconstructing a TDM data stream from a stream of packetized data: data
content, delay and frequency. The S132 Jitter Buffer settings are complex so it is important to understand the
parameters that are affected by these settings.
For TDM services, all 3 issues are important. For example, if voice data is delivered error-free, but with 1 second of
delay, then the conversation can be confusing (each person does not know how long to wait to keep from talking
over the other person). A voice connection that adds more than 150 ms of delay is considered a poor connection,
although in unusual cases, up to 400 ms of delay may be accepted. As another example, for PCM voice switching
(e.g. PBX or Class 5 switch), if the reconstructed TDM data is error-free, but the TDM line frequency is not
synchronized to the voice switch, the TDM switching process will corrupt the data. A TDM voice connection is not
significantly affected by a small amount of data corruption, whereas a computer data connection, generally,
depends on almost error-free transmission to minimize the need for re-transmission. All 3 issues are important.
The S132 transmit TDM Port Jitter/Wander performance is affected by the clocking technique that is used. If an
external clock is used, then the S132 Jitter/Wander is primarily determined by the Jitter/Wander of the external
reference. If an internal Clock Recovery Engine is used, then the Jitter (high frequency variation) is determined
from an internal S132 frequency synthesizer that is designed to comply with the TDM Jitter requirements in all
Clock Recovery settings and conditions. The Wander (low frequency variation) is determined by how well the Clock
Recovery Engine can reconstruct the timing of the incoming packet stream. The performance of the Clock
Recovery Wander depends on the maximum excursion and nature of the packet stream PDV, and on the packet
transmission error rate (high packet loss may affect the performance). When it is possible, PWs that are used to
carry Clock Recovery information should be assigned a high priority on the originating PW end point to minimize
the PDV. B.BCDR3.TXBPS can be used to select S132 internal high priority TXP processing and the TXP VLAN
Header P-bits (programmed in the TXP Header Descriptor) can be used to indicate high priority to the network.
The S132 Jitter Buffer smoothes the irregular (bursty) RXP packet rate. The Jitter Buffer stores and then supplies
data as needed according to the transmit TDM Port timing. Because the TDM Port line rate is nearly constant (with
only small variations), the TDM Port cannot significantly slow down or speed up to compensate for too much or too
little stored data. To compensate for the irregular packet rate (burstiness), an infinite depth Jitter Buffer would
insure that data is never lost/discarded, but would also potentially store so much data that the forwarding delay is
too long (potentially making a conversation impossible). A very shallow Jitter Buffer would minimize the delay, but
may not store enough data to prevent a data under-run event (missing data is replaced with dummy data). Each
PW system must determine how to balance these conditions (discard, delay and under-run).
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The delay of data at the input of the Jitter Buffer is caused by fixed and PDV (variable) delay parameters according
to the equation below.
Maximum Jitter Buffer Input Delay = PCT + fixed transmission and circuit processing delay + Total PDV
PCT (Packet Creation Time) is a fixed delay that is equal to the amount of time that it takes to receive enough data
from a TDM Port to fill the Payload section of a PW Bundle. The B.BCDR1.PMS (Packet Payload Size) setting is
programmed according to the desired PCT value using the equations below. For example it may be desirable for a
CES payload to carry 8 frames of data (from the equations below, PCT = 1 ms and PMS = 8).
T1/E1 Nx64 CES: B.BCDR1.PMS = “# T1/E1 Frames per Packet Payload” = PCT ÷ 125us
T1 SAT:
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ 5.2us
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ 3.9us
B.BCDR1.PMS = “# bytes per Packet Payload” = PCT ÷ (8/fTDM
E1 SAT:
“Slow rate” SAT:
)
(where “fTDM” is equal to the data bit rate at the TDM Port).
The fixed transmission delay will differ for each PW connection according to the distance between the end points
(e.g. a signal may take 500 us to travel 100 km). The fixed circuit processing delay varies according to the type and
number of network nodes (e.g. routers) and the S132 fixed circuit delays. These fixed delays do not affect the Clock
Recovery performance or Jitter Buffer depth (unless they change, e.g. when switching to a backup/protection line).
PDV is caused when congestion occurs at a port that has more than one packet waiting to be transmitted and can
be caused by circuits that process data in “blocks” (delayed waiting to finish a block).
There are several PDV parameters that are identified in the equation below and described in Table 9-6.
Total PDV = Network PDV + S132 Ether Media PDV + S132 Schedule PDV + S132 BFD PDV + S132 MTIE PDV
Table 9-6. PDV Parameters that affect the latency of a PW packet
PDV Type
Description
Network
PDV:
Network PDV is generated by the packet switches between the two PW End Points. Each packet
switch becomes congested when more than one incoming switch port has a packet to send to the
same outgoing switch Port (one incoming packet must wait for the other). For example some
networks may assume that each packet switch might introduce up to 1 ms of PDV.
S132
S132 Ethernet Media PDV is generated when the Ethernet Port Line Rate (100 Mb/s or 1000 Mb/s)
delays the delivery of the packet because the line rate is unable to transmit infinitely fast. For
example if 32 packets that are 64 bytes in length, are waiting to be transmitted at the S132 Ethernet
Port, the last packet will not be transmitted until after the 31 other packets are transmitted. The
Ethernet Media PDV can be a large number. For this reason, the 1000 Mb/s line rate should be used
whenever possible to minimize this parameter. The Ethernet Media PDV is dependent on the
Ethernet line rate, the number of Bundles, the size of the Ethernet packets that are being transmitted
and includes the Ethernet 20-byte Inter-packet Gap (IPG). The equation below assumes all of the
Bundles use the same packet size. Table 9-7 provides 6 examples that use this equation.
Ethernet
Media
PDV:
S132 Ethernet Media PDV = [# Bundles * (# pkt bytes + 20 byte IPG) * 8 bits/byte] ÷ line rate
S132 RXP
& TXP
The S132 RXP and TXP Scheduling PDV values are caused by the limited rate at which data can be
transferred to/from the SDRAM. Similar to the Ethernet Media PDV, if 32 packets are ready (in the
Scheduling SDRAM) to be sent, the S132 Buffer Manager can only retrieve one packet at a time and the last
PDV:
packet is delayed waiting for the other 31 packets. This PDV parameter increases the Total PDV only
if the Ethernet Media is able to forward packets faster than the S132 Buffer Manager can retrieve the
packets from the SDRAM (i.e. the Scheduling PDV is “hidden” by the Ethernet Media PDV as long as
the Buffer Manager can keep up with the Ethernet Port transmission rate).
S132 RXP
The S132 RXP and TXP BFD PDV values are caused as the S132 waits for sufficient data to fill the
& TXP BFD SDRAM Staging Buffers. The depths of these buffers are programmed using the BFD registers to
PDV:
determine the data block size that is used to store and retrieve data from the SDRAM. This PDV
parameter can vary from 125 us to 500 us according to the BFD setting (one in each direction).
S132 RXP
The S132 MTIE PDV is generated by the varying output frequency of the Clock Recovery Engine.
MTIE PDV: Before the Clock Recovery Engine has locked to the incoming RXP packet rate, the transmit TDM
Port line rate can vary (slightly) adding to the Total PDV. After the Clock Recovery Engine is locked
to the RXP data rate, this parameter becomes insignificant. This parameter is difficult to characterize,
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but is generally not important to consider since its impact is only during the “start-up” of a TDM Line.
Table 9-7. Maximum S132 Ethernet Media PDV
Maximum Number
of Bundles
Packet Size for 100 Mb/s Interface
Packet Size for 1000 Mb/s Interface
64 Bytes
193 Bytes
0.663 ms
5.30 ms
1500 Bytes
64 Bytes
0.0215 ms
0.172 ms
193 Bytes
0.0663 ms
0.530 ms
1500 Bytes
0.389 ms
3.11 ms
32 Bundles
0.215 ms
1.73 ms
3.89 ms
31.1 ms
256 Bundles
As depicted in Table 9-7, the S132 Ethernet media interface (MII/GMII) can introduce a high PDV level with
systems that have a high number of Bundles when using the 100 Mb/s interface and a large packet size. Most
applications will want to minimize delay. The S132 Ethernet Media PDV parameter can be minimized by using
smaller packet sizes and the 1000 Mb/s Interface. A TXP Bundle that is used for Clock Recovery at the far PW End
Point should be programmed for S132 high priority TXP processing (B.BCDR3.TXBPS). If only one TXP Bundle
from each receive TDM port is programmed for high priority, then each high priority TXP Bundle will not be delayed
by more than 31 other Bundles (no more than one Bundle for each of the other enabled TDM Ports).
The following provides an example set of assumptions for a T1-SAT PW:
Ethernet Media PDV
Packet Payload size = 193 bytes (PCT = 1 ms)
MPLS Header size with 2 MPLS Labels, Control Word, RTP Headers and 4-byte Ethernet FCS = 46 bytes
Ethernet Media Type = 100 Mb/s
Maximum PW Bundles (not including OAM Bundles) = 32
Ethernet Media PDV = [# Bundles * (# bytes per pkt + 20 byte IPG) * 8 bits/byte] ÷ line rate
Ethernet Media PDV = [32 * (193 + 46 + 20) * 8b] ÷ 100 Mb/s = [32 * (259 * 8b)] ÷ 100 Mb/s = 660 us
Scheduling PDV
The scheduling PDV is assumed to be “hidden” by the Ethernet Media PDV and can be ignored.
BFD PDV
RXP & TXP BFD settings = 125 us (in each direction)
MTIE PDV
The startup MTIE is assumed to be insignificant except at startup.
Total PDV
Total PDV = Network PDV + Ethernet Media PDV + Scheduling PDV + TXP & RXP BFD PDV + MTIE PDV
Total PDV = Network PDV + 660 us + (125 us * 2) = Network PDV + 910 us
The S132 can support up to 500 ms of packet Jitter (PDV) for up to 256 Bundles (one Jitter Buffer is provided for
each Bundle). In most cases, however, the PDV of a network will be limited to a much smaller value like 10 ms. The
Jitter Buffers for all Bundles are located in a single block of memory that begins at the SDRAM address specified by
G.BMCR2.JBSO. The Jitter Buffer memory block is divided into equal sized Jitter Buffer FIFOs according to the
G.GCR.JBMD setting (one FIFO per Bundle; JBMD sets the depth for all Jitter Buffer FIFOs to 32 Kbyte, 64 Kbyte,
128 Kbyte or 256 Kbyte).
The Maximum PDV that each Jitter Buffer can support can be determined according to the equation below. The
“Register Guide”, “SDRAM” subsection includes a table (based on this equation) that describes the “Maximum
PDV” each Jitter Buffer can store for various combinations of PCT, JBMD and “maximum Timeslots in a Bundle”.
Max PDV in ms = Integer(([Roundup((JBMD in bytes) – 2048) ÷ ((PCT in ms / 0.125) + 4)) + 1] * PCT in ms) ÷ 2)
where the “Roundup” function provides the next higher integer value for non-integer numbers
In addition to the global Jitter Buffer settings (JBSO and JBMD) there are two Jitter Buffer settings for each Bundle
to program the Bundle’s Jitter Buffer Playout Watermark (B.BCDR5.PDVT) and Jitter Buffer Overrun Watermark
(B.BCDR5.MJBS).
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The PDVT setting specifies how much data must be stored by the Jitter Buffer before “play-out” (FIFO read) begins.
After “play-out” begins the Jitter Buffer will continue to supply data until the Jitter Buffer is empty. If the Jitter Buffer
empties, then the Jitter Buffer must again fill to the PDVT level before data will again be forwarded.
The MJBS watermark can be used to indicate when the level of stored data exceeds an “expected” maximum
(overrun) level. This can be used to monitor for “unexpected” fill levels (e.g. too much data accumulated because of
improperly configured input or output clocks or if the MJBS setting does not allow for the maximum PDV). MJBS
can be monitored to implement a discard process that prevents each Bundle’s Jitter Buffer from over-filling and
adding to the latency of the data (some Clock Recovery Engine firmware revisions may include a function to
discard Jitter Buffer data when MJBS indicates the Jitter Buffer has too much data). The MJBS register should be
programmed to a level that is lower than the JBMD level so that an MJBS Overrun condition can be detected before
JBMD discarding begins. Figure 9-16 depicts the relationship between the JBMD, MJBS and PDVT settings (the
blue area depicts data that is stored in the Jitter Buffer FIFO).
Figure 9-16. Bundle Jitter Buffer FIFO
Bundle Jitter Buffer FIFO
If the SAT/CES TDM Data exceeds the
JBMD level data, new data is discarded.
JBMD
If the SAT/CES TDM Data exceeds the
MJBS Watermark, a Jitter Buffer
Overrun event is counted
MJBS
This area is empty and
can store SAT/CES TDM
Data from RXP packets.
(B.BDSR2.JEBEC).
New SAT/CES packet data is stored here
SAT/CES TDM Data is not forwarded to
the TDM Line until the fill level exceeds
the PDVT Watermark.
PDVT
This area is filled with
SAT/CES TDM Data that
is waiting to be transmited
on the TDM line.
SAT/CES data is read out from here and sent to TDM Port
The purpose of the Jitter Buffer is to store data that can be transmitted during time periods when the S132 must
wait for a packet that has been “delayed”. At the receiving end of a PW, when a packet is received the PW end
point cannot know whether the PDV for that packet was “zero”, the maximum PDV value or any value in between.
If the receiving PW end point knew that the PDV for a received packet was zero, then the best situation would be to
begin storing data and not forward that data until a time period equal to the maximum PDV. Or, if the PW end point
instead knew that a packet was received with the maximum PDV, then the best situation would be to immediately
forward the data (data will never come later than the maximum PDV; storing would add unnecessary delay).
However the PW end point does not know the PDV level for each packet and thereby must make an assumption.
There are three approaches for setting the PDVT and MJBS values. Each system should be analyzed to determine
which approach is preferred. In each of these approaches the minimum Jitter Buffer delay is equal to the PDVT
setting, while the maximum Jitter Buffer delay (maximum fill level) is either equal to the MJBS or JBMD setting
(MJBS is the maximum if MJBS is monitored as a watermark for discarding; otherwise the maximum is JBMD).
The first approach assumes that it is important to never discard data. This approach results in “2 * Total PDV” ≤
“Jitter Buffer Delay” ≤ “MJBS or JBMD”. This may be the most commonly used setting for existing/installed TDM
over PW services. The settings for this approach are specified by the following equations:
PDVT1 (in ms) = 2 * Total PDV (in ms)
MJBS1 (in ms) = PCT (in ms) + 2 * Total PDV (in ms)
The PCT value is included as part of the MJBS setting to provide a watermark condition that is slightly higher than
the PDVT (playout) watermark and because the originating and terminating ends of the PW cannot be perfectly
phase synchronized together. When the PCT is included as part of the MJBS value, in most cases, the S132 fixed
circuit processing delays can be disregarded (included as part of the PCT value, e.g. BFD PDV).
The second approach assumes that delay must be minimized and only a small amount of discarding should be
allowed. This approach results in a temporary, maximum latency = “2 PDV + PCT”. But as the PDV varies from its
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minimum to its maximum value, a small number of packets are discarded and the latency is reduced to “PDV +
PCT”. You could say that this approach assumes the PDV = 0 for the first packet. The maximum number of packets
that will be discarded during the life of the connection will be the Integer value of (PDV ÷ PCT) + 1 (e.g. if PDV = 10
ms and PCT = 2 ms, then up to 6 packets may be discarded). The discard timing is not predictable since the
discarding only occurs when the PDV extremes are reached. The settings for this approach are specified by:
PDVT2 (in ms) = Total PDV (in ms)
MJBS2 (in ms) = PCT (in ms) + Total PDV (in ms)
The third approach also assumes that the delay and data errors must be minimized but also prevents the latency
from exceeding “PDV + PCT”. Instead of allowing for a small number of packet discards, this approach allows for a
small amount of dummy data insertion. The Jitter Buffer immediately forwards the first data is received, as though
the packet is assumed to be received with maximum PDV. Since this will not normally be the case, a Jitter Buffer
underrun will be expected. However, the amount of dummy data that is inserted (to stabilize the Jitter Buffer fill
level) is limited by the Total PDV value. For example if PDV = 10 ms and PCT = 2 ms, then ≤ 12 ms of dummy data
may be transmitted. The timing of the dummy data is not predictable since the insertion of dummy data depends on
when the PDV extremes are reached. The settings for this approach are specified by the following equations:
PDVT3 = 0x0001 (minimum setting > 0)
MJBS3 (in ms) = PCT (in ms) + Total PDV (in ms)
The PDVT and MJBS values are programmed using the equations below and should be rounded up to the nearest
integer setting. The units used by these registers vary according to the application:
PDVT setting units for T1/E1 CES: 125, 250 or 500 us (according to the Pn.PTCR1.BFD setting)
PDVT setting units for SAT: 32 ÷ “TDM Port bit rate” (e.g. the T1 SAT PDVT setting is in 20.7 us steps)
MJBS setting units for T1/E1 CES: 500 us
MJBS setting units for SAT: 1024 ÷ “TDM Port bit rate” (e.g. the E1 SAT PDVT setting is in 500 us steps)
The Jitter Buffer Fill Level impacts the total delay of the reconstructed TDM data stream. The fill level of the Jitter
Buffer is constantly changing according to the bursty nature of the RXP packets. So the delay of a TDM data
stream is not referenced to when an RXP packet is received but is instead viewed as the delay from the receive
TDM Port at the far PW End Point to the transmit TDM Port at the near/local end.
If the Jitter Buffer can store enough data to equal (or exceed) the Total PDV, then the Total PDV can be viewed as
being included in the Maximum Jitter Buffer Fill Level. Because the Jitter Buffer fill level is constantly changing, it is
not easy to define an independent Jitter Buffer delay parameter (to calculate the total delay). But in general the
“highest” Jitter Buffer fill level can be equated to the “Jitter Buffer + Total PDV” delay (assuming Maximum Fill Level
≥ Total PDV). The term “highest” is used, because it is possible that the Jitter Buffer fill level will stabilize at a level
that is lower than the programmed Maximum Fill Level (e.g. the Jitter Buffer “highest” fill level may stabilize at a 6
ms level, while MJBS may be programmed to 8 ms). Although the Jitter Buffer for a PW may stabilize below the
Maximum Fill Level, the total delay is most commonly estimated with the equation below:
Max Total Delay ≅ PCT + fixed transmission delay + TXP BFD + Max Jitter Buffer Fill Level
For a T1 SAT PW and assuming PCT = 1 ms, fixed transmission delay = 2.5 ms (e.g. 500 km fiber), Network PDV
= 3 ms and the remaining PDV = 910 us (from the previous Total PDV example), the 3 approaches will result in:
Approach #1 (No Data Discard)
PDVT1 (in ms) = 2 * 3.91 ms = 7.82 ms (PDVT1 register = 0x017A or 378 decimal which equates to 7.82 ms)
MJBS1 (in ms) = 1 ms + 7.82 ms = 8.82 ms (MJBS1 register = 0x0012 or 18 decimal which equates to 9 ms)
Max Total Delay1 = 1 ms + 2.5 ms + 9 ms = 12.5 ms (assuming MJBS is used to discard data)
Approach #2 (Minimize Delay With Limited Overrun)
PDVT2 (in ms) = 3.91 ms (PDVT2 register = 0x00BD or 189 decimal which equates to 3.91 ms)
MJBS2 (in ms) = 1 ms + 3.91 ms = 4.91 ms (MJBS2 register = 0x000A or 10 decimal which equates to 5 ms)
Max Total Delay2 = 1 ms + 2.5 ms + 5 ms = 8.5 ms (assuming MJBS is used to discard data)
For this approach the initial Max Total Delay may be as much as 1 + 2.5 + 2 * 5 = 13.5 ms, but will drop to Max
Total Delay = 8.5 ms after packets have been discarded due to Jitter Buffer overrun events.
Approach #3 (Minimize Delay With Limited Underrun)
PDVT3 (in ms) = 0 ms (PDVT3 register = 0x0001 which equates to 20.7 us)
MJBS3 (in ms) = 1 ms + 3.91 ms = 4.91 ms (MJBS3 register = 0x000A or 10 decimal which equates to 5 ms)
Max Total Delay3 = 1 ms + 2.5 ms + 5 ms = 8.5 ms (assuming MJBS is used to discard data)
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The Jitter Buffer Maximum Fill Level generally determines the maximum delay. Although the fill level will initially
stabilize at a level just high enough to support the Total PDV, when anomalies occur (e.g. temporary line failures
and RXP PW protection switching) the Jitter Buffer can fill beyond the “Total PDV” level. If the Jitter Buffer fill level
is not “corrected” after an anomaly, because of the near constant rate of the transmit TDM Port, the “extra” data will
not dissipate and will increase the total delay. For example if the Maximum Fill Level is programmed to 1 second
(MJBS or JBMD), and the Total PDV is 10 ms, initially the Jitter Buffer may stabilize at a 10 ms level. But anomalies
could cause the Jitter Buffer to fill beyond the 10 ms level (e.g. equipment programming changes) and as more
anomalies occur, the fill level could accumulate to any level up to 1 second.
There are several registers that the CPU can use to monitor the Jitter Buffer Fill level. Monitoring can be
implemented by polling the Jitter Buffer Maximum and Minimum fill levels or by monitoring for Overrun/Underrun
event indications (data discarded or dummy data inserted). The Jitter Buffer Fill Levels can help to identify setup
errors. Other Jitter Buffer functions that can be enabled include Packet Reordering (for packets received out of
order), packet discard monitoring for too early, too late and duplicate packet Sequence Number. The registers that
support these Jitter Buffer functions include: G.GCR.IPSE, G.GCR.RDPC, G.GSR1.JBS, G.GSRIE1.JBUIE,
G.GSR6.JBGS, PC.CR1.DPDE, B.BCDR1.SCSNRE, B.BDSRL1.JBLPDSL, B.BDSR2 - B.BDSR3, B.BDSR5 -
B.BDSR7, B.GxSRL, and JB.GxSRL.
A Jitter Buffer overflow can occur for three reasons: the selected Transmit TDM Port clock is not the same rate as
that used by the RXP packets (i.e. the wrong clock was selected); clock recovery is selected but has not yet fully
converged to the RXP Packet data rate and is running too slow; the Jitter Buffer depth is too small to handle the
maximum incoming PDV.
The Jitter Buffer is also used by HDLC Connections. However, HDLC Connections, in general, do not transport
constant bit rate data streams (unlike SAT/CES Payload Connections), so the Jitter Buffer is instead used as a
more simplistic FIFO. The Jitter Buffer PDVT and MJBS settings, and the Packet Reordering, Early/Late and
Duplicate Discard functions do not have any meaning with HDLC Connections. HDLC data is forwarded as soon as
it is available. JBMD defines the depth of the FIFO.
9.2.6 TDM Diagnostic Functions
The S132 supports TDM Loopback and TDM BERT Functions for diagnostic testing of the TDM Ports.
9.2.6.1 TDM Loopback
The S132 supports 3 types of Loopbacks for the TDM Ports: TDM Port Line Loopback, TDM Port Timeslot
Loopback and Bundle Loopback. Any number of TDM Ports can be in loopback at the same time.
The TDM Port Line Loopback is enabled using Pn.PTCR2.PRPTLL. This loopback takes data from RDAT and re-
transmits that data on TDAT. All data that is received on RDAT is looped back to TDAT.
The TDM Port Timeslot Loopback is enabled using Pn.PTCR3.PRPTTSL (32 bits, one for each TDM Port
Timeslot). This loopback also takes data from RDAT and re-transmits that data on TDAT, but only for those
Timeslots that have the loopback function enabled. Timeslots that do not have the loopback function enabled
continue to pass data (from Receive TDM Port to TXP Packet and from RXP packet to transmit TDM Port).
For either of these loopbacks to function properly the programmed Transmit TDM Port clock and synchronization
sources (when applicable) must be set to be the same as that of the Receive TDM Port.
When either loopback is enabled, the data for receive TDM Timeslots, that are in loopback, will continue to be
transmitted in TXP packets if TXP Bundles are assigned to the Receive TDM Port and enabled. The TXP packet
stream can be disabled by de-activating the Bundle or by disabling TXP Bundle transmission (B.BCDR3.TXPMS).
RXP Packet data that is received for Timeslots that are in loopback is still forwarded to the Jitter Buffer and is still
used for Clock Recovery. When the loopback is removed, any data that is waiting in the Jitter Buffer is forwarded to
the TDM Port. To prevent the Jitter Buffer from filling with data during a loopback, the payload data for a Bundle
can be discarded (B.BCDR4.RXBDS). Clock Recovery will continue to function for an RXP Bundle that is in one of
these 2 loopbacks as long as the Bundle is selected for Clock Recovery (B.BCDR4.PCRE).
The Transmit TDM Port can only use one timing source, so caution must be exercised when enabling loopbacks for
some Timeslots while other Timeslots are not in loopback. A frequency difference between the looped back RDAT
data and the (non-looped) RXP Packet data will result in occasional slips (corrupted data).
These 2 loopbacks are depicted in Figure 9-17 using a T1/E1 example. The arrow depicts the loopback direction.
The diagram does not depict how “normal” data continues to be forwarded to/from the Ethernet Phy.
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Figure 9-17. T1/E1 Port Line Loopback and TDM Port Timeslot Loopback Diagram
T1/E1
Framer/LIU
S132
Ethernet
Phy
X
X
The TDM Bundle Loopback is enabled using Pn.PRCR3.PTPRTSL (32 bits, one for each TDM Port Timeslot). This
loopback takes received RXP packet data and re-transmits that data in TXP packets. To work properly, when this
loopback is used, all Timeslots for an RXP Bundle should be enabled for loopback; the TXP and RXP Bundles
should be programmed to use the same number of Timeslots and the same functions (e.g. if the RXP Bundle is
Structured, the TXP Bundle should also be Structured); and the Receive TDM Port timing source should be equal
to the data rate of the RXP Packet data (the Receive TDM Port timing determines the fill rate of the TXP Packet).
In the RXP direction, data received from RXP packets is also transmitted at the transmit TDM Port. In the TXP
direction, data that is received at the TDM Port for Timeslots that are in loopback is discarded. This loopback is
depicted in Figure 9-18 using a T1/E1 example. The arrow in the figure shows the direction of the looped back data.
The diagram does not depict how “normal” data continues to be forwarded to and from the Ethernet Phy.
Figure 9-18. T1/E1 Port Bundle Loopback Diagram
T1/E1
Framer/LIU
S132
Ethernet
Phy
X
X
The TDM Bundle Loopback de-encapsulates the payload data from RXP packets, sends the RXP payload data
back in the TXP direction and then re-encapsulates the data into a TXP packet. The data for the TDM Line and
TDM Line Timeslot Loopbacks is not “packetized” (encapsulated/de-encapsulated) before loopback.
Each TDM Loopback type can be enabled for both Structured and Unstructured data streams.
9.2.6.2 TDM BERT
A TDM Port can be tested using a BERT test pattern. The S132 supports “Full Channel” (bidirectional) and “Half
Channel” (unidirectional) TDM BERT Testing. Only one TDM BERT Test can be enabled on an S132 device at a
time. The “Full Channel” and “Half Channel” BERT Tests are depicted in Figure 9-19 using a T1/E1 Example.
Figure 9-19. TDM Port BERT Diagram
Remote T1/E1
Device
S132
Full Channel
(Roundtrip)
BERT
RXP TDM
Decap BERT
Generator
T1/E1
LIU &
Framer
Ethernet
Phy
X
Remote T1/E1
Device
PSTN
TXP TDM
Encap BERT
Monitor
BERT
Monitor
Half
Chan
(1-way)
BERT
BERT
Generator
The Full Channel (Roundtrip) Test requires a loopback at the far end (left side of diagram). The S132 Decap BERT
Pattern Generator sends a BERT Pattern to the S132 Transmit TDM Port. The Encap BERT Monitor verifies that
data, returned at the Receive TDM Port, is error free.
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The Half Channel (one-way) Test requires an equivalent BERT Tester at the far end (on the left side of the
diagram). The S132 BERT Pattern Generator sends a BERT Pattern to the S132 Transmit TDM Port. The far end
uses a BERT Monitor to verify that the data is received error free. Similarly, the far end can transmit a BERT
Pattern in the opposite direction and the S132 BERT Monitor can be used to verify the received data is error free.
There is also a Packet BERT that is described in the “Packet BERT” section. The TDM BERT Engine can be
enabled at the same time as the Packet BERT. However, the two BERT Engines share several register settings, so
the TDM and Packet BERT tests do not function independent of each other. For Half Channel TDM BERT Testing
the Generator and Monitor must be programmed to match what is expected at the far end (left side of Figure 9-19).
There is no register setting to program the BERT Test Engine to “Full” or “Half” Channel Testing. The connections
that are external to the S132 determine the Full vs. Half Channel application.
The S132 TDM BERT Engine uses an Encap BERT Monitor and a Decap BERT Generator. The MD.EBCR.ERBE
enable/disables the TDM Encap BERT Monitor and MD.EBCR.ERBBS selects the TXP Bundle that is to be
monitored. Programming ERBBS with a TXP Bundle number identifies the TDM Port and Timeslots that are tested
(from the B.BCDR4.PNS and B.BCDR2.ATSS that are assigned to that TXP Bundle). The MD.DBCR.DTBE
enable/disables the TDM Decap BERT Generator and MD.DBCR.DTBBS selects the RXP Bundle that is replaced
with the generated pattern (from the B.BCDR4.PNS and B.BCDR2.ATSS that are assigned to that RXP Bundle).
The TDM BERT Engine supports 3 Test Pattern Types: Pseudo-Random Bit Sequence (PRBS), Quasi-Random Bit
Sequence (QRSS) and Repetitive Patterns. The TDM BERT Generator Test Pattern Type is programmed using
DB.BPCR.PTS and DB.BPCR.QRSS. The TDM BERT Monitor Test Pattern Type is programmed using
EB.BPCR.PTS and EB.BPCR.QRSS. For Full Channel testing these should be programmed to the same settings.
For the Pseudo-Random pattern, the “z” coefficient, “y” coefficient and Seed for the X + Xy +1 PRBS pattern is
selected for the Generator using DB.BPCR.PTF, DB.BPCR.PLF and DB.BPCR.BPS; and for the Monitor using
EB.BPCR.PTF, EB.BPCR.PLF and EB.BPCR.BPS.
For the Quasi-Random pattern the PTF, PLF and BPS registers are ignored and the X20 + X17 +1 QRBS pattern is
used. The Quasi-Random pattern is similar to a PRBS pattern but with the number of “consecutive zeros" in the
pattern limited to 14.
For the Repetitive pattern, the pattern length and pattern value are selected for the Generator using,
DB.BPCR.PLF, DB.BPCR.BPS; and for the Monitor using EB.BPCR.PLF and EB.BPCR.BPS. The EB.BPCR.PTF
and DB.BPCR.PTF settings are ignored.
The DB.BCR.TNPL is used to initiate the TDM BERT Generator with a New Test Pattern Load and TPIC is used to
enable Test Pattern Inversion.
The EB.BCR.RNPL is used to initiate the TDM BERT Monitor with a New Test Pattern Load, RPIC enables Test
Pattern Inversion, MPR enables Manual Resynchronization and APRD Disables the automatic “Pattern
Resynchronization” function (the APRD = “0” setting enables auto-resynchronization when test pattern lock is lost).
The EB.BSR, EB.BSRL, EB.BSRIE, EB.RBECR, EB.RBCR are used to Monitor the status of the TDM BERT Test
and measure the bit error performance.
The TDM BERT Generator can be programmed to insert errors in the BERT Test Pattern using the DB.TEICR
register. This can be used to demonstrate that the monitoring function (local or far end) is functioning properly.
RXP and TXP Packet functions, for Bundles that have been assigned to a TDM BERT Test, continue to function
when a BERT Test has been enabled (e.g. Clock Recovery) except that the RXP Packet payload is replaced by the
TDM BERT Test Pattern in the transmit TDM Port Timeslots. For most applications the TXP and RXP Bundles
should be disabled during a TDM BERT Test.
Special Consideration
CAS Signaling functions should be disabled for a Bundle that is used for TDM BERT Testing. In some applications
the BERT Test Pattern may be over-written with CAS Signaling.
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9.3 Packet Processing Functions
The S132 includes one Ethernet Port to receive and transmit Ethernet packets. The high level functions include:
•
•
•
•
•
•
•
•
•
•
100 Mbps MII or 1000 Mbps GMII Interface
Ethernet II and IEEE 802.2 LLC/SNAP formats
0, 1 or 2 VLAN Tags with programmed TPID values
2000 byte Maximum Ethernet Frame Length
2 programmable Ethernet DAs
Broadcast Ethernet DA
L2TPv3, UDP, MEF-8 or MFA-8 PW protocol
0, 1 or 2 Outer MPLS Labels
•
Optional Control Word and RTP Headers
Flexible PW Sequence Numbering functions
•
•
•
Missing Packet Detection
Packet Re-ordering
•
RXP CPU packet monitoring
•
•
•
In-band VCCV
32 Out-band VCCV BIDs (UDP-specific OAM)
Several programmed “send to CPU” Conditions
0, 1, or 2 L2TPv3 Cookies
Up to 256 PW Bundles
•
•
•
Special Ethernet Type
Detected Packet Error Conditions
PW Bundle Debug
•
•
•
Any mix of SAT, CES, HDLC and Clock Only
T1, E1 or slower payload data rates
CES with/without Sub-channel CAS Signaling
•
TXP Packet Generation
•
•
•
•
•
256 programmed TXP Bundle Headers
Flexible CPU generated TXP packet format
CES/SAT packets with/without RTP Timestamp
CPU packets with/without OAM Timestamps
High and Low Priority TXP PW Queues
•
•
“IPv4-only”, “IPv6-only” or “IPv4 and IPv6”
•
•
3 programmed IPv4 DAs
2 programmed IPv6 IP DAs
UDP
•
•
•
2 programmed UDP Protocol Types (or ignore)
Selectable 16-bit or 32-bit PW-ID
Optional 16-bit PW-ID Mask
•
•
•
•
Ethernet Port RMON Statistics
Ethernet Port Loopback
Ethernet Port BERT Testing
MDIO Interface for Phy device Management
•
Verify and generate FCS for IPv4 and UDP
9.3.1 Ethernet MAC
The Ethernet MAC/port can support 100 Mbps using an MII interface or 1000 Mbps using a GMII interface to
transmit and receive data with an external Ethernet Phy device. The MAC also provides RMON statistics and an
MDIO interface for communicating with the Phy device. Figure 9-20 provides a high level view of the Ethernet MAC
environment.
Figure 9-20. Ethernet MAC Environment
DS34S132
ETHCLK
TXP Pkt
MDIO
Scheduling & Generation
Ethernet MAC
Ethernet
TXP MII/GMII
Phy
RXP Pkt Classifier
RXP MII/GMII
Ethernet RMON Statistics
The Ethernet Line rate is selected using M.NET_CONFIG.GIG_MODE_EN and G.GCR.GMMS.
For 100 Mbps the S132 uses an MII interface with two 4-bit, unidirectional data-buses. Transmit data (TXD [3:0])
and Receive data (RXD [3:0]) are timed using the RXCLK and TXCLK inputs from the Phy device. The ETHCLK
input must be 25 MHz and G.GCR.EC25 = 1.
For 1000 Mbps, the S132 uses a GMII interface with two 8-bit, unidirectional data-buses. Transmit data (TXD [7:0])
is timed using the GTXCLK output. Receive data (RXD [7:0]) is timed using the RXCLK input from the Phy device.
Both GTXCLK and RXCLK are 125 MHz signals. The GTXCLK signal is derived from a 125 MHz ETHCLK input
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(G.GCR.EC25 = 0). In some cases ETHCLK can be tied to RXCLK to have the Phy device drive both inputs at one
time (as long as the RXCLK output from the Phy is a constant, non-gapped 125 MHz signal).
M.NET_CONTROL.TXP_HALT, START_TXP, TXP_EN and RXP_EN enable/disable the flow of RXP and TXP
data at the Ethernet MAC/Port.
The MAC must be programmed to operate in the Full-duplex mode (M.NET_CONFIG.EN_FRMS_UDUP = 0 and
M.NET_CONFIG.FULL_DUPLEX = 1). The Half-duplex mode and Pause Control are not supported because they
can adversely affect the delay/latency of the PW packets.
The standard maximum Ethernet Frame size is 1518 bytes. The MAC can be programmed to accept RXP Ethernet
frames with byte lengths of 1518 bytes or 1536 bytes using M.NET_CONFIG.RXP_1536FRMS or up to 2000 bytes
using M.NET_CONFIG.JUMBO_FRMS.
The MAC can be programmed to accept or discard all non-VLAN frames using M.NET_CONFIG.DISC_NOVLAN.
The MAC, when programmed as prescribed in the “Register Guide”, “Global Ethernet MAC” section, checks each
received RXP packet for valid Ethernet preamble, FCS, alignment and length. Packets with errors are discarded. In
the TXP direction the MAC appends an Ethernet FCS and adds padding to packets that are < 64-bytes in length.
The MDIO interface can be enabled using M.MAN_PORT_EN, and programmed using the M.PHY_MAN and
M.NET_STATUS registers.
MDC (MDIO Clock) is divided down from the SYSCLK input. MDC_CLK_DIV sets the “divided by” value and should
be set such that MDC frequency = SYSCLK ÷ (selected MDC_CLK_DIV divider value) ≤ 2.5 MHz. For example if
SYSCLK = 50 MHz and MDC_CLK_DIV = 010b (selects divide by 32), then the MDC frequency will be 1.56 MHz.
9.3.1.1 Ethernet Port Diagnostic Functions
The S132 supports Ethernet Loopback and Packet BERT Functions for diagnostic testing of the Ethernet Port.
9.3.1.1.1 Ethernet Loopback
The M.NET_CONTROL.LB_LOCAL = 1 enables the Ethernet Port Loopback that sends all receive TXP packet
data back in the RXP direction. CES, SAT, HDLC and Clock data/information that is received at a TDM Port is
encapsulated into TXP packets using the programmed Bundle settings. TXP packets that are initiated by the CPU
are also encapsulated into TXP CPU Packets. The combination of all TXP packet types is looped back in the RXP
direction. The RXP packets are forwarded according to the programmed RXP Bundle settings (forwarded to the
TDM Ports and/or CPU). No data is transmitted toward the Ethernet Phy and no data is received from the Ethernet
Phy while the Ethernet loopback is active. This loopback is depicted in Figure 9-21 using a T1/E1 example (the
loopback of TXP CPU packets to the CPU is not depicted).
Figure 9-21. Ethernet Port Local Loopback
T1/E1
Framer/LIU
S132
Ethernet
Phy
X
X
9.3.1.1.2 Packet BERT
An Ethernet path can be tested using a BERT Test Pattern. The S132 supports “Full Channel” and “Half Channel”
Packet BERT Testing. Only one Packet BERT Test can be enabled on an S132 device at a time. The “Full
Channel” and “Half Channel” BERT Tests are depicted in Figure 9-22.
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Figure 9-22. Ethernet Port BERT Diagram
Remote Ethernet
Device
Full Channel
Roundtrip
BERT
S132
Ethernet
Phy
T1/E1
Framer/
LIU
RXP Packet
Decap BERT
Monitor
PSN
TXP Packet
Encap BERT
Generator
Remote Ethernet
Device
X
BERT
Pattern
Half
Chan
(1-way)
BERT
BERT
Monitor
The Full Channel (Roundtrip) Test requires a loopback at the far end (on the right side of the diagram). The S132
Packet BERT Pattern Generator sends a BERT Pattern to the S132 Transmit Ethernet Port. The BERT Monitor
verifies that the data returned at the Receive Ethernet Port is error free.
The Half Channel (one-way) Test requires an equivalent BERT Tester at the far end (on the right side of the
diagram). The S132 Packet BERT Pattern Generator sends a BERT Pattern to the S132 Transmit Ethernet Port.
The far end must use a BERT Pattern Monitor to verify that the data is received error free. Similarly, the far end can
transmit a BERT Pattern in the opposite direction. The S132 BERT Monitor can be used to verify that the data is
received error free.
The Packet BERT Engine can be enabled at the same time as the TDM BERT. The two BERT Engines share
several register settings, so the TDM and Packet BERT tests are not independent of each other. For Half Channel
Packet BERT Testing the Generator and Monitor must be programmed to match what is expected at the far end
(right side of Figure 9-22). There is no register setting to program the BERT Test Engine to “Full” or “Half” Channel
Testing. The connections that are external to the S132 determine the Full vs. Half Channel application.
The S132 Packet BERT Engine uses an Encap BERT Generator and a Decap BERT Monitor. The
MD.EBCR.ETBE enable/disables the Packet BERT Generator and MD.EBCR.ETBBS selects the TXP Bundle that
the generated BERT Test Pattern is to be inserted into. The BERT Test Pattern is placed in the Payload section. If
a Bundle that is programmed to support sub-channel CAS Signaling is assigned to a Packet BERT Test, the sub-
channel CAS Signaling is unaffected (not tested) by the BERT Test. The MD.DBCR.DRBE enable/disables the
Packet BERT Monitor and MD.DBCR.DRBBS selects the RXP Bundle that is to be monitored.
The Packet BERT Engine supports 3 Test Pattern Types: Pseudo-Random Bit Sequence (PRBS), Quasi-Random
Bit Sequence (QRSS) and Repetitive Patterns. The Packet BERT Generator Test Pattern Type is programmed
using EB.BPCR.PTS and EB.BPCR.QRSS. The Packet BERT Monitor Test Pattern Type is programmed using
DB.BPCR.PTS and DB.BPCR.QRSS.
For the Pseudo-Random pattern, the “z” coefficient, “y” coefficient and Seed for the X + Xy +1 PRBS pattern is
selected for the Generator using EB.BPCR.PTF, EB.BPCR.PLF and EB.BPCR.BPS; and for the Monitor using
DB.BPCR.PTF, DB.BPCR.PLF and DB.BPCR.BPS.
For the Quasi-Random pattern the PTF, PLF and BPS registers are ignored and the X20 + X17 +1 QRBS pattern is
used. The Quasi-Random pattern is similar to a PRBS pattern but with the number of “consecutive zeros" in the
pattern limited to 14.
For the Repetitive pattern, the pattern length and pattern value are selected for the Generator using EB.BPCR.PLF
and EB.BPCR.BPS; and for the Monitor using DB.BPCR.PLF and DB.BPCR.BPS. The PTF settings are ignored.
The EB.BCR register is used to program the Packet BERT Generator for New Test Pattern Load (TNPL; initiate
generation of the test pattern) and Test Pattern Inversion (TPIC).
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The DB.BCR register is used to program the Packet BERT Monitor for New Test Pattern Load (RNPL), Test Pattern
Inversion (RPIC), Manual Resynchronization (MPR) and Pattern Resynchronization Disable (APRD).
The DB.BSR, DB.BSRL, DB.BSRIE, DB.RBECR, DB.RBCR are used to Monitor the Packet BERT Test status.
The Packet BERT Generator can be programmed to insert errors in the BERT Test Pattern using the EB.TEICR
register. This can be used to demonstrate that the monitoring function (local or far end) is functioning properly.
Receive and transmit TDM Port Timeslot functions, for Bundles that have been assigned to a Packet BERT Test,
continue to function when a Packet BERT Test has been enabled except that the received TDM Port Timeslot data
for the TXP Bundle that is assigned to the Packet BERT Test is replaced by the Packet BERT Test Pattern. For
most applications the TDM Port Timeslots should be disabled during a Packet BERT Test.
Special Consideration
CAS Signaling functions should be disabled for a Bundle that is used for Ethernet BERT Testing.
9.3.2 RXP Packet Classification
The header for a packet commonly contains several different header fields. The Classifier iteratively steps through
each field of the header, looking for recognized formats and values. When the Classifier detects a recognized
format/value, the Classifier either continues the classification process or has sufficient information to forward the
packet to the next internal circuit block. Programmed settings determine the outcome for each interpretive step and
are described in this section at a functional level. Figure 9-23 depicts the various destinations for RXP Packets.
Figure 9-23. RXP Packet Classifier Environment
Pkt sent to Buffer Manager TXP CPU Queue
DS34S132
CPU Connection
Timing information sent to
Timing Connection
RXP Clock Recovery Engine
Ethernet
MAC
RXP Pkt
Classifier
Payload sent to Buffer Manager
HDLC Connection
for RXP HDLC Engine
Payload sent to Buffer Manager Jitter
SAT/CES Connection
Buffer for RXP SAT/CES Engine
Discard
When the Classifier determines that the format of a received RXP Packet header is not recognized, the packet may
be discarded or forwarded to the CPU depending on the packet format and programmed settings. The program
settings that determine Discard vs. CPU for unrecognized format/values are referred to as Discard Switches. These
are described in the CPU Packet Classification section.
9.3.2.1 Generalized Packet Classification
The Classifier can be programmed to recognize 2 Ethernet DAs (PC.CR17 – PC-CR19) and the Ethernet
Broadcast Address. If a received Ethernet DA is not equal to one of these values the packet is either forwarded to
the CPU or discarded (PC.CR1.DPS9).
To be accepted an RXP Packet must use the DIX/Ethernet II or IEEE 802 LLC/SNAP format and can include 0, 1,
or 2 VLAN tags. If VLAN tags are included, the inner VLAN tag TPID must equal PC.CR3.VITPID (normally 0x8100
for CVLAN). When a packet includes 2 VLAN tags the outer VLAN TPID must equal PC.CR3.VOTPID (for SVLAN).
The next packet header field that is tested is the Ethernet Type. The Classifier tests the Ethernet Type to determine
if the packet uses a recognized PW Header. Six PW Headers can be recognized: MEF-8, MFA-8, UDP/IPv4,
UDP/IPv6, L2TPv3/IPv4 and L2TPv3/IPv6.
For UDP and L2TPv3 applications, the Ethernet Type field must either be equal to IPv4 or IPv6. The S132 can be
programmed to only recognize IPv4, only recognize IPv6 or to recognize both IPv4 and IPv6 (PC.CR1.RXPIVS and
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PC.CR1.RXPDSD). If a packet is received that includes an Ethernet Type field that is equal to an IP version that is
not enabled, the packet is discarded. According to the enabled IP version(s), the S132 can recognize up to 3 IPv4
DAs (PC.CR6 – PC.CR8) and up to 2 IPv6 DAs (PC.CR9 – PC.CR16). If the packet matches the enabled IP
version(s), but does not match one of the programmed IP DAs, the packet is either forwarded to the CPU or
discarded (PC.CR1.DPS1).
For MEF-8 applications the received Ethernet Type is compared against the programmed PC.CR4.MET value. For
MFA-8 the Ethernet Type field is compared against the Unicast and Multicast MPLS Ethernet Type values. Table
9-8 identifies each of the recognized PW Ethernet Types.
Table 9-8. Recognized PW Ethernet Types
Ethernet Type
MEF-8
Ethernet Type value
PC.CR4.MET
0x8847
Comment
Should be programmed to 0x88D8
Hardwired value in the S132.
Hardwired value in the S132.
Hardwired value in the S132.
Hardwired value in the S132.
MFA-8 Unicast MPLS
MFA-8 Multicast MPLS
IPv4
0x8848
0x0800
IPv6
0x86DD
The information for identifying UDP and L2TPv3 headers is hardwired in the Classifier, without any enable settings.
If a received packet header matches one of the 6 PW Header Types, the packet is further processed as a PW
packet. If the packet does not include one of the recognized PW Header Types the packet is further analyzed to
determine whether it is a CPU packet (see “CPU Packet Classification section”).
A packet with a recognized PW Header that includes the Ethernet Broadcast Address can be further processed or
discarded (PC.CR1.DBTP).
9.3.2.2 PW (BID and OAM BID) Packet Classification
When one of the 6 PW Header Types has been detected, the Classifier next interprets the packet to find its PW-ID
and then tests the PW-ID to see if it matches a recognized Bundle or OAM Bundle. The S132 can recognize up to
256 PW/Bundles and up to 32 OAM PW/Bundles. “Bundles” can be programmed to include CES, SAT, HDLC, PW-
Timing (Clock Recovery) and/or CPU connections. The 256 Bundles are referred to as “Bundle 0” through “Bundle
255”. “OAM Bundles” are similar to “Bundles”, but restricted in their use.
“OAM Bundles” are commonly used in UDP applications to provide CPU, Out-band VCCV connections (such as
“UDP-specific OAM”). The “OAM Bundles” are referred to as “OAM Bundle 0” through “OAM Bundle 31”. Each
OAM Bundle is usually associated with one or more of the 256 Bundles (to provide OAM for those Bundles). The
use of OAM Bundles is optional and the association between “normal” Bundles and OAM Bundles must be made
outside of the S132 (there are no internal S132 association settings or interactions). They are all treated
independently by the S132.
The BID and OAM BID values must be programmed for each Bundle and OAM Bundle. The B.BACR register is
used to select which of the 256 Bundles or 32 OAM Bundles is to be programmed, the B.BADR1 register to select
the Active or Inactive state and the B.BADR2 register to specify the BID or OAM BID value.
For each “normal” Bundle there is a wide range of settings that can be programmed. The B.BCCR register is used
to select which of the 256 Bundles is to be programmed and the B.BCDR1 – B.BCDR5 registers are used to specify
the Bundle parameters. The OAM Bundles do not support other programmable “per-Bundle” parameters.
When the Classifier has determined that a received packet includes a recognized PW Header, the received PW-ID
is compared against each of the active BIDs and OAM BIDs. The BID bit-width varies according to the PW Header
type. The Classifier is hard-wired to support a 20-bit comparison for MEF- and MFA-8 and a 32-bit comparison for
L2TPv3. For UDP the Classifier can be programmed to support a 16-bit or 32-bit comparison (G.GCR.UBIDLS).
To find a matching BID/OAM BID, the Classifier initially compares all of its active BIDs and OAM BIDs against each
received PW-ID without verifying that the received Header Type is also correct. The received PW-ID field is
identified (according to the received PW header type) and then compared against 256 BIDs and 32 OAM BIDs. If a
received PW-ID does not match any of the active BIDs or OAM BIDs the packet is either forwarded to the CPU or
discarded (PC.CR1.DPS6).
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The S132 includes several BID/OAM BID settings and tests for UDP applications that are not used by the non-UDP
applications. These are explained in the “UDP Settings” section. For non-UDP applications, the “UDP Settings”
section can be skipped/ignored.
9.3.2.2.1 UDP Settings
For UDP packets the S132 can be programmed to perform the following BID comparison rules using PC.UBIDLS,
PC.UBIDLCE and B.BCDR4.RXUBIDLS.
A) Always 16-bit and accepted in either the UDP Source or Destination position (automatic position detection)
B) Always 16-bit and only accepted in the UDP Port position according to B.BCDR4.RXUBIDLS (set per Bundle)
C) Always 16-bit in the UDP Destination Port position
D) Always 16-bit in the UDP Source Port position
E) Always 32-bit in the combined Source and Destination Port positions
The UDP OAM BID comparison rules follow the BID comparison rules except when the “per Bundle setting” using
B.BCDR4.RXUBIDLS (rule “B” above) is enabled. When this rule has been enabled, the S132 tests for 16-bit OAM
BIDs in either UDP Port position (rule “A” above; auto detected).
If a matching BID or OAM BID is not found in the location specified by these registers, the UDP packet is either
forwarded to the CPU or discarded (PC.CR1.DPS6).
The “16-bit Auto-detected” and “Per-Bundle 16-bit using RXUBIDLS” settings are designed to allow a mixture of
PWs with the BID in the UDP Source Port location and other PWs with the BID in the UDP Destination Port
location. The “16-bit Per-Bundle using RXUBIDLS” setting requires that the BID location is programmed for all
Bundles (RXUBIDLS). The “16-bit Auto-detected” does not use a location setting, but rather tests both locations
accepting a match in either location.
When the S132 is programmed to use 32-bit BIDs, the UDP 16-bit Source and 16-bit Destination Port values are
combined into a single 32-bit value in the same order in which they are received (the Source Port becomes the 16
MSbits for the 32-bit BID). The 32-bit setting is also applied to the OAM BIDs so that there is only one accepted bit-
width for all BIDs and OAM BIDs (either all are 16-bit or all are 32-bit).
The S132 can ignore any of the UDP PW-ID bit positions from bit-0 to bit-15 using PC.CR20.UBIDM. This can be
used to support a smaller UDP BID bit-width (e.g. bits 0 – 11), or to mask particular bit positions. As an example,
with UBIDM = 0xF0FF the Classifier will match any received PW-ID = 0xCZ00 (where Z = any hex value 0 to F)
with BID = 0xC000 (bits 8 – 11 are ignored). When using the 32-bit BIDs, bits 16 – 31 cannot be masked.
The S132 can verify each received UDP Protocol Type field against either of two programmed values
(PC.CR2.UPVC1 and PC.CR2.UPVC2) or can ignore the UDP Protocol Type (PC.CR1.UPVCE). When enabled,
the UDP Protocol Type is tested in the UDP Source or Destination Port location, whichever location is not used by
the BID/OAM BID (e.g. if the BID is tested in the Source location, the Protocol Type is tested in the Destination
location). For UDP packets that match a BID but do not include the correct UDP Protocol Type (when UDP Protocol
testing is enabled), PC.CR1.DPS5 determines whether the packet is discarded or sent to the CPU.
The UDP Protocol Type is ignored (not tested), regardless of the UPVCE and DPS5 settings, for 3 conditions: when
no matching BID/OAM BID is found, when a matching OAM BID is found and when using the 32-bit BID mode.
PC.SRL.UPVCSL and PC.SRL.UBIDLCSL can be used as debug tools to monitor the UDP BID location and
Protocol Type value are correct. These status indications are available with all of the UDP BID test modes.
However, the UBIDLCSL status only indicates whether the UDP BID was found in the location specified by the
RXUBIDLS for each Bundle (regardless of the BID Test Mode setting). This means that for BID Test modes A, C, D
and E the UBIDLCSL status may not agree with the results of the enabled BID Test mode (BID Test Modes A, C, D
and E do not use the RXUBIDLS settings to determine where to look for the BID).
9.3.2.2.2 Handling of Packets with a Matching BID or OAM BID
When a packet matches an OAM BID (any PW Header type), then the packet is either forwarded to the CPU or
discarded (PC.CR1.DPS7). The Classifier does not regard the remaining header fields.
If a BID match is found, then the PW Header Type that is programmed for that Bundle is verified
(B.BCDR4.RXHTS). If the PW Header Type does not match, the packet is discarded.
When the PW-ID and PW Header Type match that of a programmed Bundle the Classifier can optionally verify the
functions identified in Table 9-9. If the packet passes these tests the Classification process continues.
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Table 9-9. Malformed PW Header Handling (not including the UDP specific settings)
Test Description
Functional Settings Special “Fail” Setting
“Fail” Result
Wrong Payload Size
B.BCDR1.PMS,
-
Discard
B.BCDR1.SCSCFPD
RTP Header existence
B.BCDR4.RE
-
Discard
Control Word Header existence
B.BCDR4.CWE
-
Discard
Wrong # L2TPv3 Cookies or MPLS Labels B.BCDR4.RXLCS
PC.CR1.DPS10
Discard/CPU
The first nibble of the Control Word of a PW packet is used to identify whether the packet payload carries data that
is destined for a TDM Port or that is destined for the CPU (In-band VCCV OAM). When the first nibble is equal to
0x0 the payload is destined for the TDM Port. The Classifier can be programmed to monitor for In-band VCCV
packets by enabling the Control Word monitoring function (B.BCDR4.RXOICWE) and by specifying the Control
Word value that is expected. The commonly used nibble value for (CPU) In-band VCCV packets is 0x1. When
RXOICWE is enabled, the first byte of each received Control Word is compared against PC.CR5.VOV using
PC.CR5.VOM to specify how many bits are to be Masked/Ignored. If the first byte matches VOV and VOM, then the
packet is forwarded to the CPU. If the first byte does not match VOV and VOM, and the first nibble is not 0x0 the
packet is discarded. In-band VCCV can be enabled (per Bundle) for SAT, CES, HDLC and Clock Only Bundles.
If a packet matches all of the Bundle test conditions so far described and has not already been discarded or
forwarded to the CPU, the packet payload/information is forwarded to the HDLC Engine, SAT/CES Engine, Clock
Recovery or CPU. Table 9-10 identifies the register settings that are required for each Connection/Bundle Type that
is listed.
Table 9-10. Bundle Forwarding Options
Connection/Bundle Type
Destination setting
Engine Type setting Clock Recovery setting
B.BCDR4.RXBDS
B.BCDR1.PMT
B.BCDR4.PCRE
SAT/CES Payload Only
SAT/CES Payload & PW-Timing
Clock Only (PW-Timing only)
HDLC
TDM Port
TDM Port
Discard
TDM Port
CPU
SAT/CES
disable
SAT/CES
enable
SAT/CES
enable
HDLC
disable
CPU Debug RXP PW Bundle1
HDLC or SAT/CES
enable/disable
1
Note:
The SAT/CES and HDLC PW packets can be diverted from their “normal destination” and forwarded to the CPU for
debug purposes by setting the RXBDS to send the packet to the CPU.
The forwarding of payload data for RXP SAT/CES Payload Connections and HDLC Connections can be disabled
using B.BCDR4.RXBDS = 11. When a Payload Connection is disabled and the Jitter Buffer for that Bundle is
empty, the data that is transmitted at the TDM Port is filled with Conditioning Data. The PW-Timing Connection is
disabled using B.BCDR4.PCRE (it is not disabled using B.BCDR4.RXBDS).
Special considerations
Each programmed BID and OAM BID value must be unique across all PW Header types. For example one Bundle
cannot use BID = “17” with UDP and another Bundle use BID = “17” with L2TPv3 (OAM BID = “17” would also not
be allowed). In systems that are unable to co-ordinate the assignment of PW-IDs across all supported PW Header
Types, only one PW Header Type should be used by the S132 to insure unique BIDs and OAM BIDs.
9.3.2.2.3 L-bit Signaling for RXP PWs
The L-bit in the Control Word of a PW packet can be used to indicate across the PSN when a T1/E1 fault has been
detected. The CPU can monitor for received L-bit changes for each RXP Bundle using the G.GCR.LBCDE,
B.G0SRL.CWCDSL - B.G31SRL.CWCDSL, B.G0SRL.CWCDIE - B.G31SRL.CWCDIE, G.GSR5.BGS, G.GSR1.BS
and G.GSRIE1.BIE Registers. This is explained in more detail in the Monitor & Interrupt section.
The S132 can also be programmed to automatically discard the RXP Packet payload when the received L-bit = 1
(invalid payload) and B.BCDR1.LBCAI = 1 (conditioning for L-bit = 1).
9.3.2.3 CPU Packet Classification
Packets that are not identified as PW packets are further processed according to the rules described in this section
to determine whether they are to be sent to the CPU (or discarded). The previously described “send to CPU”
conditions in the “Generalized Packet Classification” and “PW Packet Classification” sections are also repeated in
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this section so that all “send to CPU conditions” are described together in one section (e.g. OAM BIDs, In-band
VCCV, “CPU Debug RXP PW Bundle” and error condition Discard Switches).
9.3.2.3.1 Packets with Broadcast Ethernet DA (DPC.CR1.DPBTP and DPC.CR1.DPBCP)
When an Ethernet packet is received with the Ethernet Broadcast Destination Address (DA) and the packet
includes one of the PW Header Types, the PC.CR1.DPBTP setting determines whether the packet is sent to the
CPU (0) or Discarded (1).
When an Ethernet packet is received with the Ethernet Broadcast DA and the packet doe not include one of the PW
Header Types, the PC.CR1.DPBCP setting determines whether the packet is sent to the CPU (0) or Discarded (1).
9.3.2.3.2 Packets with Unknown Ethernet DA (PC.CR7 – PC.CR19 and DPC.CR1.DPS9)
When an Ethernet packet is received and the packet includes an Ethernet DA that is not recognized (not equal to
PC.CR7 – PC.CR12, PC.CR13 – PC.CR19 or the Ethernet Broadcast Address), the PC.CR1.DPS9 setting is used
to determine whether the packet is forwarded to the CPU (0) or Discarded (1). Packets with the Ethernet Broadcast
DA are regarded as having a “known” address and are not affected by the DPS9 setting.
If the Ethernet DA registers are not programmed (PC.CR7 – PC.CR19; DA values in their default state = “0”) the
combined settings of PC.CR1.DPS9, PC.CR1.DPBTP and PC.CR1.DPBCP can be used to specify that all valid
Ethernet packets that do not use the “0” DA value are forwarded to the CPU (0) or Discarded (1).
9.3.2.3.3 PW Packets with Unknown PW-ID (DPS6)
When a packet is received with a recognized PW Header (MEF-8, MFA-8, UDP or L2TPv3) but the received PW-ID
does not match any of the programmed BIDs or OAM BIDs, the PC.CR1.DPS6 setting determines whether the
packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.4 MEF OAM Ethernet Type Packets (MOET)
MEF OAM Ethernet Type packets are recognized when the received Ethernet Type field is equal to the
programmed PC.CR4.MOET. The PC.CR1.DPS7 setting determines whether the packet is forwarded to the CPU
(0) or Discarded (1).
9.3.2.3.5 CPU Destination Ethernet Type Packets (CDET and DPS8)
When an Ethernet packet is received with an Ethernet Type field that is equal to PC.CR20.CDET, the
PC.CR1.DPS8 setting determines whether the packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.6 ARP Packet with Known IP Destination Address (PC.CR6 – PC.CR8 and DPS3)
When an ARP packet is received (Ethernet Type = 0x0806) with an IP Destination Address that equals one of the
IPv4 addresses programmed at PC.CR6 – PC.CR8, the PC.CR1.DPS3 setting determines whether the packet is
forwarded to the CPU (0) or Discarded (1).
9.3.2.3.7 ARP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR8 and DPS0)
When an ARP packet is received (Ethernet Type = 0x0806) with an IP Destination Address that is not equal to one
of the IPv4 addresses programmed at PC.CR6 – PC.CR8, the PC.CR1.DPS0 setting determines whether the
packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.8 Packet with Unknown Ethernet Type (DPS2)
When an Ethernet packet is received with an Ethernet Type field that is not recognized (not equal to ARP, Unicast
MPLS, Multicast MPLS, IPv4, IPv6, PC.CR20.CDET, PC.CR4.MET or PC.CR4.MOET), the PC.CR1.DPS2 setting
determines whether the packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.9 IP Packets with Unknown IP Protocol (DPS4)
When an IP packet is received with an IP Protocol field that is not UDP or L2TPV3, the PC.CR1.DPS4 setting
determines whether the packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.10 IP Packet with Unknown IP Destination Address (PC.CR6 – PC.CR16 and DPS1)
When an IP packet is received with an IP DA that is not equal to one of the IP addresses programmed at PC.CR6 –
PC.CR16, the PC.CR1.DPS1 setting determines whether the packet is forwarded to the CPU (0) or Discarded (1).
The IP version that is recognized is selected with PC.CR1.RXPIVS and PC.CR1.RXPDSD.
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9.3.2.3.11 “CPU Debug RXP PW Bundle” Setting (RXBDS)
PW Bundles (not including OAM Bundles) are normally used for SAT, CES, HDLC or PW-Timing Connections, but
can be programmed to instead send packets to the CPU for debug. When the CPU Debug setting is enabled
(B.BCDR4.RXBDS), the received packets for the RXP Bundle are redirected to the CPU (instead of sending the
data to the SAT/CES/HDLC/Clock Recovery Engines). The RXP Bundle parameters can be fully programmed or
partially programmed. A received packet is identified as a “CPU Debug RXP PW Bundle” packet when the packet
includes any of the PW Header Types, the PW-ID of the packet matches a BID and the Bundle that uses that BID is
programmed to “CPU Debug” (RXBDS). The other Bundle register settings are ignored.
9.3.2.3.12 PW Bundle with Unknown UDP Protocol Type (UPVCE and DPS5)
When the Classifier is programmed to verify the UDP Payload Protocol (PC.CR1.UPVCE) and a UDP packet is
received with a recognized BID, but with a UDP Payload Protocol value that is not equal to PC.CR2.UPVC1 or
UPVC2, PC.CR1.DPS5 selects whether the packet is sent to the CPU (0) or Discarded (1). The DPS5 setting does
not affect packets that are otherwise identified as CPU packets.
9.3.2.3.13 PW Bundle In-band VCCV OAM (RXOICWE and DPS7)
In-band VCCV CPU Connections can be thought of as “secondary” connections that are used to support the
“primary” SAT/CES/HDLC/Clock Only PW for functions like setup, configuration and monitoring. An In-band VCCV
connection can be established before the primary connections have been established. The In-band VCCV may be
used, e.g., to negotiate the configuration settings of the primary connection before enabling the primary connection.
The Classifier monitors for In-band VCCV packets for a Bundle when B.BCDR4.RXOICWE = 1. The PC.CR1.DPS7
setting determines whether In-band VCCV packets are forwarded to the CPU (0) or Discarded (1).
9.3.2.3.14 PW Bundle with Too Many MPLS Labels (DPS10)
When an MFA-8 (MPLS) packet is received with a recognized BID and the packet includes more than 2 MPLS
Labels, PC.CR1.DPS10 determines whether the packet is forwarded to the CPU (0) or Discarded (1).
9.3.2.3.15 PW OAM Bundle - Out-band VCCV OAM Packets (DPS7)
Up to 32 Out-band VCCV OAM Connections can be programmed using OAM BIDs. OAM BIDs are used to support
what the standards call “UDP-specific OAM”, “Out-band VCCV” or “OAM using Separate PW-ID” (meaning OAM
PW-IDs that are separate/unique from the PW-IDs used by the primary PW connection). The UDP application
commonly uses this OAM form instead of the “In-band VCCV” form. This OAM format is not commonly used with
L2TPv3, MEF-8 or MFA-8. A packet is recognized as an OAM Bundle when the received packet includes a one of
the PW Header Types and the received PW-ID matches one of the 32 programmed OAM BIDs. The PC.CR1.DPS7
setting determines whether this packet type is forwarded to the CPU (0) or Discarded (1).
9.3.3 TXP Packet Generation
The TXP Packet Generator schedules the packet data for CPU, PW-Timing, HDLC and SAT/CES Payload
Connections and appends the TXP Header (including FCS field values when required) and TXP Timestamp (when
required). The Ethernet FCS is appended outside this block in the Ethernet MAC block.
Figure 9-24. TXP Packet Generation Environment
RXP CPU Queue packets from Buffer Manager
DS34S132
CPU Connection
TXP RTP Timestamp
information from Buffer Manager
TXP Timing Connection
TXP Pkt
Scheduling &
Generation
Ethernet
MAC
TXP HDLC Payload data from
Buffer Manager
HDLC Connection
TXP SAT/CES Payload data from
Buffer Manager
SAT/CES Connection
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9.3.3.1 TXP SAT/CES/HDLC/Clock Only PW Packet Generation
A TXP Header Descriptor is programmed for each activated SAT, CES, HDLC and Clock Only Bundle (up to 256).
The TXP Header Descriptors are retrieved from memory as they are needed for each outgoing TXP PW Packet.
Figure 9-25 depicts the format of the data that is programmed in the TXP Header Descriptor. The Header Control is
used to identify the number of bytes included in the transmitted TXP Header and where the TXP Local Timestamp,
Length and FCS fields are located in the header so that the S132 can modify these fields “on-the-fly” when
required. The Header Control field values are not included in the transmitted Ethernet packets.
Figure 9-25. SAT/CES/HDLC/Clock Only PW TXP Header Descriptor
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Header Control
2-bytes of Dummy Fill = 0x00.00
Ethernet Header including …
… DA, SA, optional VLAN Tags, optional LLC/SNAP and Type/Length fields
Application Protocol Header (e.g. UDP/IP, L2TPv3/IP, MFA-8, MEF-8)
Optional RTP and Control Word Headers
The 256 TXP Header Descriptors are programmed in an SDRAM memory block that begins at address
EMI.BMCR1.TXHSO. The TXP Header Descriptor for each Bundle is stored in a 128-byte SDRAM slot that is
addressed/indexed at the location = TXHXSO + (Bundle Number * 128 bytes).
The TXP Header Control for SAT/CES and HDLC PW packets is a 32-bit Dword (depicted in Table 9-11.
Table 9-11. TXP SAT/CES/HDLC/Clock Only PW Header Control
Field
Bit [x:y]
Description
Reserved.
RSVD
[31:26]
TXP Header Length specifies how many Dwords are in the packet header including the
TXELEN [25:21]
Ethernet, Application, RTP and Control Word Headers (when applicable).
TXP Control Word Exists. 1 = included; 0 = not included.
TXP RTP Exists. 1 = included; 0 = not included.
Reserved.
TXCWE [20]
TXRE
RSVD
[19]
[18:16]
TXP Application Header Length specifies how many Dwords are included in the
Application Protocol Header beginning just after the Ethernet Header and including the
Control Word and RTP Headers (when applicable).
TXALEN [15:11]
TXP Application Header Offset = Dword offset of Application Header in Ethernet packet.
TXAOFF [10:6]
TXAOFF = (“Application Header starting byte position in Ethernet packet” - 2) ÷ 4
TXP UDP Header Exists. 1 = included; 0 = not included.
TXUDPE [5]
TXIPV6E [4]
TXIPV4E [3]
TXVLTC [2:1]
TXETHF [0]
TXP IPv6 Header Exists. 1 = included; 0 = not included.
TXP IPv4 Header Exists. 1 = included; 0 = not included.
TXP VLAN Tag Count specifies # VLAN tags in the header (valid values = 0, 1 or 2).
TXP Ethernet Header Format. 0 = DIX/Ethernet II format; 1 = IEEE 802.2 LLC/SNAP.
The S132 automatically generates TXP SAT/CES/Clock Only packets when sufficient data has been received from
the TDM Port to satisfy the B.BCDR1.PMS (effective payload size) and B.BCDR3.TXBTS (payload type) settings.
All SAT/CES/Clock Only Bundles must be assigned at least one Timeslot (B.BCDR2.ATSS and TSAn.m).
B.BCDR3.TXPMS selects whether the packet stream for the TXP Bundle is disabled, transmitted without payload
(Clock Only) or transmitted with payload (normal).
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TXP SAT/CES/Clock Only Packets can optionally include an RTP Timestamp using the RTP Exists field in the TXP
Header Descriptor Header Control (RTP is not commonly used with HDLC Bundles).
A TXP HDLC packet is generated for each HDLC packet that is received from the TDM Port with a correct HDLC
FCS value. The HDLC packet encoding is removed before the TXP Header is appended. HDLC packets that are
received with bad HDLC FCS values are discarded. HDLC TXP Packet transmission can be enable/disabled using
B.BCDR3.TXPMS.
The IP Length, IP FCS, UDP Length and UDP FCS fields are auto generated for SAT, CES, HDLC and Clock Only
packets when these fields are enabled by the TXP Header Descriptor Header Control.
9.3.3.1.1 L-bit Signaling
The L-bit in the Control Word of a PW packet can be used to indicate, across the PSN, when the data contained in
a TDMoP PW payload may be corrupted (e.g. for a T1/E1 LOS condition, L-bit = 1). The Pn.PRCR1.LBSS register
selects whether the L-bit in each TXP Packet is controlled on a “per-Bundle basis” using the TXP Header
Descriptor or on a “per-TDM Port basis” using Pn.PRCR1.LB. When the “per-Bundle” method is selected, the CPU
must modify all of the programmed TXP Header Descriptors that are associated with a TDM Port that requires an L-
bit change. When the “per-TDM Port” method is selected, changing Pn.PRCR1.LB changes the L-bit value in all
TXP Packets for that TDM Port.
The standards allow TXP SAT/CES PW packets, to optionally truncate/remove the payload section when the TXP
L-bit = 1 to save network bandwidth during receive TDM fault conditions (detected by the external TDM Port
Framer/LIU). B.BCDR3.TXPMS can be programmed to “transmit without payload”, so that the TXP Bundle packet
transmit rate does not change but with a smaller packet size (like that of a Clock Only packet).
9.3.3.2 TXP CPU Packet Generation
The generation of TXP Bundle packets is described in the “TXP CPU Packet Interface” section.
9.3.3.3 TXP Packet Scheduling
The transmit PDV for Bundles that are used for clock recovery can be minimized to improve the clock recovery
performance at the far end by programming the TXP Bundle with the high scheduling priority (B.BCDR3.TXBPS)
and, for networks that support VLAN CoS, by assigning a high P-bit priority in the VLAN tag (the P-bit value is
provided by the CPU in the TXP Header Descriptor; high priority packets are processed before low priority
packets). Bundles that can be used for Clock Recovery include SAT/CES Bundles with payload and Clock Only
Bundles without payload. The TXP Clock Only Bundle is designed to provide the best possible transmit PDV and
latency by suppressing the payload. HDLC Bundles should normally be assigned low priority (B.BCDR3.TXBPS).
9.3.3.4 TXP Packet Queue Monitoring
The TXP Packet Queue fill levels can be monitored using the G.TPISR1 (TXP Bundle High Priority Queue),
G.TPISR2 (TXP Bundle Low Priority Queue) and G.TPISR3 (TXP CPU Queue) registers. Each of these queues
also provides a maskable interrupt using G.TPISRL.HPQOSL, G.TPISRL.LPQOSL and EMA.WSRL1.WFOSL.
9.4 CPU Packet Interface
•
•
•
•
Up to 512 stored RXP CPU packets
RXP CPU packet size up to 2000 bytes
RXP Local Timestamp
•
•
•
Up to 512 stored TXP CPU packets
TXP CPU packet size up to 2000 bytes
TXP RTP (OAM) Timestamp generation
RXP Packet Classification Results
RXP CPU Packets that are received from the Ethernet Port are stored in an SDRAM RXP CPU Queue for the CPU
to Read. The CPU Writes TXP CPU Packets into an SDRAM TXP CPU Queue that are later transmitted at the
Ethernet Port. The depth of the RXP CPU FIFO and TXP CPU Queues are programmed at EMI.BMCR3.PRSO and
EMI.BMCR3.PRSO.
9.4.1 RXP CPU Packet Interface
RXP CPU Packets that are received at the Ethernet Port are stored in 2 Kbyte slots in the SDRAM RXP CPU
Queue. The S132 stores an RXP CPU Header Descriptor with each RXP CPU packet to provide information about
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the CPU Packet. The format of the packet and Header Descriptor are provided in Figure 9-26 and Table 9-12
through Table 9-14.
Figure 9-26. Stored RXP CPU Packet
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
3-Dword RXP Header Descriptor
2-bytes of Dummy Fill = 0x00.00 Entire RXP CPU packet from …
… the Ethernet Destination Address to the end of Ethernet Payload but not including the Ethernet FCS
Table 9-12. RXP CPU Header Descriptor – 1st Dword
Field
Bit [x:y]
Description
RXP Packet Length. The length (in bytes) of the complete RXP CPU Packet from the
RXPLEN [31:21]
Ethernet DA to the end of the Ethernet Payload (not including the Ethernet FCS).
RXP Non-Bundle Packet. 0 = packet matches a Bundle; 1 = not a packet for a Bundle.
RXNBP [20]
Reserved.
RSVD
RXRE
RSVD
TBN
[19:11]
[10]
RXP RTP Exists. 1 = RTP Header is included.
Reserved.
[9:8]
TDM Bundle Number. When RXNBP = 0, these bits identify the Bundle Number.
[7:0]
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Table 9-13. RXP CPU Header Descriptor – 2nd Dword
Field
Bit [x:y]
Description
Reserved.
RSVD
[31:30]
RXP IPv6 packet. 1 = IPv6 Header; 0 = not IPv6.
RXP IPv4 packet. 1 = IPv4 Header; 0 = not IPv4.
RXP MEF OAM packet. 1 = MEF OAM Header; 0 = not MEF OAM.
RXIPV6 [29]
RXIPV4 [28]
RXMO
RXIVO
[27]
[26]
RXP In-band VCCV OAM packet. 1 = In-band VCCV Header; 0 = not In-band VCCV.
RXP MPLS Label Count. 1 = number of outer MPLS labels.
RXP LLC/SNAP Format. 1 = IEEE 802.2 LLC/SNAP Header; 0 = not LLC/SNAP.
RXP DIX Format. 1 = DIX Header; 0 = not DIX.
RXMLC [25:24]
RXLSF
RXDF
RSVD
[23]
[22]
[21]
Reserved.
RXP L2TPv3 packet. 1 = L2TPv3 Header; 0 = not L2TPv3.
RXP 2 VLAN Tagged packet. 1 = 2 VLAN tags in header; 0 = does not have 2 tags.
RXP VLAN Tagged packet. 1 = 1 or 2 VLAN tags in header; 0 = no VLAN tags.
RXP UDP packet. 1 = UDP Header; 0 = not UDP.
RXL2TP [20]
RX2VT
RXVT
[19]
[18]
RXUDP [17]
RXIP [16]
RXP IP packet. 1 = IPv4 or IPv6 Header; 0 = not IPv4 or IPv6.
RXP MEF packet. 1 = MEF Header; 0 = not MEF.
RXMEF [15]
RXMPLS [14]
RXP MPLS packet. 1 = MPLS Header; 0 = not MPLS.
Reserved.
RSVD
[13:11]
RXP MPLS Label Error. 1 = more than 3 MPLS labels; 0 = not more than 3 labels.
RXP Unknown Ethernet DA. 1 = unknown Ethernet DA; 0 = recognized Ethernet DA.
RXP CPU Ethernet Type. 1 = “CPU Destination” Ethernet Type.
RXP Out-band VCCV OAM. 1 = Out-band VCCV Header (matches OAM BID).
RXP Unknown PW. 1 = packet with a PW Header Type but with unknown PW-ID.
RXP Unknown UDP Protocol. 1 = UDP with unknown UDP protocol.
RXP Unknown IP Protocol. 1 = IP with unknown IP protocol.
RXP Recognized ARP packet. 1 = ARP Ethernet Type with recognized IP DA.
RXP Unknown Ethernet Type. 1 = unknown Ethernet Type
RXP Unknown IP DA. 1 = IP with unknown DA
RXMLE [10]
RXUEDA [9]
RXCET [8]
RXOVO [7]
RXUPW [6]
RXUUP [5]
RXUIPP [4]
RXRARP [3]
RXUET [2]
RXUIPA [1]
RXUARP [0]
RXP Unknown ARP packet. 1 = ARP Ethernet Type with unknown IP DA.
Table 9-14. RXP CPU Header Descriptor – 3rd Dword
Field
Bit [x:y]
Description
RXP Local Timestamp. 32-bit Timestamp with 100 us or 1 us resolution (G.GCR.OTRS),
RXLTS
[31:0]
latched at the time the packet is received by the Packet Classifier.
The RXP Local Timestamp may be used by the CPU for OAM Timestamp purposes (not for clock recovery).
RXP CPU Packets are first stored in the SDRAM RXP CPU Queue. The CPU controls the transfer of each RXP
CPU packet to an internal staging RXP CPU FIFO that the CPU can read from. The FIFO holds one RXP CPU
Packet at a time. The RXP CPU Queue can hold up to 512 packets (each 2Kbyte slot of the RXP CPU Queue is
reserved for one packet).
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The CPU process of Reading the RXP CPU packets can be polling based using the EMA.RSR1.RFRS status bit or
interrupt driven using the EMA.RSRL1.RFRSL (latched status) and EMA.RSRIE1.RFRIE (Interrupt enable) register
bits. When the CPU detects that a packet is waiting in the RXP CPU FIFO, the CPU must specify the read
operation (EMA.RCR.RPCRC = 110b), specify the read transfer length in Dwords (EMA.RCR.TL) and then begin
reading the data at EMA.RDR.EMRD. The EMA.RCR.TL value specifies how many Dwords are transferred from
the RXP CPU Queue to the RXP CPU FIFO.
The smallest possible RXP Packet Read is 19 Dwords for a 64-byte Ethernet Packet with the 4-byte FCS removed,
3-Dword Header Descriptor and 2-byte Dummy Fill appended to the beginning of the packet. The initial Transfer
Length for each packet can be any value from 1 to 18. The first Dword of the Header Descriptor that is Read by the
CPU identifies the length of the RXP CPU Packet. This is used to determine how many remaining Dwords must be
transferred from the RXP CPU Queue to the RXP CPU FIFO and then Read by the CPU. Each successive Read
Transfer at EMA.RDR.EMRD causes the S132 to update the register with the next Dword in the RXP CPU FIFO.
The EMA.RSR1, EMA.RSR2, EMA.RSRL1 and EMA.RSRIE1 registers provide other control and status bits for the
SDRAM RXP CPU Queue and the RXP CPU FIFO.
9.4.2 TXP CPU Packet Interface
The CPU writes each TXP CPU packet into an S132 staging TXP CPU FIFO and then controls the Writing
(transfer) of the packet to the TXP CPU Queue in the SDRAM. The TXP CPU FIFO can hold 1 packet. The TXP
CPU Queue can hold up to 512 packets. The S132 transmits each packet in the TXP CPU Queue when the
Ethernet Port is not busy transmitting PW packets.
The TXP CPU packets from the CPU must include all of the fields that will be transmitted at the Ethernet Port
including the Ethernet and Application Headers, but not including the Ethernet FCS. Each TXP CPU packet can be
2 Kbytes in length. The CPU must also append a TXP Header Descriptor to the beginning of each packet with
information about the packet. The format of the packet and TXP Header Descriptor are provided in Figure 9-27.
Figure 9-27. Stored TXP CPU Packet and Header Descriptor
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
1 Dword - Header Control
2-bytes of Dummy Fill = 0x00.00
… the Ethernet Destination Address to the end of Ethernet Payload but not including the Ethernet FCS
Entire TXP CPU packet from …
The TXP CPU Header Control is a single 32-bit Dword as depicted in Table 9-15.
Table 9-15. TXP CPU Header Control
Field
Bit [x:y]
Description
TXP Packet Length. The length (in bytes) of the complete TXP CPU Packet from the
TXPLEN [31:21]
Ethernet DA to the end of the Ethernet Payload (not including the Ethernet FCS).
TXP OAM Timestamp Offset = Dword position for TXP OAM Timestamp in Ethernet packet.
TXOTSO [20:12]
TXOTSO = (“Timestamp starting byte position in Ethernet packet” - 2) ÷ 4
TXP OAM Timestamp Enable. 1 = insert TXP OAM Timestamp; 0 = disabled.
TXOTSE [11]
TXP UDP/IP Application Offset = Dword position of IP Header in Ethernet packet.
TXAOFF [10:6]
TXAOFF = (“IP Header starting byte position in Ethernet packet” - 2) ÷ 4
TXP UDP Header FCS Modify Enable. 1 = insert UDP FCS (only valid if TXIPV4 = 1 or
TXUDP [5]
TXIPV6 = 1).
TXP IPv6 Header Exists. 1 = header includes IPv6; 0 = not IPv6.
TXP IPv4 Header Exists. 1 = header includes IPv4 (S132 will insert IP FCS); 0 = not IPv4.
Reserved.
TXIPV6 [4]
TXIPV4 [3]
RSVD
[2:0]
The S132 can be programmed to add a 32-bit TXP OAM Timestamp to a TXP CPU Packet. One example use for
the TXP OAM Timestamp is described in RFC5087 Appendix D (TDMoIP Performance Monitoring Mechanisms).
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When TXOTSE is enabled, TXOTSO identifies the OAM Timestamp Dword position in the packet. The CPU must
make the initial OAM Timestamp value 0x0000 in the packet stored in the TXP CPU FIFO. The S132 overwrites
that position with the current OAM Timestamp value as the packet is being transmitted at the Ethernet Port.
The S132 uses the ETHCLK signal to generate the TXP OAM Timestamps. The TXP OAM Timestamp Resolution
can be programmed for 1 us or 100 us using G.GCR.OTRS.
The OAM Timestamp can only be positioned on Dword boundaries within the Application Header. Because
Ethernet Headers do not commonly include an integer number of Dwords, the Application Header is commonly
offset by 2 bytes in the Ethernet packet, as depicted in Figure 9-25 (Ethernet packets do not include the “dummy”
bytes depicted in this figure). If the OAM Timestamp position is referenced instead to the beginning of the Ethernet
packet, some example OAM Timestamp byte positions are 46, 50, 54 (etc.), which would equate to TXOTSO
Dword = 11, 12 , 13 (etc.; respectively).
When a TXP CPU Packet uses the IPv4 protocol, the S132 can be programmed to assist with the generation of the
IPv4 Header FCS. The CPU must pre-calculate and include an IP FCS for all of the fields of the IP Header but the
IP Total Length field. The S132 modifies the IP FCS on-the-fly to include the IP Total Length. This allows the CPU
to store a “generic” pre-calculated IP FCS with each stored IP Header in CPU memory. The CPU pre-calculates the
IP FCS for the IP Header beginning with the IP Version field and ending with the IP Destination Address, but using
“0” values in the IP Total Length and IP Header FCS fields. The IPv6 Header does not include an FCS.
When a TXP CPU Packet uses the UDP/IP protocol, the S132 can be programmed to assist with the generation of
the FCS in the UDP Header. The CPU must include a UDP FCS for all but the IP length and UDP length fields. The
CPU pre-calculates the UDP FCS with a Pseudo IP Header that is added to the beginning of the UDP packet
(added only for this UDP FCS calculation) and including the entire UDP packet (from UDP Source Port to the end
of the UDP Payload; per RFC768), but calculates with “0” values in the “UDP Length” field of the Pseudo IP
Header, the ”Length” field of the UDP Header and the “Checksum” field of the UDP Header. The S132 modifies the
pre-calculated UDP FCS on-the-fly to include the lengths. This function can be used when the S132 is programmed
to add a TXP OAM Timestamp.
If the S132 FCS functions are not needed, then the CPU should not identify the packet as IPv4 or UDP (so that the
S132 does not modify the FCS values) and the CPU must include the IP and UDP FCS values for transmission.
All of these functions can be enabled at the same time or in various combinations as identified in Table 9-16. When
the CPU is ready the CPU writes the entire TXP CPU Packet including the pre-calculated FCS values, the “real”
packet length values and TXP OAM Timestamp = “0” (when applicable). For example, when TXOTSO = 1, TXUDP
= 1 and TXIPV4 = 1 (Add TXP OAM Timestamp & Re-calculate UDP FCS & IPv4 FCS), the CPU provides the
entire CPU packet (from Ethernet DA to the end of the Ethernet Payload) including the IP Total Length field (to
indicate the size of the IP packet), the pre-calculated IP FCS, the UDP Length field (to indicate the size of the UDP
packet), the pre-calculated UDP FCS and the “0” value in the TXP OAM Timestamp position. The S132 then
overwrites with the TXP OAM Timestamp and corrects the IP FCS and UDP FCS values.
Table 9-16. Modify FCS and Add TXP OAM Timestamp Functions
Application
TXOTSE TXUDP TXIPV6 TXIPV4
Re-calculate IPv4 FCS to include Length
0
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
0
1
0
For IPv4: Re-calculate UDP FCS & IPv4 FCS to include Length
For IPv6 packets: Re-calculate UDP FCS to include Length
Add TXP OAM Timestamp to any protocol (with no FCS modifications)
For IPv4: Add TXP OAM Timestamp & Re-calculate UDP FCS & IPv4 FCS
For IPv6: Add TXP OAM Timestamp & Re-calculate UDP FCS
The Write TXP CPU Packet process can be polling based using the EMA.WSR1.WFES status bit or interrupt driven
using the EMA.WSRL1.WFESL (latched status) and EMA.WSRIE1.WFEIE (Interrupt enable) register bits. When
the CPU is ready to Write a TXP CPU Packet into the TXP CPU FIFO, the CPU should begin by verifying that the
TXP CPU FIFO is empty (read the FIFO status at EMA.WSR1.WFES or flush the FIFO with EMA.WCR.TPCWC =
3). The CPU then Writes the Dwords for the packet at EMA.WDR.EMWD. Each successive Write at
EMA.WDR.EMWD fills the next Dword position in the FIFO. When the entire packet has been stored in the TXP
CPU FIFO the CPU must indicate the length of the packet (EMA.WCR.TL), how many packet bytes are included in
the last Dword (EMA.WCR.TLBE) and indicate that the packet should be transferred to the TXP CPU Queue in the
SDRAM (EMA.WCR.TPCWC = 6). When the complete packet has been transferred to the TXP CPU Queue,
EMA.WSR1.WFES will indicate that the FIFO is empty.
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The EMA.WSR1, EMA.WSR2, EMA.WSRL1 and EMA.WSRIE1 registers provide other control and status bits for
the TXP CPU FIFO and the SDRAM TXP CPU Queue.
9.5 Clock Recovery Functions
The S132 includes a DSP to implement its Clock Recovery functions. The Clock Recovery functions include the
RXP and TXP PW-Timing functions. The DSP is controlled by firmware code. The firmware code must be
downloaded to the S132 each time a global reset is initiated (e.g. after power up). In addition to the firmware code,
the Clock Recovery functions must be programmed using the CR. Registers. The CR. Registers enable the PW-
Timing functions to be configured according to each PW application (e.g. DCR-DT vs. ACR). The functionality of
the firmware and its configuration registers is defined in an independent S132 Firmware Definition document.
9.6 Miscellaneous Global Functions
9.6.1 Global Resets
A Global Reset can be implemented using G.GRCR.RST or the RST_N pin.
9.6.2 Latched Status and Counter Register Reset
The S132 provides Latched Status register bits so that the CPU can discover transient events that might otherwise
be missed by a simple “real-time” status register. Programming the G.GCR.LSBCRE register selects whether to
clear (restore to the default value) the Latched Status bits automatically when the CPU Reads the Latched Status
register, or to wait until the CPU performs an explicit Write operation to over-write the Latched Status value.
The G.GCR.CCOR bit selects whether the “Clear on Read” function is enabled for the RXP Bundle Counts, TXP
Bundle Counts and Packet Classifier Counts or whether the “Clear on Read” function for these registers is disabled
(the counters roll over after they reach their maximum value).
9.6.3 Buffer Manager
The Buffer Manager controls and monitors the SDRAM that stores the Bundle and RXP/TXP CPU Queues and the
TXP Header Descriptors. The Buffer Manager environment is depicted in Figure 9-28.
Figure 9-28. Buffer Manager Environment
To SDRAM
DS34S132
RXP/TXP
SAT/CES Engines
TXP Pkt
Generator
SAT/CES Connections
HDLC Connections
Buffer
Manager
RXP/TXP
HDLC Engines
RXP Pkt
Classifier
CPU Connections
To external CPU
The starting addresses for the Queues and TXP Header Descriptor section are programmed using the EMI
registers. Each address is a 16-bit address that indexes a 2 Kbyte segment of SDRAM memory (2^16 x 2 Kbyte = 1
Gbit). For a smaller SDRAM size the address bit-width is reduced (e.g. a 512 Kbit SDRAM uses 15-bit addressing).
The programmed starting addresses are programmed using the following queue depth equations. The “Register
Guide” section provides example settings that can be used in most applications.
RXP CPU Queue:
TXP CPU Queue:
TXP Header Descriptors:
16384 * maximum # of RXP CPU Packets
16384 * maximum # of TXP CPU Packets
1024 * maximum # of BIDs
TXP Bundle Payload Queues:
131072 * maximum # of BIDs
RXP Bundle Jitter Buffer Queues: G.GCR.JBMD setting in Kbytes * maximum # BIDs
Total SDRAM storage area:
sum of all of the above
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9.6.3.1 SDRAM Interface
The S132 has been designed to work with DDR-SDRAM devices that are compatible with the JEDEC JESD79C
standard and that support 2-2-2 timing with a clock rate of at least 125 MHz. Table 9-17 identifies several SDRAM
device sizes that can be used to support different Jitter Buffer Depth/Bundle Count combinations.
Table 9-17. SDRAM Device Selection Table
Single SDRAM Device Description
Qty SDRAM Total SDRAM Max Configurable Values
Devices per bits per
Array
Size
Data
Width
Bundle
Count
Jitter Buffer
Depth (JBMD)
Targeted Vendor Part #1
DS34S132
DS34S132
Micron MT46V32M16P-6T or
Samsung K4H511638B-TCB3
512 Mb 16 bit
512 Mb 16 bit
2
1 Gbit
256
256 Kbyte
128
256
64
256 Kbyte
128 Kbyte
256 Kbyte
128 Kbyte
64 Kbyte
256 Kbyte
128 Kbyte
64 Kbyte
32 Kbyte
Micron MT46V32M16P-6T or
Samsung K4H511638B-TCB3
1
1
512 Mbit
256 Mbit
256 Mb 16 bit Micron MT46V16M16P-75E
128
256
32
64
128 Mb 16 bit Micron MT46V8M16P-75E
1
128 Mbit
128
256
1
Note:
These SDRAM vendor parts are targeted for use with the S132. Compatibility with these parts has not yet been fully
verified.
The external SDRAM is used by many of the S132 processes so the SDRAM interface should be configured before
any of the TDM or Ethernet Ports are enabled. The SDRAM column width, memory size and control functions must
be programmed (EMI.DCR2 and EMI.DCR3) to match to the DDR SDRAM that is used. EMI.DCR1.DIR should be
used to reset the SDRAM after changing the EMI.DCR2 and EMI.DCR3 settings.
The SDRAM clock must be 125 MHz and can be derived from the ETHCLK or DDRCLK (G.GCR.ECDC).
9.6.4 CPU Electrical Interconnect
The CPU interface is used to program the S132, to transmit and receive CPU Packets (to/from the Ethernet Port)
and to monitor the various status and interrupt signals from the S132. The CPU interface supports two processor
interface types, one to work with processors like the Freescale MPC870 (depicted in Figure 9-29) and the other to
work with processors like the Freescale MPC8313 (depicted in Figure 9-30 and Figure 9-31). The MPC8313 style
processor supports a non-multiplexed and multiplexed mode, which determines whether the S132 PA[13:10]
signals are connected to the processor address or data bus.
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Figure 9-29. MPC870 32-bit Bus Interface
VDD33
MPC870
DS34S132
PALE
PWIDTH
PTA_CTRL
PWRCTRL
LCLK
LCSn
LBCTL
LGTA
IRQn
SYSCLK
PCS_N
PRW
PTA_N
PINT_N
LA[12]
LA[13]
LA[14]
LA[15]
LA[16]
LA[17]
LA[18]
LA[19]
LA[20]
LA[21]
LA[22]
LA[23]
LA[24]
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PD[31]
PD[30]
PD[29]
PD[28]
PD[27]
PD[26]
PD[25]
PD[24]
PD[23]
PD[22]
PD[21]
PD[20]
PD[19]
PD[18]
PD[17]
PD[16]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[20]
D[21]
D[22]
D[23]
D[24]
D[25]
D[26]
D[27]
D[28]
D[29]
D[30]
D[31]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
The MPC870 and MPC8313 are processor products of Freescale Semiconductor, Inc.
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DS34S132 DATA SHEET
Figure 9-30. MPC8313, Non-multiplexed Bus Interface
Figure 9-31. MPC8313, Multiplexed Bus Interface
VDD33
MPC8313
MPC8313
DS34S132
PALE
DS34S132
PALE
LALE
PWIDTH
PTA_CTRL
PWRCTRL
VSS
PWIDTH
PTA_CTRL
PWRCTRL
VSS
LCLK
LCSn
LBCTL
LGTA
IRQn
SYSCLK
PCS_N
PRW
PTA_N
PINT_N
LCLK
LCSn
LBCTL
LGTA
IRQn
SYSCLK
PCS_N
PRW
PTA_N
PINT_N
LA[12]
LA[13]
LA[14]
LA[15]
LA[16]
LA[17]
LA[18]
LA[19]
LA[20]
LA[21]
LA[22]
LA[23]
LA[24]
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
PA[13]
PA[12]
PA[11]
PA[10]
PA[9]
PA[8]
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
LA[16]
LA[17]
LA[18]
LA[19]
LA[20]
LA[21]
LA[22]
LA[23]
LA[24]
PD[31:16]
PD[31:16]
Not
Not
used
used
LAD[0]
LAD[1]
LAD[2]
LAD[3]
LAD[4]
LAD[5]
LAD[6]
LAD[7]
LAD[8]
LAD[9]
LAD[10]
LAD[11]
LAD[12]
LAD[13]
LAD[14]
LAD[15]
LAD[0]
LAD[1]
LAD[2]
LAD[3]
LAD[4]
LAD[5]
LAD[6]
LAD[7]
LAD[8]
LAD[9]
LAD[10]
LAD[11]
LAD[12]
LAD[13]
LAD[14]
LAD[15]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
PD[15]
PD[14]
PD[13]
PD[12]
PD[11]
PD[10]
PD[9]
PD[8]
PD[7]
PD[6]
PD[5]
PD[4]
PD[3]
PD[2]
PD[1]
PD[0]
9.6.5 Interrupt Hierarchy
The S132 includes a 3-level hierarchical interrupt system for interrupting the CPU. There are more than 700
conditions that can generate an interrupt on PINT_N. The 3-level hierarchy enables the CPU to discover any active
interrupt condition with no more than 3 register reads.
The Level 3 Latched Status registers are the lowest level registers in the hierarchy and indicate when an interrupt
condition has been detected. The latched bits insure that the CPU does not “miss” transient interrupt conditions.
Real-time Status Register indications are also provided for some of the Level 3 Interrupt Conditions.
The Level 2 Status registers (G.GSR4, G.GSR5 and G.GSR6) are used to combine 640 latched active Level 3
interrupt conditions into Level 2 group status indications. The Level 3 registers that are combined are B.GxSRL,
JB.GxSRL, G.PTSRL and G.PRSRL. Each Level 2 bit indicates if any of its “group member” (Level 3 Latched
register) bits are enabled and are indicating an active interrupt event has been detected.
The Level 1 Interrupt register, G.GSR1, combines the remaining Level 3 Latched register indications with the Level
2 group status indications so that that the CPU can read one register (G.GSR1) to monitor all latched, active Level
3 interrupt conditions. These Level 1 and Level 2 register bits are real-time (non-latched) bits to indicate when any
enabled Level 3 latched interrupt condition is active.
The Level 1 interrupt register, G.TPISRL, provides latched indications for each of its interrupt conditions. There are
no Level 3 or Level 2 registers associated with these interrupt conditions.
One Interrupt Enable bit is provided for each of the latched interrupt register bits and for each of the Level 1, real-
time G.GSR1 register indications so that any number or combination of the interrupt conditions can be disabled
from generating an interrupt toward the CPU. When any latched register bit indicates that an active interrupt was
detected (1), that latched bit is enabled, and its associated Level 1 register bit is enabled, the S132 will generate an
active Interrupt signal (0) toward the CPU on PINT_N. The inactive state for PINT_N signal can be programmed to
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DS34S132 DATA SHEET
be high impedance or logic 1 using G.GCR1.IIM. Table 9-18 identifies the interrupt functions and how they relate to
each other.
Table 9-18. Interrupt Hierarchy
Monitor Function
Level 3 Interrupt Condition Registers
Level 2 Group Registers Level 1 – Global Register bits
G.GSR1 Interrupts
Ethernet Port BERT
TDM Port BERT
TXP packet CAS
Xmt TDM Port CAS
Ethernet MAC
Status
EB.BSR
DB.BSR
NA
Latched Status Interrupt Enable Status Latched Status G.GSR1 Status G.GSRIE Enable
EB.BSRL
DB.BSRL
G.GSR2
G.GSR3
EB.BSRIE
DB.BSRIE
G.GSRIE2
G.GSRIE3
NA
NA
NA
NA
NA
NA
NA
NA
NA
EBS
EBIE
DBS
DBIE
PTCS
PRCS
MIRS
PTCIE
PRCIE
MIRIE
NA
NA
M.IRQ_STATUS M.IRQ_ENABLE NA
M.IRQ_DISABLE
Clock Recovery Engines (note 1)
(note 1)
(note 1)
(note 1)
(note 1)
CRHS
BS
CRHIE
BIE
Control Word
NA
NA
NA
NA
NA
NA
B.GxSRL
JB.GxSRL
G.PTSRL
G.PRSRL
PC.SRL
B.GxSRIE
JB.GxSRIE
G.PTSRIE
G.PRSRIE
PC.SRIE
G.GSR5 NA
G.GSR6 NA
Jitter Buffer Underrun
Underrun/ Frame Align
Overrun/ Frame Align
Packet Classifier
JBS
PS
JBIE
PIE
NA
G.GSR4
NA
NA
NA
NA
NA
NA
NA
NA
PCS
PCIE
SDRAM Queue Error
EMI.BMSRL
EMI.BMSRIE
EMA.WSRIE1
EMA.RSRIE1
EMIS
EMIIE
TXP CPU FIFO & Queue EMA.WSR1 EMA.WSRL1
RXP CPU FIFO & Queue EMA.RSR1 EMA.RSRL1
EMAWS
EMARS
EMAWIE
EMARIE
G.TIPSRL Interrupts
Status
NA
Latched Status Interrupt Enable Status
Latched Status G.TPISRL
G.TPISRIE
HPQOSIE
LPQOSIE
High Priority Overflow
NA
NA
NA
NA
NA
NA
NA
NA
HPQOSL
LPQOSL
Low Priority Overflow
NA
1
Notes:
The Clock Recovery Engine interrupts are specified by the DSP firmware load (not included here).
Figure 9-32 depicts the interrupt hierarchy using an example “Monitor Function A” (e.g. Monitor Function “A” = “Rcv
TDM Port CAS Change”). The “[x:y]” notation means “[Group:Member]”. Some Monitor Functions have only one
“group” so the Level 3 “OR” output would be connected directly to the Level 1 “AND” input (the Level 2 Status is
“NA = Not Applicable” and there is no Level 2 OR gate). Some of the Status signals are latched (Latched Status)
and others are not as indicated in Table 9-18. When a Status is provided, but without a “Latched Status” signal, the
non-latched, Status bypasses the “latch” function in Figure 9-32. In this case the Status connects directly to the
next logic element (OR gate or AND gate) in the interrupt hierarchy (e.g. the Level 2, G.GSR5 Status register bits
are ORed together bypassing the latch function in the diagram). The G.TIPSRL interrupts are not driven by any
lower level conditions. All G.TIPSRL conditions are Latched Status and connect directly to the Level 1 “OR”.
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Figure 9-32. Interrupt Hierarchy Diagram
G.GSR1 Level 3
G.GSR1 Level 2
Function "A"
G.GSR1 Level 1
Latched
Status[0:0]
Status[0:0]
Level 2 Group 0
Status
Function "A"
Level 2 Group 0
Latched Status
Monitor Function "A" [0,0] Latch
Latched
Status[0:y]
Monitor Function "A" [0,y]
Latch
Status[0:y]
bypass
Latch
Function "A"
Level 1
Monitor Function "A" [0,0] Interrupt En
Status bit
Monitor Function "A" [0,y] Interrupt En
Status[x:0]
Latched
Status[x:0]
Monitor Function "A" [x,0]
Latch
bypass
Latch
Latched
Status[x:y]
Status[x:y]
Monitor Function "A" [x,y]
Function "A"
Level 2 Group 0
Latched Status
Latch
Function "A"
Level 2 Group x
Status
Monitor Function "A" [x,0] Interrupt En
Monitor Function "A" [x,y] Interrupt En
G.GSR1 Status bit
Monitor Function
"A" Interrupt
G.GSR1 Status bit Monitor Function "A" Interrupt Enable
Interrupt Conditions for other
G.GSR1 Monitor Functions
CPU
Interrupt
CPU Interrupt (PINT_N) Output
G.TPISRL Level 1
PINT_N
HPQOSL
High Priority Queue Overflow
Latch
Latch
High Priority Queue Overflow Interrupt Enable
LPQOSL
Low Priority Queue Overflow
Low Priority Queue Overflow Interrupt Enable
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10
DEVICE REGISTERS
10.1 Register Block Address Ranges
Table 10-1. Register Block Address Ranges
Registers
Address Range
Global Registers
Global Configuration Registers (G.)
Global Status Registers (G.)
0000h – 002Fh
0030h – 005Fh
0060h – 007Fh
Global Status Register Interrupt Enables (G.)
Individual Bundle and Jitter Buffer Registers
Global Bundle Reset Registers (B.)
Global Bundle Data Control Registers (B.)
Global Bundle Data Registers (B.)
Bundle Group Status Latch Registers (B.)
Bundle Group Status Register Interrupt Enables (B.)
Jitter Buffer Status Registers (JB.)
Jitter Buffer Status Register Interrupt Enables (JB.)
Packet Classifier Registers
0080h – 008Fh
0094h – 00A3h
00A4h – 00EFh
0100h – 017Fh
0180h – 01FFh
0200h – 027Fh
0280h – 02FFh
Packet Classifier Configuration Registers (PC.)
Packet Classifier Status Register Latches (PC.)
Packet Classifier Status Register Interrupt Enables (PC.)
Packet Classifier Counter Registers (PC.)
SDRAM Interface and Access Registers
External Memory Interface Configuration Registers (EMI.)
External Memory Interface Status Registers (EMI.)
External Memory Interface Status Register Interrupt Enables (EMI.)
External Memory DLL/PLL Test Registers (EMI.)
Write Registers (EMA.)
0300h – 035Fh
0360h – 0367h
0368h – 036Fh
0370h – 037Fh
0380h – 039Fh
03A0h – 03AFh
03B0h – 03B7h
03B8h – 03BFh
03C0h – 03DFh
03E0h – 03FFh
Read Registers (EMA.)
Test, Diagnostics and Clock Registers
Encap BERT Registers (EB.)
Decap BERT Registers (DB.)
Miscellaneous Diagnostic Registers (MD.)
Test Registers (TST.)
Clock Recovery Registers (CR.)
0400h – 043Fh
0440h – 047Fh
0480h – 04AFh
0600h – 067Fh
0800h – 0BFFh
Ethernet MAC Registers
MAC Registers (M.)
0C00h – 0DBFh
Per Port Registers
Port n TXP SW CAS Registers (TXSCn.; n = 0 to 31)
Port n Xmt (RXP) SW CAS Registers (RXSCn. ; n = 0 to 31)
Port n Transmit Configuration Registers (Pn.; n = 0 to 31)
Port n Transmit Status Registers (Pn.; n = 0 to 31)
Port n Transmit Status Register Latches (Pn.; n = 0 to 31)
Port n Transmit Status Register Interrupt Enables (Pn.; n = 0 to 31)
Port n Receive Configuration Registers (Pn.; n = 0 to 31)
Port n Receive Status Registers (Pn.; n = 0 to 31)
Port n Receive Status Register Latches (Pn.; n = 0 to 31)
Port n Receive Status Register Interrupt Enables (Pn.; n = 0 to 31)
Time Slot Assignment Registers (TSAn.m.; n = 0 – 31; m = 0 – 31)
1000h – 11FFh
1200h – 13FFh
2000h – 2FFFh
3000h – 4000h
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10.2 Register Address Reference List
Table 10-2. Register Address Reference List
Register Name
Addr (hex)
Description
Global Configuration Registers (G.)
IDR.
0000
ID Register
GCR
GRCR
CCR
0004
0008
000C
0010
0014
0018
001C
Global Configuration Register
Global Reset Control Register
CLAD Control Register
Ethernet Conditioning Configuration Register 1
Ethernet Conditioning Configuration Register 2
TDM Conditioning Configuration Register 1
TDM Conditioning Configuration Register 2
ECCR1
ECCR2
TCCR1
TCCR2
Global Status Registers (G.)
GSR1
GSR2
GSR3
GSR4
GSR5
0030
0034
0038
003C
0040
0044
0048
004C
0050
0054
0058
Global Status Register 1
Global Status Register 2
Global Status Register 3
Global Status Register 4
Global Status Register 5
Global Status Register 6
Transmit Packet Interface Status Register 1
Transmit Packet Interface Status Register 2
Transmit Packet Interface Status Register 3
Transmit Packet Interface Status Register Latches
Transmit Packet Interface Status Register Interrupt Enable
GSR6
TPISR1
TPISR2
TPISR3
TPISRL
TPISRIE
Global Status Register Interrupt Enable Registers (G.)
GSRIE1
GSRIE2
GSRIE3
0060
0064
0068
Global Status Register Interrupt Enable 1
Global Status Register Interrupt Enable 2
Global Status Register Interrupt Enable 3
Bundle Reset Registers (B.)
BRCR1
BRCR2
BRSR
0080
0084
0088
Bundle Reset Control Register 1.
Bundle Reset Control Register 2.
Bundle Reset Status Register.
Bundle Data Control Registers (B.)
BACR
BCCR
0094
Bundle Activation Control Register
Bundle Configuration Control Register
Bundle Encap Status Control Register
Bundle Decap Status Control Register
0098
009C
00A0
BESCR
BDSCR
Bundle Data Registers (B.)
BADR1
BADR2
BCDR1
BCDR2
BCDR3
BCDR4
BCDR5
BESR1
BESR2
BESR3
BDSR1
BDSR2
BDSR3
BDSR4
BDSR5
00A4
00A8
00AC
00B0
00B4
00B8
00BC
00C0
00C4
00C8
00D0
00D4
00D8
00DC
00E0
00E4
Bundle Activation Data Register 1
Bundle Activation Data Register 2
Bundle Configuration Data Register 1
Bundle Configuration Data Register 2
Bundle Configuration Data Register 3
Bundle Configuration Data Register 4
Bundle Configuration Data Register 5
Bundle Encap Status Register 1
Bundle Encap Status Register 2
Bundle Encap Status Register 3
Bundle Decap Status Register 1
Bundle Decap Status Register 2
Bundle Decap Status Register 3
Bundle Decap Status Register 4
Bundle Decap Status Register 5
Bundle Decap Status Register 6
BDSR6
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Register Name
Addr (hex)
Description
BDSR7
BDSR8
BDSR9
00E8
00EC
00F0
Bundle Decap Status Register 7
Bundle Decap Status Register 8
Bundle Decap Status Register 9
Bundle Group Status Latch Registers (B.)
G0SRL
G1SRL
G2SRL
G3SRL
G4SRL
G5SRL
G6SRL
G7SRL
0100
0104
0108
010C
0110
0114
0118
011C
0120
0124
0128
012C
0130
0134
0138
013C
0140
0144
0148
014C
0150
0154
0158
015C
0160
0164
0168
016C
0170
0174
0178
017C
Group 0 Status Register Latch
Group 1 Status Register Latch
Group 2 Status Register Latch
Group 3 Status Register Latch
Group 4 Status Register Latch
Group 5 Status Register Latch
Group 6 Status Register Latch
Group 7 Status Register Latch
Group 8 Status Register Latch
Group 9 Status Register Latch
Group 10 Status Register Latch
Group 11 Status Register Latch
Group 12 Status Register Latch
Group 13 Status Register Latch
Group 14 Status Register Latch
Group 15 Status Register Latch
Group 16 Status Register Latch
Group 17 Status Register Latch
Group 18 Status Register Latch
Group 19 Status Register Latch
Group 20 Status Register Latch
Group 21 Status Register Latch
Group 22 Status Register Latch
Group 23 Status Register Latch
Group 24 Status Register Latch
Group 25 Status Register Latch
Group 26 Status Register Latch
Group 27 Status Register Latch
Group 28 Status Register Latch
Group 29 Status Register Latch
Group 30 Status Register Latch
Group 31 Status Register Latch
G8SRL
G9SRL
G10SRL
G11SRL
G12SRL
G13SRL
G14SRL
G15SRL
G16SRL
G17SRL
G18SRL
G19SRL
G20SRL
G21SRL
G22SRL
G23SRL
G24SRL
G25SRL
G26SRL
G27SRL
G28SRL
G29SRL
G30SRL
G31SRL
Bundle Group Status Register Interrupt Enable Registers (B.)
G0SRIE
G1SRIE
G2SRIE
G3SRIE
G4SRIE
G5SRIE
G6SRIE
G7SRIE
G8SRIE
G9SRIE
G10SRIE
G11SRIE
G12SRIE
G13SRIE
G14SRIE
G15SRIE
G16SRIE
G17SRIE
0180
0184
0188
018C
0190
0194
0198
019C
01A0
01A4
01A8
01AC
01B0
01B4
01B8
01BC
01C0
01C4
Group 0 Status Register Interrupt Enable
Group 1 Status Register Interrupt Enable
Group 2 Status Register Interrupt Enable
Group 3 Status Register Interrupt Enable
Group 4 Status Register Interrupt Enable
Group 5 Status Register Interrupt Enable
Group 6 Status Register Interrupt Enable
Group 7 Status Register Interrupt Enable
Group 8 Status Register Interrupt Enable
Group 9 Status Register Interrupt Enable
Group 10 Status Register Interrupt Enable
Group 11 Status Register Interrupt Enable
Group 12 Status Register Interrupt Enable
Group 13 Status Register Interrupt Enable
Group 14 Status Register Interrupt Enable
Group 15 Status Register Interrupt Enable
Group 16 Status Register Interrupt Enable
Group 17 Status Register Interrupt Enable
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Register Name
Addr (hex)
Description
G18SRIE
G19SRIE
G20SRIE
G21SRIE
G22SRIE
G23SRIE
G24SRIE
G25SRIE
G26SRIE
G27SRIE
G28SRIE
G29SRIE
G30SRIE
G31SRIE
01C8
01CC
01D0
01D4
01D8
01DC
01E0
01E4
01E8
01EC
01F0
01F4
01F8
01FC
Group 18 Status Register Interrupt Enable
Group 19 Status Register Interrupt Enable
Group 20 Status Register Interrupt Enable
Group 21 Status Register Interrupt Enable
Group 22 Status Register Interrupt Enable
Group 23 Status Register Interrupt Enable
Group 24 Status Register Interrupt Enable
Group 25 Status Register Interrupt Enable
Group 26 Status Register Interrupt Enable
Group 27 Status Register Interrupt Enable
Group 28 Status Register Interrupt Enable
Group 29 Status Register Interrupt Enable
Group 30 Status Register Interrupt Enable
Group 31 Status Register Interrupt Enable
Jitter Buffer Status Registers (JB.)
G0SRL
G1SRL
G2SRL
G3SRL
G4SRL
G5SRL
G6SRL
G7SRL
0200
Group 0 Status Register Latch
Group 1 Status Register Latch
Group 2 Status Register Latch
Group 3 Status Register Latch
Group 4 Status Register Latch
Group 5 Status Register Latch
Group 6 Status Register Latch
Group 7 Status Register Latch
Group 8 Status Register Latch
Group 9 Status Register Latch
Group 10 Status Register Latch
Group 11 Status Register Latch
Group 12 Status Register Latch
Group 13 Status Register Latch
Group 14 Status Register Latch
Group 15 Status Register Latch
Group 16 Status Register Latch
Group 17 Status Register Latch
Group 18 Status Register Latch
Group 19 Status Register Latch
Group 20 Status Register Latch
Group 21 Status Register Latch
Group 22 Status Register Latch
Group 23 Status Register Latch
Group 24 Status Register Latch
Group 25 Status Register Latch
Group 26 Status Register Latch
Group 27 Status Register Latch
Group 28 Status Register Latch
Group 29 Status Register Latch
Group 30 Status Register Latch
Group 31 Status Register Latch
0204
0208
020C
0210
0214
0218
021C
0220
0224
0228
022C
0230
0234
0238
023C
0240
0244
0248
024C
0250
0254
0258
025C
0260
0264
0268
026C
0270
0274
0278
027C
G8SRL
G9SRL
G10SRL
G11SRL
G12SRL
G13SRL
G14SRL
G15SRL
G16SRL
G17SRL
G18SRL
G19SRL
G20SRL
G21SRL
G22SRL
G23SRL
G24SRL
G25SRL
G26SRL
G27SRL
G28SRL
G29SRL
G30SRL
G31SRL
Jitter Buffer Status Register Interrupt Enable Registers (JB.)
G0SRIE
G1SRIE
G2SRIE
G3SRIE
G4SRIE
G5SRIE
G6SRIE
0280
0284
0288
028C
0290
0294
0298
Group 0 Status Register Interrupt Enable
Group 1 Status Register Interrupt Enable
Group 2 Status Register Interrupt Enable
Group 3 Status Register Interrupt Enable
Group 4 Status Register Interrupt Enable
Group 5 Status Register Interrupt Enable
Group 6 Status Register Interrupt Enable
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Register Name
Addr (hex)
Description
G7SRIE
G8SRIE
G9SRIE
029C
02A0
02A4
02A8
02AC
02B0
02B4
02B8
02BC
02C0
02C4
02C8
02CC
02D0
02D4
02D8
02DC
02E0
02E4
02E8
02EC
02F0
02F4
02F8
02FC
Group 7 Status Register Interrupt Enable
Group 8 Status Register Interrupt Enable
Group 9 Status Register Interrupt Enable
G10SRIE
G11SRIE
G12SRIE
G13SRIE
G14SRIE
G15SRIE
G16SRIE
G17SRIE
G18SRIE
G19SRIE
G20SRIE
G21SRIE
G22SRIE
G23SRIE
G24SRIE
G25SRIE
G26SRIE
G27SRIE
G28SRIE
G29SRIE
G30SRIE
G31SRIE
Group 10 Status Register Interrupt Enable
Group 11 Status Register Interrupt Enable
Group 12 Status Register Interrupt Enable
Group 13 Status Register Interrupt Enable
Group 14 Status Register Interrupt Enable
Group 15 Status Register Interrupt Enable
Group 16 Status Register Interrupt Enable
Group 17 Status Register Interrupt Enable
Group 18 Status Register Interrupt Enable
Group 19 Status Register Interrupt Enable
Group 20 Status Register Interrupt Enable
Group 21 Status Register Interrupt Enable
Group 22 Status Register Interrupt Enable
Group 23 Status Register Interrupt Enable
Group 24 Status Register Interrupt Enable
Group 25 Status Register Interrupt Enable
Group 26 Status Register Interrupt Enable
Group 27 Status Register Interrupt Enable
Group 28 Status Register Interrupt Enable
Group 29 Status Register Interrupt Enable
Group 30 Status Register Interrupt Enable
Group 31 Status Register Interrupt Enable
Packet Classifier Configuration Registers (PC.)
CR1
CR2
CR3
CR4
CR5
CR6
CR7
CR8
0300
0304
0308
030C
0310
0314
0318
031C
0320
0324
0328
032C
0330
0334
0338
033C
0340
0344
0348
034C
0350
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5
Configuration Register 6
Configuration Register 7
Configuration Register 8
Configuration Register 9
Configuration Register 10
Configuration Register 11
Configuration Register 12
Configuration Register 13
Configuration Register 14
Configuration Register 15
Configuration Register 16
Configuration Register 17
Configuration Register 18
Configuration Register 19
Configuration Register 20
Configuration Register 21
CR9
CR10
CR11
CR12
CR13
CR14
CR15
CR16
CR17
CR18
CR19
CR20
CR21
Packet Classifier Status Latch Registers (PC.)
SRL 0360
Status Register Latch
Packet Classifier Status Interrupt Enable Registers (PC.)
SRIE
0368
Status Register Interrupt Enable
Packet Classifier Counter Registers (PC.)
CPCR
PCECR
SPCR
0370
0374
0378
Classified Packet Counter Register
IP/UDP Packet Checksum Error Counter Register
Stray Counter Register
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DS34S132 DATA SHEET
Register Name
Addr (hex)
Description
FOCR
037C
FIFO Overflow Counter Register
External Memory Interface Configuration Registers (EMI.)
BMCR1
BMCR2
BMCR3
DCR1
DCR2
DCR3
0380
0384
0388
0390
0394
0398
Buffer Manager Configuration Register 1
Buffer Manager Configuration Register 2
Buffer Manager Configuration Register 3
DDR SDRAM Configuration Register 1
DDR SDRAM Configuration Register 2
DDR SDRAM Configuration Register 3
External Memory Interface Status Registers (EMI.)
BMSRL 03A0 Buffer Manager Status Register Latch
External Memory Interface Status Interrupt Enable Registers (EMI.)
BMSRIE 03B0 Buffer Manager Status Register Interrupt Enable
External Memory Interface Test Status Registers (EMI.)
TSRL 03B4 Test Status Register Latched
External Memory DLL/PLL Test Registers (EMI.)
TCR1
TCR2
03B8
03BC
Test Configuration Register 1
Test Configuration Register 2
Write Registers (EMA.)
WCR
WAR
WDR
WSR1
WSR2
WSRL1
WSRIE1
03C0
03C4
03C8
03CC
03D0
03D4
03D8
Write Control Register
Write Address Register
Write Data Register
Write Status Register 1
Write Status Register 2
Write Status Register Latch 1
Write Status Register Interrupt Enable 1
Read Registers (EMA.)
RCR
RAR
RDR
RSR1
RSR2
RSRL1
RSRIE1
03E0
03E4
03E8
03EC
03F0
03F4
03F8
Read Control Register
Read Address Register
Read Data Register
Read Status Register 1
Read Status Register 2
Read Status Register Latch 1
Read Status Register Interrupt Enable 1
Encap BERT Registers (EB.)
BCR
BPCR
BSPR
TEICR
BSR
BSRL
BSRIE
RBECR
0400
0404
0408
0410
0414
0418
041C
0420
0424
0430
BERT Control Register
BERT Pattern Configuration Register
BERT Seed / Pattern Register
Transmit Error Insertion Control Register
BERT Status Register
BERT Status Register Latch
BERT Status Register Interrupt Enable
Receive Bit Error Count Register
Receive Bit Count Register
RBCR
TSTCR
Test Control Register
Decap BERT Registers (DB.)
BCR
0440
0444
0448
0450
0454
0458
045C
0460
0464
BERT Control Register
BPCR
BSPR1
TEICR
BSR
BSRL
BSRIE
RBECR
RBCR
BERT Pattern Configuration Register
BERT Seed / Pattern Register
Transmit Error Insertion Control Register
BERT Status Register
BERT Status Register Latch
BERT Status Register Interrupt Enable
Receive Bit Error Count Register
Receive Bit Count Register
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DS34S132 DATA SHEET
Register Name
Addr (hex)
Description
TSTCR
0470
Test Control Register
Miscellaneous Diagnostic Registers (MD.)
DCR
EBCR
DBCR
MBSR1
MBSR2
MBSR3
MBSR4
MBSR5
0480
0484
0488
04A0
04A4
04A8
04AC
04B0
Diagnostic Control Register
Encap BERT Control Register
Decap BERT Control Register
Memory BIST Status Register 1
Memory BIST Status Register 2
Memory BIST Status Register 3
Memory BIST Status Register 4
Memory BIST Status Register 5
Test Registers (TST.)
GTR1
BTCR1
BTCR2
BTCR3
BTCR4
BTCR5
BTCR6
CRJBT
BTSR1
BTSR2
BTSR3
BTSR4
BTSR5
BTSR6
CTCR1
CTCR2
CTCR3
CTCR4
EDTCR
EDTSR1
EDTSR2
EDTSR3
EDTSR4
EDTSR5
0600
0604
0608
060C
0610
0614
0618
061C
0624
0628
062C
0630
0634
0638
0640
0644
0648
064C
0660
0664
0668
066C
0670
0674
06FC
Global Test Control Register 1
Block Test Control Register 1
Block Test Control Register 2
Block Test Control Register 3
Block Test Control Register 4
Block Test Control Register 5
Block Test Control Register 6
Clock Recovery Jitter Buffer Test
Block Test Status Register 1
Block Test Status Register 2
Block Test Status Register 3
Block Test Status Register 4
Block Test Status Register 5
Block Test Status Register 6
CLAD Test Control Register 1
CLAD Test Control Register 2
CLAD Test Control Register 3
CLAD Test Control Register 4
Encap/Decap Test Control Register
Encap/Decap Test Status Register 1
Encap/Decap Test Status Register 2
Encap/Decap Test Status Register 3
Encap/Decap Test Status Register 4
Encap/Decap Test Status Register 5
Block Test Control Register 6
FID
Clock Recovery Registers (CR.)
CRCR
0800
Clock Recovery Control Register
MAC Registers (M.)
NET_CONTROL.
NET_CONFIG
NET_STATUS
RSVD
USER_IO
TX_STATUS
RX_QPTR
TX_QPTR
RX_STATUS
IRQ_STATUS
IRQ_ENABLE
IRQ_DISABLE
IRQ_MASK
PHY_MAN
RX_PAUSE_TIME
TX_PAUSE_QUANT
0C00
0C04
0C08
0C0C
0C10
0C14
0C18
0C1C
0C20
0C24
0C28
0C2C
0C30
0C34
0C38
0C3C
Network Control Register
Network Configuration Register
Network Status Register
Reserved
User Input/Output Register
Transmit Status Register
Receive Buffer Queue Base Address
Transmit Queue Base Address
Receive Status Register
Interrupt Status Register
Interrupt Enable Register
Interrupt Disable Register
Interrupt Mask Register
Phy Maintenance Register
Received Pause Quantum Register
Transmit Pause Quantum Register
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DS34S132 DATA SHEET
Register Name
Addr (hex)
Description
HASH_BOT
HASH_TOP
LADDR1_BOT
LADDR1_TOP
LADDR2_BOT
LADDR2_TOP
LADDR3_BOT
LADDR3_TOP
LADDR4_BOT
LADDR4_TOP
ID_CHECK1
ID_CHECK2
ID_CHECK3
ID_CHECK4
RSVD
IPG_STRETCH
MOD_ID
0C80
0C84
0C88
0C8C
0C90
0C94
0C98
0C9C
0CA0
0CA4
0CA8
0CAC
0CB0
0CB4
0CB8
0CBC
0CFC
0D00
0D04
0D08
0D0C
0D10
0D14
0D18
0D1C
0D20
0D24
0D28
0D2C
0D30
0D34
0D38
0D3C
0D44
0D48
0D4C
0D50
0D54
0D58
0D5C
0D60
0D64
0D68
0D6C
0D70
0D74
0D78
0D7C
0D80
0D84
0D88
0D8C
0D90
0D94
0D98
Hash Register Bottom
Hash Register Top
Specific Address 1 Bottom
Specific Address 1 Top
Specific Address 2 Bottom
Specific Address 2 Top
Specific Address 3 Bottom
Specific Address 3 Top
Specific Address 4 Bottom
Specific Address 4 Top
Type ID Match 1
Type ID Match 2
Type ID Match 3
Type ID Match 4
Reserved
IPG Stretch Register
Module Revision ID Register
Octet Transmitted Bottom
Octet Transmitted Top
Frames Transmitted Top
Broadcast Frames Transmitted
Multicast Frames Transmitted
Pause Frames Transmitted
64 Byte Frames Transmitted
65 to 127 Byte Frames Transmitted
128 to 255 Byte Frames Transmitted
256 to 511 Byte Frames Transmitted
512 to 1023 Byte Frames Transmitted
1024 to 1518 Byte Frames Transmitted
Greater Than 1518 Byte Frames Transmitted
Transmit Under Runs
Single Collision Frames
Multiple Collision Frames
Late Collisions
Deferred Transmission Frames
Carrier Sense Errors
Octets Received Bottom
Octets Received Top
Frames Received
Broadcast Frames Received
Multicast Frames Received
Pause Frames Received
OCT_TX_BOT
OCT_TX_TOP
STATS_FRAMES_TX
BROADCAST_TX
MULTICAST_TX
STATS_PAUSE_TX
FRAME64_TX
FRAME65_TX
FRAME128_TX
FRAME256_TX
FRAME512_TX
FRAME1024_TX
FRAME1519_TX
STATS_TX_URUN
STATS_SINGLE_COL
STATS_MULTI_COL
STATS_LATE_COL
STATS_DEF_TX
STATS_CRS_ERRORS
OCT_RX_BOT
OCT_RX_TOP
STATS_FRAMES_RX
BROADCAST_RX
MULTICAST_RX
STATS_PAUSE_RX
FRAME64_RX
64 Byte Frames Received
65 to 127 Byte Frames Received
128 to 255 Byte Frames Received
256 to 511 Byte Frames Received
512 to 1023 Byte Frames Received
1024 to 1518 Byte Frames Received
1519 to Maximum Byte Frames Received
Undersized Frames Received
Oversized Frames Received
Jabbers Received
FRAME65_RX
FRAME128_RX
FRAME256_RX
FRAME512_RX
FRAME1024_RX
FRAME1519_RX
STATS_USIZE_FRAMES
STATS_EXCESS_LEN
STATS_JABBERS
STATS_FCS_ERRORS
STATS_LENGTH_ERRORS
STATS_RX_SYM_ERR
Frame Check Sequence Errors
Length Field Frame Errors
Receive Symbol Errors
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DS34S132 DATA SHEET
Register Name
Addr (hex)
Description
STATS_ALIGN_ERRORS
STATS_RX_RES_ERR
STATS_RX_ORUN
IP_HDR_CHK
TCP_CHK
UDP_CHK
RSVD
REG_TOP
0D9C
0DA0
0DA4
0DA8
0DAC
0DB0
0E00
0E3C
Alignment Errors
Receive Resource Errors
Receive Overruns
IP Header Checksum Errors
TCP Checksum Errors
UDP Checksum Errors
Reserved
Reserved
Port n TXP SW CAS Registers (TXSCn.; n = 0 to 31)
CR1
CR2
CR3
CR4
1000 + n*0010 Port n Configuration Register 1
1004 + n*0010 Port n Configuration Register 2
1008 + n*0010 Port n Configuration Register 3
100C + n*0010 Port n Configuration Register 4
Port n Xmt (RXP) SW CAS Registers (RXSCn. ; n = 0 to 31)
CR1
CR2
CR3
CR4
1200 + n*0010 Port n Configuration Register 1
1204 + n*0010 Port n Configuration Register 2
1208 + n*0010 Port n Configuration Register 3
120C + n*0010 Port n Configuration Register 4
Port n Transmit Configuration Registers (Pn.; n = 0 to 31)
PTCR1
PTCR2
PTCR3
2000 + n*0080 Port n Transmit Configuration Register 1
2004 + n*0080 Port n Transmit Configuration Register 2
2008 + n*0080 Port n Transmit Configuration Register 3
Port n Transmit Status Registers (Pn.; n = 0 to 31)
PTSR1
PTSR2
PTSR3
PTSR4
2020 + n*0080 Port n Transmit Status Register 1
2024 + n*0080 Port n Transmit Status Register 2
2028 + n*0080 Port n Transmit Status Register 3
202C + n*0080 Port n Transmit Status Register 4
Port n Transmit Status Latch Registers (Pn.; n = 0 to 31)
PTSRL
2030 + n*0080 Port n Transmit Status Register Latch
Port n Transmit Status Interrupt Enable Registers (Pn.; n = 0 to 31)
PTSRIE
2038 + n*0080 Port n Transmit Status Register Interrupt Enable
Port n Receive Configuration Registers (Pn.; n = 0 to 31)
PRCR1
PRCR2
PRCR3
PRCR4
PRCR5
2040 + n*0080 Port n Receive Configuration Register 1
2044 + n*0080 Port n Receive Configuration Register 2
2048 + n*0080 Port n Receive Configuration Register 3
204C + n*0080 Port n Receive Configuration Register 4
2050 + n*0080 Port n Receive Configuration Register 5
Port n Receive Status Registers (Pn.; n = 0 to 31)
PRSR1
PRSR2
PRSR3
PRSR4
2060 + n*0080 Port n Receive Status Register 1
2064 + n*0080 Port n Receive Status Register 2
2068 + n*0080 Port n Receive Status Register 3
206C + n*0080 Port n Receive Status Register 4
Port n Receive Status Latch Registers (Pn.; n = 0 to 31)
PRSRL
2070 + n*0080 Port n Receive Status Register Latch
Port n Receive Status Interrupt Enable Registers (Pn.; n = 0 to 31)
PRSRIE
2078 + n*0080 Port n Receive Status Register Interrupt Enable
Time Slot Assignment Registers (TSAn.m.; port “n” = 0 to 31 and Timeslot “m” = 0 to 31)
CR
3000 + m*0004 Configuration Register
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DS34S132 DATA SHEET
10.3 Register Definitions
In the sub-sections that follow each register definition includes a Register Type definition with 3 Type Categories:
Signal Type, Clear Type and Misc Type. The Type definition uses the form “a-b-c” where a = Signal Type, b = Clear
Type and c = Misc Type. If one of these categories is not applicable to a register bit, then an underscore, “_”, is
used (e.g. ros-cor-_).
Signal Type
Clear Type
cor: Clear On Read
cow: Clear On Write
crw: Clear on Read or Write
(G.GCR.LSBCRE selected)
cnr: Clear on None or Read
(G.GCR.CCOR selected)
Misc Type
ix: Interrupt level “x”
(x = 1, 2 or 3)
sc: Saturating Counter
nc: Non-saturating Counter
ros: Read Only Status
rls: Read Latched Status
rcs: Read Count Status
woc: Write Only Control
rwc: Read/Write Control
rod: “ros” Delayed
rld: “rls” Delayed
rcd: “rcs” Delayed
rwd: “rwc” Delayed
The term “Delayed” means that the Read or Write operation does not complete within one clock cycle and the
external CPU must provide sufficient time for the operation to complete. These are RAM-based registers that do not
support immediate read/write operations. The data in this type of register is not valid until after the first Write to the
register (the data is invalid/unknown after a reset).
The term “Clear” indicates how a latch or counter is returned to its reset state. “Clear on Read” means the signal is
reset by a Read operation. For “Clear on Write”, a Write with any register value resets the register. “Clear On None”
is used by some counters to mean that the count is not reset by any action. For registers with the clear option
“crw”, the global G.GCR.LSBCRE bit selects between “Clear On Read” and “Clear On Write”. For registers with the
clear option “cnr”, the global G.GCR.CCOR bit selects between “Clear On Read” and “Clear On None”.
Saturating Counters stop incrementing at their maximum count. Non-saturating counters roll-over back to “zero”
after they reach their maximum count.
The “x” that is used in the “ix” Type means that the interrupt level may be any of x = 1 to 3, where 1 is lowest level
interrupt in the S132 interrupt hierarchy (e.g. roi1). All interrupt generating registers have an associated register that
is used to enable or disable (mask) the interrupt.
The “Description” term “Reserved” means that this bit has only one valid setting. The bit name in the far left column
may be “RSVD” or some other name (e.g. “CCRSTDP”). In most cases, the only valid setting is the default value. In
a few cases (as noted) they use a non-default value that is indicated in the Description column (e.g. Reserved. This
must be programmed to “1”.)
Numbers are written in decimal notation unless a “b” suffix is used for binary (e.g. 010b) or a “0x” prefix or “h” suffix
is used for hexadecimal (e.g. “0x4F” or “0800h”; the “0x” and ‘h” notation have the same meaning).
Yellow shading is used to identify the 32-bit register name and characteristics. White (non-shaded) rows are used
to define the bit field s within each 32-bit register.
10.3.1 Global Registers (G.)
10.3.1.1 Global Configuration Registers (G.)
Table 10-3. Global Configuration Registers
G. Field Addr (A:)
Name
IDR.
ID
Bit [x:y] Type
Description
A:0000h
ID Register. Default: 00.0J.JJh where J = JTAG ID
ID. Reserved
[31:20] ros-_-_
[19:4] ros-_-_
ID. Same information as the lower 16 bits of JTAG CODE ID portion of the JTAG
ID
ID register. JTAG ID[27:12].
Originial Rev ID. Was not modified to reflect Rev A2 ID. Still reads 4’b0000.
ID
[3:0] ros-_-_
A:0004h
GCR.
RSVD
Global Configuration Register. Default: 0x00.00.08.00
Reserved.
[31:28]
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
Bit [x:y] Type
Description
Ethernet Clock 25 MHz selects the rate of the ETHCLK input.
0 = ETHCLK is being driven by 125MHz source
1 = ETHCLK is being driven by 25MHz source
EC25
[27] rwc-_-_
[26] rwc-_-_
[25] rwc-_-_
Ethernet Clock DDR SDRAM Clock selects the SDCLK source.
0 = SDCLK is sourced from ETHCLK (125 MHz only; tie DDRCLK low)
1 = SDCLK is sourced from DDRCLK (independent of ETHCLK)
ECDC
IIM
Interrupt Inactive Mode determines the inactive mode of the INT_N pin. The
INT_N pin always drives low when an enabled interrupt source is active.
0 = Pin is high impedance when all enabled interrupts are inactive
1 = Pin drives high when all enabled interrupts are inactive
Reorder or Duplicate Packet Counters selects which condition increments the
Reorder Counters (see B.BDSR6.SCRPC).
0 = Count the number of reordered good packets
1 = Count the number of duplicate packets
RDPC
JLPC
IPSE
[24] rwc-_-_
[23] rwc-_-_
[22] rwc-_-_
Jump or Lost Packet Counters selects which condition increments the Jumped
Packet Counters (see B.BDSR5.SCJPC)
0 = Count the jump size for good packets
1 = Count the number of lost packets not received before playout.
Indicate Playout Start Enable selects which conditions are indicated by the Jitter
Buffer Underrun Status bits (see GxSRL.JBU).
0 = Detect Jitter Buffer Underrun only
1 = Detect Jitter Buffer Underrun and “Start of Playout” changes (monitor
B.BDSR3.JBLL to determine if change is Underrun or Playout)
Jitter Buffer Max Depth = the byte depth for all Jitter Buffers.
0 = 256KB per Jitter Buffer
JBMD
[21:20] rwc-_-_
1 = 128KB per Jitter Buffer
2 = 64KB per Jitter Buffer
3 = 32KB per Jitter Buffer
Global Recovered Clock Source Select selects which Clock Recovery Engine
(0 – 31) generates the Global Recovered Clock. 0x00 = Clock Recovery Engine 0.
GRCSS
GMMS
[19:15] rwc-_-_
[14:12] rwc-_-_
GMII - MII Mode Select selects the Ethernet port mode and interface type.
0 = Ethernet port disabled
2 = Ethernet port enabled using MII interface
3 = Ethernet port enabled using GMII interface
Clear Counter On Read selects the clear function for the RX Bundle, TX Bundle
and Packet Classifier counters (affects registers with “-cnr-” in the “Type” column).
The counters will roll over after the maximum value.
0 = Counters do not clear
CCOR
[11] rwc-_-_
1 = Each Read operation clears the counter
RXP HDLC Minimum Flag Insertion selects minimum number of HDLC flags
that are inserted between HDLC frames at the Transmit TDM Ports. The number
of inserted flags is 1 more than this programmed value (i.e. 0 setting = 1 flag).
RXHMFIS
OTRS
[10:8] rwc-_-_
[7] rwc-_-_
[6] rwc-_-_
OAM Timestamp Resolution Select selects OAM Timestamps resolution.
0 = 1us OAM Timestamp resolution
1 = 100us OAM Timestamp resolution
Latch Status Bit Clear on Read Enable selects when the latched status register
bits are cleared, but does not apply to the Clock Recovery Status Registers or the
Ethernet MAC Status Registers.
LSBCRE
0 = Latched status register bits are cleared when the CPU writes to the register
1 = Latched status register bits are cleared when the CPU reads the register
L Bit Change Detect Enable = “1” enables L-bit change detection for all Bundles.
LBCDE
RBCDE
[5] rwc-_-_
[4] rwc-_-_
R Bit Change Detect Enable = “1” enables R-bit change detection for all
Bundles.
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
Bit [x:y] Type
Description
M Bit Change Detect Enable = “1” enables M-bit change detection for all
MBCDE
[3:2] rwc-_-_
Bundles. Each M-bit can be enabled individually.
Fragmentation Bit Change Detect Enable = “1” enables F-bit change detection
FBCDE
[1:0] rwc-_-_
for all Bundles. Each F-bit can be enabled individually.
GRCR.
A:0008h
Global Reset Control Register. Default: 00.00.07.FEh
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
RSVD
[31:11]
[10]
[9]
CCRSTDP
DRSTDP
SCRSTDP
MRSTDP
EMARSTDP
[8]
[7]
[6]
TERSTDP
TDRSTDP
TPIRSTDP
RPIRSTDP
[5]
[4]
[3]
[2]
Global Datapath Reset selects the internal global datapath reset state (CPU
programmed control registers are not reset by this function, but should be re-
programmed to insure S132 functions properly after performing this reset).
0 = Normal operation
RSTDP
[1] rwc-_-_
1 = Force Data Path to default state (must be “1” > 100ns; similar to RST_N = 0)
Global Reset selects the reset state for the internal global datapath, status and
control registers. The Bundle (B.), Timeslot Assignment (TSAn.m.), TXP SW CAS
(TXSCn.) and Xmt SW CAS (RXSCn.) registers are not reset by this. However,
these registers should be considered to be reset and reloaded after de-assertion
of this reset. This reset function is similar to the reset for the RST_N pin.
0 = Normal operation
RST
[0] rwc-_-_
1 = Force internal registers to their default values (must be high > 100ns)
CCR.
RSVD
FS
A:000Ch
CLAD Control Register. Default: 0x00.00.00.78
Reserved.
[31:7]
Frequency Select selects the CLAD input clock rate. The CLAD input clock can
[6:3] rwc-_-_
be sourced from the REFCLK or CMNCLK pins (selected using G.CCR.SCS).
0000b = 5 MHz
0001b = 5.12 MHz
0010b = 10 MHz
0011b = 10.24 MHz 1000b = 20.48 MHz
0100b = 12.8 MHz
0101b = 13 MHz
0110b = 19.44 MHz
0111b = 20 MHz
1001b = 25 MHz
1010b = 38.88 MHz
1011b = 77.76 MHz
11xxb = 155.52 MHz
LIU Clock Enable = “1” enables LIUCLK. “0” disables LIUCLK PLL and output.
LCE
LCS
[2] rwc-_-_
[1] rwc-_-_
LIU Clock Select selects the LIUCLK output rate.
0 = 1.544 MHz output clock
1 = 2.048 MHz output clock
Synthesis Clock Select selects the CLAD input clock source.
0 = REFCLK input
SCS
[0] rwc-_-_
1 = CMNCLK input
ECCR1. A:0010h
Ethernet Conditioning Configuration Register 1. Default: 0x00.00.00.00
Ethernet Conditioning Octet A. TXP Ethernet Conditioning Octet A
Ethernet Conditioning Octet B. TXP Ethernet Conditioning Octet B
Ethernet Conditioning Octet C. TXP Ethernet Conditioning Octet C
Ethernet Conditioning Octet D. TXP Ethernet Conditioning Octet D
ECOA
ECOB
ECOC
ECOD
[31:24] rwc-_-_
[23:16] rwc-_-_
[15:8] rwc-_-_
[7:0] rwc-_-_
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
Bit [x:y] Type
Description
ECCR2. A:0014h
Ethernet Conditioning Configuration Register 2. Default: 0x00.00.00.00
Ethernet Conditioning Octet E. TXP Ethernet Conditioning Octet E
Ethernet Conditioning Octet F. TXP Ethernet Conditioning Octet F
Ethernet Conditioning Octet G. TXP Ethernet Conditioning Octet G
Ethernet Conditioning Octet H. TXP Ethernet Conditioning Octet H
ECOE
ECOF
ECOG
ECOH
[31:24] rwc-_-_
[23:16] rwc-_-_
[15:8] rwc-_-_
[7:0] rwc-_-_
TCCR1. A:0018h
TDM Conditioning Configuration Register 1. Default: 0x00.00.00.00
TDM Conditioning Octet A. RXP TDM Conditioning Octet A.
TDM Conditioning Octet B. RXP TDM Conditioning Octet B
TDM Conditioning Octet C. RXP TDM Conditioning Octet C
TDM Conditioning Octet D. RXP TDM Conditioning Octet D
TDM Conditioning Configuration Register 2. Default: 0x00.00.00.00
TDM Conditioning Octet E. RXP TDM Conditioning Octet E
TDM Conditioning Octet F. RXP TDM Conditioning Octet F
TDM Conditioning Octet G. RXP TDM Conditioning Octet G
TDM Conditioning Octet H. RXP TDM Conditioning Octet H
TCOA
TCOB
TCOC
TCOD
[31:24] rwc-_-_
[23:16] rwc-_-_
[15:8] rwc-_-_
[7:0] rwc-_-_
TCCR2. A:001Ch
ETCOE
TCOF
TCOG
TCOH
[31:24] rwc-_-_
[23:16] rwc-_-_
[15:8] rwc-_-_
[7:0] rwc-_-_
10.3.1.2 Global Status Registers (G.)
Table 10-4. Global Status Registers (G.)
G. Field Addr (A:)
Name
GSR1.
RSVD
EBS
Bit [x:y] Type
Description
A:0030h
Global Status Register 1. Default: 0x00.00.00.00
Reserved.
[31:18]
Encap (Ethernet) BERT Status = “1” indicates one or more Packet BERT Status
Latch bits = “1” (EB.BSRL) and are enabled (EB.BSIE). The combination of EBS =
1 and G.GSRIE1.EBIE = 1 forces an interrupt on INT_N.
[17] ros-_-i1
Decap (TDM Port) BERT Status = “1” indicates one or more TDM BERT Status
Latch bits = “1” (DB.BSRL) and are enabled (DB.BSIE). The combination of DBS
= 1 and G.GSRIE1.DBIE = 1 forces an interrupt on INT_N.
DBS
[16] ros-_-i1
[15] ros-_-i1
[14] ros-_-i1
[13] ros-_-i1
Port Transmit CAS Status = “1” indicates one or more Transmit (RXP) CAS
Status Latch bits = “1” (G.GSR2) and are enabled (G.GSRIE2). The combination
of PTCS = 1 and G.GSRIE1.PTCIE = 1 forces an interrupt on INT_N.
PTCS
PRCS
MIRS
Port Receive CAS Status = “1” indicates one or more Receive (TXP) CAS Status
Latch bits = “1” (G.GSR3) and are enabled (G.GSRIE3). The combination of
PRCS = 1 and G.GSRIE1.PRCIE = 1 forces an interrupt on INT_N.
MAC Interrupt Register Status = “1” indicates one or more M.IRQ_STATUS
Status Latch bits = “1” and are enabled (M.IRQ_ENABLE and M.IRQ_DISABLE).
The combination of MIRS = 1 and G.GSRIE1.MIRIE = 1 forces an interrupt on
INT_N.
Clock Recovery Hardware Status = “1” indicates one or more Clock Recovery
Engine Status Latch bits = “1” (the Clock Recovery Status is defined by the DSP
Firmware load). The combination of any CRHS[x] = 1 (x = 8 to 12) and
G.GSRIE1.CRHIE[x] = 1 forces an interrupt on INT_N.
CRHS
BS
[12:8] ros-_-i1
[7] ros-_-i1
Bundle Status = “1” indicates one or more Group Bundle Status bits are “1”
(G.GSR5). The combination of BS = 1 and G.GSRIE1.BIE = 1 forces an interrupt
on INT_N.
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
Bit [x:y] Type
Description
Jitter Buffer Status = “1” indicates one or more Jitter Buffer Status bits are “1”
(G.GSR6). The combination of JBS = 1 and G.GSRIE1.JBIE = 1 forces an
interrupt on INT_N.
JBS
[6] ros-_-i1
[5] ros-_-i1
[4] ros-_-i1
[3] ros-_-i1
Port Status = “1” indicates one or more TDM Per Port Status bits are “1”
(G.GSR4). The combination of PS = 1 and G.GSRIE1.PIE = 1 forces an interrupt
on INT_N.
PS
Packet Classifier Status = “1” indicates one or more Packet Classifier special
event/errors have been detected (PC.SRL) and enabled (PC. SRIE). An interrupt
is generated on INT_N when PCS = 1 and G.GSRIE1.PCIE = 1.
PCS
EMIS
External Memory Interface Status = “1” indicates one or more SDRAM Queue
Errors have been detected (EMI.BMSRL) and enabled (EMI.BMSRIE). An
interrupt is generated on INT_N when EMIS = 1 and G.GSRIE1.EMIIE = 1.
Reserved.
RSVD
[2]
External Memory Access Write Status = “1” indicates one or more TXP CPU
Packet Write Status Latch bits = “1” (EMA.WSRL1) and enabled (EMA.WSRIE1).
The combination of EMAWS = 1 and G.GSRIE1.EMAWIE = 1 forces an interrupt
on INT_N.
EMAWS
[1] ros-_-i1
External Memory Access Read Status = “1” indicates one or more RXP CPU
Packet Read Status Latch bits = “1” (EMA.RSRL1) and enabled (EMA.RSRIE1).
The combination of EMARS = 1 and G.GSRIE1.EMARIE = 1 forces an interrupt
on INT_N.
EMARS
[0] ros-_-i1
GSR2.
A:0034h
[31:0] rls-crw-i3
Global Status Register 2. Default: 0x00.00.00.00
Per-Port Transmit (RXP) CAS Latched Status = “1” in PPTCSL bit position “x”
(x = 0 to 31) indicates one or more received RXP CAS Codes for Transmit TDM
Port “x” have changed. The combination of any PPTCSL[x] = 1 and its associated
G.GSRIE2.PPTCSIE[x] = 1 will make G.GSR1.PTCS = 1.
PPTCSL
GSR3.
A:0038h
[31:0] rls-crw-i3
Global Status Register 3. Default: 0x00.00.00.00
Per-Port Receive (TXP) CAS Latched Status = “1” in PPRCSL bit position “x” (x
= 0 to 31) indicates one or more CAS Codes received from TDM Port “x” have
changed (TXP direction). The combination of any PPRCSL[x] = 1 and its
associated G.GSRIE3.PPRCSIE[x] = 1 will make G.GSR1.PRCS = 1.
PPRCSL
GSR4.
A:003Ch
[31:0] ros-crw-i2
Global Status Register 4. Default: 0x00.00.00.00
Per-Port Latched Status = “1” in PPS bit “x” (x = 0 to 31) indicates one or more
Frame Alignment or Over/underrun errors have been detected at TDM Port “x”
(any “Pn.PTSRL[z] and Pn.PTSRIE[z]” = 1 or any “Pn.PRSRL[z] and
Pn.PTSRIE[z]” = 1; where “Pn” = “Port x” and z = bit 0 or bit 1). This is a latched
status register, which means a 0 to 1 transition on any associated
PTSRL[z]/PRSRL[z] forces a latched PPS=1. The G.GCR.LSBCRE register
selects whether a Read or Write operation to GSR4 clears the register (-crw-;
even if all PTSRL[z]/PRSRL[z] transition back to “0”, a PPS[x] = 1 value will not
clear until GSR4 is cleared by a Read or Write operation). Any PPS[x] = 1 will
force G.GSR1.PS = 1.
PPS
GSR5.
A:0040h
[31:0] ros-_-i2
Global Status Register 5. Default: 0x00.00.00.00
Bundle Group Status = “1” in BGS bit position “x” (x = 0 to 31) indicates one or
more PW Control Word changes have been detected in Bundle Group “x” (any
B.GxSRL[z] = 1 and B.GxSRIE[z] = 1 for z = 0 to 7). Bundles with a detected
change can be identified from: Bundle # = BGS “x” bit position x 8 + B.GxSRL “z”
bit position. Any BGS[x] = 1 (x = 0 to 31) will force G.GSR1.BS = 1.
BGS
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
GSR6.
JBGS
Bit [x:y] Type
A:0044h
[31:0] ros-_-i2
Description
Global Status Register 6. Default: 0x00.00.00.00
Jitter Buffer Group Status = “1” in JBGS bit position “x” (x = 0 - 31) indicates
one or more Jitter Buffer Underruns have been detected in Bundle Group “x” (any
JB.GxSRL[z] = 1 and JB.GxSRIE[z] = 1 for z = 0 to 7). Bundles with a detected
change can be identified from: Bundle # = JBGS “x” bit position x 8 + JB.GxSRL
“z” bit position. Any JBGS[x] = 1 (x = 0 to 31) will force G.GSR1.JBS = 1.
TPISR1. A:0048h
Transmit Packet Interface Status Register 1. Default: 0x00.00.00.00
Reserved.
RSVD
[31:11]
TXP High Priority Queue Level indicates # packets in the queue (0 – 1024).
Transmit Packet Interface Status Register 2. Default: 0x00.00.00.00
Reserved.
TXHPQL
[10:0] ros-_-_
TPISR2. A:004Ch
RSVD
[31:11]
TXP Low Priority Queue Level indicates # packets in the queue (0 – 1024).
Transmit Packet Interface Status Register 3. Default: 0x00.00.00.00
Reserved.
TXLPQL
[10:0] ros-_-_
TPISR3. A:0050h
RSVD
[31:10]
[9:0] ros-_-_
TXP CPU Queue Level indicates # packets in the queue (0 – 512).
TXCQL
TPISRL. A:0054h
Transmit Packet Interface Status Register Latches. Default: 0x00.00.00.00
Reserved.
RSVD
[31:3]
[2] rls-crw-i1
High Priority Queue Overflow Status Latch = “1” indicates an overflow of the
TXP TDM High Priority Queue (data discarded). The combination of HPQOSL = 1
and G.TPISRIE.HPQOSIE = 1 forces an interrupt on INT_N.
HPQOSL
Low Priority Queue Overflow Status Latch = “1” indicates an overflow of the
TXP TDM Low Priority Queue (data discarded). The combination of LPQOSL = 1
and G.TPISRIE.LPQOSIE = 1 forces an interrupt on INT_N.
LPQOSL
[1] rls-crw-i1
Reserved.
RSVD
[0]
TPISRIE. A:0058h
Transmit Packet Interface Status Register Interrupt Enable. Default:
0x00.00.00.00
Reserved.
RSVD
[31:3]
[2] rwc-_-i1
High Priority Queue Overflow Status Interrupt Enable. (see TPISRL.HPQOSL)
HPQOSI
E
Low Priority Queue Overflow Status Interrupt Enable. (see TPISRL.LPQOSL)
LPQOSIE
RSVD
[1] rwc-_-i1
[0]
Reserved.
10.3.1.3 Global Status Register Interrupt Enables (G.)
Table 10-5. Global Status Register Interrupt Enables (G.)
G. Field Addr (A:)
Name
Bit [x:y] Type
Description
GSRIE1. A:0060h
Global Status Register Interrupt Enable 1. Default: 0x00.00.00.00
Reserved.
RSVD
EBSIE
DBSIE
PTCIE
PRCIE
MIRIE
CRHIE
BIE
[31:18]
[17] rwc-_-i1
Encap (Ethernet) BERT Status Interrupt Enable. (see G.GSR1.EBS)
Decap (TDM Port) BERT Status Interrupt Enable. (see G.GSR1.DBS)
Port Transmit (RXP) CAS Interrupt Enable. (see G.GSR1.PTCS)
Port Receive (TXP) CAS Interrupt Enable. (see G.GSR1.PRCS)
MAC Interrupt Register Interrupt Enable. (see G.GSR1.MIRS)
Clock Recovery Hardware Interrupt Enable. (see G.GSR1.CRHS)
Bundle Interrupt Enable. (see G.GSR1.BS)
[16] rwc-_-i1
[15] rwc-_-i1
[14] rwc-_-i1
[13] rwc-_-i1
[12:8] rwc-_-i1
[7] rwc-_-i1
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DS34S132 DATA SHEET
G. Field Addr (A:)
Name
JBUIE
PIE
Bit [x:y] Type
Description
Jitter Buffer Interrupt Enable. (see G.GSR1.JBS)
Port Interrupt Enable. (see G.GSR1.PS)
[6] rwc-_-i1
[5] rwc-_-i1
[4] rwc-_-i1
[3] rwc-_-i1
[2]
Packet Classifier Interrupt Enable. (see G.GSR1.PCS)
External Memory Interface Interrupt Enable. (see G.GSR1.EMIS)
Reserved.
PCIE
EMIIE
RSVD
EMAWIE
EMARIE
External Memory Access Write Interrupt Enable. (see G.GSR1.EMAWS)
External Memory Access Read Interrupt Enable. (see G.GSR1.EMARS)
[1] rwc-_-i1
[0] rwc-_-i1
GSRIE2. A:0064h
Global Status Register Interrupt Enable 2. Default: 0x00.00.00.00
Per Port Transmit (RXP) CAS Interrupt Enable. (see G.GSR2.PPTCSL)
Global Status Register Interrupt Enable 3. Default: 0x00.00.00.00
Per Port Receive (TXP) CAS Interrupt Enable. (see G.GSR3.PPRCSL)
PPTCIE
[31:0] rwc-_-i3
GSRIE3. A:0068h
PPRCIE
[31:0] rwc-_-i3
10.3.2 Bundle Registers (B.)
10.3.2.1 Bundle Reset Registers (B.)
Table 10-6. Bundle Reset Registers (G.)
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
BRCR1. A:0080h
Bundle Reset Control Register 1. Default: 0x00.00.00.00
Sequence Number Seed = Sequence # seed used in the next TXP packet for the
Bundle number specified by RXTXBS when the TXP direction is released from
reset (B.BRCR2.TXBRE). SNS should be a random/unpredictable value.
SNS
[31:16] rwc-_-_
Reserved.
RSVD
[15:8]
RXP or TXP Bundle Select specifies the Bundle Number that is used in the next
Bundle Reset (B.BRCR2) or Bundle Reset Status (B.BRSR) operation. To change
a Bundle Data Path Reset State, B.BRCR2 must be programmed first to specify
the new RXP and TXP Data Path Reset States. Next a write to BRCR1 initiates
the B.BRCR2 reset command to the Bundle specified by RXTXBS (and initiates a
new TXP Sequence Number). To read the status of a Bundle Data Path Reset
State, RXTXBS must be programmed first to specify the Bundle number. Next a
read to B.BRSR will provide the status of the TXP and RXP Reset States for the
Bundle specified by RXTXBS.
RXTXBS
[7:0] rwc-_-_
BRCR2. A:0084h
Bundle Reset Control Register 2. Default: 0x00.00.00.00
Reserved.
RSVD
[31:2]
[1] rwc-_-_
RXP Bundle Reset Enable selects the Reset State for the RXP Payload Data
Path of the Bundle identified by B.BRCR1. RXBRE does not affect RXP Clock
Recovery for SAT/CES Bundles with payload or SAT/CES Clock Only Bundles.
0 = Release Bundle Reset to forward payload data and reset Bundle Status
1 = Hold Bundle Data Path in reset (does not reset Bundle Status value)
RXBRE
TXP Bundle Reset Enable selects the Reset State for the TXP Bundle Payload
Data Path identified by B.BRCR1. TXBRE disables transmission of TXP Bundles
(it blocks the receive TDM Port data and disables TXP Bundle Status registers).
0 = Release Bundle Reset to forward payload data and reset Bundle Status
1 = Hold Bundle Data Path in reset (does not reset Bundle Status values)
TXBRE
[0] rwc-_-_
BRSR.
A:0088h
[31:2]
Bundle Reset Status Register. Default: 0x00.00.00.00
Reserved.
RSVD
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
RXP Bundle Reset Status indicates whether the RXP packet payload data path
for the selected Bundle (B.BRCR1.RXTXBS) is released from reset.
0 = The RXP side of the Bundle is in reset
RXBRS
[1] ros-_-_
1 = The RXP side of the Bundle is released from reset
TXP Bundle Reset Status indicates whether the TXP packet payload path for the
selected Bundle (B.BRCR1.RXTXBS) is released from reset.
0 = The TXP side of the Bundle is in reset
TXBRS
[0] ros-_-_
1 = The TXP side of the Bundle is released from reset
10.3.2.2 Bundle Data Control Registers (B.)
Table 10-7. Bundle Data Control Registers (B.)
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
BACR.
RSVD
OBS
A:0094h
[31:13]
Bundle Activation Control Register. Default: 0x00.00.00.00
Reserved.
OAM Bundle Select selects whether B.BACR.BS is for a Bundle or OAM Bundle.
0 = BS is for a Bundle ID
[12] rwc-_-_
1 = BS is for an OAM Bundle ID
Write Enable, on a transition from zero to one, writes the B.BADR1 and B.BADR2
register values to the Bundle selected by B.BACR.OBS and BS.
WE
RE
[11] rwc-_-_
[10] rwc-_-_
Read Enable, on a transition from zero to one, loads the B.BADR1 and B.BADR2
registers with values from the Bundle selected by B.BACR.OBS and BS. The
B.BADR1 and B.BADR2 read operations may take more than one CPU access
time, so the CPU should perform a no-op before reading the BADRx values.
Reserved.
RSVD
BS
[9:8] rwc-_-_
[7:0] rwc-_-_
Bundle Select specifies the Bundle or OAM Bundle Number that is used when
accessing B.BADR1 and B.BADR2. When OBS = 0, the valid BS values are 0 to
255. When OBS = 1, the valid BS values are 0 to 31.
BCCR.
RSVD
WE
A:0098h
[31:12]
Bundle Configuration Control Register. Default: 0x00.00.00.00
Reserved.
Write Enable, on a transition from zero to one, writes the programmed settings in
[11] rwc-_-_
B.BCDR1 - B.BCDR5 registers to the Bundle selected by B.BCCR.BS.
Read Enable, on a transition from zero to one, loads the B.BCDR1 - B.BCDR5
registers with values from the Bundle selected by B.BCCR.BS. The B.BCDR1 -
B.BCDR5 read operations may take more than one CPU access time, so the CPU
should perform a no-op before reading the BCDRx values.
RE
[10] rwc-_-_
Reserved.
RSVD
BS
[9:8] rwc-_-_
[7:0] rwc-_-_
Bundle Select selects the Bundle Number (0 – 255) that is used when accessing
the B.BCDR1 - B.BCDR5 registers.
BESCR. A:009Ch
TXP Bundle Encap Status Control Register. Default: 0x00.00.00.00
Reserved.
RSVD
ESRE
[31:11]
[10] rwc-_-_
Encap Status Read Enable, on a transition from zero to one, loads the B.BESR1
– B.BESR3 registers with values from the Bundle selected by B.BESCR.ESBS.
The B.BESR1 - B.BESR3 read operations may take more than one CPU access
time, so the CPU should perform a no-op before reading the BESRx values.
Reserved.
RSVD
ESBS
[9:8] rwc-_-_
[7:0] rwc-_-_
Encap Status Bundle Select selects the Bundle Number (0 – 255) that is used
when accessing the B.BESR1 – B.BESR3 registers.
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
BDSCR. A:00A0h
RXP Bundle Decap Status Control Register. Default: 0x00.00.00.00
Reserved.
RSVD
DSRE
[31:11]
[10] rwc-_-_
Decap Status Read Enable, on a transition from zero to one, loads B.BDSR1 –
B.BDSR9 with values from the Bundle selected by B.BDSCR.DSBS. The
B.BDSR1 - B.BDSR9 read operations may take more than one CPU access time,
so the CPU should perform a no-op before reading the BDSRx values.
Reserved.
RSVD
DSBS
[9:8] rwc-_-_
[7:0] rwc-_-_
Decap Status Bundle Select selects the Bundle Number (0 – 255) that is used
when accessing the B.BDSR1 – B.BDSR9 registers.
10.3.2.3 Bundle Data Registers (B.)
Table 10-8. Bundle Data Registers (B.)
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
BADR1. A:00A4h
Bundle Activation Data Register 1. Default: 0x00.00.00.00
Reserved.
RSVD
ABE
[31:1]
[0] rwd-_-_
Active Bundle Enable = “1” indicates the RXP Bundle selected by B.BACR is
enabled. When “0” the RXP Bundle is disabled/ignored. This bit does not affect
the Bundle’s TXP direction. The chip reset functions disable all 256 Bundles
(G.GRCR.RST and RST_N pin).
BADR2. A:00A8h
Bundle Activation Data Register 2. Default: 0x00.00.00.00
Bundle ID Value is the BID or OAM BID value for the Bundle Number or OAM
Bundle Number selected by B.BACR. The bit width of BIDV varies as indicated
below. When BIDV bit width <32, the unused MSbits of the BIDV must be “0”.
32 bits - L2TPv3 and UDP when 32-bit width is selected by PC.PCCR1.UBIDLS
20 bits - MPLS and MEF
BIDV
[31:0] rwd-_-_
16 bits - UDP when 16-bit width is selected by PC.PCCR1.UBIDLS
BCDR1. A:00ACh
Bundle Configuration Data Register 1. Default: 0x00.00.00.00
Reserved.
RSVD
LBCAI
[31:24]
[23] rwd-_-_
L Bit Conditioning Auto Insert determines how the RXP packet payload is
handled when L-bit = 1. This setting does not affect the Clock Recovery functions
or the Jumped Packet Count.
0 = L-bit is ignored, payload is processed normally (no special handling).
1 = Discard RXP packet payload (if it exists).
Note: If LBCAI = 1 and L-bit = 1, the packet is not counted as lost.
Payload Machine Type.
0 = HDLC Payload Machine Type
1 = Reserved
PMT
[22:21] rwd-_-_
2 = Reserved
3 = SAT/CES Machine Type
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
PMS
[20:10] rwd-_-_
Payload Size. The Range of valid values is 1 – 2047
CES: # frames of assigned TDM Port data associated with each RXP/TXP packet
(for CES with CAS, the PMS value does not include the CAS Signaling bytes)
SAT: # bytes of assigned TDM Port data associated with each RXP/TXP packet.
HDLC: Max # bytes in received HDLC packets (TXP direction only; not incl. FCS).
Note: For SAT/CES packets that include payload data, PMS specifies # bytes or
frames of TDM Port Data are carried in the packet payload. Packets for SAT/CES
Clock Only Bundles do not include payload data, so PMS specifies # of assigned
bytes/frames that exist on the TDM Port Line (but are not carried in the packet) for
each RXP/TXP packet. The PMS setting has the same meaning for both, but the
payload is deleted (does not exist) in the RXP/TXP packets. For HDLC, if a
received packet size exceeds PMS, the packet is discarded.
SCSCFP
D
[9] rwd-_-_
[8] rwd-_-_
SAT/CES Sanity Check Fail Packet Discard.
0 = Disable RXP Sanity Check
1 = Discard RXP packet if T1/E1 payload in RXP packet does not equal PMS.
Note: For SAT/CES Bundle packets, if B.BCDR1.LBCAI = 1 and L-bit = 1 (“Invalid
Payload” indication), the Sanity Check is auto-disabled for that packet. For HDLC
and Clock Only Bundles the only valid setting is SCSCFPD = 0.
SAT/CES Sequence Number/HDLC Transmission Reordering Enable.
SAT/CES Bundles
SCSNRE
0 = Disable RXP Sequence Number reordering
1 = Enable RXP Sequence Number reordering
HDLC Bundles
0 = use HDLC MSB first transmission (transmit and receive directions)
1 = use HDLC LSB first transmission (transmit and receive directions)
SAT/CES RXP Bundle CAS Source Select / HDLC FCS Processing Disable.
SAT/CES Bundles
SCRXBC
SS
[7] rwd-_-_
0 = When Jitter Buffer empties send last stored RXP CAS codes to TSIG/TDAT
1 = When Jitter Buffer empties send Xmt SW CAS codes (RXSCn) to
TSIG/TDAT
HDLC Bundles
0 = FCS processing is enabled (RXP & TXP directions).
1 = FCS processing is disabled (RXP & TXP directions).
SAT/CES TXP Bundle CAS Source Select / HDLC FCS 32 Bit Width Select.
SAT/CES Bundles
SCTXBC
SS
[6] rwd-_-_
0 = Use CAS data received at TDM Port for TXP Bundle
1 = Use CAS data from TXP SW CAS codes (TXSCn) in TXP packets
HDLC Bundles
0 = Use 16-bit FCS (RXP & TXP directions)
1 = Use 32-bit FCS (RXP & TXP directions)
Reorder Sequence Number Select.
0 = Use the Control Word Sequence Number for reordering RXP packets
1 = Use the RTP Sequence Number for reordering RXP packets
RSNS
[5] rwd-_-_
[4] rwd-_-_
SAT/CES TXP Conditioning Enable / HDLC Packet Sequence # Select 1.
SAT/CES Bundles
SCTXCE
When this bit is set the selected condition data (See SCTXCOS bits) will be sent
in the packet to the PSN. When reset, normal operation is active.
HDLC Bundles - see SCTXDFSE bit description.
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
CES TXP Destination Framing SF or ESF / HDLC Packet Seq # Select 0.
CES Bundles (T1 Only; for TXP direction)
SCTXDF
SE
[3] rwd-_-_
0 = Framer at far end PW termination point uses T1-SF framing.
1 = Framer at far end PW termination point uses T1-ESF framing.
HDLC Bundles: Combined SCTXCE/SCTXDFSE bits (TXP & RXP directions);
0/0b = Sequence Number is always 0
0/1b = Sequence Number is auto-incremented and wrap-around uses zero
1/0b = Reserved
1/1b = Sequence Number is auto-incremented and wrap-around skips zero
SAT/CES TXP Conditioning Octet Select / HDLC Time Slot Width Select.
SAT/CES Bundles – selects TXP packet Conditioning Data value
0 = Ethernet Conditioning Octet A (G.ECCR1.ECOA)
1 = Ethernet Conditioning Octet B (G.ECCR1.ECOB)
2 = Ethernet Conditioning Octet C (G.ECCR1.ECOC)
3 = Ethernet Conditioning Octet D (G.ECCR1.ECOD)
4 = Ethernet Conditioning Octet E (G.ECCR2.ECOE)
5 = Ethernet Conditioning Octet F (G.ECCR2.ECOF)
6 = Ethernet Conditioning Octet G (G.ECCR2.ECOG)
7 = Ethernet Conditioning Octet H (G.ECCR2.ECOH)
SCTXCO
S
[2:0] rwd-_-_
HDLC Bundles – HDLC Encapsulation bit-width
0 = Use Nx8-bit HDLC encapsulation (for Unstructured and Nx64 Kb/s HDLC)
1 = Use Structured 7-bit HDLC encapsulation + 1 unassigned bit
2 = Use Structured 2-bit HDLC encapsulation (2 MSbits) + 6 unassigned LSbits
3 = Use Structured 2-bit HDLC encapsulation (2 LSbits) + 6 unassigned MSbits
4 to 7 reserved
BCDR2. A:00B0h
Bundle Configuration Data Register 2. Default: 0x00.00.00.00
Active Time Slot Select selects which TDM Port Timeslots are used by this
Bundle (TXP and RXP directions). One bit for each Timeslot (E1: 0 – 31; T1: 0 –
23). ATSS[x] = 0 = Timeslot “x” disabled. 1 = Timeslot “x” enabled. For an
Unstructured Bundle (SAT or HDLC), ATSS = 0x0000.0001.
ATSS
[31:0] rwd-_-_
BCDR3. A:00B4h
Bundle Configuration Data Register 3. Default: 0x00.00.00.00
Reserved.
RSVD
[31:5]
TXP Packet Mode Select.
TXPMS
[4:3] rwd-_-_
0 = Stop Transmission of TXP packets (CES, SAT, HDLC and Clock Only)
1 = Transmit TXP packets with payload (CES, SAT and HDLC)
2 = Transmit TXP packets without payload (Clock Only)
3 = reserved
TXP Bundle Structure Type Select.
TXBTS
TXBPS
[2:1] rwd-_-_
[0] rwd-_-_
0 = SAT or HDLC for Unstructured TDM Port
1 = CES without CAS or HDLC for Structured T1/E1 Port
2 = CES with CAS or HDLC for Structured T1/E1 Port
3 = Reserved
TXP Bundle Priority Select selects transmit priority for SAT/CES TXP packets.
0 = Low priority (“normal” for Bundles not used for far end Clock Recovery)
1 = High priority (“normal” for Bundles used for far end Clock Recovery)
BCDR4. A:00B8h
Bundle Configuration Data Register 4. Default: 0x00.00.00.00
Reserved.
RSVD
RXRE
[31:22]
[21] rwd-_-_
RXP RTP Enable.
0 = RTP header is not accepted in RXP packets.
1 = RTP header is required
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
RXP Control Word Enable.
RXCWE
[20] rwd-_-_
0 = Control Word is not accepted in RXP packets (optional for HDLC)
1 = Control Word is required (only valid setting for CES/SAT; optional for HDLC)
RXP Header Type Select selects the PW Header Type that is required.
0 = MPLS (MFA-8)
1 = UDP over IP (IPv4 or IPv6)
2 = L2TPv3 over IP (IPv4 or IPv6)
3 = MEF-8
RXHTS
RXBTS
RXLCS
[19:18] rwd-_-_
RXP Bundle Structure Type Select.
0 = SAT or HDLC for Unstructured TDM Port
1 = CES without CAS or HDLC for Structured T1/E1 Port
2 = CES with CAS or HDLC for Structured T1/E1 Port
3 = Reserved
[17:16] rwd-_-_
[15:14] rwd-_-_
RXP Labels Cookie Select selects maximum # of Labels or Cookies allowed.
MPLS:
0 = Reserved
1 = One label in the RXP MPLS Header (1 Inner Label)
2 = Two labels in the RXP MPLS Header (1 Inner and 1 Outer Label)
3 = Three labels in the RXP MPLS Header (1 Inner and 2 Outer Labels)
L2TPv3:
0 = No Cookies in the RXP L2TPv3 Header
1 = One Cookie in the RXP L2TPv3 Header
2 = Two Cookies in the RXP L2TPv3 Header
3 = Reserved
RXP UDP Bundle ID Location Select selects UDP BID location when
PC.CR1.UBIDLS= 0 and PC.CR1.UBIDLCE = 1 (otherwise RXUBIDLS is ignored)
0 = Test UDP Source Port for BID match
RXUBIDL
S
[13] rwd-_-_
[12] rwd-_-_
1 = Test UDP Destination Port for BID match
CES Last Value Insertion.
SCLVI
CES Bundles – selects type of data transmitted in place of missing RXP packets
0 = Last Value Insertion disabled, use Conditioning Data (B.BCDR1.SCTXCOS)
1 = Repeat Timeslot data for up to 3 TDM frames then use Conditioning Data
HDLC Bundles - selects Inter-frame Fill used between transmit HDLC packets.
0 = Use 0x7E for Inter-frame Fill
1 = Use all ones for Inter-frame Fill
Xmt Conditioning Octet Select selects Xmt Conditioning Data transmitted at
TDM Port for unassigned timeslots, missing packets and empty Jitter Buffer.
0 = TDM Conditioning Octet A (G.TCCR1.TCOA)
RXCOS
[11:9] rwd-_-_
1 = TDM Conditioning Octet B (G.TCCR1.TCOB)
2 = TDM Conditioning Octet C (G.TCCR1.TCOC)
3 = TDM Conditioning Octet D (G.TCCR1.TCOD)
4 = TDM Conditioning Octet E (G.TCCR2.TCOE)
5 = TDM Conditioning Octet F (G.TCCR2.TCOF)
6 = TDM Conditioning Octet G (G.TCCR2.TCOG)
7 = TDM Conditioning Octet H (G.TCCR2.TCOH)
RXP OAM In Control Word Enable enables processing of In-band VCCV
packets when Control Word matches PC.CR5.VOV and PC.CR5.VOM.
0 = Do not look for In-band VCCV indication in Control Word
RXOICW
E
[8] rwd-_-_
1 = Send “In-band VCCV” packet to CPU or discard according to PC.CR1.DPS7
RXP Bundle Destination Select.
RXBDS
[7:6] rwd-_-_
0 = Send packet to SAT/CES Jitter Buffer or HDLC Buffer
1 = Send packet to CPU (“CPU Debug RXP PW Bundle” setting)
2 = reserved
3 = Discard the packet (timing information is still available for Clock Recovery)
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
Port Number Select selects TDM Port associated with Bundle (PNS = 0 = TDM
PNS
[5:1] rwd-_-_
Port #1, PNS = 31 = TDM Port #32).
Port Clock Recovery Enable.
PCRE
[0] rwd-_-_
0 = Do not use this Bundle for Clock Recovery
1 = Use RXP Bundle for Clock Recovery (enable Clock Connection)
BCDR5. A:00BCh
Bundle Configuration Data Register 5. Default: 0x00.00.00.00
Reserved.
RSVD
PDVT
[31:25]
Packet Delay Variation Time selects minimum Jitter Buffer fill level required
before RXP payload data is forwarded to the transmit TDM Port. This function is
not used with Clock Only Bundles.
[24:10] rwd-_-_
SAT Bundles with payload and SAT Clock Only Bundles
Forward data when fill level = PDVT * 32 TDM Port bit periods
CES Bundles with payload and CES Clock Only Bundles (set unused bits = “0”)
For Pn.PTCR1.BFD = 1: Forward when fill level = PDVT * 125 us; use bits [19:10]
For Pn.PTCR1.BFD = 2: Forward when fill level = PDVT * 250 us; use bits [20:10]
For Pn.PTCR1.BFD = 3: Forward when fill level = PDVT * 500 us; use bits [21:10]
Maximum Jitter Buffer Sense selects Jitter Buffer Overrun Fill level that
increments the Overrun Event Count (JEBEC). This function is not used with
Clock Only Bundles. This function does not generate an interrupt.
SAT Bundles: Overrun Fill Level = MJBS * 1024 TDM Port bit periods
CES Bundles: Overrun Fill Level = MJBS * 500 us
MJBS
[9:0] rwd-_-_
BESR1. A:00C0h
Bundle Encap Status Register 1. Default: 0x00.00.00.00
Port Receive HDLC Abort Status Latch = “1” indicates one or more HDLC Abort
PRHASL
[31] rld-cor-_
codes have been detected on one or more receive TDM Ports.
Reserved.
RSVD
[30:20]
Port Receive HDLC Error Frame Count = number of receive TDM Port HDLC
PRHEFC
[19:0] rld-cnr-nc
frames with an error (including FCS, alignment, abort, too short or too long).
BESR2. A:00C4h
Bundle Encap Status Register 2. Default: 0x00.00.00.00
Good Packet TXP Count = # transmitted TXP packets (all Bundle types)
Bundle Encap Status Register 3. Default: 0x00.00.00.00
Reserved.
GPTXC
[31:0] rld-cnr-nc
BESR3. A:00C8h
RSVD
[31:5]
[4] rld-cor-_
Short HDLC Frame Status Latch = “1” indicates the size for one or more receive
SHFSL
TDM Port HDLC frames was < 4 bytes (including FCS bytes).
Long HDLC Frame Status Latch = “1” indicates the size for one or more
received HDLC frames was > maximum size (including FCS; B.BCDR1.PMS)
LHFSL
AESL
[3] rld-cor-_
[2] rld-cor-_
[1] rld-cor-_
[0] rld-cor-_
Alignment Error Status Latch = “1” indicates one or more receive TDM Port
HDLC frames had an alignment error.
CRC Error Status Latch = “1” indicates one or more receive TDM Port HDLC
frames had a CRC (FCS) Error.
CESL
TXP Packet Space Full Status Latch = “1” indicates one or more receive TDM
TXPSFSL
Port HDLC frames were discarded due to TXP packet buffer overflow in SDRAM.
BDSR1. A:00D0h
Bundle Decap Status Register 1. Default: 0x00.00.00.00
Jitter Buffer Late Packet Discard Status Latch = “1” indicates one or more RXP
JBLPDSL
[31] rld-cor-_
packets discarded due to late arrival (Sequence # already passed; SAT/CES).
Reserved.
RSVD
PDC
[30:20]
Packet stream Defect Count = # SAT/CES RXP packet stream defect events.
PC.CR21.PDCC selects which defect conditions are counted. BDSR1.PDC and
BDSR2.JBEC can be programmed to count the same or different conditions. Not
valid for Clock Only Bundles. For HDLC Bundles only Overruns can be counted.
[19:0] rld-cnr-nc
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
BDSR2. A:00D4h
Bundle Decap Status Register 2. Default: 0x00.00.00.00
Reserved.
RSVD
JBEC
[31:20]
Jitter Buffer Event Count = # SAT/CES RXP packet stream defect events.
PC.CR21.JBECC selects which defect conditions are counted. BDSR1.PDC and
BDSR2.JBEC can be programmed to count the same or different conditions. Not
valid for Clock Only Bundles. For HDLC Bundles only Overruns can be counted.
[19:0] rld-cnr-nc
BDSR3. A:00D8h
Bundle Decap Status Register 3. Default: 0x00.00.00.00
Reserved.
RSVD
JBLL
[31]
Jitter Buffer Low Level = lowest Jitter Buffer fill level since last read. A read
operation forces JBLL = “all ones” until next Jitter Buffer current level available.
When Underrun is reached, the value remains zero until it is read by the CPU.
The # JBLL bits is equal to the # JBCL bits (not valid for HDLC or Clock Only).
[30:16] rld-cor-_
Reserved.
RSVD
JBHL
[15]
Jitter Buffer High Level = highest Jitter Buffer fill level since last read (not valid
for HDLC or Clock Only). A read operation forces JBLL = “all zeros” until next
Jitter Buffer current level available. When Overrun is reached, JBHL =
B.BCDR5.MJBS until read by CPU. The # JBHL bits is equal to the # JBCL bits.
[14:0] rld-cor-_
BDSR4. A:00DCh
Bundle Decap Status Register 4. Default: 0x00.00.00.00
Good Packet RXP Count = # received good RXP packets (all Bundle types)
Bundle Decap Status Register 5. Default: 0x00.00.00.00
GPRXC
[31:0] rld-cnr-nc
BDSR5. A:00E0h
SAT/CES Jumped/Lost Packet Count indicates how many Jumped or Lost
Sequence # conditions have been detected (according to G.GCR.JLPC).
SAT/CES Bundles – accumulated difference between expected and received
packet Sequence #. Total Missing Packets can be calculated with:
Total Missing Packets = Jumped Packets – Re-ordered Packets
= (B.BSDR5.SCJPC – B.BSDR6.SCRPC)
SCJPC
[31:0] rld-cnr-nc
HDLC Bundles (Jumped Count only) – accumulated difference between expected
and received packet Sequence # for difference < 32,768 (see B.BSDR6.SCRPC).
BDSR6. A:00E4h
Bundle Decap Status Register 6. Default: 0x00.00.00.00
Reserved.
RSVD
[31:20]
SAT/CES Reordered/Duplicate Packet Count indicates how many Re-ordered
or Duplicate packet conditions have been detected (according to G.GCR.RDPC).
SAT/CES Bundles - # successfully Re-ordered or Duplicate packet events.
SCRPC
[19:0] rld-cnr-nc
HDLC Bundles - # RXP packet with a Sequence Number Jump > 32,767.
Bundle Decap Status Register 7. Default: 0x00.00.00.00
Reserved.
BDSR7. A:00E8h
RSVD
[31:24]
[23] rld-cor-_
SAT/CES Payload Size/Sequence Error Status Latch.
SCPSES
L
SAT Bundles: “1” = 1 or more RXP packets with payload size ≠ B.BCDR1.PMS
CES Bundles: “1” = 1 or more RXP packets with payload size ≠ B.BCDR1.PMS
(for CES with CAS this test function includes the expected CAS Signaling bytes).
HDLC Bundles “1” = 1 or more RXP packets with late or early Sequence Number
Jump > 32,768.
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
Packet Length Error Status Latch “1” = one (or more) RXP packets were
detected with a payload size larger than indicated by the header length fields (as
indicated below). The RTP and Control Word fields are optional according to the
B.BCDR4.RXRE and B.BCDR4.RXCWE settings.
PLESL
[22] rld-cor-_
IPv4/IPv6 -
IPv4 Total Length field > (actual payload + IP Header + Control Word + RTP)
IPv6 Payload Length field > (actual payload + IP Header + Control Word + RTP)
MPLS -
Control Word Length field > (actual payload + Control Word + RTP)
SAT/CES Jitter Buffer Early Packet Discard Status Latch.
SAT/CES Bundles
SCJBEP
DSL
[21] rld-cor-_
“1” = one (or more) RXP packets were discarded due to a Sequence Number that
was earlier than the Jitter Buffer Current Level.
HDLC Bundles
“1” = one (or more) RXP packets were discarded due to an HDLC buffer overflow.
Jitter Buffer Current Level.
JBCL
[20:6] rod-_-_
SAT Bundles
Jitter Buffer Fill Level = JBCL * 32 TDM Port Bit Periods
CES Bundles
For Pn.PTCR1.BFD = 1: Jitter Buffer Fill Level = JBCL * 125 us
For Pn.PTCR1.BFD = 2: Jitter Buffer Fill Level = JBCL * 250 us
For Pn.PTCR1.BFD = 3: Jitter Buffer Fill Level = JBCL * 500 us
L Bit Data = Control Word L-bit state in most recent RXP packet for this Bundle.
R Bit Data = Control Word R-bit state in most recent RXP packet for this Bundle.
LBD
RBD
DMD
[5] rod-_-_
[4] rod-_-_
Defect Modifier Data = the state of the Control Word M-bits in the most recent
[3:2] rod-_-_
RXP packet for this Bundle (one for each M-bit).
Fragmentation Bit Data = the state for the Control Word Frag-bits in the most
FBD
[1:0] rod-_-_
recent RXP packet for this Bundle (one for each Frag bit).
BDSR8. A:00ECh
Bundle Decap Status Register 8. Default: 0x00.00.00.00
Reserved.
RSVD
[31:20]
SAT/CES Malformed Packet Count = number received packets that fail to match
the configured payload length, but excluding packets with L-bit = 1. This count is
enabled and incremented by the Sanity Check function (B.BCDR1.SCSCFPD).
SCMPC
[19:0] rld-cor-_
BDSR9. A:00F0h
Bundle Decap Status Register 9. Default: 0x00.00.00.00
Reserved.
RSVD
[31:20]
SAT/CES R-Bit Packet Count = # received packets with Control Word, R bit = 1.
SCRBPC
[19:0] rld-cor-_
10.3.2.4 Bundle Status Latch Registers (B.)
Table 10-9. Bundle Status Latch Registers (B.)
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
G0SRL. A:0100h
Group 0 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [7:0] respectively.
CWCDSL
[7:0]
[7:0] rls-cor-i3
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
G1SRL. A:0104h
Group 1 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [15:8] respectively.
CWCDSL
[15:8]
[7:0] rls-cor-i3
G2SRL. A:0108h
Group 2 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [23:16] respectively.
CWCDSL
[23:16]
[7:0] rls-cor-i3
G3SRL. A:010Ch
Group 3 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [31:24] respectively.
CWCDSL
[31:24]
[7:0] rls-cor-i3
G4SRL. A:0110h
Group 4 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [39:32] respectively.
CWCDSL
[39:32]
[7:0] rls-cor-i3
G5SRL. A:0114h
Group 5 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [47:40] respectively.
CWCDSL
[47:40]
[7:0] rls-cor-i3
G6SRL. A:0118h
Group 6 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [55:48] respectively.
CWCDSL
[55:48]
[7:0] rls-cor-i3
G7SRL. A:011Ch
Group 7 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [63:56] respectively.
CWCDSL
[63:56]
[7:0] rls-cor-i3
G8SRL. A:0120h
Group 8 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [71:64] respectively.
CWCDSL
[71:64]
[7:0] rls-cor-i3
G9SRL. A:0124h
Group 9 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [79:72] respectively.
CWCDSL
[79:72]
[7:0] rls-cor-i3
G10SRL. A:0128h
Group 10 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [87:80] respectively.
CWCDSL
[87:80]
[7:0] rls-cor-i3
G11SRL. A:012Ch
Group 11 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [95:88] respectively.
CWCDSL
[95:88]
[7:0] rls-cor-i3
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
G12SRL. A:0130h
Group 12 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [103:96] respectively.
CWCDSL
[103:96]
[7:0] rls-cor-i3
G13SRL. A:0134h
Group 13 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [111:104] respectively.
CWCDSL
[111:104]
[7:0] rls-cor-i3
G14SRL. A:0138h
Group 14 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [119:112] respectively.
CWCDSL
[119:112]
[7:0] rls-cor-i3
G15SRL. A:013Ch
Group 15 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [127:120] respectively.
CWCDSL
[127:120]
[7:0] rls-cor-i3
G16SRL. A:0140h
Group 16 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [135:128] respectively.
CWCDSL
[135:128]
[7:0] rls-cor-i3
G17SRL. A:0144h
Group 17 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [143:136] respectively.
CWCDSL
[143:136]
[7:0] rls-cor-i3
G18SRL. A:0148h
Group 18 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [151:144] respectively.
CWCDSL
[151:144]
[7:0] rls-cor-i3
G19SRL. A:014Ch
Group 19 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [159:152] respectively.
CWCDSL
[159:152]
[7:0] rls-cor-i3
G20SRL. A:0150h
Group 20 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [167:160] respectively.
CWCDSL
[167:160]
[7:0] rls-cor-i3
G21SRL. A:0154h
Group 21 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [175:168] respectively.
CWCDSL
[175:168]
[7:0] rls-cor-i3
G22SRL. A:0158h
Group 22 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [183:176] respectively.
CWCDSL
[183:176]
[7:0] rls-cor-i3
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DS34S132 DATA SHEET
B. Field Addr (A:)
Name
Bit [x:y] Type
Description
G23SRL. A:015Ch
Group 23 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [191:184] respectively.
CWCDSL
[191:184]
[7:0] rls-cor-i3
G24SRL.
Group 24 Status Register Latch. Default: 0x00.00.00.00
Reserved.
A:0160h
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [199:192] respectively.
CWCDSL
[199:192]
[7:0] rls-cor-i3
G25SRL. A:0164h
Group 25 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [207:200] respectively.
CWCDSL
[207:200]
[7:0] rls-cor-i3
G26SRL. A:0168h
Group 26 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [215:208] respectively.
CWCDSL
[215:208]
[7:0] rls-cor-i3
G27SRL. A:016Ch
Group 27 Status Register Latch.
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [223:216] respectively.
CWCDSL
[223:216]
[7:0] rls-cor-i3
G28SRL. A:0170h
Group 28 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [231:224] respectively.
CWCDSL
[231:224]
[7:0] rls-cor-i3
G29SRL. A:0174h
Group 29 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [239:232] respectively.
CWCDSL
[239:232]
[7:0] rls-cor-i3
G30SRL. A:0178h
Group 30 Status Register Latch.
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [247:240] respectively.
CWCDSL
[247:240]
[7:0] rls-cor-i3
G31SRL. A:017Ch
Group 31 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Status Latch = “1” indicates change detected in a
Control Word for a Bundle. Bits [7:0] indicate Bundles [255:248] respectively.
CWCDSL
[255:248]
[7:0] rls-cor-i3
10.3.2.5 Bundle Status Register Interrupt Enables (B.)
Table 10-10. Bundle Status Register Interrupt Enables (B.)
B. Field Addr (A:)
Name
G0SRIE. A:0180h
RSVD [31:8]
Bit [x:y] Type
Description
Group 0 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
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B. Field Addr (A:)
Name
Bit [x:y] Type
Description
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G0SRL[z] = 1 and B.G0SRIE[z] = 1, forces G.GSR5[0] = 1.
CWCDIE
[7:0]
[7:0] rwc-_-i3
G1SRIE. A:0184h
Group 1 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G1SRL[z] = 1 and B.G1SRIE[z] = 1, forces G.GSR5[1] = 1.
CWCDIE
[15:8]
[7:0] rwc-_-i3
G2SRIE. A:0188h
Group 2 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G2SRL[z] = 1 and B.G2SRIE[z] = 1, forces G.GSR5[2] = 1.
CWCDIE
[23:16]
[7:0] rwc-_-i3
G3SRIE. A:018Ch
Group 3 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G3SRL[z] = 1 and B.G3SRIE[z] = 1, forces G.GSR5[3] = 1.
CWCDIE
[31:24]
[7:0] rwc-_-i3
G4SRIE. A:0190h
Group 4 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G4SRL[z] = 1 and B.G4SRIE[z] = 1, forces G.GSR5[4] = 1.
CWCDIE
[39:32]
[7:0] rwc-_-i3
G5SRIE. A:0194h
Group 5 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G5SRL[z] = 1 and B.G5SRIE[z] = 1, forces G.GSR5[5] = 1.
CWCDIE
[47:40]
[7:0] rwc-_-i3
G6SRIE. A:0198h
Group 6 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G6SRL[z] = 1 and B.G6SRIE[z] = 1, forces G.GSR5[6] = 1.
CWCDIE
[55:48]
[7:0] rwc-_-i3
G7SRIE. A:019Ch
Group 7 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G7SRL[z] = 1 and B.G7SRIE[z] = 1, forces G.GSR5[7] = 1.
CWCDIE
[63:56]
[7:0] rwc-_-i3
G8SRIE. A:01A0h
Group 8 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G8SRL[z] = 1 and B.G8SRIE[z] = 1, forces G.GSR5[8] = 1.
CWCDIE
[71:64]
[7:0] rwc-_-i3
G9SRIE. A:01A4h
Group 9 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G9SRL[z] = 1 and B.G9SRIE[z] = 1, forces G.GSR5[9] = 1.
CWCDIE
[79:72]
[7:0] rwc-_-i3
G10SRIE. A:01A8h
Group 10 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G10SRL[z] = 1 and B.G10SRIE[z] = 1, forces G.GSR5[10] = 1.
CWCDIE
[87:80]
[7:0] rwc-_-i3
G11SRIE. A:01ACh
RSVD [31:8]
Group 11 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
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B. Field Addr (A:)
Name
Bit [x:y] Type
Description
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G11SRL[z] = 1 and B.G11SRIE[z] = 1, forces G.GSR5[11] = 1.
CWCDIE
[95:88]
[7:0] rwc-_-i3
G12SRIE. A:01B0h
Group 12 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G12SRL[z] = 1 and B.G12SRIE[z] = 1, forces G.GSR5[12] = 1.
CWCDIE
[103:96]
[7:0] rwc-_-i3
G13SRIE. A:01B4h
Group 13 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G13SRL[z] = 1 and B.G13SRIE[z] = 1, forces G.GSR5[13] = 1.
CWCDIE
[111:104]
[7:0] rwc-_-i3
G14SRIE. A:01B8h
Group 14 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G14SRL[z] = 1 and B.G14SRIE[z] = 1, forces G.GSR5[14] = 1.
CWCDIE
[119:112]
[7:0] rwc-_-i3
G15SRIE. A:01BCh
Group 15 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G15SRL[z] = 1 and B.G15SRIE[z] = 1, forces G.GSR5[15] = 1.
CWCDIE
[127:120]
[7:0] rwc-_-i3
G16SRIE. A:01C0h
Group 16 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G16SRL[z] = 1 and B.G16SRIE[z] = 1, forces G.GSR5[16] = 1.
CWCDIE
[135:128]
[7:0] rwc-_-i3
G17SRIE. A:01C4h
Group 17 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G17SRL[z] = 1 and B.G17SRIE[z] = 1, forces G.GSR5[17] = 1.
CWCDIE
[143:136]
[7:0] rwc-_-i3
G18SRIE. A:01C8h
Group 18 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G18SRL[z] = 1 and B.G18SRIE[z] = 1, forces G.GSR5[18] = 1.
CWCDIE
[151:144]
[7:0] rwc-_-i3
G19SRIE. A:01CCh
Group 19 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G19SRL[z] = 1 and B.G19SRIE[z] = 1, forces G.GSR5[19] = 1.
CWCDIE
[159:152]
[7:0] rwc-_-i3
G20SRIE. A:01D0h
Group 20 Status Register Interrupt Enable.
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G20SRL[z] = 1 and B.G20SRIE[z] = 1, forces G.GSR5[20] = 1.
CWCDIE
[167:160]
[7:0] rwc-_-i3
G21SRIE. A:01D4h
Group 21 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G21SRL[z] = 1 and B.G21SRIE[z] = 1, forces G.GSR5[21] = 1.
CWCDIE
[175:168]
[7:0] rwc-_-i3
G22SRIE. A:01D8h
RSVD [31:8]
Group 22 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
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B. Field Addr (A:)
Name
Bit [x:y] Type
Description
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G22SRL[z] = 1 and B.G22SRIE[z] = 1, forces G.GSR5[22] = 1.
CWCDIE
[183:176]
[7:0] rwc-_-i3
G23SRIE. A:01DCh
Group 23 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G23SRL[z] = 1 and B.G23SRIE[z] = 1, forces G.GSR5[23] = 1.
CWCDIE
[191:184]
[7:0] rwc-_-i3
G24SRIE. A:01E0h
Group 24 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G24SRL[z] = 1 and B.G24SRIE[z] = 1, forces G.GSR5[24] = 1.
CWCDIE
[199:192]
[7:0] rwc-_-i3
G25SRIE. A:01E4h
Group 25 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G25SRL[z] = 1 and B.G25SRIE[z] = 1, forces G.GSR5[25] = 1.
CWCDIE
[207:200]
[7:0] rwc-_-i3
G26SRIE. A:01E8h
Group 26 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G26SRL[z] = 1 and B.G26SRIE[z] = 1, forces G.GSR5[26] = 1.
CWCDIE
[215:208]
[7:0] rwc-_-i3
G27SRIE. A:01ECh
Group 27 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G27SRL[z] = 1 and B.G27SRIE[z] = 1, forces G.GSR5[27] = 1.
CWCDIE
[223:216]
[7:0] rwc-_-i3
G28SRIE. A:01F0h
Group 28 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G28SRL[z] = 1 and B.G28SRIE[z] = 1, forces G.GSR5[28] = 1.
CWCDIE
[231:224]
[7:0] rwc-_-i3
G29SRIE. A:01F4h
Group 29 Status Register Interrupt Enable.
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G29SRL[z] = 1 and B.G29SRIE[z] = 1, forces G.GSR5[29] = 1.
CWCDIE
[239:232]
[7:0] rwc-_-i3
G30SRIE. A:01F8h
Group 30 Status Register Interrupt Enable.
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G30SRL[z] = 1 and B.G30SRIE[z] = 1, forces G.GSR5[30] = 1.
CWCDIE
[247:240]
[7:0] rwc-_-i3
G31SRIE. A:01FCh
Group 31 Status Register Interrupt Enable.
Reserved.
RSVD
[31:8]
Control Word Change Detect Interrupt Enable. For z = 0 to 7, the combination
of B.G31SRL[z] = 1 and B.G31SRIE[z] = 1, forces G.GSR5[31] = 1.
CWCDIE
[255:248]
[7:0] rwc-_-i3
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DS34S132 DATA SHEET
10.3.3 Jitter Buffer Registers (JB.)
10.3.3.1 Jitter Buffer Status Registers (JB.)
Table 10-11. Jitter Buffer Status Registers (JB.)
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G0SRL. A:0200h
Group 0 Status Register Latch.
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer Underrun or “Start of Playout” according
JBU [7:0]
[7:0] rls-cor-i3
to the G.GCR.IPSE setting. Bits [7:0] indicate Bundles [7:0] respectively.
G1SRL. A:0204h
Group 1 Status Register Latch.
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[15:8]
[15:8] respectively. This can also optionally indicate the start of playout.
G2SRL. A:0208h
Group 2 Status Register Latch.
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[23:16]
[23:16] respectively. This can also optionally indicate the start of playout.
G3SRL. A:020Ch
Group 3 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[31:24]
[31:24] respectively. This can also optionally indicate the start of playout.
G4SRL. A:0210h
Group 4 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[39:32]
[39:32] respectively. This can also optionally indicate the start of playout.
G5SRL. A:0214h
Group 5 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[47:40]
[47:40] respectively. This can also optionally indicate the start of playout.
G6SRL. A:0218h
Group 6 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[55:48]
[55:48] respectively. This can also optionally indicate the start of playout.
G7SRL. A:021Ch
Group 7 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[63:56]
[63:56] respectively. This can also optionally indicate the start of playout.
G8SRL. A:0220h
Group 8 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[71:64]
[71:64] respectively. This can also optionally indicate the start of playout.
G9SRL. A:0224h
Group 9 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[79:72]
[79:72] respectively. This can also optionally indicate the start of playout.
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DS34S132 DATA SHEET
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G10SRL. A:0228h
Group 10 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[87:80]
[87:80] respectively. This can also optionally indicate the start of playout.
G11SRL. A:022Ch
Group 11 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[95:88]
[95:88] respectively. This can also optionally indicate the start of playout.
G12SRL. A:0230h
Group 12 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[103:96]
[103:96] respectively. This can also optionally indicate the start of playout.
G13SRL. A:0234h
Group 13 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[111:104]
[111:104] respectively. This can also optionally indicate the start of playout.
G14SRL. A:0238h
Group 14 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[119:112]
[119:112] respectively. This can also optionally indicate the start of playout.
G15SRL. A:023Ch
Group 15 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[127:120]
[127:120] respectively. This can also optionally indicate the start of playout.
G16SRL. A:0240h
Group 16 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[135:128]
[135:128] respectively. This can also optionally indicate the start of playout.
G17SRL. A:0244h
Group 17 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[143:136]
[143:136] respectively. This can also optionally indicate the start of playout.
G18SRL. A:0248h
Group 18 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[151:144]
[151:144] respectively. This can also optionally indicate the start of playout.
G19SRL. A:024Ch
Group 19 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[159:152]
[159:152] respectively. This can also optionally indicate the start of playout.
G20SRL. A:0250h
Group 20 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[167:160]
[167:160] respectively. This can also optionally indicate the start of playout.
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DS34S132 DATA SHEET
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G21SRL. A:0254h
Group 21 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[175:168]
[175:168] respectively. This can also optionally indicate the start of playout.
G22SRL. A:0258h
Group 22 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[183:176]
[183:176] respectively. This can also optionally indicate the start of playout.
G23SRL. A:025Ch
Group 23 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[191:184]
[191:184] respectively. This can also optionally indicate the start of playout.
G24SRL. A:0260h
Group 24 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[199:192]
[199:192] respectively. This can also optionally indicate the start of playout.
G25SRL. A:0264h
Group 25 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[207:200]
[207:200] respectively. This can also optionally indicate the start of playout.
G26SRL. A:0268h
Group 26 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[215:208]
[215:208] respectively. This can also optionally indicate the start of playout.
G27SRL. A:026Ch
Group 27 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[223:216]
[223:216] respectively. This can also optionally indicate the start of playout.
G28SRL. A:0270h
Group 28 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[231:224]
[231:224] respectively. This can also optionally indicate the start of playout.
G29SRL. A:0274h
Group 29 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[239:232]
[239:232] respectively. This can also optionally indicate the start of playout.
G30SRL. A:0278h
Group 30 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[247:240]
[247:240] respectively. This can also optionally indicate the start of playout.
G31SRL. A:027Ch
Group 31 Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun “1” = Jitter Buffer underrun. Bits [7:0] indicate Bundles
JBU
[7:0] rls-cor-i3
[255:248]
[255:248] respectively. This can also optionally indicate the start of playout.
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DS34S132 DATA SHEET
10.3.3.2 Jitter Buffer Status Register Interrupt Enables (JB.)
Table 10-12. Jitter Buffer Status Register Interrupt Enables (JB.)
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G0SRIE. A:0280h
Group 0 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
G0SRL[z] = 1 and G0SRIE[z] = 1, forces G.GSR6[0] = 1.
JBUIE
[7:0]
[7:0] rwc-_-i3
G1SRIE. A:0284h
Group 1 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G1SRL[z] = 1 and JB.G1SRIE[z] = 1, forces G.GSR6[1] = 1.
JBUIE
[15:8]
[7:0] rwc-_-i3
G2SRIE. A:0288h
Group 2 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G2SRL[z] = 1 and JB.G2SRIE[z] = 1, forces G.GSR6[2] = 1.
JBUIE
[23:16]
[7:0] rwc-_-i3
G3SRIE. A:028Ch
Group 3 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G3SRL[z] = 1 and JB.G3SRIE[z] = 1, forces G.GSR6[3] = 1.
JBUIE
[31:24]
[7:0] rwc-_-i3
G4SRIE. A:0290h
Group 4 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G4SRL[z] = 1 and JB.G4SRIE[z] = 1, forces G.GSR6[4] = 1.
JBUIE
[39:32]
[7:0] rwc-_-i3
G5SRIE. A:0294h
Group 5 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G5SRL[z] = 1 and JB.G5SRIE[z] = 1, forces G.GSR6[5] = 1.
JBUIE
[47:40]
[7:0] rwc-_-i3
G6SRIE. A:0298h
Group 6 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G6SRL[z] = 1 and JB.G6SRIE[z] = 1, forces G.GSR6[6] = 1.
JBUIE
[55:48]
[7:0] rwc-_-i3
G7SRIE. A:029Ch
Group 7 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G7SRL[z] = 1 and JB.G7SRIE[z] = 1, forces G.GSR6[7] = 1.
JBUIE
[63:56]
[7:0] rwc-_-i3
G8SRIE. A:02A0h
Group 8 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G8SRL[z] = 1 and JB.G8SRIE[z] = 1, forces G.GSR6[8] = 1.
JBUIE
[71:64]
[7:0] rwc-_-i3
G9SRIE. A:02A4h
Group 9 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G9SRL[z] = 1 and JB.G9SRIE[z] = 1, forces G.GSR6[9] = 1.
JBUIE
[79:72]
[7:0] rwc-_-i3
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DS34S132 DATA SHEET
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G10SRIE. A:02A8h
Group 10 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G10SRL[z] = 1 and JB.G10SRIE[z] = 1, forces G.GSR6[10] = 1.
JBUIE
[87:80]
[7:0] rwc-_-i3
G11SRIE. A:02ACh
Group 11 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JB.G11SRL[z] = 1 and JB.G11SRIE[z] = 1, forces G.GSR6[11] = 1.
JBUIE
[95:88]
[7:0] rwc-_-i3
G12SRIE. A:02B0h
Group 12 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[103:96]
JB.G12SRL[z] = 1 and JB.G12SRIE[z] = 1, forces G.GSR6[12] = 1.
G13SRIE. A:02B4h
Group 13 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[111:104]
JB.G13SRL[z] = 1 and JB.G13SRIE[z] = 1, forces G.GSR6[13] = 1.
G14SRIE. A:02B8h
Group 14 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[119:112]
JB.G14SRL[z] = 1 and JB.G14SRIE[z] = 1, forces G.GSR6[14] = 1.
G15SRIE. A:02BCh
Group 15 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[127:120]
JB.G15SRL[z] = 1 and JB.G15SRIE[z] = 1, forces G.GSR6[15] = 1.
G16SRIE. A:02C0h
Group 16 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[135:128]
JB.G16SRL[z] = 1 and JB.G16SRIE[z] = 1, forces G.GSR6[16] = 1.
G17SRIE. A:02C4h
Group 17 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[143:136]
JB.G17SRL[z] = 1 and JB.G17SRIE[z] = 1, forces G.GSR6[17] = 1.
G18SRIE. A:02C8h
Group 18 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[151:144]
JB.G18SRL[z] = 1 and JB.G18SRIE[z] = 1, forces G.GSR6[18] = 1.
G19SRIE. A:02CCh
Group 19 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[159:152]
JB.G19SRL[z] = 1 and JB.G19SRIE[z] = 1, forces G.GSR6[19] = 1.
G20SRIE. A:02D0h
Group 20 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[167:160]
JB.G20SRL[z] = 1 and JB.G20SRIE[z] = 1, forces G.GSR6[20] = 1.
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DS34S132 DATA SHEET
JB. Field Addr (A:)
Name
Bit [x:y] Type
Description
G21SRIE. A:02D4h
Group 21 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[175:168]
JB.G21SRL[z] = 1 and JB.G21SRIE[z] = 1, forces G.GSR6[21] = 1.
G22SRIE. A:02D8h
Group 22 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[183:176]
JB.G22SRL[z] = 1 and JB.G22SRIE[z] = 1, forces G.GSR6[22] = 1.
G23SRIE. A:02DCh
Group 23 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[191:184]
JB.G23SRL[z] = 1 and JB.G23SRIE[z] = 1, forces G.GSR6[23] = 1.
G24SRIE. A:02E0h
Group 24 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[199:192]
JB.G24SRL[z] = 1 and JB.G24SRIE[z] = 1, forces G.GSR6[24] = 1.
G25SRIE. A:02E4h
Group 25 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[207:200]
JB.G25SRL[z] = 1 and JB.G25SRIE[z] = 1, forces G.GSR6[25] = 1.
G26SRIE. A:02E8h
Group 26 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[215:208]
JB.G26SRL[z] = 1 and JB.G26SRIE[z] = 1, forces G.GSR6[26] = 1.
G27SRIE. A:02ECh
Group 27 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[223:216]
JB.G27SRL[z] = 1 and JB.G27SRIE[z] = 1, forces G.GSR6[27] = 1.
G28SRIE. A:02F0h
Group 28 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[231:224]
JB.G28SRL[z] = 1 and JB.G28SRIE[z] = 1, forces G.GSR6[28] = 1.
G29SRIE. A:02F4h
Group 29 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[239:232]
JB.G29SRL[z] = 1 and JB.G29SRIE[z] = 1, forces G.GSR6[29] = 1.
G30SRIE. A:02F8h
Group 30 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[247:240]
JB.G30SRL[z] = 1 and JB.G30SRIE[z] = 1, forces G.GSR6[30] = 1.
G31SRIE. A:02FCh
Group 31 Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:8]
Jitter Buffer Underrun Interrupt Enable. For z = 0 to 7, the combination of
JBUIE
[7:0] rwc-_-i3
[255:248]
JB.G31SRL[z] = 1 and JB.G31SRIE[z] = 1, forces G.GSR6[31] = 1.
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DS34S132 DATA SHEET
10.3.4 Packet Classifier Registers (PC.)
10.3.4.1 Packet Classifier Configuration Registers (PC.)
Table 10-13. Packet Classifier Configuration Registers (PC.)
PC. Field Addr (A:)
Name
Bit [x:y] Type
Description
CR1.
A:0300h
Configuration Register 1. Default: 0x00.00.00.00
Duplicate Packet Detect Enable.
DPDE
[31:30] rwc-_-_
0 = Duplicate Packet Detect function is disabled
1 = Discard duplicate packet for Bundle used for clock recovery (BCDR4.PCRE)
2 = reserved
3 = Discard duplicate packets for all SAT/CES/HDLC Bundle types
Reserved.
RSVD
[29:26]
Discard Packet Switch 10. Discard packets with too many MPLS Labels.
0 = Forward MPLS packets with > 3 MPLS labels to CPU (> 2 outer labels)
1 = Discard those packets.
DPS10
[25] rwc-_-_
Discard Packet Switch 9. Discard packets with unknown Ethernet DA.
0 = Forward packets with unknown Ethernet DA to CPU (PC.CR17 – PC.CR19)
1 = Discard those packets.
DPS9
DPS8
DPS7
DPS6
[24] rwc-_-_
[23] rwc-_-_
[22] rwc-_-_
[21] rwc-_-_
Discard Packet Switch 8. Discard packets with Ethernet type = CPU Destination.
0 = Forward packets with Ethernet type = PC.CR20.CDET to CPU (CPU Dest.)
1 = Discard those packets.
Discard Packet Switch 7. Discard OAM packets.
0 = Forward MEF OAM, OAM BID and enabled In-band VCCV packets to CPU.
1= Discard those packets.
Discard Packet Switch 6. Discard PW packets with Unknown PWID.
0 = Forward packets to CPU that have any PW header and includes a PWID
that does not match any of the programmed BIDs or OAM BIDs
1 = Discard those packets.
Discard Packet Switch 5. Discard UDP PW packets with wrong UDP Protocol.
0 = Forward UDP packets to CPU that have a recognized BID or OAM BID but
have an unexpected UDP Protocol Type (Protocol ≠ PC.CR2.UPVC1 or
PC.CR2.UPVC2, and PC.CR1.UPVCE = 1). The UDP Protocol Type may
be in the UDP Destination or Source Port position (set using
B.BCDR4.RXUBIDLS, PC.CR1.UBIDLS and PC.CR1.UBIDLCE).
1 = Discard those packets.
DPS5
[20] rwc-_-_
Discard Packet Switch 4. Discard IP packets that do not have PW headers.
0 = Forward IP packets with unknown IP Protocol to CPU (not UDP or L2TPv3)
1 = Discard those packets.
DPS4
DPS3
DPS2
[19] rwc-_-_
[18] rwc-_-_
[17] rwc-_-_
Discard Packet Switch 3. Discard ARP packets with a recognized IPv4 DA.
0 = Forward ARP packets with a recognized IPv4 DA to CPU (PC.CR6-PC.CR8)
1 = Discard those packets.
Discard Packet Switch 2. Discard packets with unknown Ethernet Type.
0 = Forward packets to CPU that have an unknown Ethernet Type (not IPv4,
IPv6, MPLS Unicast, MPLS Multi-cast, ARP, MEF = G.CR4.MOET, MEF
OAM G.CR4.MET or CPU Destination Ethernet Type = G.CR20.CDET).
1 = Discard those packets.
Discard Packet Switch 1. Discard IP packets with unknown IP DA.
0 = Forward IP packets with unknown IP DA to CPU (not PC.CR6 - PC.CR16)
1 = Discard those packets.
DPS1
DPS0
[16] rwc-_-_
[15] rwc-_-_
Discard Packet Switch 0. Discard ARP packets with an unknown IPv4 DA.
0 = Forward ARP packets with unknown IP DA to CPU (not PC.CR6 – PC.CR8)
1 = Discard those packets
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DS34S132 DATA SHEET
PC. Field Addr (A:)
Name
Bit [x:y] Type
Description
Discard IP Checksum Packet Error.
DICPE
[14] rwc-_-_
0 = Do not discard packets due to IPv4 checksum errors.
1 = Discard those packets
Discard UDP Checksum Packet Error.
0 = Do not discard packets due to UDP checksum errors.
1 = Discard those packets
DUCPE
[13] rwc-_-_
For IPv4, a received zero UDP checksum (= checksum not calculated) is
considered valid. For IPv6, a received zero UDP checksum is considered invalid
and is discarded regardless of the DUCPE setting (see RFC1883). If the
calculated UDP checksum = 0x0000 then the checksum is replaced with 0xFFFF.
Discard Packet Length Mismatch Error.
DPLME
[12] rwc-_-_
0 = Do not discard packets due to a Control Word or IP Length field error.
1 = Discard packets with a received Control Word or IP Length field value that is
greater than the number of bytes that are received (allows for Ethernet padding).
This function does not test for an 802.3 or UDP Length field error.
Discard Broadcast TDM Packet.
DBTP
[11] rwc-_-_
[10] rwc-_-_
[9] rwc-_-_
[8] rwc-_-_
[7] rwc-_-_
0 = Enable/accept the Broadcast DA as a valid Ethernet DA for PW packets.
1 = Discard PW packets that use the Broadcast Ethernet DA.
Discard Broadcast CPU Packet.
DBCP
0 = Enable Broadcast DA as a valid Ethernet DA for CPU (non-PW) packets.
1 = Discard CPU (non-PW) packets that use the Broadcast Ethernet DA.
RXP Packet IP Version Select. (only valid when PC.CR1.RXPDSD = 1).
0 = Enable/accept the IPv4 protocol, discard all IPv6 packets.
1 = Enable/accept the IPv6 protocol, discard all IPv4 packets.
RXPIVS
RXPDSD
UPVCE
RXP Packet Dual Stack Disable.
0 = Enable/accept both the IPv4 and IPv6 protocols.
1 = Enable/accept one IP version as selected by PC.CR1.RXPIVS.
UDP Protocol Value Check Enable. (only valid if PC.CR1.UBIDLS ≠ 3)
0 = Disable UDP Protocol Type test (accept any value)
1 = Discard packets with UDP Protocol Type ≠ PC.CR2.UPVC1 or UPVC2. The
received UDP Protocol Type is tested in the UDP Port location (Source or
Destination Port) not specified as the BID/PWID location (selected using
PC.CR1.UBIDLS, PC.CR1.UBIDLCE, B.BCDR4.RXUBIDLS).
UBIDLCE
UBIDLS
[6] rwc-_-_
UDP Bundle ID Location Check Enable. (only valid if PC.CR1.UBIDLS ≠ 0)
0 = Auto-detect = Test for a BID/OAM BID match in both the UDP Source and
Destination Port (a match in either port is accepted)
1 = Test for a BID/OAM BID match in only one UDP Port location as specified
by B.BCDR4.RXUBIDLS
UDP Bundle ID Location Status Select.
[5:4] rwc-_-_
0 = Test for a 16-bit BID/OAM BID match in the UDP Source or Destination Port
location specified by PC.CR1.UBIDLCE.
1 = Test for a 16-bit BID/OAM BID match in the UDP Destination Port location.
2 = Test for a 16-bit BID/OAM BID match in the UDP Source Port location.
3 = Test for a 32-bit BID/OAM BID match against the value of the combined
Source and Destination Ports.
UDP IP Checksum Error Count Select.
UICECS
RSVD
[3:2] rwc-_-_
0 = PC.PCECR.UICPEC only counts IPv4 header checksum errors.
1 = PC.PCECR.UICPEC only counts UDP header checksum errors.
2 = PC.PCECR.UICPEC counts both IPv4 and UDP header checksum errors.
3 = Reserved.
Reserved.
[1:0]
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DS34S132 DATA SHEET
PC. Field Addr (A:)
Name
Bit [x:y] Type
A:0304h
[31:16] rwc-_-_
Description
CR2.
Configuration Register 2. Default: 0x00.00.00.00
UDP Protocol Value Constant 1 is used to compare against each received UDP
UPVC1
Protocol Type field when UPVCE = 1 (1 of 2 recognized UDP Protocol Types).
UDP Protocol Value Constant 2 is used to compare against each received UDP
UPVC2
[15:0] rwc-_-_
Protocol Type field when UPVCE = 1 (1 of 2 recognized UDP Protocol Types).
CR3.
A:0308h
Configuration Register 3. Default: 81.00.81.00h
VLAN Outer Tag Protocol ID specifies the Outer VLAN TPID value that is
accepted when a packet header also includes an Inner VLAN Tag with TPID =
PC.CR3.VITPID.
VOTPID
[31:16] rwc-_-_
[15:0] rwc-_-_
VLAN Inner Tag Protocol ID specifies the Inner VLAN TPID value that is
accepted when a packet includes 1 or 2 VLAN Tags. The common VITPID value
that is used is 0x8100.
VITPID
CR4.
A:030Ch
Configuration Register 4. Default: 0x00.00.00.00
MEF Ether Type programs the Ethernet Type field value for the MEF-8 protocol.
The IANA assigned Ethernet Type value for MEF is 0x88D8. Some systems may
otherwise use Ethernet Type = 0x8847.
MET
[31:16] rwc-_-_
MEF OAM Ether Type programs the Ethernet Type field value for the MEF OAM
MOET
[15:0] rwc-_-_
protocol.
CR5.
A:0310h
Configuration Register 5. Default: 0x00.00.00.00
VCCV OAM Mask programs the mask of the 16 most significant bits of the
Control Word that is used to identify In-band VCCV OAM packets (“1” = VOV bit is
tested/enabled, one bit mask for each of the 16 VOV bits).
VOM
[31:16] rwc-_-_
VCCV OAM Value programs the value of the 16 most significant bits of the
Control Word that are used to identify an In-band VCCV OAM packet. The VOM
bits can be used to ignore any of these 16 bits. To use the most common In-band
VCCV identifier, program VOV = 0x1000 and VOM = 0xF000.
VOV
[15:0] rwc-_-_
CR6.
A:0314h
[31:0] rwc-_-_
A:0318h
[31:0] rwc-_-_
A:031Ch
[31:0] rwc-_-_
A:0320h
[31:0] rwc-_-_
Configuration Register 6. Default: 0x00.00.00.00
IPv4 Address 1 programs the 32-bit value for the first IPv4 Destination Address.
IV4A1
CR7.
Configuration Register 7. Default: 0x00.00.00.00
IPv4 Address 2 programs the 32-bit value for the 2nd IPv4 Destination Address.
Configuration Register 8. Default: 0x00.00.00.00
IV4A2
CR8.
IPv4 Address 3 programs the 32-bit value for the 3rd IPv4 Destination Address.
IV4A3
CR9.
Configuration Register 9. Default: 0x00.00.00.00
IPv6 Address 1 A-bits programs bits 0 to 31 of the 1st 128-bit IPv6 Destination
IV6A1A
Address.
CR10.
A:0324h
[31:0] rwc-_-_
Configuration Register 10. Default: 0x00.00.00.00
IPv6 Address 1 B-bits programs bits 32 to 63 of the 1st 128-bit IPv6 Destination
IV6A1B
Address.
CR11.
A:0328h
[31:0] rwc-_-_
Configuration Register 11. Default: 0x00.00.00.00
IPv6 Address 1 C-bits programs bits 64 to 95 of the 1st 128-bit IPv6 Destination
IV6A1C
Address.
CR12.
A:032Ch
[31:0] rwc-_-_
Configuration Register 12. Default: 0x00.00.00.00
IPv6 Address 1 D-bits programs bits 96 to 127 of the 1st 128-bit IPv6 Destination
IV6A1D
Address.
CR13.
A:0330h
[31:0] rwc-_-_
Configuration Register 13. Default: 0x00.00.00.00
IPv6 Address 2 A-bits programs bits 0 to 31 of the 2nd 128-bit IPv6 Destination
IV6A2A
Address.
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DS34S132 DATA SHEET
PC. Field Addr (A:)
Name
CR14.
IV6A2B
Bit [x:y] Type
A:0334h
[31:0] rwc-_-_
Description
Configuration Register 14. Default: 0x00.00.00.00
IPv6 Address 2 B-bits programs bits 32 to 63 of the 2nd 128-bit IPv6 Destination
Address.
CR15.
A:0338h
[31:0] rwc-_-_
Configuration Register 15. Default: 0x00.00.00.00
IPv6 Address 2 C-bits programs bits 64 to 95 of the 2nd 128-bit IPv6 Destination
IV6A2C
Address.
CR16.
A:033Ch
[31:0] rwc-_-_
Configuration Register 16. Default: 0x00.00.00.00
IPv6 Address 2 D-bits programs bits 96 to 127 of the 2nd 128-bit IPv6 Destination
IV6A2D
Address.
CR17.
A:0340h
[31:0] rwc-_-_
Configuration Register 17. Default: 0x00.00.00.00
MAC Address 1 B-bits programs bits 16 to 47 of the 1st 48-bit Ethernet
MA1B
Destination Address.
CR18.
A:0344h
[31:16] rwc-_-_
Configuration Register 18. Default: 0x00.00.00.00
MAC Address 1 A-bits programs bits 0 to 15 of the 1st 48-bit Ethernet
MA1A
Destination Address.
MAC Address 2 A-bits programs bits 0 to 15 of the 2nd 48-bit Ethernet
MA2A
[15:0] rwc-_-_
Destination Address.
CR19.
A:0348h
[31:0] rwc-_-_
Configuration Register 19. Default: 0x00.00.00.00
MAC Address 2 B-bits programs bits 16 to 47 of the 2nd 48-bit Ethernet
MA2B
Destination Address.
CR20.
A:034Ch
Configuration Register 20. Default: 0x00.00.00.00
CPU Destination Ether Type programs the Ethernet Type field value that is used
CDET
[31:16] rwc-_-_
to identify “CPU Destination Ethernet Type” packets.
UDP Bundle ID Mask selects which of the 16 LSB of a received UDP BID or
OAM BID are tested for a match (“1” = test for match; “0” = ignore bit). For 32-bit
UDP BIDs and 0AM BIDs the 16 MSB are always tested.
UBIDM
[15:0] rwc-_-_
CR21.
RSVD
PDCC
A:0350h
Configuration Register 21. Default: 0x00.00.00.03
Reserved.
[31:8]
Packet stream Defect Count Control selects which Jitter Buffer fill defect
conditions are counted by G.BDSR1.PDC (one bit per defect function; 1 = enable;
any combination can be enabled): Too Early (bit 7), Too Late (bit 6), Overrun (bit
5), Underrun (bit 4). The Overrun level is programmed using B.BCDR5.MJBS.
[7:4] rwc-_-_
Jitter Buffer Event Count Control selects which Jitter Buffer fill defect conditions
are counted by G.BDSR2.JBEC (one bit per defect function; 1 = enable; any
combination can be enabled): Too Early (bit 7), Too Late (bit 6), Overrun (bit 5),
Underrun (bit 4). The Overrun level is programmed using B.BCDR5.MJBS.
JBECC
[3:0] rwc-_-_
10.3.4.2 Packet Classifier Status Register Latches (PC.)
Table 10-14. Packet Classifier Register Latches (PC.)
PC. Field Addr (A:)
Name
Bit [x:y] Type
Description
SRL.
A:0360h
Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
VMDSL
[31:8]
VLAN Mismatch Discard Status Latch = “1” indicates 1 or more RXP packets
have been received with an Outer VLAN TPID that matched PC.CR3.VOTPID, but
the Inner VLAN TPID did not match PC.CR3.VITPID.
[7] rls-crw-i3
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DS34S132 DATA SHEET
PC. Field Addr (A:)
Name
Bit [x:y] Type
Description
UDP Port Value Check Status Latch = “1” indicates 1 or more RXP UDP
packets have been received with a BID or OAM BID match, but with a UDP
Protocol Type mismatch (2 UDP Protocol values can be recognized:
PC.CR2.UPVC1 and PC.CR2.UPVC2).
UPVCSL
[6] rls-crw-i3
UDP Bundle ID Location Check Status Latch = “1” indicates 1 or more RXP
UDP packets have been received with a BID match found, but not in the location
specified by Bundle parameter B.BCDR4.RXUBIDLS .
UBIDLCS
L
[5] rls-crw-i3
[4] rls-crw-i3
Bundle ID Mismatch Status Latch = “1” indicates 1 or more RXP packets with
any of the PW headers has been received with a PW-ID that did not match any of
the active BIDs or OAM BIDs (indicates when an unknown PW-ID is received).
BIDMSL
RXPFOSL
Reserved.
[3] rls-crw-i3
[2] rls-crw-i3
RXP Packet MPLS Error Status Latch = “1” indicates 1 or more RXP MPLS
packets have been received with a header that included more than 3 Labels.
RXPMES
L
IP Checksum Packet Error Status Latch = “1” indicates 1 or more RXP IPv4
packets have been received with an IPv4 checksum error.
ICPESL
[1] rls-crw-i3
[0] rls-crw-i3
UDP Checksum Packet Error Status Latch = “1” indicates 1 or more RXP UDP
UCPESL
packets have been received with a UDP checksum error (IPv4 or IPv6).
10.3.4.3 Packet Classifier Status Register Interrupt Enables (PC.)
Table 10-15. Packet Classifier Status Register Interrupt Enables (PC.)
PC. Field Addr (A:)
Name
Bit [x:y] Type
Description
SRIE.
RSVD
VMDIE
A:0368h
[31:8]
Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
VLAN Mismatch Discard Interrupt Enable = “1” enables an interrupt (INT_N)
[7] rwc-_-i3
and forces G.GSR1.PCS = 1 when PC.SRL.VMDSL = “1”.
UDP Port Value Check Interrupt Enable = “1” enables an interrupt (INT_N) and
forces G.GSR1.PCS = 1 when PC.SRL.UPVCSL = “1”.
UPVCIE
[6] rwc-_-i3
[5] rwc-_-i3
[4] rwc-_-i3
UDP Bundle ID Location Check Interrupt Enable = “1” enables an interrupt
(INT_N) and forces G.GSR1.PCS = 1 when PC.SRL.UBIDLCSL = “1”.
UBIDLCI
E
RXP Packet Mismatch Interrupt Enable = “1” enables an interrupt (INT_N) and
RXPMIE
forces G.GSR1.PCS = 1 when PC.SRL.BIDMSL = “1”.
RXPFOSIE
Reserved.
[3] rwc-_-i3
[2] rwc-_-i3
RXP Packet MPLS Error Interrupt Enable = “1” enables an interrupt (INT_N)
RXPMEIE
and forces G.GSR1.PCS = 1 when PC.SRL.RXPMESL = “1”.
IP Checksum Packet Error Interrupt Enable = “1” enables an interrupt (INT_N)
and forces G.GSR1.PCS = 1 when PC.SRL.ICPESL = “1”.
ICPEIE
[1] rwc-_-i3
[0] rwc-_-i3
UDP Checksum Packet Error Interrupt Enable = “1” enables an interrupt
UCPEIE
(INT_N) and forces G.GSR1.PCS = 1 when PC.SRL.IUCPESL = “1”.
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DS34S132 DATA SHEET
10.3.4.4 Packet Classifier Counter Registers (PC.)
Table 10-16. Packet Classifier Counter Registers (PC.)
PC. Field Addr (A:)
Name
CPCR.
CPC
Bit [x:y] Type
Description
A:0370h
Classified Packet Counter Register. Default: 0x00.00.00.00
Classified Packet Count indicates # of “good” RXP packets that have been
[31:0] rcs-cor-nc
forwarded to a CES/SAT Engine, Clock Recovery Engine or the CPU Queue.
PCECR. A:0374h
IP/UDP Packet Checksum Error Counter Register. Default: 0x00.00.00.00
Reserved.
RSVD
[31:16]
UDP IP Checksum Packet Error Count indicates the # of received IPv4 or UDP
UICPEC
[15:0] rcs-cor-nc
checksum errors (error type selected using PC.PCECR.UICPEC).
SPCR.
A:0378h
Stray Packet Count Register. Default: 0x00.00.00.00
Stray Packet Count indicates the # of received packets that include a PW
SPC
[31:0]
Header but do not match any of the configured Bundle IDs or OAM Bundle IDs.
FOCR.
RSVD
FOC
A:037Ch
[31:16]
[15:0]
FIFO Overflow Counter Register. Default: 0x00.00.00.00
Reserved.
Reserved.
10.3.5 External Memory Interface Registers (EMI.)
10.3.5.1 External Memory Interface Configuration Registers (EMI.)
Table 10-17. External Memory Interface Configuration Registers (EMI.)
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
BMCR1.
TXPSO
A:0380h
Buffer Manager Configuration Register 1. Default: 0x00.00.00.00
TXP Packet Space Offset specifies the starting address in the external SDRAM
for storing TXP TDM payload (the location where Bundle 0 payload is stored).
TXP TDM payload starting address = 2048 bytes * TXPSO
[31:16] rwc-_-_
TXP Header Space Offset specifies the starting address in the external SDRAM
for storing TXP TDM Headers (the location where the Bundle 0 Header is stored).
TXP TDM Header starting address = 2048 bytes * TXHSO
TXHSO
[15:0] rwc-_-_
BMCR2.
RSVD
A:0384h
Buffer Manager Configuration Register 2. Default: 0x00.00.00.00
Reserved.
[31:16]
Jitter Buffer Space Offset specifies the starting address in the external SDRAM
for storing RXP TDM packets (the location where Bundle 0 packets are stored).
RXP TDM packet starting address = 2048 bytes * JBSO
JBSO
[15:0] rwc-_-_
BMCR3.
A:0388h
Buffer Manager Configuration Register 3. Default: 0x00.00.00.00
Packet Transmit Space Offset specifies the starting address in the external
SDRAM for storing TXP CPU packets.
PTSO
[31:16] rwc-_-_
TXP CPU packet starting address = 2048 bytes * PTSO
Packet Receive Space Offset specifies the starting address in the external
SDRAM for storing RXP CPU packets.
PRSO
[15:0] rwc-_-_
RXP CPU packet starting address = 2048 bytes * PRSO
DCR1.
RSVD
DIR
A:0390h
[31:1]
DDR SDRAM Configuration Register 1. Default: 0x00.00.00.00
Reserved.
DDR SDRAM Initialization Reset re-initializes the EMI.DCR3.DBMR and
[0] rwc-_-_
EMI.DCR3.DEMR register bits when DIR transitions from zero to one.
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DS34S132 DATA SHEET
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
DCR2.
RSVD
TRFC
A:0394h
DDR SDRAM Configuration Register 2. Default: 00.02.90.10h
Reserved.
[31:19]
Time Refresh From Clock selects the time the S132 allows for each SDRAM
refresh cycle to complete. This can be set to any value between the minimum tRFC
allowed by the SDRAM and the max value (0x1F = 248 ns; 0 and 1 are invalid).
Refresh Time = TRFC * 1/freqDDRCLK = TRFC * 8 ns
[18:14] rwc-_-_
DDR SDRAM CAS Latency specifies the SDRAM CAS Latency.
2 = CAS Latency 2 (all other values are reserved).
DCL
[13:11] rwc-_-_
[10:9] rwc-_-_
DDR SDRAM Column Width specifies the external SDRAM Column Width.
DCW
0 = 2048 columns per row
1 = 1024 columns per row
2 = 512 columns per row
3 = reserved
DDR SDRAM Memory Size specifies the total external SDRAM memory size.
0 = 1 Gbit (two 32 Meg x 16-bit SDRAM devices)
DMS
[8:7] rwc-_-_
1 = 512 Mbit (one 32 Meg x 16-bit SDRAM device)
2 = 256 Mbit (one 16 Meg x 16-bit SDRAM device)
3 = 128 Mbit (one 8 Meg x 16-bit SDRAM device)
Reserved.
DDW
[6:5] rwc-_-_
[4:0] rwc-_-_
DDR SDRAM Refresh Rate Select = time period between each SDRAM Refresh
DRRS
(SDRAM tREFI parameter) = DRRS * 512ns
DCR3.
DBMR
DEMR
A:0398h
DDR SDRAM Configuration Register 3. Default: 00.22.40.00h
Reserved.
Reserved.
[31:16] rwc-_-_
[15:0] rwc-_-_
10.3.5.2 External Memory Interface Status Registers (EMI.)
Table 10-18. External Memory Interface Status Registers (EMI.)
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
BMSRL.
RSVD
A:03A0h
Buffer Manager Status Register Latch. Default: 0x00.00.00.00
Reserved.
[31:9]
CPU to Ethernet Read Check Status Latch = “1” indicates one or more SDRAM
Read operations were invalid due to EMI.BMCR3.PTSO. The TXP CPU Queue
overlaps with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of CERCSL = 1 and CERCIE = 1 forces G.GSR1.EMIS = 1.
CERCSL
[8] rls-crw-i3
CPU to Ethernet Write Check Status Latch = “1” indicates one or more SDRAM
Write operations were invalid due to EMI.BMCR3.PTSO. The TXP CPU Queue
overlaps with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of CEWCSL = 1 and CEWCIE = 1 forces G.GSR1.EMIS = 1.
CEWCSL
ECRCSL
ECWCSL
[7] rls-crw-i3
[6] rls-crw-i3
[5] rls-crw-i3
Ethernet to CPU Read Check Status Latch = “1” indicates one or more SDRAM
Read operations were invalid due to EMI.BMCR3.PRSO. The RXP CPU Queue
overlaps with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ECRCSL = 1 and ECRCIE = 1 forces G.GSR1.EMIS = 1.
Ethernet to CPU Write Check Status Latch = “1” indicates one or more SDRAM
Write operations were invalid due to EMI.BMCR3.PRSO. The RXP CPU Queue
overlaps with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ECWCSL = 1 and ECWCIE = 1 forces G.GSR1.EMIS = 1.
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DS34S132 DATA SHEET
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
Ethernet to TDM Read Check Status Latch = “1” indicates one or more SDRAM
Read operations were invalid due to EMI.BMCR2.JBSO. The Jitter Buffer Queues
overlap with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ETRCSL = 1 and ETRCIE = 1 forces G.GSR1.EMIS = 1.
ETRCSL
[4] rls-crw-i3
[3] rls-crw-i3
[2] rls-crw-i3
[1] rls-crw-i3
[0] rls-crw-i3
Ethernet to TDM Write Check Status Latch = “1” indicates 1 or more SDRAM
Write operations were invalid due to EMI.BMCR2.JBSO. The Jitter Buffer Queues
overlap with another SDRAM queue due to an invalid EMI Start Address setting.
The combination of ETWCSL = 1 and ETWCIE = 1 forces G.GSR1.EMIS = 1.
ETWCSL
TXP Packet Space Read Check Status Latch = “1” indicates 1 or more SDRAM
Read operations were invalid due to EMI.BMCR1.TXPSO. The TXP TDM Packet
Queues overlap with another queue due to an invalid EMI Start Address. The
combination of TXPSRCSL = 1 and TXPSRCIE = 1 forces G.GSR1.EMIS = 1.
TXPSRCS
L
TXP Packet Space Write Check Status Latch = “1” indicates 1 or more SDRAM
Write operations were invalid due to EMI.BMCR1.TXPSO. The TXP TDM Packet
Queues overlap with another queue due to an invalid EMI Start Address. The
combination of TXPSWCSL = 1 and TXPSWCIE = 1 forces G.GSR1.EMIS = 1.
TXPSWC
SL
TXP Header Space Read Check Status Latch = “1” indicates 1 or more SDRAM
Read operations were invalid due to EMI.BMCR1.TXHSO. The TXP TDM Header
space overlaps with another queue due to an invalid EMI Start Address. The
combination of TXHSRCSL = 1 and TXHSRCIE = 1 forces G.GSR1.EMIS = 1.
TXHSRCS
L
10.3.5.3 External Memory Interface Status Register Interrupt Enables (EMI.)
Table 10-19. External Memory Interface Status Register Interrupt Enables (EMI.)
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
BMSRIE. A:03B0h
Buffer Manager Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
[31:9]
[8] rwc-_-i3
CPU to Ethernet Read Check Interrupt Enable. (see EMI.BMSRL.CERCSL)
CPU to Ethernet Write Check Interrupt Enable. (see EMI.BMSRL.CEWCSL)
Ethernet to CPU Read Check Interrupt Enable. (see EMI.BMSRL.ECRCSL)
Ethernet to CPU Write Check Interrupt Enable. (see EMI.BMSRL.ECWCSL)
Ethernet to TDM Read Check Interrupt Enable. (see EMI.BMSRL.ETRCSL)
Ethernet to TDM Write Check Interrupt Enable. (see EMI.BMSRL.ETWCSL)
TXP Packet Space Read Check Interrupt Enable. (see EMI.BMSRL.TXPSRSL)
CERCIE
CEWCIE
ECRCIE
ECWCIE
ETRCIE
ETWCIE
[7] rwc-_-i3
[6] rwc-_-i3
[5] rwc-_-i3
[4] rwc-_-i3
[3] rwc-_-i3
[2] rwc-_-i3
TXPSRCI
E
TXP Packet Space Write Check Interrupt Enable. (see
EMI.BMSRL.TXPSWCSL)
TXPSWCI
E
[1] rwc-_-i3
[0] rwc-_-i3
TXP Header Space Read Check Interrupt Enable. (see
EMI.BMSRL.TXHSRCSL)
TXHSRCI
E
TSRL
A:03B4h
[31:11]
[10] rls-crw-_
Test Status Register Latched
Reserved.
RSVD
Reserved.
EMARER
RSL
Reserved.
Reserved.
EMAWER
RSL
[9] rls-crw-_
[8] rls-crw-_
RPIRERR
SL
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DS34S132 DATA SHEET
EMI. Field Addr (A:)
Name
Bit [x:y] Type
Description
Reserved.
RPI1WER
RSL
[7] rls-crw-_
[6] rls-crw-_
[5] rls-crw-_
[4] rls-crw-_
[3] rls-crw-_
[2] rls-crw-_
[1] rls-crw-_
[0] rls-crw-_
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
RPI2WER
RSL
TDI1ERR
SL
TDI2ERR
SL
TEI1ERR
SL
TEI2ERR
SL
TPI1ERR
SL
TPI2ERR
SL
10.3.5.4 External Memory DLL/PLL Test Registers (EMI.)
Table 10-20. External Memory DLL/PLL Test Registers (EMI.)
EMI. Field Addr (A:)
Name
TCR1.
PTR
Bit [x:y] Type
Description
A:03B8h
Test Configuration Register 1. Default: 0x00.00.00.00
Reserved.
Reserved.
[31:16] rwc-_-_
[15:0] rwc-_-_
A:03BCh
DTR
TCR2.
Test Configuration Register 2. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
RSVD
PPCR
DPCR
[31:9]
[8:7] rwc-_-_
[6:0] rwc-_-_
10.3.6 External Memory Access Registers (EMA.)
10.3.6.1 Write Registers (EMA.)
Table 10-21. Write Registers (EMA.)
EMA. Field Addr (A:)
Name
Bit [x:y]
A:03C0h
[31:17]
Type
Description
WCR.
RSVD
TLBE
Write Control Register. Default: 0x00.00.00.00
Reserved.
Transfer Last Byte Enable is used to indicate to the S132 which bytes are valid
in the last double-word stored in the TXP CPU FIFO (each bit enables 1 of 4
bytes). This function is used when TPCWC = 6 and a complete TXP CPU packet
has already been stored at EMA.WDR.EMWD. TLBE = 0x1 = “1 byte in the least
significant byte position”. TLBE = 0xF = “4 bytes”.
[16:13] rwc-_-_
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DS34S132 DATA SHEET
EMA. Field Addr (A:)
Name
Bit [x:y]
Type
Description
TXP Packet and Configuration Write Control is used to control the transfer of
packets from the internal TXP CPU FIFO to the TXP CPU SDRAM Queue.
0 = idle - no operations
TPCWC
[12:10] rwc-_-_
2 = Flush/reset TXP CPU Queue (external SDRAM queue)
3 = Flush/reset TXP CPU FIFO (internal S132 FIFO Buffer)
6 = Transfer packet from TXP CPU FIFO to SDRAM TXP CPU Queue
all other values are reserved
Transfer Length is used to indicate how many double words are included in the
packet that is to be transferred from the TXP CPU FIFO to the TXP CPU Queue.
This function is used when TPCWC = 6 and a complete TXP CPU packet has
already been stored at EMA.WDR.EMWD. The maximum TL value is 512. TL = 0
means “no data”. To transfer a single byte, TL = 1, and TLBE = 0x1.
TL
[9:0] rwc-_-_
WAR.
RSVD
WDR.
EMWD
A:03C4h
[31:0]
A:03C8h
[31:0] woc-_-_
WAR. Default: 0x00.00.00.00
Reserved.
Write Data Register. Default: 0x00.00.00.00
External Memory Write Data. Data written to EMWD is stored in the internal
TXP CPU FIFO in preparation for transfer to the SDRAM TXP CPU Queue. Each
EMWD write, auto increments the FIFO address (to be ready for the next write).
WSR1.
RSVD
A:03CCh
[31:17]
[16] ros-_-i3
Write Status Register 1. Default: 0x00.00.00.00
Reserved.
Write Queue Not Full Status = “1” indicates the TXP CPU Queue is not full. Up
WQNFS
to 512 packets can be stored in the SDRAM TXP CPU Queue (see WSR2.WQL)
Reserved.
RSVD
WFES
[15:7]
[6] ros-_-i3
Write FIFO Empty Status = “1” = TXP CPU FIFO is empty, new data can be
stored. The last packet was transferred or flushed, there is no data in the FIFO.
Reserved.
RSVD
[5:0]
A:03D0h
WSR2.
RSVD
Write Status Register 2. Default: 0x00.00.00.00
Reserved.
[31]
Write Queue Level = # packets currently stored in SDRAM TXP CPU Queue.
WQL
[30:21] ros-_-_
[20:0]
Reserved.
RSVD
WSRL1.
RSVD
A:03D4h
[31:19]
[18] rls-crw-i3
Write Status Register Latch 1. Default: 0x00.00.00.00
Reserved.
Write Preempted by New Request Status Latch = “1” indicates one or more
packet transfers from the TXP CPU FIFO to the TXP CPU Queue were
preempted/corrupted by an invalid EMA.WDR.EMWD write (wait until WFES = 1
before beginning the write operation for each new packet). The combination of
WPNRSL = 1 and WPNRIE = 1 forces G.GSR1.EMAWS = 1.
WPNRSL
Reserved.
RSVD
[17]
Write Queue Not Full Status Latch is a latched “1” when EMA.WSR1.WQNFS
transitions from 0 to 1. The combination of WQNFSL = 1 and WQNFIE = 1 forces
G.GSR1.EMAWS = 1.
WQNFSL
[16] rls-crw-i3
Reserved.
RSVD
[15:8]
Write FIFO Overflow Status Latch = “1” = internal TXP CPU FIFO overflow (i.e.
more than 512 EMA.WDR.EMWD writes before an EMA.WCR.TPCWC transfer).
The combination of WFOSL = 1 and WFOIE = 1 forces G.GSR1.EMAWS = 1.
WFOSL
[7] rls-crw-i3
[6] rls-crw-i3
[5] rls-crw-i3
Write FIFO Empty Status Latch is a latched “1” when EMA.WSR1.WFES
transitions from 0 to 1. The combination of WFESL = 1 and WFEIE = 1 forces
G.GSR1.EMAWS = 1.
WFESL
Reserved.
WTOSL
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DS34S132 DATA SHEET
EMA. Field Addr (A:)
Name
Bit [x:y]
Type
Description
Reserved.
RSVD
[4:0]
WSRIE1.
RSVD
A:03D8h
Write Status Register Interrupt Enable 1. Default: 0x00.00.00.00
Reserved.
[31:19]
Write Preempt New Request Interrupt Enable (see EMA.WSRL1.WPNRSL)
WPNRIE
RSVD
[18] rwc-_-i3
[17]
Reserved.
Write Queue Not Full Interrupt Enable. (see EMA.WSRL1.WQNFSL)
WQNFIE
RSVD
[16] rwc-_-i3
Reserved.
[15:8]
Write FIFO Overflow Interrupt Enable. (see EMA.WSRL1.WFOSL)
WFOIE
WFEIE
WTOIE
RSVD
[7] rwc-_-i3
[6] rwc-_-i3
[5] rwc-_-i3
Write FIFO Empty Interrupt Enable. (see EMA.WSRL1.WFESL)
Reserved.
Reserved.
[4:0]
10.3.6.2 Read Registers (EMA.)
Table 10-22. Read Registers (EMA.)
EMA. Field Addr (A:)
Name
Bit [x:y]
Type
Description
RCR.
A:03E0h
Read Control Register. Default: 0x00.00.00.00
Reserved.
RSVD
RPCRC
[31:13]
[12:10] rwc-_-_
Receive Packet and Configuration Read Control is used to control the
transfer of packets from the RXP CPU SDRAM Queue to the internal RXP CPU
FIFO.
0 = idle - no operations
2 = Flush/reset RXP CPU Queue (external SDRAM queue)
3 = Flush/reset RXP CPU FIFO (internal S132 FIFO Buffer)
6 = Transfer packet from SDRAM RXP CPU Queue to RXP CPU FIFO
all other values are reserved
Transfer Length indicates how many double words are to be transferred from
the SDRAM RXP CPU Queue to the RXP CPU FIFO. This function is used when
RPCRC = 6. The maximum TL value is 512. TL = 1 means “1 double word of
data”. The CPU must read the first double word of each RXP CPU packet to
learn how many bytes are included in each RXP CPU packet.
TL
[9:0] rwc-_-_
RAR.
RSVD
RDR.
EMRD
A:03E4h
[31:0]
A:03E8h
[31:0] ros-_-_
Read Address Register. Default: 0x00.00.00.00
Reserved.
Read Data Register. Default: 0x00.00.00.00
External Memory Read Data. Each read from EMRD provides a double word of
RXP CPU packet data from the internal RXP CPU FIFO and auto increments the
FIFO address (to be ready for the next read). The data for each RXP CPU
packet must first be transferred from the SDRAM RXP CPU Queue (using
EMA.RCR.RPCRC) before the data is available at the RXP CPU FIFO.
RSR1.
RSVD
A:03ECh
[31:17]
[16] ros-_-i3
Read Status Register 1. Default: 0x00.00.00.00
Reserved.
Read Queue Not Empty Status = “1” indicates one or more packets are waiting
RQNES
in the SDRAM RXP CPU Queue (1 to 512 packets waiting; see RSR2.RQL).
Reserved.
RSVD
RFRS
[15:7]
[6] ros-_-i3
Read FIFO Ready Status = “1” indicates the block of data for the RXP CPU
packet (as requested by EMA.RCR.TL) has been transferred from the RXP CPU
Queue to the RXP CPU FIFO and can now be read at EMA.RDR.EMRD.
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EMA. Field Addr (A:)
Name
RSVD
RSR2.
RSVD
RQL
Bit [x:y]
[5:0]
A:03F0h
[31]
Type
Description
Reserved.
Read Status Register 2. Default: 0x00.00.00.00
Reserved.
Read Queue Level = # packets currently stored in SDRAM RXP CPU Queue.
[30:21] ros-_-_
[20:19]
Reserved.
RSVD
RQRP
Read Queue Read Pointer indicates which SDRAM RXP CPU Queue packet is
[18:10] ros-_-_
to be transferred next to the internal RXP CPU FIFO (0 to 512).
Read FIFO Level = # double words currently in the RXP CPU FIFO.
RFL
[9:0] ros-_-_
RSRL1.
RSVD
A:03F4h
[31:19]
[18] rls-crw-i3
Read Status Register Latch 1. Default: 0x00.00.00.00
Reserved.
Read Preempted by New Request Status Latch = “1” indicates one or more
data transfers from the RXP CPU Queue to the RXP CPU FIFO were
preempted/corrupted by an invalid EMA.RCR.RPCRC transfer (wait until RFRS =
1 before beginning a new RPCRC = 6 transfer operation). The combination of
RPNRSL = 1 and RPNRIE = 1 forces G.GSR1.EMARS = 1.
RPNRSL
Read Queue Overflow Status Latch = “1” = SDRAM RXP CPU Queue
overflow. One or more packets were discarded from the tail of the queue. The
combination of RQOSL = 1 and RQOIE = 1 forces G.GSR1.EMARS = 1.
RQOSL
[17] rls-crw-i3
[16] rls-crw-i3
Read Queue Not Empty Status Latch = “1” indicates one or more packets are
in the RXP CPU Queue waiting to be transferred to the RXP CPU FIFO. The
combination of RQNESL = 1 and RQNEIE = 1 forces G.GSR1.EMARS = 1.
RQNESL
Reserved.
RSVD
[15:8]
Read FIFO Underflow Status Latch = “1” indicates the RXP CPU FIFO was
read (EMRD) when no data was present in the FIFO (read when empty). The
combination of RFUSL = 1 and RFUIE = 1 forces G.GSR1.EMARS = 1.
RFUSL
[7] rls-crw-i3
Read FIFO Ready Status Latch = “1” indicates the last request to transfer data
from the SDRAM RXP CPU Queue to the RXP CPU FIFO (RPCRC = 6) is done.
The data is can be read at EMRD. The combination of RFRSL = 1 and RFRIE =
1 forces G.GSR1.EMARS = 1.
RFRSL
[6] rls-crw-i3
Reserved.
RTOSL
RSVD
[5] rls-crw-i3
Reserved.
[4:0]
A:03F8h
[31:19]
[18] rwc-_-i3
RSRIE1.
RSVD
Read Status Register Interrupt Enable 1. Default: 0x00.00.00.00
Reserved.
Read Preempt by New Request Interrupt Enable. (see EMA.RSRL1.RPNRSL)
Read Queue Overflow Interrupt Enable. (see EMA.RSRL1.RQOSL)
Read Queue Not Empty Interrupt Enable. (see EMA.RSRL1.RQNESL)
Reserved.
RPNRIE
RQOIE
RQNEIE
RSVD
[17] rwc-_-i3
[16] rwc-_-i3
[15:8]
Read FIFO Underflow Interrupt Enable. (see EMA.RSRL1.RFUSL)
Read FIFO Ready Interrupt Enable. (see EMA.RSRL1.RFRSL)
Reserved.
RFUIE
RFRIE
RTOIE
RSVD
[7] rwc-_-i3
[6] rwc-_-i3
[5] rwc-_-i3
Reserved.
[4:0]
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10.3.7 Encap BERT Registers (EB.)
Table 10-23. Encap BERT Registers (EB.)
EB. Field Addr (A:)
Name
Bit [x:y] Type
Description
BCR.
A:0400h
BERT Control Register. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
PMUM
LPMU
[31:8]
[7] rwc-_-_
[6] rwc-_-_
Local Performance Monitoring Update. A 0 to 1 transition of this bit updates the
TXP TDM BERT Performance Monitoring registers (EB.RBECR.BEC and
EB.RBECR.BC) with the latest counts and then resets the counters.
Receive New Pattern Load. A 0 to 1 transition of this bit loads the test pattern
into the receive TXP TDM BERT Monitor (QRSS, PTS, PLF[4:0], PTF[4:0], and
BSP[31:0]). This forces the TXP TDM BERT Monitor to resynchronize to the
incoming data pattern. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]
must not change until 4 SYSCLK clock cycles after RNPL transitions from 0 to 1.
RNPL
RPIC
[5] rwc-_-_
[4] rwc-_-_
Receive Pattern Inversion Control. (TXP TDM BERT Monitor)
0 = test normal (unaltered) incoming data pattern
1 = invert and then test the incoming data pattern
Manual Pattern Resynchronization. A 0 to 1 transition of this bit forces the TXP
TDM BERT Monitor to resynchronize to the incoming pattern.
MPR
[3] rwc-_-_
[2] rwc-_-_
Automatic Pattern Resynchronization Disable. For APRD = 0, the TXP TDM
BERT Monitor is forced to resynchronize to the incoming pattern when 6 received
bits, within a 64-bit window, do not match the expected pattern. For APRD = 1,
after the TXP TDM BERT Monitor finds synchronization lock, it does not attempt
to resynchronize regardless of how many bit errors are detected.
APRD
Transmit New Pattern Load. A 0 to 1 transition of this bit loads the test pattern
into the transmit TXP Packet BERT Generator (QRSS, PTS, PLF[4:0], PTF[4:0],
and BSP[31:0]). Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not
change until 4 SYSCLK clock cycles after TNPL transitions from 0 to 1.
TNPL
TPIC
[1] rwc-_-_
[0] rwc-_-_
Transmit Pattern Inversion Control. (TXP Packet BERT Generator)
0 = transmit normal (unaltered) outgoing data pattern
1 = transmit inverted outgoing data pattern
BPCR.
RSVD
PTF
A:0404h
BERT Pattern Configuration Register. Default: 0x00.00.00.00
Reserved.
[31:13]
Test Pattern “y” Coefficient is used by the TXP TDM BERT Monitor and TXP
Packet BERT Generator to specify the “y” coefficient in the PRBS pattern: xn + xy
+ 1, where y = (PTF[4:0] + 1). PTF is ignored when a QRSS or Repetitive Pattern
is enabled.
[12:8] rwc-_-_
Reserved.
RSVD
QRSS
[7]
QRSS Sequence Select is used with PTS to select the transmit TXP Packet
BERT Generator and the receive TXP TDM BERT Monitor Test Pattern:
QRSS/PTS
[6] rwc-_-_
0 / 0b = xz + xy + 1 PRBS Pattern (using PLF, PTF and BSP)
0 / 1b = Repetitive Pattern (using PLF and BSP)
1 / 0b = x20 + x17 + 1 QRSS Pattern with a forced “1” if the next 14 bits are “0”
1 / 1b = invalid setting
Pattern Type Select. Used with QRSS to select the TXP BERT Test Pattern
PTS
PLF
[5] rwc-_-_
Test Pattern “z” Coefficient or Length is used by the TXP TDM BERT Monitor
and TXP Packet BERT Generator to specify the “z” coefficient in the PRBS
pattern: xz + xy + 1, where z = (PLF[4:0] + 1); or to specify the length for a
Repetitive Pattern. PLF is ignored when the QRSS Pattern is enabled.
[4:0] rwc-_-_
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EB. Field Addr (A:)
Name
BSPR.
BSP
Bit [x:y] Type
A:0408h
[31:0] rwc-_-_
Description
BERT Seed / Pattern Register. Default: 0x00.00.00.00
BERT Seed/Pattern specifies the seed value for the transmit PRBS pattern, or
the transmit and receive Repetitive Pattern. BSP[31] is the 1st transmitted bit and
the expected 1st receive bit. BSP is ignored when the QRSS Pattern is enabled.
TEICR.
RSVD
TEIR
A:0410h
Transmit Error Insertion Control Register. Default: 0x00.00.00.00
Reserved.
[31:6]
Transmit Error Insertion Rate specifies the rate at which errors are inserted in
the TXP Packet BERT Generator output data stream (TSEI = 0). One out of every
10k bits is inverted where k = TEIR and k > 0. TEIR = 0 disables the Transmit
Error Insertion Rate function. TEIR = 1 results in every 10th bit being inverted. If
this register is written to during the middle of an error insertion process, the TEIR
insertion rate is updated after the next error is inserted.
[5:3] rwc-_-_
Bit Error Insertion Enable = “0” disables error insertion (disables TEIR & TSEI)
BEI
[2] rwc-_-_
[1] rwc-_-_
Transmit Single Error Insert A 0 to 1 transition forces a single bit error in the
TXP Packet BERT Generator output stream (TEIR = 0). If this bit transitions more
than once between error insertion opportunities, only one error will be inserted.
TSEI
Reserved.
MEIMS
BSR.
[0] rwc-_-_
A:0414h
[31:2]
[1] ros-_-i3
BERT Status Register. Default: 0x00.00.00.00
Reserved.
RSVD
BEC
Performance Monitoring Update Status = “1” indicates the TXP TDM BERT
Monitor bit error count > 0 (EB.RBECR.BEC).
Out Of Synchronization = “1” indicates the TXP TDM BERT Monitor is not
OOS
[0] ros-_-i3
synchronized to the incoming pattern.
BSRL.
RSVD
BEL
A:0418h
[31:3]
[2] rls-crw-i3
BERT Status Register Latch. Default: 0x00.00.00.00
Reserved.
Bit Error Latched = “1” when one or more bit errors are detected.
Bit Error Count Latched = “1” when EB.BSR.BEC transitions from 0 to 1.
Out Of Synchronization Latched = “1” when EB.BSR.OOS changes state.
BECL
OOSL
BSRIE.
RSVD
BEIE
[1] rls-crw- i3
[0] rls-crw- i3
A:041Ch
[31:3]
[2] rwc-_-i3
BERT Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Bit Error Interrupt Enable. The combination of BEIE = 1 and EB.BSRL.BEL = 1
forces G.GSR1.EBS = 1.
Bit Error Count Interrupt Enable. The combination of BECIE = 1 and
EB.BSRL.BECL = 1 forces G.GSR1.EBS = 1.
BECIE
OOSIE
[1] rwc-_-i3
[0] rwc-_-i3
Out Of Synchronization Interrupt Enable. The combination of OOSIE = 1 and
EB.BSRL.OOSL = 1 forces G.GSR1.EBS = 1.
RBECR. A:0420h
Receive Bit Error Count Register. Default: 0x00.00.00.00
Reserved.
RSVD
BEC
[31:24]
[23:0]
rcs-cor-sc
rcs-cor-sc
Bit Error Count = # bit errors during the previous update period (EB.BCR.LPMU)
but not including errors during an Out of Sync condition (EB.BSR.OOS = 1).
RBCR.
A:0424h
Receive Bit Count Register. Default: 0x00.00.00.00
Bit Count = # received bits during the previous update period (EB.BCR.LPMU)
BC
[31:0]
but not including errors during an Out of Sync condition (EB.BSR.OOS = 1).
TSTCR. A:0430h
RSVD [31:0]
Test Control Register. Default: 0x00.00.00.00
Reserved.
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10.3.8 Decap BERT Registers (DB.)
Table 10-24. Decap BERT Registers (DB.)
DB. Field Addr (A:)
Name
Bit [x:y] Type
Description
BCR.
A:0400h
BERT Control Register. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
PMUM
LPMU
[31:8]
[7] rwc-_-_
[6] rwc-_-_
Local Performance Monitoring Update. A 0 to 1 transition of this bit updates the
RXP Packet BERT Performance Monitoring registers (DB.RBECR.BEC and
DB.RBECR.BC) with the latest counts and then resets the counters.
Receive New Pattern Load. A 0 to 1 transition of this bit loads the test pattern
into the receive RXP Packet BERT Monitor (QRSS, PTS, PLF[4:0], PTF[4:0], and
BSP[31:0]). This forces the RXP Packet BERT Monitor to resynchronize to the
incoming data pattern. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0]
must not change until 4 SYSCLK clock cycles after RNPL transitions from 0 to 1.
RNPL
RPIC
[5] rwc-_-_
[4] rwc-_-_
Receive Pattern Inversion Control. (RXP Packet BERT Monitor)
0 = test normal (unaltered) incoming data pattern
1 = invert and then test the incoming data pattern
Manual Pattern Resynchronization. A 0 to 1 transition of this bit forces the RXP
Packet BERT Monitor to resynchronize to the incoming pattern.
MPR
[3] rwc-_-_
[2] rwc-_-_
Automatic Pattern Resynchronization Disable. For APRD = 0, the RXP Packet
BERT Monitor is forced to resynchronize to the incoming pattern when 6 received
bits, within a 64-bit window, do not match the expected pattern. For APRD = 1,
after the RXP Packet BERT Monitor finds synchronization lock, it does not attempt
to resynchronize regardless of how many bit errors are detected.
APRD
Transmit New Pattern Load. A 0 to 1 transition of this bit loads the test pattern
into the transmit RXP TDM BERT Generator (QRSS, PTS, PLF[4:0], PTF[4:0],
and BSP[31:0]). Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and BSP[31:0] must not
change until 4 SYSCLK clock cycles after TNPL transitions from 0 to 1.
TNPL
TPIC
[1] rwc-_-_
[0] rwc-_-_
Transmit Pattern Inversion Control. (RXP TDM BERT Generator)
0 = transmit normal (unaltered) outgoing data pattern
1 = transmit inverted outgoing data pattern
BPCR.
RSVD
PTF
A:0404h
BERT Pattern Configuration Register. Default: 0x00.00.00.00
Reserved.
[31:13]
Test Pattern “y” Coefficient is used by the RXP Packet BERT Monitor and RXP
TDM BERT Generator to specify the “y” coefficient in the PRBS pattern: xn + xy +
1, where y = (PTF[4:0] + 1). PTF is ignored when a QRSS or Repetitive Pattern is
enabled.
[12:8] rwc-_-_
Reserved.
RSVD
QRSS
[7]
QRSS Sequence Select is used with PTS to select the transmit RXP TDM BERT
Generator and the receive RXP Packet BERT Monitor Test Pattern:
QRSS/PTS
[6] rwc-_-_
0 / 0b = xz + xy + 1 PRBS Pattern (using PLF, PTF and BSP)
0 / 1b = Repetitive Pattern (using PLF and BSP)
1 / 0b = x20 + x17 + 1 QRSS Pattern with a forced “1” if the next 14 bits are “0”
1 / 1b = invalid setting
Pattern Type Select. Used with QRSS to select the RXP BERT Test Pattern
PTS
PLF
[5] rwc-_-_
Test Pattern “z” Coefficient or Length is used by the RXP Packet BERT
Monitor and RXP TDM BERT Generator to specify the “z” coefficient in the PRBS
pattern: xz + xy + 1, where z = (PLF[4:0] + 1); or to specify the length for a
Repetitive Pattern. PLF is ignored when the QRSS Pattern is enabled.
[4:0] rwc-_-_
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DB. Field Addr (A:)
Name
Bit [x:y] Type
Description
BSPR1. A:0408h
BERT Seed / Pattern Register. Default: 0x00.00.00.00
BERT Seed/Pattern specifies the seed value for the transmit PRBS pattern, or
the transmit and receive Repetitive Pattern. BSP[31] is the 1st transmitted bit and
the expected 1st receive bit. BSP is ignored when the QRSS Pattern is enabled.
BSP
[31:0] rwc-_-_
TEICR.
RSVD
TEIR
A:0410h
Transmit Error Insertion Control Register. Default: 0x00.00.00.00
Reserved.
[31:6]
Transmit Error Insertion Rate specifies the rate at which errors are inserted in
the RXP TDM BERT Generator output data stream (TSEI = 0). One out of every
10k bits is inverted where k = TEIR and k > 0. TEIR = 0 disables the Transmit
Error Insertion Rate function. TEIR = 1 results in every 10th bit being inverted. If
this register is written to during the middle of an error insertion process, the TEIR
insertion rate is updated after the next error is inserted.
[5:3] rwc-_-_
Bit Error Insertion Enable = “0” disables error insertion (disables TEIR & TSEI)
BEI
[2] rwc-_-_
[1] rwc-_-_
Transmit Single Error Insert A 0 to 1 transition forces a single bit error in the
RXP TDM BERT Generator output stream (TEIR = 0). If this bit transitions more
than once between error insertion opportunities, only one error will be inserted.
TSEI
Reserved.
MEIMS
BSR.
[0] rwc-_-_
A:0414h
[31:2]
[1] ros-_-i3
BERT Status Register. Default: 0x00.00.00.00
Reserved.
RSVD
BEC
Performance Monitoring Update Status = “1” indicates the RXP Packet BERT
Monitor bit error count > 0 (DB.RBECR.BEC).
Out Of Synchronization = “1” indicates the RXP Packet BERT Monitor is not
OOS
[0] ros-_-i3
synchronized to the incoming pattern.
BSRL.
RSVD
BEL
A:0418h
[31:3]
[2] rls-crw-i3
BERT Status Register Latch. Default: 0x00.00.00.00
Reserved.
Bit Error Latched = “1” when one or more bit errors are detected.
Bit Error Count Latched = “1” when DB.BSR.BEC transitions from 0 to 1.
Out Of Synchronization Latched = “1” when DB.BSR.OOS changes state.
BECL
OOSL
BSRIE.
RSVD
BEIE
[1] rls-crw-i3
[0] rls-crw-i3
A:041Ch
[31:3]
[2] rwc-_-i3
BERT Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
Bit Error Interrupt Enable. The combination of BEIE = 1 and DB.BSRL.BEL = 1
forces G.GSR1.EBS = 1.
Bit Error Count Interrupt Enable. The combination of BECIE = 1 and
DB.BSRL.BECL = 1 forces G.GSR1.EBS = 1.
BECIE
OOSIE
[1] rwc-_-i3
[0] rwc-_-i3
Out Of Synchronization Interrupt Enable. The combination of OOSIE = 1 and
DB.BSRL.OOSL = 1 forces G.GSR1.EBS = 1.
RBECR. A:0420h
Receive Bit Error Count Register. Default: 0x00.00.00.00
Reserved.
RSVD
BEC
[31:24]
[23:0]
rcs-cor-sc
rcs-cor-sc
Bit Error Count = # bit errors during the previous update period (DB.BCR.LPMU)
but not including errors during an Out of Sync condition (DB.BSR.OOS = 1).
RBCR.
A:0424h
Receive Bit Count Register. Default: 0x00.00.00.00
Bit Count = # received bits during the previous update period (DB.BCR.LPMU)
BC
[31:0]
but not including errors during an Out of Sync condition (DB.BSR.OOS = 1).
TSTCR. A:0430h
RSVD [31:0]
Test Control Register. Default: 0x00.00.00.00
Reserved.
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10.3.9 Miscellaneous Diagnostic Registers (MD.)
Table 10-25. Miscellaneous Diagnostic Registers (MD.)
MD. Field Addr (A:)
Name
DCR.
RSVD
MBE
Bit [x:y] Type
Description
A:0480h
Diagnostic Control Register. Default: 0x00.00.00.00
Reserved.
[31:1]
Memory BIST Enable enables the memory BIST test. This test runs until
[0] rwc-_-_
complete. The result is visible in the diagnostic register
EBCR.
RSVD
ETBE
A:0484h
[31:24]
Encap BERT Control Register. Default: 0x00.00.00.00
Reserved.
Encap Transmit BERT Enable enables TXP Packet BERT Generator to insert a
[24] rwc-_-_
test pattern into the packet payload section of a TXP Bundle (see ETBBS).
Encap Transmit BERT Bundle Select selects the TXP Bundle # that carries the
ETBBS
[23:16] rwc-_-_
output data stream of the TXP Packet BERT Generator (ETBE = 1).
Reserved.
RSVD
ERBE
[15:9]
Encap Receive BERT Enable enables the TXP TDM BERT Monitor to test the
[8] rwc-_-_
receive TDM Port Timeslot data for a TXP Bundle (see ERBBS).
Encap Receive BERT Bundle Select selects the TXP Bundle # that receives the
ERBBS
[7:0] rwc-_-_
TDM Port Timeslot data that is tested by the TXP TDM BERT Monitor (ERBE = 1).
DBCR.
RSVD
DTBE
A:0488h
[31:24]
Decap BERT Control Register. Default: 0x00.00.00.00
Reserved.
Decap Transmit BERT Enable enables RXP TDM BERT Generator to insert a
[24] rwc-_-_
test pattern into the transmit TDM Port Timeslot of an RXP Bundle (see DTBBS).
Decap Transmit BERT Bundle Select selects RXP Bundle # for the TDM Port
DTBBS
[23:16] rwc-_-_
Timeslots that transmit the RXP TDM BERT Generator output data (DTBE = 1).
Reserved.
RSVD
DRBE
[15:9]
Decap Receive BERT Enable enables the RXP Packet BERT Monitor to test the
[8] rwc-_-_
RXP packet payload data for an RXP Bundle (see DRBBS).
Decap Receive BERT Bundle Select selects the RXP Bundle # for the RXP
DRBBS
[7:0] rwc-_-_
packet payload data that is tested by the RXP Packet BERT Monitor (DRBE = 1).
MBSR1. A:04A0h
Memory BIST Status Register 1. Default: 0x00.00.00.00
Memory BIST Done. Memory BIST Done Status Bits (only valid if DCR.MBE = 1).
MBD
[31:0] ros-_-_
MBSR2. A:04A4h
Memory BIST Status Register 2. Default: 0x00.00.00.00
Memory BIST Done. Memory BIST Done Status Bits (only valid if DCR.MBE = 1).
Memory BIST Status Register 3. Default: 0x00.00.00.00
MBD
[31:0] ros-_-_
MBSR3. A:04A8h
Memory BIST Fail. Memory BIST Fail Status Bits. M.MBSR3.MBF[x] is only valid
MBF
[31:0] ros-_-_
when M.MBRS1.MBD[x] = 1 and M.DCR.MBE = 1 (x = 0 to 31).
MBSR4. A:04ACh
Memory BIST Status Register 4. Default: 0x00.00.00.00
Memory BIST Fail. Memory BIST Fail Status Bits. M.MBSR4.MBF[x] is only valid
MBF
[31:0] ros-_-_
when M.MBRS2.MBD[x] = 1 and M.DCR.MBE = 1 (x = 0 to 31).
MBSR5. A:04B0h
Memory BIST Status Register 5. Default: 0x00.00.00.00
ROM BIST Signature. (only valid if DCR.MBE = 1 and the BIST has completed).
RBS
[31:0] ros-_-_
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10.3.10 Test Registers (TST.)
Table 10-26. Test Registers (TST.)
TST. Field Addr (A:)
Name
Bit [x:y] Type
Description
GTR1.
RSVD
A:0600h
Global Test Control Register 1. Default: 0x00.00.00.00
Reserved.
[31:7]
Reserved.
CTCE
[6] rwc-_-_
[5] rwc-_-_
[4] rwc-_-_
[3] rwc-_-_
[2] rwc-_-_
[1] rwc-_-_
[0] rwc-_-_
A:0604h
Reserved.
CWLUPM
SOEE
Reserved.
Reserved.
COEE
Reserved.
MTPOE
MCRS
Reserved.
Reserved.
INTE
BTCR1.
RSVD
Block Test Control Register 1. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
TPIBTC
BTCR2.
RSVD
[15:0] rwc-_-_
A:0608h
Block Test Control Register 2. Default: 0x00.00.00.00
Reserved.
Reserved.
[31:16]
RPIBTC
BTCR3.
RSVD
[15:0] rwc-_-_
A:060Ch
[31:16]
Block Test Control Register 3. Default: 0x00.00.00.00
Reserved.
Reserved.
TDIBTC
BTCR4.
RSVD
[15:0] rwc-_-_
A:0610h
Block Test Control Register 4. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
TEIBTC
BTCR5.
RSVD
[15:0] rwc-_-_
A:0614h
Block Test Control Register 5. Default: 0x00.00.00.00
Reserved.
Reserved.
[31:16]
EMIBTC
BTCR6.
RSVD
[15:0] rwc-_-_
A:0618h
Block Test Control Register 6. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
SBIBTC
SBIBTC
SBIBTC
CRJBT
RSVD
[15:8] rwc-_-_
[7:4] ros-_-_
[3:0] rwc-_-_
A:061Ch
[31:16
Silicon Revision ID
Reserved.
Clock Recovery Jitter Buffer Test. Default: 0x00.00.00.00
Reserved.
Reserved.
JBBS
[15:8] rwc-_-_
[7:5]
Reserved.
RSVD
Reserved.
CRCS
[4:0] rwc-_-_
A:0624h
BTSR1.
TPIBTS
BTSR2.
RPIBTS
BTSR3.
TDIBTS
Block Test Status Register 1. Default: 0x00.00.00.00
Reserved.
[31:0]
A:0628h
Block Test Status Register 2. Default: 0x00.00.00.00
Reserved.
[31:0]
A:062Ch
[31:0]
Block Test Status Register 3. Default: 0x00.00.00.00
Reserved.
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DS34S132 DATA SHEET
TST. Field Addr (A:)
Name
Bit [x:y] Type
Description
BTSR4.
TEIBTS
BTSR5.
EMIBTS
BTSR6.
SBIBTS
CTCR1.
PD
A:0630h
[31:0]
Block Test Status Register 4. Default: 0x00.00.00.00
Reserved.
A:0634h
[31:0]
Block Test Status Register 5. Default: 0x00.00.00.00
Reserved.
A:0638h
[31:0]
Block Test Status Register 6. Default: 0x00.00.00.00
Reserved.
A:0640h
CLAD Test Control Register 1. Default: 0x00.00.00.00
Reserved.
[31:28] rwc-_-_
Reserved.
RST
[27:24] rwc-_-_
[23:22] rwc-_-_
[21:19] rwc-_-_
[18:17] rwc-_-_
[16:7]
Reserved.
TCS
Reserved.
IRA
Reserved.
VRA
Reserved.
RSVD
PMIA
Reserved.
[6:0] rwc-_-_
CTCR2.
RSVD
PPCS
A:0644h
CLAD Test Control Register 2. Default: 0x00.00.00.00
Reserved.
[31:9]
Reserved.
[8:7] rwc-_-_
[6:0] rwc-_-_
Reserved.
PPIA
CTCR3.
RSVD
PTECS
PTEIA
CTCR4.
RSVD
PTSTVA
PTSTCS
PTSTIA
EDTCR
RSVD
EDMEM
EDBDL
A:0648h
CLAD Test Control Register 3. Default: 0x00.00.00.00
Reserved.
[31:9]
Reserved.
[8:7] rwc-_-_
[6:0] rwc-_-_
Reserved.
A:064Ch
CLAD Test Control Register 4. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
[31:25]
[24:9] rwc-_-_
[8:7] rwc-_-_
[6:0] rwc-_-_
A:0660h
[31:10]
[9:8] rwc-_-_
[7:0] rwc-_-_
Encap/Decap Test Control Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
EDTSR1 A:0664h
Encap/Decap Test Status Register 1
Reserved.
RSVD
[31:1]
[0] ros-_-_
Reserved.
EDVLD
EDTSR2 A:0668h
Encap/Decap Test Status Register 2
Reserved.
EDRDT
[31:0] ros-_-_
EDTSR3 A:066Ch
Encap/Decap Test Status Register 3
Reserved.
EDRDT
[31:0] ros-_-_
EDTSR4 A:0670h
Encap/Decap Test Status Register 4
Reserved.
EDRDT
[31:0] ros-_-_
EDTSR5 A:0674h
Encap/Decap Test Status Register 5
Reserved.
EDRDT
[31:0] ros-_-_
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TST. Field Addr (A:)
Name
FID.
FRI
Bit [x:y] Type
A:06FCh
[31:0] ros-_-_
Description
Block Test Control Register 6. Default: 0x00.00.00.1A
Reserved.
10.3.11 Clock Recovery Registers (CR.)
These registers are defined by the S132 Clock Recovery firmware load (according to the firmware revision).
10.3.12 MAC Registers (M.)
Table 10-27. MAC Registers (M.)
Addr (A:)
M. Field Name
NET_CONTROL.
RSVD
Bit [x:y] Type
Description
A:0C00h
Network Control Register. Default: 0x00.00.00.00
Reserved.
[31:9]
Read Snapshot = “1” enables the Ethernet RMON statistics registers to
RD_SNAP
[14] rwc-_-_
provide latched values. When “0” they provide real-time/raw values.
Take Snapshot A 0 to 1 transition latches the current Ethernet statistics
TAKE_SNAP
[13] woc-_-_
into the statistics registers and then resets the counters (RD_SNAP = 1).
Reserved.
Reserved.
TX_0Q_PAUSE
TX_PAUSE
TX_HALT
[12] woc-_-_
[11] woc-_-_
[10] woc-_-_
Transmit Halt = “1” disables MAC transmission. If a packet is already
partially transmitted, the complete packet is transmitted before stopping.
Start Transmission = “1” starts transmission.
START_TX
[9] woc-_-_
[8]
Reserved.
RSVD
Reserved.
STATS_WR_EN
STATS_INC
STATS_CLR
MAN_PORT_EN
[7] rwc-_-_
[6] woc-_-_
[5] woc-_-_
[4] rwc-_-_
Reserved.
Statistics Clear = “1” clears the statistics registers.
Management Port Enable = “1” to enable the MDIO management port.
When “0” forces MDIO to high impedance state and MDC low.
Transmit Enable = “1” enables MAC transmission. “0” immediately stops
transmission (partially transmitted packets are aborted).
TX_EN
RX_EN
[3] rwc-_-_
[2] rwc-_-_
Receive Enable = “1” enables the MAC to receive data. When “0”, frame
reception will stop immediately (partially received packets are aborted).
Loop Back Local = “1” enables the Ethernet Loopback (TXP to RXP)
LB_LOCAL
LB
[1] rwc-_-_
[0] rwc-_-_
A:0C04h
Reserved.
NET_CONFIG.
RSVD
Network Configuration Register. Default: 00.0C.00.00h
Reserved.
Reserved.
[31:30]
BAD_PREAMB
IPG
[29] rwc-_-_
[28] rwc-_-_
IPG Stretch Enable = “1” enables the MAC to increase the Inter Packet
Gap to > 96 bit times (see M.IPG_STRETCH).
Reserved.
RSVD
[27] rwc-_-_
[26] rwc-_-_
[25] rwc-_-_
[24] rwc-_-_
[23] rwc-_-_
[22:21]
Reserved.
IGN_RX_FCS
EN_FRMS_HDUP
RX_CHK_EN
DIS_CP_PAUSE
RSVD
Reserved.
Reserved.
Reserved. This must be programmed to “1”.
Reserved.
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DS34S132 DATA SHEET
Addr (A:)
M. Field Name
Bit [x:y] Type
Description
MDC Clock Division selects the MDC frequency where MDCfreq
=
MDC_CLK_DIV
[20:18] rwc-_-_
SYSCLK ÷ MDC_CLK_DIV. To comply with IEEE 802.3, MDCfreq must
not exceed 2.5 MHz.
1 = divide by 32 (for SYSCLK ≤ 80 MHz)
2 = divide by 48 (for SYSCLK ≤ 120MHz)
4 = divide by 64 (for SYSCLK ≤ 160 MHz)
5 = divide by 96 (for SYSCLK ≤ 240 MHz)
6 = divide by 128 (for SYSCLK ≤ 320 MHz)
7 = divide by 224 (for SYSCLK ≤ 540 MHz)
Reserved. This must be programmed to “1”.
FCS_REMOVE
LGTH_FRM_DIS
RX_BUF_OFFSET
PAUSE_EN
[17] rwc-_-_
[16] rwc-_-_
[15:14] rwc-_-_
[13] rwc-_-_
[12] rwc-_-_
[11]
Reserved. This must be programmed to “1”.
Reserved.
Reserved.
Reserved.
Reserved.
RETRY_TST
RSVD
Gigabit Mode Enable.
GIG_MODE_EN
[10] rwc-_-_
0 = 100 Mb/s operation using an MII interface
1 = 1000 Mb/s operation using a GMII interface
Reserved.
EXT_AMATCHEN
RX_1536FRMS
[9] rwc-_-_
[8] rwc-_-_
Receive 1536 Byte Frames.
0 = maximum receive Ethernet packet length is 1518 bytes
1 = maximum receive Ethernet packet length is 1536 bytes
Reserved.
Reserved.
UNI_HSH_EN
[7] rwc-_-_
[6] rwc-_-_
[5] rwc-_-_
MULT_HSH_EN
NO_BROADCAST
No Broadcast.
0 = This function is disabled.
1 = Packets with the Ethernet Broadcast DA are discarded.
Reserved. This must be programmed to “1”.
Reserved.
COPY_FRMS
JUMBO_FRMS
DISC_NONVLAN
FULL_DUPLEX
SPEED
[4] rwc-_-_
[3] rwc-_-_
[2] rwc-_-_
[1] rwc-_-_
[0] rwc-_-_
A:0C08h
Discard Non-VLAN = 1 = discard with no VLAN tags.
Reserved. This must be programmed to “1”.
Reserved. This must be programmed to “1”.
NET_STATUS.
RSVD
Network Status Register. Default: 00.00.00.04h
Reserved.
[31:3]
PHY Management Idle = 1 = MDIO (Phy) management is idle (i.e. has
PHY_MAN_IDLE
[2] ros-_-_
completed).
MDIO Status indicates the status/value of the MDIO signal.
MDIOS
[1] ros-_-_
[0] ros-_-_
Reserved.
SYNC_STAT
RSVD.
A:0C0Ch
Reserved.
USER_IO.
USER_PRG_IN
USER_PRG_OUT
TX_STATUS.
RSVD
A:0C10h
User Input/Output Register. Default: 0x00.00.00.00
Reserved.
Reserved.
[31:16] ros-_-_
[15:0] rwc-_-_
A:0C14h
Transmit Status Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
[31:9]
TX_HRESP
LATE_COL
TX_URUN
[8] rls-cow-_
[7] rls-cow-_
[6] rls-cow-_
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Addr (A:)
M. Field Name
TX_COMPLETE
TX_BUF_EXH
TX_GO
Bit [x:y] Type
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
[5] rls-cow-_
[4] rls-cow-_
[3] rls-cow-_
[2] rls-cow-_
[1] rls-cow-_
[0] rls-cow-_
TX_RETRY_EXC
TX_COL
TX_USED
RX_QPTR.
A:0C18h
Receive Buffer Queue Base Address. Default: 0x00.00.00.00
Reserved.
RX_BUF_QBA
RSVD
[31:2] rwc-_-_
[1:0]
Reserved.
TX_QPTR.
A:0C1Ch
Transmit Queue Base Address. Default: 0x00.00.00.00
Reserved.
Reserved.
TX_B UF_QBA
RSVD
[31:2] rwc-_-_
[1:0]
RX_STATUS.
RSVD
A:0C20h
[31:4]
[3] rls-cow-_
Receive Status Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
RX_HRESP
RX_ORUN
[2] rls-cow-_
[1] rls-cow-_
[0] rls-cow-_
RX_DONE
RX_BUF_USED
IRQ_STATUS.
RSVD
A:0C24h
[31:16]
[15] rls-cor-_
Interrupt Status Register. Default: 0x00.00.00.00
Reserved.
Reserved.
IRQ_EXT_INT
IRQ_PAUSE_TX
IRQ_PAUSE_0
IRQ_PAUSE_RX
IRQ_HRESP
IRQ_RX_ORUN
RSVD
Reserved.
[14] rls-cor-_
[13] rls-cor-_
[12] rls-cor-_
[11] rls-cor-_
[10] rls-cor-_
[9:8]
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
IRQ_TX_DONE
IRQ_TX_ERROR
IRQ_RETRY_EXC
IRQ_TX_URUN
IRQ_TX_USED
IRQ_RX_USED
IRQ_RX_DONE
IRQ_MAN_DONE
[7] rls-cor-_
[6] rls-cor-_
[5] rls-cor-_
[4] rls-cor-_
[3] rls-cor-_
[2] rls-cor-_
[1] rls-cor-_
[0] rls-cor-i3
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
PHY Management Operation Complete = “1” = MDIO operation done.
IRQ_ENABLE.
A:0C28h
[31:16]
[15] woc-_-_
Interrupt Enable Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
RSVD
EN_IRQ_EXT_INT
EN_IRQ_PAUSE_TX
EN_IRQ_PAUSE_0
EN_IRQ_PAUSE_RX
EN_IRQ_HRESP
EN_IRQ_RX_ORUN
[14] woc-_-_
[13] woc-_-_
[12] woc-_-_
[11] woc-_-_
[10] woc-_-_
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DS34S132 DATA SHEET
Addr (A:)
M. Field Name
RSVD
Bit [x:y] Type
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
[9:8]
EN_IRQ_TX_DONE
EN_IRQ_TX_ERROR
EN_IRQ_RETRY_EXC
[7] woc-_-_
[6] woc-_-_
[5] woc-_-_
[4] woc-_-_
[3] woc-_-_
[2] woc-_-_
[1] woc-_-_
[0] woc-_-i3
EN_IRQ_TX_URUN
EN_IRQ_TX_USED
EN_IRQ_RX_USED
EN_IRQ_RX_DONE
EN_IRQ_MAN_DONE
Enable PHY Management Operation Complete. The combination of
EN_IRQ_MAN_DONE = 1, DIS_IRQ_MAN_DONE = 0 and
IRQ_MAN_DONE = 1, forces MIRS = 1.
IRQ_DISABLE.
RSVD
A:0C2Ch
Interrupt Disable Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
[31:18]
RSVD
[17:16]
DIS_IRQ_EXT_INT
DIS_IRQ_PAUSE_TX
[15] woc-_-_
[14] woc-_-_
[13] woc-_-_
[12] woc-_-_
[11] woc-_-_
[10] woc-_-_
[9:8]
DIS_IRQ_PAUSE_0
DIS_IRQ_PAUSE_RX
DIS_IRQ_HRESP
DIS_IRQ_RX_ORUN
RSVD
DIS_IRQ_TX_DONE
DIS_IRQ_TX_ERROR
DIS_IRQ_RETRY_EXC
[7] woc-_-_
[6] woc-_-_
[5] woc-_-_
[4] woc-_-_
[3] woc-_-_
[2] woc-_-_
[1] woc-_-_
[0] woc-_-i3
DIS_IRQ_TX_URUN
DIS_IRQ_TX_USED
DIS_IRQ_RX_USED
DIS_IRQ_RX_DONE
DIS_IRQ_MAN_DONE
Disable PHY Management Operation Complete. (see
EN_IRQ_MAN_DONE)
IRQ_MASK.
A:0C30h
Interrupt Mask Register. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
RSVD
[31:16]
MSK_IRQ_EXT_INT
MSK_IRQ_PAUSE_TX
[15] ros-_-_
[14] ros-_-_
[13] ros-_-_
[12] ros-_-_
[11] ros-_-_
[10] ros-_-_
[9:8]
MSK_IRQ_PAUSE_0
MSK_IRQ_PAUSE_RX
MSK_IRQ_HRESP
MSK_IRQ_RX_ORUN
RSVD
MSK_IRQ_TX_DONE
MSK_IRQ_TX_ERROR
MSK_IRQ_RETRY_EXC
[7] ros-_-_
[6] ros-_-_
[5] ros-_-_
[4] ros-_-_
[3] ros-_-_
MSK_IRQ_TX_URUN
MSK_IRQ_TX_USED
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Addr (A:)
M. Field Name
Bit [x:y] Type
Description
Reserved.
Reserved.
MSK_IRQ_RX_USED
MSK_IRQ_RX_DONE
[2] ros-_-_
[1] ros-_-_
[0] ros-_-_
Mask PHY Management Operation Complete. A read of this register
returns the value of the management done interrupt mask. 0: Interrupt is
enabled 1: Interrupt is disabled A write to this register directly affects the
state of the corresponding bit in the interrupt status register, causing an
interrupt to be generated if a 1 is written.
MSK_IRQ_MAN_D
ONE
PHY_MAN.
A:0C34h
Phy Maintenance Register. Default: 0x00.00.00.00
Reserved.
PHY_SET3
[31] rwc-_-_
Reserved. This must be programmed to “1”.
Phy Set 2 selects the MDIO Operation: 2 = Read; 1 = Write.
Phy Address selects the MDIO Phy address.
Phy Register Address selects the MDIO Register address.
Reserved. This must be programmed to “2”.
PHY_CL22
[30] rwc-_-_
PHY_SET2
[29:28] rwc-_-_
[27:23] rwc-_-_
[22:18] rwc-_-_
[17:16] rwc-_-_
[15:0] rwc-_-_
PHY_ADDR
PHY_REG_ADDR
PHY_SET1
Phy Data to be Written provides the Write data sent to the Phy or the
PHY_DATA_WR
Read data received from the Phy according to the PHY_SET2 operation.
RX_PAUSE_TIME. A:0C38h
Received Pause Quantum Register. Default: 0x00.00.00.00
Reserved.
RSVD
[31:16]
Reserved.
RX_PAUSE_Q
[15:0] ros-_-_
TX_PAUSE_QUAN A:0C3Ch
T.
Transmit Pause Quantum Register. Default: 00.00.FF.FFh
Reserved.
RSVD
[31:16]
Reserved.
TX_PAUSE_Q
HASH_BOT.
[15:0] rwc-_-_
A:0C80h
[31:0] rwc-_-_
A:0C84h
[31:0] rwc-_-_
A:0C88h
[31:0] rwc-_-_
A:0C8Ch
Hash Register Bottom. Default: 0x00.00.00.00
Reserved.
HASH_BOT
HASH_TOP.
Hash Register Top. Default: 0x00.00.00.00
Reserved.
HASH_TOP
LADDR1_BOT.
SPEC_ADD1_BOT
LADDR1_TOP.
RSVD
Specific Address 1 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 1 Top. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
SPEC_ADD1_TOP
LADDR2_BOT.
SPEC_ADD2_BOT
LADDR2_TOP.
RSVD
[15:0] rwc-_-_
A:0C90h
[31:0] rwc-_-_
A:0C94h
Specific Address 2 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 2 Top. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
SPEC_ADD2_TOP
LADDR3_BOT.
SPEC_ADD3_BOT
LADDR3_TOP.
RSVD
[15:0] rwc-_-_
A:0C98h
[31:0] rwc-_-_
A:0C9Ch
Specific Address 3 Bottom. Default: 0x00.00.00.00
Reserved.
Specific Address 3 Top. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
SPEC_ADD3_TOP
LADDR4_BOT.
SPEC_ADD4_BOT
[15:0] rwc-_-_
A:0CA0h
[31:0] rwc-_-_
Specific Address 4 Bottom. Default: 0x00.00.00.00
Reserved.
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DS34S132 DATA SHEET
Addr (A:)
M. Field Name
Bit [x:y] Type
Description
LADDR4_TOP.
RSVD
A:0CA4h
Specific Address 4 Top. Default: 0x00.00.00.00
Reserved.
[31:16]
Reserved.
SPEC_ADD4_TOP
ID_CHECK1.
EN_TYPE_ID_M1
RSVD
[15:0] rwc-_-_
A:0CA8h
Type ID Match 1. Default: 0x00.00.00.00
Reserved.
[31] rwc-_-_
[30:16]
Reserved.
Reserved.
TYPE_ID_M1
ID_CHECK2.
EN_TYPE_ID_M2
RSVD
[15:0] rwc-_-_
A:0CACh
[31] rwc-_-_
[30:16]
Type ID Match 2. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
TYPE_ID_M2
ID_CHECK3.
EN_TYPE_ID_M3
RSVD
[15:0] rwc-_-_
A:0CB0h
Type ID Match 3. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
[31] rwc-_-_
[30:16]
TYPE_ID_M3
ID_CHECK4.
EN_TYPE_ID_M4
RSVD
[15:0] rwc-_-_
A:0CB4h
Type ID Match 4. Default: 0x00.00.00.00
Reserved.
Reserved.
Reserved.
Reserved.
[31] rwc-_-_
[30:16]
TYPE_ID_M4
RSVD.
[15:0] rwc-_-_
A:0CB8h
IPG_STRETCH.
RSVD
A:0CBCh
[31:16]
IPG Stretch Register. Default: 0x00.00.00.00
Reserved.
Inter-Packet Gap can be used to modify the Inter Packet Gap between
transmitted packets. Bits 7:0 are multiplied with the previously
transmitted frame length (including preamble) bits 15:8 +1 divide the
frame length. If the resulting number is greater than 96 and bit 28 is set
in the M.NET_CONFIG.IPG = 1 network configuration register then the
resulting number is used for the transmit inter-packet-gap. 1 is added to
bits 15:8 to prevent a divide by zero.
IPG
[15:0] rwc-_-_
MOD_ID.
A:0CFCh
Module Revision ID Register. Default: 00.02.00.00h
Reserved.
RSVD
[31:16] ros-_-_
[15:0] ros-_-_
A:0D00h
Reserved.
MOD_REV
OCT_TX_BOT.
TX_OCTETS_FRM
Octet Transmitted Bottom. Default: 0x00.00.00.00
rcs-cor-sc
[31:0]
Transmitted Octets in Frame [31:0] = # octets in transmitted frames
(48-bit count using OCT_TX_BOT and OCT_TX_TOP).
OCT_TX_TOP.
RSVD
A:0D04h
Octet Transmitted Top. Default: 0x00.00.00.00
Reserved.
[31:16]
rcs-cor-sc
[15:0]
Transmitted Octets in Frame [47:32]. (see OCT_TX_BOT)
Frames Transmitted Top. Default: 0x00.00.00.00
TX_OCTETS_FRM
STATS_FRAMES_ A:0D08h
TX.
rcs-cor-sc
rcs-cor-sc
[31:0]
Frames Transmitted = # transmitted frames.
FRMS_TX
[31:0]
BROADCAST_TX. A:0D0Ch
Broadcast Frames Transmitted. Default: 0x00.00.00.00
Broadcast Frames Transmitted = # transmitted Ethernet Broadcast
BRDCST_TX
frames.
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Addr (A:)
M. Field Name
MULTICAST_TX.
MLTCST_TX
Bit [x:y] Type
Description
A:0D10h
Multicast Frames Transmitted. Default: 0x00.00.00.00
rcs-cor-sc
Multicast Frames Transmitted = # transmitted Ethernet Multicast
[31:0]
frames.
STATS_PAUSE_TX A:0D14h
.
Pause Frames Transmitted. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
[31:16]
[15:0]
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
PAUSE_TX
FRAME64_TX.
64B_TX
A:0D18h
[31:0]
64 Byte Frames Transmitted. Default: 0x00.00.00.00
64 Byte Frames Transmitted = # transmitted frames with 64 bytes.
65 to 127 Byte Frames Transmitted. Default: 0x00.00.00.00
FRAME65_TX.
65TO127B_TX
A:0D1Ch
[31:0]
65 to 127 Byte Frames Transmitted = # transmitted frames with 65 to
127 bytes.
FRAME128_TX.
A:0D20h
128 to 255 Byte Frames Transmitted. Default: 0x00.00.00.00
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
128 to 255 Byte Frames Transmitted = # transmitted frames with 128
to 255 bytes.
128TO255B_TX
[31:0]
FRAME256_TX.
A:0D24h
256 to 511 Byte Frames Transmitted. Default: 0x00.00.00.00
256 to 511 Byte Frames Transmitted = # transmitted frames with 256
to 511 bytes.
256TO511B_TX
[31:0]
FRAME512_TX.
A:0D28h
512 to 1023 Byte Frames Transmitted. Default: 0x00.00.00.00
512 to 1023 Byte Frames Transmitted = # transmitted frames with 512
to 1023 bytes.
512TO1023B_TX
[31:0]
FRAME1024_TX.
A:0D2Ch
1024 to 1518 Byte Frames Transmitted. Default: 0x00.00.00.00
1024 to 1518 Byte Frames Transmitted = # transmitted frames with
1024 to 1518 bytes.
1024TO1518B_TX
[31:0]
FRAME1519_TX.
A:0D30h
Greater Than 1518 Byte Frames Transmitted. Default: 0x00.00.00.00
1519 Bytes or More Frames Transmitted = # transmitted frames with >
1519-bytes.
1519B_OR_MORE
[31:0]
STATS_TX_URUN. A:0D34h
Transmit Under Runs. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
Reserved.
TX_URUNS
STATS_SINGLE_C A:0D38h
OL.
Single Collision Frames. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
[32:18]
[17:0]
SINGLE_COL
STATS_MULTI_CO A:0D3Ch
L.
Multiple Collision Frames. Default: 0x00.00.00.00
Reserved.
RSVD
[32:18]
[17:0]
Reserved.
MLT_COL
STATS_EXCESS_ A:0D40h
COL.
Excessive Collisions. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
[31:10]
[9:0]
EXC_COL
STATS_LATE_COL A:0D44h
.
Late Collisions. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
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Addr (A:)
M. Field Name
LATE_COL
Bit [x:y] Type
Description
Reserved.
rcs-cor-sc
[9:0]
A:0D48h
STATS_DEF_TX.
RSVD
Deferred Transmission Frames. Default: 0x00.00.00.00
Reserved.
[32:18]
[17:0]
rcs-cor-sc
Reserved.
DEF_TX_FRMS
STATS_CRS_ERR A:0D4Ch
ORS.
Carrier Sense Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
rcs-cor-sc
Reserved.
CRS_ERRORS
OCT_RX_BOT.
RX_OCTETS_FRM
A:0D50h
[31:0]
Octets Received Bottom. Default: 0x00.00.00.00
Received Octets in Frame [31:0] = # octets in received frames (48-bit
count using OCT_RX_BOT and OCT_RX_TOP). This count does not
include octets for frames discarded by enabled MAC discard functions
(e.g. packet length > 1536 bytes). OCT_RX_BOT should be read before
OCT_RX_TOP.
OCT_RX_TOP.
RSVD
A:0D54h
[31:16]
[15:0]
Octets Received Top. Default: 0x00.00.00.00
Reserved.
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
Received Octets in Frame [47:32]. (see OCT_RX_BOT)
RX_OCTETS_FRM
STATS_FRAMES_ A:0D58h
RX.
Frames Received. Default: 0x00.00.00.00
Frames Received = # received frames, not including frames discarded
by enabled MAC discard functions.
FRMS_RX
[31:0]
BROADCAST_RX. A:0D5Ch
Broadcast Frames Received. Default: 0x00.00.00.00
Broadcast Frames Received = # received Ethernet Broadcast frames,
not including frames discarded by enabled MAC discard functions.
BRDCST_RX
[31:0]
MULTICAST_RX.
A:0D60h
Multicast Frames Received. Default: 0x00.00.00.00
Multicast Frames Received = # received Ethernet Multicast frames, not
MLTCST_RX
[31:0]
including frames discarded by enabled MAC discard functions.
STATS_PAUSE_R A:0D64h
X.
Pause Frames Received. Default: 0x00.00.00.00
Reserved.
RSVD
[31:16]
[15:0]
rcs-cor-sc
rcs-cor-sc
Reserved.
PAUSE_RX
FRAME64_RX.
64B_RX
A:0D68h
[31:0]
64 Byte Frames Received. Default: 0x00.00.00.00
64 Byte Frames Received = # received frames with 64 bytes, not
including frames discarded by enabled MAC discard functions.
FRAME65_RX.
A:0D6Ch
65 to 127 Byte Frames Received. Default: 0x00.00.00.00
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
65 to 127 Byte Frames Received = # received frames with 65 to 127
bytes, not including frames discarded by enabled MAC discard functions.
65TO127B_RX
[31:0]
FRAME128_RX.
A:0D70h
128 to 255 Byte Frames Received. Default: 0x00.00.00.00
128 to 255 Byte Frames Received = # received frames with 128 to 255
bytes, not including frames discarded by enabled MAC discard functions.
128TO255B_RX
[31:0]
FRAME256_RX.
A:0D74h
256 to 511 Byte Frames Received. Default: 0x00.00.00.00
256 to 511 Byte Frames Received = # received frames with 256 to 511
256TO511B_RX
[31:0]
bytes, not including frames discarded by enabled MAC discard functions.
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DS34S132 DATA SHEET
Addr (A:)
M. Field Name
FRAME512_RX.
512TO1023B_RX
Bit [x:y] Type
Description
A:0D78h
512 to 1023 Byte Frames Received. Default: 0x00.00.00.00
rcs-cor-sc
512 to 1023 Byte Frames Received = # received frames with 512 to
1023 bytes, not including frames discarded by enabled MAC discard
functions.
[31:0]
FRAME1024_RX.
A:0D7Ch
1024 to 1518 Byte Frames Received. Default: 0x00.00.00.00
rcs-cor-sc
rcs-cor-sc
1024 to 1518 Byte Frames Received = # received frames with 1024 to
1518 bytes, not including frames discarded by enabled MAC discard
functions.
1024TO1518B_RX
[31:0]
FRAME1519_RX.
A:0D80h
1519 to Maximum Byte Frames Received. Default: 0x00.00.00.00
1519 Bytes or More Frames Received = # received frames with > 1518
bytes, not including frames discarded by enabled MAC discard functions.
1519B_OR_MORE_
RX
[31:0]
STATS_USIZE_FR A:0D84h
AMES.
Undersized Frames Received. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
rcs-cor-sc
Undersized Frames Received = # received frames with < 64 bytes, not
including frames with an Ethernet FCS error or an alignment error.
USIZE_RX
STATS_EXCESS_L A:0D88h
EN.
Oversized Frames Received. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
Oversized Frames Received = # received frames with more than 1518
or 1536 bytes as specified by M.NET_CONFIG.RX_1536FRMS. This
count does not include frames that have either a CRC error, an
alignment error or a receive symbol error.
OSIZE_RX
STATS_JABBERS. A:0D8Ch
Jabbers Received. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
Jabbers Received = # received frames with more than 1518 or 1536
bytes, as specified by M.NET_CONFIG.RX_1536FRMS, and that also
include a CRC error, an alignment error or a receive symbol error.
JAB_RX
STATS_FCS_ERR A:0D90h
ORS.
Frame Check Sequence Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
rcs-cor-sc
Frame Check Sequence Errors = # received frames with FCS errors
and a length between 64 and 1518 bytes (1536 if RX_1536FRMS = 1).
FCS_ERR
STATS_LENGTH_ A:0D94h
ERRORS.
Length Field Frame Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
Length Field Frame Errors = # received frames with an Ethernet Length
field error and a measured length between 64 and 1518 bytes (1536
bytes if RX_1536FRMS = 1).
LGTH_FRM_ERR
STATS_RX_SYM_ A:0D98h
ERR.
Receive Symbol Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
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DS34S132 DATA SHEET
Addr (A:)
M. Field Name
Bit [x:y] Type
Description
rcs-cor-sc
[9:0]
Received Symbol Errors = # received frames with input pin RX_ER = 1
during reception. For the 100 Mb/s mode Symbol Errors are counted
regardless of the frame length. For the 1000 Gb/s mode the frame must
satisfy the Ethernet Slot Time requirements to be counted as a Symbol
Error. Receive Symbol Errors are also counted as an FCS Error or an
Alignment Error if the frame is between 64 and 1518 bytes (1536 bytes if
RX_1536FRMS = 1). If the frame is larger it is also counted as a jabber
error. If the frame is too small it is also counted as an Undersized Error.
RX_SYM_ERR
STATS_ALIGN_ER A:0D9Ch
RORS.
Alignment Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[31:10]
[9:0]
rcs-cor-sc
Alignment Errors = # received frames with a length that is not an
integral number of bytes, has a bad FCS when the length is truncated to
the nearest integral number of bytes and the integral number of bytes is
between 64 and 1518 bytes (1536 bytes if RX_1536FRMS = 1).
ALIGN_ERR
STATS_RX_RES_E A:0DA0h
RR.
Receive Resource Errors. Default: 0x00.00.00.00
Reserved.
RSVD
[32:18]
[17:0]
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
rcs-cor-sc
Reserved.
RX_RES_ERR
STATS_RX_ORUN. A:0DA4h
Receive Overruns. Default: 0x00.00.00.00
Reserved.
Reserved.
RSVD
[31:10]
[9:0]
RX_ORUNS
IP_HDR_CHK.
RSVD
A:0DA8h
[31:8]
IP Header Checksum Errors. Default: 0x00.00.00.00
Reserved.
Reserved.
IP_HDR_CHK
TCP_CHK.
RSVD
[7:0]
A:0DACh
[31:8]
TCP Checksum Errors. Default: 0x00.00.00.00
Reserved.
Reserved.
TCP_CHK
UDP_CHK.
RSVD
[7:0]
A:0DB0h
[31:8]
UDP Checksum Errors. Default: 0x00.00.00.00
Reserved.
Reserved.
UDP_CHK
RSVD.
[7:0]
A:0E00h
[31:0]
Reserved.
Reserved.
Reserved.
Reserved.
RSVD
REG_TOP.
RSVD
A:0E3Ch
[31:0]
10.3.13 TXP SW CAS Registers (TXSCn.)
Table 10-28. TXP SW CAS Registers (TXSCn.)
TXSCn
Addr (A:)
Field Name Bit [x:y] Type
Description
CR1.
A:1000h
[31:28] rwd-_-_
Configuration Register 1. Default: na
CAS Time Slot 0 = Timeslot 0 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 1 = Timeslot 1 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 2 = Timeslot 2 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 3 = Timeslot 3 TXP Bundle Conditioning SW CAS code.
CTS0
CTS1
CTS2
CTS3
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
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TXSCn
Addr (A:)
Field Name Bit [x:y] Type
Description
CAS Time Slot 4 = Timeslot 4 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 5 = Timeslot 5 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 6 = Timeslot 6 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 7 = Timeslot 7 TXP Bundle Conditioning SW CAS code.
Configuration Register 2. Default: na
CTS4
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
[3:0] rwd-_-_
CTS5
CTS6
CTS7
CR2.
A:1004h
CAS Time Slot 8 = Timeslot 8 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 9 = Timeslot 9 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 10 = Timeslot 10 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 11 = Timeslot 11 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 12 = Timeslot 12 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 13 = Timeslot 13 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 14 = Timeslot 14 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 15 = Timeslot 15 TXP Bundle Conditioning SW CAS code.
CTS8
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
CTS9
CTS10
CTS11
CTS12
CTS13
CTS14
CTS15
CR3.
[3:0] rwd-_-_
A:1008h
Configuration Register 3. Default: na
CAS Time Slot 16 = Timeslot 16 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 17 = Timeslot 17 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 18 = Timeslot 18 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 19 = Timeslot 19 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 20 = Timeslot 20 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 21 = Timeslot 21 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 22 = Timeslot 22 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 23 = Timeslot 23 TXP Bundle Conditioning SW CAS code.
Configuration Register 4. Default: na
CTS16
CTS17
CTS18
CTS19
CTS20
CTS21
CTS22
CTS23
CR4.
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
[3:0] rwd-_-_
A:100Ch
CAS Time Slot 24 = Timeslot 24 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 25 = Timeslot 25 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 26 = Timeslot 26 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 27 = Timeslot 27 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 28 = Timeslot 28 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 29 = Timeslot 29 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 30 = Timeslot 30 TXP Bundle Conditioning SW CAS code.
CAS Time Slot 31 = Timeslot 31 TXP Bundle Conditioning SW CAS code.
CTS24
CTS25
CTS26
CTS27
CTS28
CTS29
CTS30
CTS31
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
[3:0] rwd-_-_
10.3.14 Xmt (RXP) SW CAS Registers (RXSCn.)
Table 10-29. Xmt (RXP) SW CAS Registers (RXSCn.)
RXSCn.
Addr (A:)
Field Name Bit [x:y] Type
Description
CR1.
A:1200h
[31:28] rwd-_-_
Configuration Register 1. Default: na
CAS Time Slot 0 = Timeslot 0 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 1 = Timeslot 1 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 2 = Timeslot 2 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 3 = Timeslot 3 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 4 = Timeslot 4 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 5 = Timeslot 5 RXP Bundle Conditioning SW CAS code.
CTS0
CTS1
CTS2
CTS3
CTS4
CTS5
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
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RXSCn.
Addr (A:)
Field Name Bit [x:y] Type
Description
CAS Time Slot 6 = Timeslot 6 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 7 = Timeslot 7 RXP Bundle Conditioning SW CAS code.
Configuration Register 2. Default: na
CTS6
[7:4] rwd-_-_
[3:0] rwd-_-_
CTS7
CR2.
A:1204h
CAS Time Slot 8 = Timeslot 8 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 9 = Timeslot 9 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 10 = Timeslot 10 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 11 = Timeslot 11 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 12 = Timeslot 12 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 13 = Timeslot 13 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 14 = Timeslot 14 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 15 = Timeslot 15 RXP Bundle Conditioning SW CAS code.
Configuration Register 3. Default: na
CTS8
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
CTS9
CTS10
CTS11
CTS12
CTS13
CTS14
CTS15
CR3.
[3:0] rwd-_-_
A:1208h
CAS Time Slot 16 = Timeslot 16 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 17 = Timeslot 17 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 18 = Timeslot 18 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 19 = Timeslot 19 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 20 = Timeslot 20 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 21 = Timeslot 21 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 22 = Timeslot 22 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 23 = Timeslot 23 RXP Bundle Conditioning SW CAS code.
CTS16
CTS17
CTS18
CTS19
CTS20
CTS21
CTS22
CTS23
CR4.
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
[3:0] rwd-_-_
A:120Ch
Configuration Register 4. Default: na
CAS Time Slot 24 = Timeslot 24 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 25 = Timeslot 25 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 26 = Timeslot 26 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 27 = Timeslot 27 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 28 = Timeslot 28 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 29 = Timeslot 29 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 30 = Timeslot 30 RXP Bundle Conditioning SW CAS code.
CAS Time Slot 31 = Timeslot 31 RXP Bundle Conditioning SW CAS code.
CTS24
CTS25
CTS26
CTS27
CTS28
CTS29
CTS30
CTS31
[31:28] rwd-_-_
[27:24] rwd-_-_
[23:20] rwd-_-_
[19:16] rwd-_-_
[15:12] rwd-_-_
[11:8] rwd-_-_
[7:4] rwd-_-_
[3:0] rwd-_-_
10.3.15 TDM Port n Registers (Pn.; n = 0 to 31)
10.3.15.1Port n Transmit Configuration Registers (Pn.)
Table 10-30. Port n Transmit Configuration Registers (Pn.)
Pn. Field Addr (A:)
Name
PTCR1.
DR
Bit [x:y] Type
Description
A:2000h
Port Transmit Configuration Register 1. Default: 81.FC.00.00h
Reserved.
Reserved.
[31] rwc-_-_
[30:29]
RSVD
SFS
Structured Format Select selects the transmit TDM Port Structure type.
0 = unstructured format (no framing; for SAT or HDLC applications)
1 = structured format (with T1 or E1 framing; for CES or HDLC applications)
[28] rwc-_-_
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DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
Frame Format Select selects the transmit TDM Port Frame type (only valid if
FFS
[27] rwc-_-_
SFS = 1).
0 = E1 frame structure
1 = T1 frame structure
Multiframe Format Select selects the transmit TDM Port CAS multi-frame type
(only valid if SFS = 1).
0 = No multiframe structure
1 = E1 multiframe structure (16 frame multiframe structure)
2 = T1 - SF multiframe structure (12 frame multiframe structure)
3 = T1 – ESF multiframe structure (24 frame multiframe structure)
MFS
BFD
[26:25] rwc-_-_
Buffer Frame/Fragment Depth selects the number of 125 us periods of TDM
data internally buffered by the S132 for the CES/SAT engines (see PTCR1.BPF).
The number of bytes specified by BFD * BPF must be ≤ B.BCDR1.PMS for all
RXP Bundles assigned to this TDM Port.
[24:23] rwc-_-_
0 = Disable SAT/CES data path for transmit TDM Port
1 = 1 Frame/Fragment per staging buffer (125 us staging buffer)
2 = 2 Frame/Fragments per staging buffer (250 us staging buffer)
3 = 4 Frame/Fragments per staging buffer (500 us staging buffer)
Bytes Per Frame/Fragment = # bytes transmitted from TDM Port during a 125 us
period (125 us = time period for 1 CES Frame or 1 SAT Fragment). For T1, BPF =
23 (0x17; SAT/CES). For E1, BPF = 31 (0x1F; SAT/CES).
0 = 1 byte per 125 us period
BPF
[22:18] rwc-_-_
31 = 32 bytes per 125 us period
Decap Priority selects the RXP (Decap) SAT/CES/HDLC processing priority
0 = low priority (processed after all high priority data has been completed)
1 = high priority
DP
[17] rwc-_-_
[16] rwc-_-_
Disable Overwrite Signaling On TDAT = “1” disables the S132 from over-writing
CAS codes in the transmit TDM Port TDAT pin, T1/E1 CAS code positions (T1
robbed-bit signaling and E1 Timeslot 16). When DOSOT = 0, the S132 over-writes
those TDAT time positions. DOSOT does not affect the transmit TDM Port TSIG
data (when a TDM Port is programmed to transmit CAS the CAS codes are
transmitted on TSIG regardless of the DOSOT setting).
DOSOT
Reserved.
RSVD
[15:0]
PTCR2.
RSVD
A:2004h
[31:8]
[9] rwc-_-_
Port Transmit Configuration Register 2. Default: 00.00.00.08h
Reserved.
Port Receive to Port Transmit Line Loopback = “1” enables the TDM Port Line
Loopback from RDAT, RSYNC, RSIG to TDAT, TSYNC, TSIG respectively. The
transmit timing is not automatically changed when PRPTLL = 1. Pn.PTCR2.TSS
must be programmed so the incoming RDAT data stream timing is used to time
TCLKO and RCLK. PRPTLL = 1 over-rides Pn.PTCR2.TDS forcing TSYNC to be
an output.
PRPTLL
0 = TDAT/TSYNC/TSIG pass data from RXP packets (normal)
1 = TDAT/TSYNC/TSIG loopback data from receive inputs RDAT/RSYNC/RSIG
Transmit Input Output Enable.
0 = TDAT/TSIG/TSYNC disabled (high-impedance)
1 = TDAT/TSIG/TSYNC enabled (Pn.PTCR2.TDS selects TSYNC direction)
TIOE
TCE
[8] rwc-_-_
[7] rwc-_-_
[6] rwc-_-_
Transmit Clock Enable.
0 = TCLKO disabled (high-impedance)
1 = TCLKO enabled with timing source selected by Pn.PTCR2.TSS
Transmit Frame Timing Synchronized to RSYNC.
TSRS
0 = Transmit Frame Timing synchronized to RSYNC input
1 = Transmit Frame Timing synchronized to TSYNC input (when TDS = 0)
19-4750; Rev 1; 07/11
141 of 194
DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
TSYNC Direction Select. (only valid when TIOE = 1).
0 = TSYNC is an input
1 = TSYNC is an output
TDS
[5] rwc-_-_
[4] rwc-_-_
[3] rwc-_-_
[2:0] rwc-_-_
Transmit Output Edge Select.
0 = TDM Port TDAT/TSIG/TSYNC outputs timed using TCLKO positive edge
1 = TDM Port TDAT/TSIG/TSYNC outputs timed using TCLKO negative edge
TOES
TIES
TSS
Transmit Input Edge Select. (only valid when TDS = 1)
0 = TDM Port TSYNC input timed using TCLKO positive edge
1 = TDM Port TSYNC input timed using TCLKO negative edge
TCLKO Source Select selects the timing source for TCLKO.
0 = RCLKn pin input signal
1 = internal aclk_n signal (port “n” recovered clock)
2 = internal grclk signal (globally selected recovered clock)
4 = EXTCLK[0] pin input signal
5 = EXTCLK[1] pin input signal
all other values are reserved
PTCR3.
A:2008h
[31:0] rwc-_-_
Port Transmit Configuration Register 3. Default: 0x00.00.00.00
PR to PT Time Slot Loop = “1” enables the TDM Port Timeslot Loopback from
RDAT, RSYNC, RSIG to TDAT, TSYNC, TSIG respectively (1 bit for each
timeslot; for T1, bits 31:24 are not used). The transmit timing is not automatically
changed when PRPTLL = 1. Pn.PTCR2.TSS must be programmed so the
incoming RDAT data stream timing is used to time TCLKO and RCLK. PRPTLL =
1 over-rides Pn.PTCR2.TDS forcing TSYNC to be an output. Any number of
timeslots can be in loopback while others Timeslot are not in loopback, but the
receive TDM Port timing and all RXP packet data streams must be frequency
synchronized to work error free. This loopback is only valid if Pn.PTCR1.SFS = 1
(CES).
PRPTTSL
0 = pass Timeslot data from RXP packets to TDAT/TSYNC/TSIG (normal)
1 = loopback Timeslot data from RDAT/RSYNC/RSIG to TDAT/TSYNC/TSIG
10.3.15.2Port n Transmit Status Registers (Pn.)
Table 10-31. Port n Transmit Status Registers (Pn.)
Pn. Field Addr (A:)
Name
PTSR1.
CTS0
CTS1
CTS2
CTS3
CTS4
CTS5
CTS6
CTS7
PTSR2.
CTS8
CTS9
CTS10
CTS11
CTS12
Bit [x:y] Type
Description
A:2020h
Port Transmit Status Register 1. Default: 0x00.00.00.00
CAS Time Slot 0 = value of CAS code transmitted at TDM Port for Timeslot 0.
CAS Time Slot 1 = value of CAS code transmitted at TDM Port for Timeslot 1.
CAS Time Slot 2 = value of CAS code transmitted at TDM Port for Timeslot 2.
CAS Time Slot 3 = value of CAS code transmitted at TDM Port for Timeslot 3.
CAS Time Slot 4 = value of CAS code transmitted at TDM Port for Timeslot 4.
CAS Time Slot 5 = value of CAS code transmitted at TDM Port for Timeslot 5.
CAS Time Slot 6 = value of CAS code transmitted at TDM Port for Timeslot 6.
CAS Time Slot 7 = value of CAS code transmitted at TDM Port for Timeslot 7.
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
A:2024h
Port Transmit Status Register 2. Default: 0x00.00.00.00
CAS Time Slot 8 = value of CAS code transmitted at TDM Port for Timeslot 8
CAS Time Slot 9 = value of CAS code transmitted at TDM Port for Timeslot 9
CAS Time Slot 10 = value of CAS code transmitted at TDM Port for Timeslot 10.
CAS Time Slot 11 = value of CAS code transmitted at TDM Port for Timeslot 11.
CAS Time Slot 12 = value of CAS code transmitted at TDM Port for Timeslot 12.
142 of 194
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
19-4750; Rev 1; 07/11
DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
CAS Time Slot 13 = value of CAS code transmitted at TDM Port for Timeslot 13.
CAS Time Slot 14 = value of CAS code transmitted at TDM Port for Timeslot 14.
CAS Time Slot 15 = value of CAS code transmitted at TDM Port for Timeslot 15.
Port Transmit Status Register 3. Default: 0x00.00.00.00
CTS13
CTS14
CTS15
PTSR3.
CTS16
CTS17
CTS18
CTS19
CTS20
CTS21
CTS22
CTS23
PTSR4.
CTS24
CTS25
CTS26
CTS27
CTS28
CTS29
CTS30
CTS31
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
A:2028h
CAS Time Slot 16 = value of CAS code transmitted at TDM Port for Timeslot 16.
CAS Time Slot 17 = value of CAS code transmitted at TDM Port for Timeslot 17.
CAS Time Slot 18 = value of CAS code transmitted at TDM Port for Timeslot 18.
CAS Time Slot 19 = value of CAS code transmitted at TDM Port for Timeslot 19.
CAS Time Slot 20 = value of CAS code transmitted at TDM Port for Timeslot 20.
CAS Time Slot 21 = value of CAS code transmitted at TDM Port for Timeslot 21
CAS Time Slot 22 = value of CAS code transmitted at TDM Port for Timeslot 22.
CAS Time Slot 23 = value of CAS code transmitted at TDM Port for Timeslot 23.
Port Transmit Status Register 4. Default: 0x00.00.00.00
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
A:202Ch
CAS Time Slot 24 = value of CAS code transmitted at TDM Port for Timeslot 24.
CAS Time Slot 25 = value of CAS code transmitted at TDM Port for Timeslot 25.
CAS Time Slot 26 = value of CAS code transmitted at TDM Port for Timeslot 26.
CAS Time Slot 27 = value of CAS code transmitted at TDM Port for Timeslot 27.
CAS Time Slot 28 = value of CAS code transmitted at TDM Port for Timeslot 28.
CAS Time Slot 29 = value of CAS code transmitted at TDM Port for Timeslot 29.
CAS Time Slot 30 = value of CAS code transmitted at TDM Port for Timeslot 30.
CAS Time Slot 31 = value of CAS code transmitted at TDM Port for Timeslot 31.
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
10.3.15.3Port n Transmit Status Register Latches (Pn.)
Table 10-32. Port n Transmit Status Register Latches (Pn.)
Pn. Field Addr (A:)
Name
PTSRL.
RSVD
BUSL
Bit [x:y] Type
Description
A:2030h
Port Transmit Status Register Latch. Default: 0x00.00.00.00
Reserved.
[31:2]
Buffer Underrun Status Latch = “1” indicates the transmit TDM Port ran out of
data. The S132 internal transmit processes were not able to keep up with the
transmit rate for this TDM Port.
[1] rls-crw-i3
Change Of Frame Alignment Status Latch = “1” indicates a change of frame or
COFASL
[0] rls-crw-i3
multi-frame timing error was detected (only valid for SFS = 1).
10.3.15.4Port n Transmit Status Register Interrupt Enables (Pn.)
Table 10-33. Port n Transmit Status Register Interrupt Enables (Pn.)
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
PTSRIE. A:2038h
Port Transmit Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
BUIE
[31:2]
[1] rwc-_-i3
Buffer Underrun Interrupt Enable. The combination of PTSRL.BUSL = 1 and
BUIE = 1 forces G.GSR1.PS = 1.
Change Of Frame Alignment Interrupt Enable. The combination of
COFAIE
[0] rwc-_-i3
PTSRL.COFASL = 1 and COFAIE = 1 forces G.GSR1.PS = 1.
19-4750; Rev 1; 07/11
143 of 194
DS34S132 DATA SHEET
10.3.15.5Port n Receive Configuration Registers (Pn.)
Table 10-34. Port n Receive Configuration Registers (Pn.)
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
PRCR1. A:2040h
Port Receive Configuration Register 1. Default: 81.FC.00.00h
Datapath Reset. When this bit is set, it will force the internal data path registers in
the corresponding port receive interface to their default state. This bit must be set
high for a minimum of 100ns. See section 10.3 Reset And Power Down.
0 = Normal operation
DR
[31] rwc-_-_
1 = Force all data path registers to their default values
Reserved.
RSVD
SFS
[30:29]
[28] rwc-_-_
Structured Format Select. This bit selects structured or unstructured formatting.
Unstructured format is used for SAT and unstructured HDLC. Structured format is
used for CES and structured HDLC.
0 = unstructured format
1 = structured format
Frame Format Select. This bit selects the frame format for the port receive.
FFS
[27] rwc-_-_
0 = E1 frame select
1 = T1 frame select
Multiframe Format Select. Used to determine the type of multiframe format
being used. The CAS machine uses this to determine when data may be captured
and passed to the packet interface. Additionally, the RSYNC uses this to know the
multiframe frame size for aligning the frame and the multiframe counters. Note
that this register has no affect in unstructured modes.
0 = none No multiframes.
MFS
[26:25] rwc-_-_
1 = E1 MF 16
2 = T1 SF 12
3 = T1 ESF 24
Buffer Frame Depth. Used to indicate the number of frames per segment. It is
also used to indicate the port has been disabled. When the frames of the segment
are filled, the PRDME is toggled.
0 = Disable Request to Encap
1 = 1 frame per segment
BFD
BPF
[24:23] rwc-_-_
[22:18] rwc-_-_
2 = 2 frame per segment
3 = 4 frame per segment
Bytes Per Frame. This is used to select the number of bytes to capture for
unstructured modes. For T1 this must be set to 17h and for E1 should be 1Fh.
00h = 1 byte captured
01h = 2 bytes captured
...
17h = 24 bytes captured
...
1Fh = 32 bytes captured
Encap Priority. This is used to prioritize processing of this port by the encap
engine. If more than one port has this bit set, then all of the high priority ports are
processed first, followed by the low priority ports.
EP
[17] rwc-_-_
0 = low priority for encap processing
1 = high priority for encap processing
CAS Source selects the receive T1/E1 Port CAS Signaling Source.
0 = RDAT pin
1 = RSIG pin
CS
[16] rwc-_-_
[15] rwc-_-_
C Bit Value for SF to ESF. Sets the value of the C bit when mapping SF locally
CBVSE
to ESF at the destination.
19-4750; Rev 1; 07/11
144 of 194
DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
D Bit Value for SF to ESF. Sets the value of the D bit when mapping SF locally
DBVSE
[14] rwc-_-_
to ESF at the destination.
L Bit. This sets the L bit value for all Bundles sourced by this port.
LB
[13] rwc-_-_
[12] rwc-_-_
L Bit Source Select selects the L-bit source for all TXP Bundles for this T1/E1
LBSS
port: 0 = PRCR1.LB value or 1 = L-bit programmed in each TXP Bundle header.
SAT Payload Length. Set to the # bytes per packet payload (SAT mode only).
SPL must = PMS and must be ≥ BPF. For example for T1 SAT, SPL = PMS =
0x17 (for 24 timeslots) and BPF must be set to 0x17 or less.
SPL
[11:1] rwc-_-_
Reserved.
RSVD
[0]
PRCR2. A:2044h
Port Receive Configuration Register 2. Default: 00.00.00.08h
Reserved.
RSVD
RSTS
[31:7]
[6] rwc-_-_
Receive Frame Synchronization .
0 = synchronized to RSYNC signal input
1 = synchronized to internal TDM Port Transmit frame timing (system timing)
RSYNC Direction Select. This bit selects the direction of the RSYNC signal.
RDS
[5] rwc-_-_
0 = input
1 = output
Reserved.
RSVD
RIES
[4]
Receive Input Edge Select. This bit selects the edge to be used for port receive
[3] rwc-_-_
data capture on inputs relative to RCLK.
0 = positive edge
1 = negative edge
Reserved.
RSVD
RSS
[2:1]
[0] rwc-_-_
RCLK Source Select. This bit is used to select the source of the clock used to
time the port receive interface. This selects the source clock for capture of RDAT,
RSIG, and RSYNC.
0 = RCLK Signal input
1 = TCLKO Signal output
PRCR3. A:2048h
Port Receive Configuration Register 3. Default: 0x00.00.00.00
PT to PR Time Slot Loopback. Each bit selects the TDM loopback for the
corresponding time slot from the port transmit to the port receive; bit 0 enables
port loop back for time slot 0, bit 1 enables port loop back for time slot 1, etc. You
may use either the loopback for PR to PT or PT to PR, but not both at the same
time; i.e. the control for the unused direction must not have any timeslots selected
for loopback. Note that for T1, bits 31:24 are not used.
PTPRTSL
[31:0] rwc-_-_
PRCR4. A:204Ch
Port Receive Configuration Register 4. Default: 0x00.00.00.00
Reserved.
RSVD
[31:17]
[16] rwc-_-_
RTP Time Stamp Generator Mode Select.
TSGMS
0 = derived from CMNCLK (Differential Timestamp)
1 = derived from RSS selected receive TDM Port timing (Absolute Timestamp)
Timestamp Generator M Coefficient is defined by the following equation where
TSPCLK = “remote PW Timestamp clock rate” (TSPCLK and CMNCLK are
specified in bits/sec; only valid for TSGMS = 0). In most applications TSPCLK =
CMNCLK and TSGMC = 4096 decimal = 0x1000.
TSGMC
[15:0] rwc-_-_
TSGMC = Integer [4096 * (TSPCLK ÷ CMNCLK)]
PRCR5. A:2050h
Port Receive Configuration Register 5. Default: 0x00.00.00.00
Reserved.
RSVD
[31:29]
Timestamp Generator N1 Coefficient is defined by the following equation (see
TSGMC). In most applications TSPCLK = CMNCLK and TSGN1C = 0x0000.
TSGN1C = (CMNCLK ÷ 8000) * [TSGMC – 4096 * (TSPCLK ÷ CMNCLK)]
TSGN1C
[28:16] rwc-_-_
19-4750; Rev 1; 07/11
145 of 194
DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
Reserved.
RSVD
[15:13]
Timestamp Generator N0 Coefficient is defined by the following equation (see
TSGN1C). In most applications TSPCLK = CMNCLK and TSGN0C = CMNCLK ÷
8000 (e.g. if TSGN0C = CMNCLK = 2.048 Mb/s then TSGN0C = 256 = 0x0100).
TSGN0C = TSGN1C + (CMNCLK ÷ 8000)
TSGN0C
[12:0] rwc-_-_
10.3.15.6Port n Receive Status Registers (Pn.)
Table 10-35. Port n Receive Status Registers (Pn.)
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
PRSR1. A:2060h
Port Receive Status Register 1. Default: 0x00.00.00.00
CAS Time Slot 0 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 0.
CAS Time Slot 1 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 1
CAS Time Slot 2 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 2
CAS Time Slot 3 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 3
CAS Time Slot 4 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 4
CAS Time Slot 5 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 5
CAS Time Slot 6 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 6
CAS Time Slot 7 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 7
Port Receive Status Register 2. Default: 0x00.00.00.00
CTS0
CTS1
CTS2
CTS3
CTS4
CTS5
CTS6
CTS7
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
PRSR2. A:2064h
CAS Time Slot 8 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 8
CAS Time Slot 9 = CAS code received at TDM Port (Pn.PRCR2.CS) for Timeslot 9
CAS Time Slot 10 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 10
CAS Time Slot 11 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 11
CAS Time Slot 12 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 12
CAS Time Slot 13 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 13
CAS Time Slot 14 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 14
CAS Time Slot 15 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 15
CTS8
[31:28] ros-_-_
CTS9
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
CTS10
CTS11
CTS12
CTS13
CTS14
CTS15
[3:0] ros-_-_
PRSR3. A:2068h
Port Receive Status Register 3. Default: 0x00.00.00.00
CAS Time Slot 16 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 16
CAS Time Slot 17 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 17
CAS Time Slot 18 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 18
CAS Time Slot 19 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 19
CAS Time Slot 20 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 20
CAS Time Slot 21 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 21
CAS Time Slot 22 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 22
CAS Time Slot 23 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 23
Port Receive Status Register 4. Default: 0x00.00.00.00
CTS16
CTS17
CTS18
CTS19
CTS20
CTS21
CTS22
CTS23
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
[7:4] ros-_-_
[3:0] ros-_-_
PRSR4. A:206Ch
CAS Time Slot 24 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 24
CAS Time Slot 25 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 25
CAS Time Slot 26 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 26
CAS Time Slot 27 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 27
CAS Time Slot 28 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 28
CAS Time Slot 29 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 29
146 of 194
CTS24
CTS25
CTS26
CTS27
CTS28
CTS29
[31:28] ros-_-_
[27:24] ros-_-_
[23:20] ros-_-_
[19:16] ros-_-_
[15:12] ros-_-_
[11:8] ros-_-_
19-4750; Rev 1; 07/11
DS34S132 DATA SHEET
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
CAS Time Slot 30 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 30
CAS Time Slot 31 = CAS code received at TDM Port (Pn.PRCR2.CS) for TS 31
CTS30
CTS31
[7:4] ros-_-_
[3:0] ros-_-_
10.3.15.7Port n Receive Status Register Latches (Pn.)
Table 10-36. Port n Receive Status Register Latches (Pn.)
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
PRSRL. A:2070h
Port Receive Status Register Latch. Default: 0x00.00.00.00
Reserved.
RSVD
BOSL
[31:2]
[1] rls-crw-i3
Buffer Overrun Status Latch = “1” indicates the receive TDM Port received data
faster than it could be processed (TXP payload data was lost).
Change Of Frame Alignment Status Latch = “1” indicates a change of frame or
COFASL
[0] rls-crw-i3
multi-frame timing error was detected (only valid for SFS = 1).
10.3.15.8Port n Receive Status Register Interrupt Enables (Pn.)
Table 10-37. Port n Receive Status Register Interrupt Enables (Pn.)
Pn. Field Addr (A:)
Name
Bit [x:y] Type
Description
PRSRIE. A:2078h
Port Receive Status Register Interrupt Enable. Default: 0x00.00.00.00
Reserved.
RSVD
BOIE
[31:2]
[1] rwc-_-i3
Buffer Overrun Interrupt Enable. The combination of BOIE = 1 and
PRSRL.BOSL = 1 forces G.GSR1.PS = 1.
Change Of Frame Alignment Interrupt Enable. The combination of and
COFAIE
[0] rwc-_-i3
COFAIE = 1 and PRSRL.COFASL = 1 forces G.GSR1.PS = 1.
10.3.16 Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m)
Table 10-38. Timeslot Assignment Registers (TSAn.m.; “n” = TDM Port n; “m” = Timeslot m)
TSAn.m.
Addr (A:)
Field Name Bit [x:y]
Type
Description
CR.
A1:3000h
+n*0020h
+m*0004h
Configuration Register. Default: na (SRAM unknown values after reset)
Reserved.
RSVD
TSAS
[31:17]
Timeslot Assigned Select = “1” = TDM Port “n” Timeslot “m” is assigned to the
[16] rwd-_-_
Bundle # specified by BNS (“0” = unassigned/unused).
Reserved.
RSVD
BNS
[15:8]
[7:0] rwd-_-_
Bundle Number Select = Bundle # for TDM Port “n”, Timeslot “m” (for TSAS = 1).
1
Note:
There are 1024 TSAn.m. registers (32 TDM Ports * 32 Timeslots = 1024). The TSAn.m. address = 3000h+ (n*0020h +
m*0004h) where the TDM Port “n” varies from 0 to 0x1F and the TS “m” varies from 0 to 0x1F. In binary this can
viewed as 11.00P4P3.P2P1P0T4.T3T2T1T0 where P4P3P2P1P0 = 5-bit TDM Port # (0 – 31 decimal) and T4T3T2T1T0 = 5-
bit TS # (0 – 31 decimal; T1 does not use the values 24 – 31). For an Unstructured TDM Port (SAT or HDLC) TS 0
must be assigned.
19-4750; Rev 1; 07/11
147 of 194
DS34S132 DATA SHEET
10.4 Register Guide
The Register Guide Section provides example settings for some of the more common applications, especially for
applications in which one register setting determines which settings are valid for other related registers. The S132
registers and their functional operation cannot be fully understood without also reading the Functional Description
and Register Definition sections. When those two sections are understood this section enables an S132 user to
quickly identify interactions and settings that must be made for particular applications.
Figure 10-1 provides a high level view of how the Register Guide sub-sections relate to each other. The arrows
depict the flow of RXP and TXP packet data. The boxes each represent one of the Register Guide sub-sections
and give a high level view of how the sub-sections relate to each other.
Figure 10-1. Register Guide High Level Diagram
10.4.6 SDRAM settings
10.4.5 Status Monitoring
10.4.3
Send to
CPU
Settings
Non-PW CPU packets (e.g. special Ethernet Types & error conditions)
To CPU
RXP Bundle
10.4.2 Bundle and OAM Bundle Settings
Bundle Pkts for
/
OAM
CPU
RXP
Packets
RXP Bundle
OAM Bundle
pkts for CPU
/
10.4.4 TDM
Port Settings
To/From
Ethernet
Port
RXP Bundle/
OAM Bundle
Packets
/
To/From
TDM
Ports
/
RXP SAT
CES
HDLC
/
Clock Only
Bundle pkts
SAT/CES/
HDLC/Clock-
only
TXP SAT/
CES/HDLC/
Clock Only
Bundle pkts
TXP Packets
SAT, CES, HDLC &
Clock-Only Bundles
10.4.1 Global
Packet Settings
From
CPU
CPU TXP Packets
Throughout this section example register values are presented as decimal values except when the “0x” notation is
used to identify a hex value (e.g. 0x17) or when the letter “b” follows a “1” or “0” to indicate a binary value (e.g.
“10b”). This means that a “5” when indicated for a 3-bit register field equates to “101” binary (register bits are
always programmed using binary equivalent values). Register bit numbers, paragraph text and equations are
always indicated using decimal values (e.g. for “bit 10”, the value “10” is a decimal value).
An “x” value (by itself) is used in the tables that follow to indicate “any valid value”. In many cases the only “valid
values” are listed in the “Comment” column of the table. If the “Comment column” does not provide specific values,
then “any” value is legal. Dark shading and/or “NA” are used to identify rows or cells within each table that are “Not
Applicable” to the identified application. When a Write register bit is identified in this way, the “0” value should be
written to that register unless specified otherwise. When a Read register bit is identified in this way, the returned
register bit value should be ignored.
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DS34S132 DATA SHEET
10.4.1 Global Packet Settings
Table 10-39. Global Ethernet MAC (M.) Control Register Settings (Values are in hex)
Bit #
Register Bit Name r/w Val Comments
M.NET_CONTROL
- Network Control Register
10 TX_HALT
wo
wo
rw
rw
rw
x
x
x
x
x
TXP Transmit Halt (wait to finish if packet already started)
Start TXP Transmission
9
4
3
2
START_TX
MAN_PORT_EN
TX_EN
MDIO Management Port Enable
TXP Transmit Enable (immediate)
Receive Enable (immediate)
RX_EN
NET_CONFIG
25 EN_FRMS_HDUP
- Network Configuration Register
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0
0
4
1
1
0
0
x
0
x
x
?
0
x
1
1
Reserved
22:21 DATBUS_WIDTH
20:18 MDC_CLK_DIV
17 FCS_REMOVE
Reserved
Reserved
Reserved
16 LGTH_FRM_DIS
15:14 RX_BUF_OFFSET
13 PAUSE_EN
Discard Frames with Length Field Errors
Reserved
Receive Pause Enable
10 GIG_MODE_EN
Select MAC Interface type: 0 = MII I/F (10/100 Mbps); 1 = GMII I/F (1 Gbps)
9
8
5
4
3
2
1
0
EXT_AMATCHEN
RX_1536FRMS
NO_BROADCAST
COPY_FRMS
Reserved
Maximum Receive Frame Size: 0 = 1518 bytes; 1 = 1536 bytes
Discard Ethernet Broadcast Frames
Forward all valid Ethernet Frames (disregard filter settings)
Reserved
JUMBO_FRMS
DISC_NONVLAN
FULL_DUPLEX
SPEED
Discard frames that do not include VLAN tags
Enable Full Duplex
Reserved
PHY_MAN
31 PHY_SET3
- Phy Maintenance Register
rw
rw
rw
rw
rw
rw
rw
0
1
x
x
x
2
x
Reserved
30 PHY_CL22
Reserved
29:28 PHY_SET2
MDIO Operation: 2 = Read; 1 = Write.
27:23 PHY_ADDR
22:18 PHY_REG_ADDR
17:16 PHY_SET1
MDIO Phy Address
MDIO Register Address (register address in Phy that is selected by PHY_ADDR)
Reserved
15:0 PHY_DATA_WR
“Write data sent to PHY” or “Read data from PHY” according to the selected PHY_SET2 operation
Notes: “s” = Status; “x” = any valid value; r = Read; w = Write; “wo” = “Write Only”; “Val” = “Value”.
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DS34S132 DATA SHEET
Table 10-40. Global Ethernet Packet Classification (PC.) Settings
Register
Functional Description
Comments
Ethernet
CR17 - CR19
CR1.DBTP
CR1.DBCP
CR1.DPS9
CR3.VITPID
CR3.VOTPID
CR1.DPS2
Ethernet DA1 and DA2
The S132 can recognize up to 2 programmed Ethernet DAs.
Broadcast TDMoP Pkt Discard
Broadcast CPU Pkt Discard
Unknown Ethernet DA Discard
VLAN Inner Tag Protocol ID
VLAN Outer Tag Protocol ID
TDMoP packets with the Broadcast DA: continue processing (0) or discard(1)
Non-TDMoP packets with the Broadcast DA: continue processing (0) or discard(1)
Packets with DA ≠ DA1, DA2 or Broadcast DA: send to CPU (0) or discard (1)
Packets with 1 or 2 VLAN Tags must use this TPID in the Inner Tag position.
Packets with 2 VLAN Tags must use this TPID in the Outer Tag position.
Packets with unknown Ethernet Type: send to CPU (0) or discard (1)
Unknown Ethernet Type
Discard
IPv4 & IPv6
CR1.RXPIVS &
CR1.RXPDSD
IP Version
Select “Only IPv4” (0x1), “Only IPv6” (0x3) or “both IPv4 and IPv6” (0x0)
CR6 - CR8
CR9 – CR16
CR1.DPS1
CR1.DPS4
CR1.DICPE
IPv4 Destination Address 1 - 3
IPv6 Destination Address 1 - 2
Unknown IP DA Discard
The S132 can recognize up to 3 CPU configured IPv4 DAs.
The S132 can recognize up to 2 CPU configured IPv6 DAs.
Send to CPU (0) or Discard (1).
Unknown IP Protocol Discard
Bad IPv4 Checksum
Packets with unknown IP Protocol: send to CPU (0) or discard (1)
Ignore Bad Checksum and Forward pkt (0) or Discard pkt (1).
All PW Protocols (MEF-8, MPLS, IP/UDP and IP/L2TPv3)
CR1.DPS6
CR1.DPS7
Unknown PW-ID Discard
OAM Discard
PW packets with unknown PW-ID: send to CPU (0) or discard (1)
Send to CPU (0) or Discard (1) MEF OAM, In-band VCCV and OAM BIDs
MEF-8
CR4.MET
CR4.MOET
MEF Ether Type
Identify pkt with this Ether Type as a MEF-8 TDMoP pkt. Default = 0x88D8.
Identify pkt with this Ether Type as a MEF-8 OAM (CPU) pkt.
MEF OAM Ether Type
MPLS
CR1.DPS10
>2 MPLS Outer Label Discard
Send to CPU (0) or Discard (1).
UDP1
CR1.UBIDLS
UDP BID Global Location
Select
0 = Test UDP pkt for 16-bit BID based on UBIDLCE setting and test UDP pkt for
16-bit OAM BID in either UDP Source or Destination Port location
1 = Test UDP pkt for 16-bit BID/OAM BID match in UDP Destination Port
2 = Test UDP pkt for 16-bit BID/OAM BID match in UDP Source Port
3 = Test UDP pkt for 32-bit BID/OAM BID match in Source and Dest. Port
CR1.UBIDLCE
UDP BID per-Bundle Location
Select (only for UBIDLS=0)
0 = Auto detect = Test UDP pkt for 16-bit BID match in UDP Source or Dest. Port
1 = Test UDP pkt for 16-bit BID in UDP Port selected by B.BCDR4.RXUBIDLS
CR20.UBIDM
CR1.UPVCE
UDP BID Mask
UDP BID/OAM BID bit Mask (0 = ignore bit; 1 = test bit; 0xFFFF = test all bits)
0 = Ignore UDP Protocol Type
UDP Protocol Check En
(valid for UBIDLS ≠ 3)
1 = Process UDP pkt with BID but UDP Protocol ≠ UPVC1/2 according to DPS5
0 = Send to CPU, UDP pkt with BID but UDP Protocol ≠ UPVC1/2
1 = Discard UDP pkt with BID match but UDP Protocol ≠ UPVC1/2
For UDP pkt with a checksum error: Ignore checksum (0) or Discard packet (1).
UDP Protocol Type values for when UPVCE is enabled (default 0x085E).
CR1.DPS5
Unknown UDP Protocol Type
Discard (valid for UPVCE = 1)
CR1.DUCPE
UDP Checksum Error
CR2.UPVC1 &
CR2.UPVC2
UDP Protocol Type 1 - 2
L2TPv3 ( there are no specialized Global L2TPv3 settings)
ARP
CR1.DPS3
CR1.DPS0
ARP with Known IP DA
Send to CPU (0) or Discard (1) ARP packets with known IPv4 DA.
Send to CPU (0) or Discard (1) ARP packets with unknown IPv4 DA.
ARP with Unknown IP DA
CPU Destination Ethernet Type
CR20.CDET
MEF OAM Ether Type
CPU Dest. Ether Type Discard
Identify pkt with this Ether Type as CPU Destination Ethernet Type.
CR1.DPS8
Send to CPU (0) or Discard (1) packets with CPU Destination Ethernet Type
1
Note:
The interactions between the various UDP settings are further described in Table 10-41.
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DS34S132 DATA SHEET
Table 10-41. Valid UDP BID Location and UDP Protocol Type Settings
UDP BID Location Test
Mode
BID Test Settings
PC.CR1 PC.CR1 B.BCDR4.
UBIDLS UBIDLCE RXUBIDLS
Protocol Test Settings
UDP Protocol Type Test Location
PC.CR1.
UPVCE
PC.CR1.
DPS5
0
1
0
0
0/1
0
UDP Protocol is Ignored
1
All Bundles:
0
0
0
1
0
0
For BID & OAM BID: 16-bit auto-discover2
A
“16-bit auto discover”
UDP Protocol is Ignored
Per-Bundle setting:
“16-bit Source Port” 1
For BID: 16-bit Destination Port
For OAM BID: auto-discover2
1
0
1
0/1
0
B
UDP Protocol is Ignored
Per-Bundle setting:
0
1
1
0
1
0
“16-bit Destination Port” 1
For BID: 16-bit Source Port
For OAM BID: auto-discover2
0/1
0
1
0
UDP Protocol is Ignored
All Bundles:
C
D
“16-bit Destination Port”
0/1
For BID & OAM BID: 16-bit Source Port
0
1
0
0
0/1
0
UDP Protocol is Ignored
All Bundles:
2
3
0
0
0
0
“16-bit Source Port”
For BID & OAM BID: 16-bit Destination Port
UDP Protocol is Ignored
E
All Bundles: “32-bit”
1
Notes:
The BID test location for the Per-Bundle tests are programmed per Bundle using B.BCDR4.RXUBIDLS.
The BID is auto discovered and the UPVC1/UPVC2 test is performed on the “other” UDP Port position.
2
10.4.2 Bundle and OAM Bundle Settings
Table 10-42. Bundle and OAM Bundle Control Registers (B.)
Register
Bits
Functional Description
Comments
Bundle Reset Control
BRCR1
BRCR2
BRSR
SNS
Sequence Number Seed
Bundle # to be Reset
RESET Bundle: To Reset an RXP Bundle payload data path, first select the
Bundle reset direction (“RXP only”, “TXP only”, “RXP and TXP” or “none”) using
RXBRE and TXBRE (1 = reset; 0 = release = no reset). When the Bundle number
(0-255) is written to RXTXBS, the Bundle will be reset. The Reset Status can be
monitored using RXBRS and TXBRS. This function is not used with OAM Bundles.
RXTXBS
RXBRE
TXBRE
RXBRS
TXBRS
RXP Bundle Reset Enable
TXP Bundle Reset Enable
RXP Bundle Reset Status
TXP Bundle Reset Status
Release Bundle: To Release a TXP Bundle payload data path from Reset, first
select the direction using RXBRE and TXBRE (0 = release; 1 = reset = do not
release). When the Bundle # is written to RXTXBS and Sequence Seed to SNS,
the Bundle is ready with a new Sequence Seed value waiting to be activated. A
Bundle’s Status Registers are not enabled until the Bundle is released from Reset.
Bundle Activation Control
BACR
OBS
WE
RE
OAM Bundle Select
Write Enable
Assign Bundle ID (PWID): To Assign a Bundle ID to a Bundle, first program the
Bundle ID using BIDV. Then use OBS = 0 and BS to select the Bundle Number (0
– 255). The BIDV value will be written to that Bundle Number when the WE
transitions from “0 to 1”.
Read Enable
BS
Bundle Number
Activate Bundle
Bundle ID
Bundle Activate State: To Activate or De-activate a Bundle ID, first program the
Activate state using ABE. Then use OBS = 0 and BIDV to select the Bundle
Number (0 – 255). The Activate state will be written to that Bundle Number when
WE transitions from “0 to 1”. All Bundles must be released from Reset after a
Power up/Reset before they can be Activated.
BADR1
BADR2
ABE
BIDV
Bundle Configuration Control
BCCR
WE
RE
BS
Write Enable
Configure Bundle Attributes: To configure the attributes of a Bundle, first
program all of the attributes in B.BCDR1 through B.BCDR5. Then use BS to
specify the Bundle Number (0-255). The new set of attributes will be written to that
Bundle when WE transitions from “0 to 1”. The BCDR1 – BCDR5 settings are
described in Bundle Configuration tables (that follow) according to the application.
Read Enable
Bundle Number
Misc Bundle Functions
BCDR1-5
In the Bundle Configuration tables that follow (for B.BCDR1 through B.BCDR5): “x” = “any valid value”; for the
column titles, “M” = “MPLS”, “U” = “UDP”, “L” = “L2TPv3”, “E” = “MEF”. Values not identified in the Comment
column are invalid. Values included in “[ ]” brackets means “recommended value”, but other values in the comment
column are possible. The “RT” column indicates whether the configuration register is used in the “RXP only”, “TXP
only” or “RXP and TXP” directions.
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DS34S132 DATA SHEET
10.4.2.1 SAT Bundle Settings
Table 10-43. SAT Bundle Settings
Reg-bit Bit Name
RT
M
U
L
E
Bit Name Description
Comments
BCDR1
23 LBCAI
22:21 PMT
20:10 PMS
R
x
x
x
x
L Bit Conditioning Auto Insert
Payload Machine Type
1 = Discard payload if “L-bit = 1”; 0 = disable
3 = SAT/CES Payload Machine Type
RT
RT
3
x
3
x
3
x
3
x
RXP & TXP Payload
Monitored Size in bytes
For T1, PCT = 1 ms: PMS = 0x0C1 (193 bytes decimal)
For E1, PCT = 1 ms: PMS = 0x100 (256 bytes decimal)
For 256 Kb/s, PCT = 1 ms: PMS = 0x020 (32 bytes decimal)
9
8
7
6
5
4
3
SCSCFPD
SCSNRE
R
R
[0]
[1]
0
[0]
[1]
0
[0]
[1]
0
[0]
[1]
0
SAT/CES Sanity Check
1 = Discard if rcvd pkt ≠ PMS; 0 = do not test against PMS
SAT/CES Seq # Reorder En
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Condition En
CES T1 TXP Framing
0 = Disable Reordering; 1 = Enable Reordering
SCRXBCSS
NA
NA
R
NA
SCTXBCSS
0
0
0
0
NA
RSNS
[0]
x
[0]
x
[0]
x
[0]
x
0 = Control Word Sequence #; 1 = RTP Sequence #
0 = normal; 1 = use TXP Conditioning data
NA
SCTXCE
SCTXDFSE
T
NA
T
0
0
0
0
2:0 SCTXCOS
BCDR2
31:0 ATSS1
BCDR3
x
x
x
x
SAT/CES TXP Cond. Octet
Select 1 of 8 TXP Conditioning Octets
RT
1
1
1
1
Active Timeslot Select
0x0000.0001
4:3 TXPMS
2:1 TXBTS
T
T
T
x
0
x
x
0
x
x
0
x
x
0
x
TXP Packet Mode Select
TXP Bundle Type
0 = Disable; 1 = Xmt with payload; 2 = Xmt without payload
0 = SAT for Unstructured TDM Port
0
TXBPS
TXP Bundle Priority
0=low priority (normal); 1=high (for PW Timing Connections)
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
1
0
0
x
x
1
1
0
0
x
1
2
0
x
x
1
3
0
0
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
1 = Control Word is required
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
0 = SAT for Unstructured TDM Port
RXP Label/Cookie Select
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
x
[1]
[0]
x
0
[0]
x
0
[0]
x
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = disable last value insert; 1 = insert last value if pkt lost
Selects 1 of 8 Conditioning Octets for the transmit TDM Port
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard (timing still available for ck recov)
Select TDM Port #0 - #31
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
11:9 RXCOS
R
8
RXOICWE
R
[1]
x
[0]
x
[1]
x
[1]
x
7:6 RXBDS
5:1 PNS1
R
RT
R
x
x
x
x
0
PCRE
x
x
x
x
0 = do not use for Ck Recovery; 1 = use for Ck Recovery
BCDR5
24:10 PDVT
R
R
x
x
x
x
x
x
x
x
PDV Tolerance
(see Table 10-44)
(see Table 10-44)
9:0 MJBS
Max Jitter Buffer Size
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
Table 10-44. PMS/PDVT/MJBS for SAT with various PCT, PDV and BFD values
Example Applications
PMS
PDVT
Settings
MJBS
Settings
Line
Rate
Jitter Buffer
Discard Method
Given Parameters
Tot PDV
Settings
JB Fill
Level
JB Fill
Level
PCT
BFD
Decimal
Hex
Decimal
483
483
1
Hex
1E3
1E3
1
Decimal
17
Hex
11
“No Discard”
1 ms
6 ms
5 ms
10 ms
20 ms
5 ms
125 us
125 us
125 us
125 us
193
1,158
3,860
256
C1
486
F14
100
10 ms
10 ms
NA
11 ms
16 ms
40 ms
11 ms
T1
E1
Limited Overrun
Limited Underrun
“No Discard”
25
19
20 ms
1 ms
61
3D
16
10 ms
640
280
22
Limited Overrun
Limited Underrun
“No Discard”
6 ms
20 ms
1 ms
10 ms
20 ms
5 ms
125 us
125 us
125 us
125 us
125 us
1,536
5,120
8
600
1400
8
10 ms
NA
640
1
280
1
16 ms
40 ms
11 ms
16 ms
40 ms
32
80
1
20
50
1
10 ms
10 ms
NA
20
20
1
14
14
1
64
Kb/s
48
30
1
1
“Limited Overrun”
“Limited Underrun”
6 ms
10 ms
20 ms
20 ms
160
A0
3
3
19-4750; Rev 1; 07/11
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DS34S132 DATA SHEET
10.4.2.2 CES without CAS Bundle Settings
Table 10-45. CES without CAS Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
R
x
x
x
x
L Bit Conditioning Auto Insert
Payload Machine Type
1 = Discard payload if “L-bit = 1”; 0 = disable
3 = SAT/CES Payload Machine Type
RT
RT
3
x
3
x
3
x
3
x
Payload Monitored Size
# of Frames of data in TXP & RXP pkt payload.
For PCT = 1 ms: PMS = 0x008 (8 frames)
For PCT = 8 ms: PMS = 0x040 (64 frames)
9
8
7
6
5
4
3
SCSCFPD
R
R
[0]
[1]
0
[0]
[1]
0
[0]
[1]
0
[0]
[1]
0
SAT/CES Sanity Check
1 = Discard if rcvd pkt ≠ PMS; 0 = do not test against PMS
SCSNRE
SCRXBCSS
SCTXBCSS
SAT/CES Seq # Reorder En
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Conditioning
CES T1 TXP Framing
0 = Disable Reordering; 1 = Enable Reordering
NA
NA
R
NA
0
0
0
0
NA
RSNS
[0]
x
[0]
x
[0]
x
[0]
x
0 = Control Word Sequence #; 1 = RTP Sequence #
0 = normal; 1 = use TXP Conditioning data
NA
SCTXCE
SCTXDFSE
T
NA
T
0
0
0
0
2:0 SCTXCOS
BCDR2
31:0 ATSS1
BCDR3
x
x
x
x
SAT/CES TXP Cond. Octet
Select 1 of 8 TXP Conditioning Octets
RT
T
x
x
x
x
x
x
x
x
Active Timeslot Select
1b = included in Bundle (T1: TS #0 - 23; E1: TS #1 - 31)
4:3 TXPMS
TXP Packet Mode Select
0 = Disable; 1 = Transmit with payload; 2 = Transmit without
payload (for TDM Port faults)
2:1 TXBTS
T
T
1
x
1
x
1
x
1
x
TXP Bundle Type
1 = CES without CAS for Structured T1/E1 Port
0
TXBPS
TXP Bundle Priority
0=low priority (normal); 1=high (for PW Timing Connections)
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
1
0
1
x
x
1
1
1
0
x
1
2
1
x
x
1
3
1
0
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
1 = Control Word is required
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
1 = CES without CAS for Structured T1/E1 Port
RXP Label/Cookie Select
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
x
[1]
[0]
x
0
[0]
x
0
[0]
x
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = insert last value if pkt lost; 1 = disable last value insert
Selects 1 of 8 Conditioning Octets for the transmit TDM Port
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard (timing still available for ck recov)
Select TDM Port #0 - #31
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
11:9 RXCOS
R
8
RXOICWE
R
[1]
x
[0]
x
[1]
x
[1]
x
7:6 RXBDS
5:1 PNS1
R
RT
R
x
x
x
x
0
PCRE
x
x
x
x
0 = do not use for Ck Recovery; 1 = use for Ck Recovery
BCDR5
24:10 PDVT
R
R
x
x
x
x
x
x
x
x
Packet Delay Variation Time
Max Jitter Buffer Size
(see Table 10-46 for examples)
(see Table 10-46 for examples)
9:0 MJBS
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
Table 10-46. PMS/PDVT/MJBS for T1/E1 CES without CAS for various PCT, PDV and BFD values
Example Applications
Jitter Buffer Given Timing Parameters
PMS
PDVT
Settings
MJBS
Settings
Line
Rate
Settings
JB Fill
Level
10 ms
10 ms
NA
JB Fill
Level
Discard Method
PCT
1 ms
6 ms
20 ms
Tot PDV
5 ms
BFD
Decimal
Hex
Decimal
Hex
14
14
1
Decimal
22
Hex
16
8
48
8
30
A0
80
80
1
11 ms
16 ms
40 ms
“No Discard”
125 us
125 us
125 us
T1
or
E1
32
20
“Limited Overrun”
“Limited Underrun”
10 ms
20 ms
160
80
50
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DS34S132 DATA SHEET
10.4.2.3 CES with CAS Bundle Settings
Table 10-47. CES with CAS Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
R
x
x
x
x
L Bit Conditioning Auto Insert
Payload Machine Type
1 = Discard payload if “L-bit = 1”; 0 = disable
3 = SAT/CES Payload Machine Type
RT
RT
3
x
3
x
3
x
3
x
Payload Monitored Size
# of Frames of data in TXP & RXP Packet Payload.
For PCT = 1 ms: PMS = 0x008 (8 frames)
For PCT = 8 ms: PMS = 0x040 (64 frames)
9
8
7
6
5
4
3
SCSCFPD
R
R
R
T
R
T
T
T
[0]
[1]
x
[0]
[1]
x
[0]
[1]
x
[0]
[1]
x
SAT/CES Sanity Check
1 = Discard if rcvd pkt ≠ PMS; 0 = do not test against PMS
0 = Disable Reordering; 1 = Enable Reordering
0 = Use CAS from RXP Pkt; 1 = use Xmt SW CAS
0 = Use CAS from Rcv T1/E1 Port; 1 = use TXP SW CAS
0 = Control Word Sequence #; 1 = RTP Sequence #
0 = normal; 1 = use TXP Conditioning data
SCSNRE
SCRXBCSS
SCTXBCSS
SAT/CES Seq # Reorder En
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Conditioning
CES T1 TXP Framing
x
x
x
x
RSNS
[0]
x
[0]
x
[0]
x
[0]
x
SCTXCE
SCTXDFSE
x
x
x
x
0 = SF Framing; 1 = ESF Framing (for E1 this is NA)
Select 1 of 8 TXP Conditioning Octets
2:0 SCTXCOS
BCDR2
31:0 ATSS1
BCDR3
x
x
x
x
SAT/CES TXP Cond. Octet
RT
T
x
x
x
x
x
x
x
x
Active Timeslot Select
1b= included in Bundle (T1:TS #0-23; E1:TS #1-15 & 17-31)
4:3 TXPMS
TXP Packet Mode Select
0 = Disable; 1 = Transmit with payload; 2 = Transmit without
payload (for TDM Port faults)
2:1 TXBTS
T
T
2
x
2
x
2
x
2
x
TXP Bundle Type
2 = CES with CAS for Structured T1/E1 Port
0
TXBPS
TXP Bundle Priority
0=low priority (normal); 1=high (for PW Timing Connections)
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
1
0
2
x
x
1
1
2
0
x
1
2
2
x
x
1
3
2
0
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
1 = Control Word is required
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
2 = CES with CAS for Structured T1/E1 Port
RXP Label/Cookie Select
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
x
[1]
[0]
x
0
[0]
x
0
[0]
x
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = insert last value if pkt lost; 1 = disable last value insert
Selects 1 of 8 Conditioning Octets for the transmit TDM Port
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard (timing still available for ck recov)
Select TDM Port #0 - #31
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
11:9 RXCOS
R
8
RXOICWE
R
[1]
x
[0]
x
[1]
x
[1]
x
7:6 RXBDS
5:1 PNS1
R
RT
R
x
x
x
x
0
PCRE
x
x
x
x
0 = do not use for Ck Recovery; 1 = use for Ck Recovery
BCDR5
24:10 PDVT
R
R
x
x
x
x
x
x
x
x
Packet Delay Variation Time
Max Jitter Buffer Size
(see Table 10-48 for examples)
(see Table 10-48 for examples)
9:0 MJBS
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
Table 10-48. PMS/PDVT/MJBS for T1/E1 CES with CAS for various PCT, PDV and BFD values
Example Applications
Jitter Buffer Given Timing Parameters
PMS
PDVT
Settings
MJBS
Settings
Line
Rate
Settings
JB Fill
Level
10 ms
10 ms
NA
JB Fill
Level
Discard Method
PCT
1 ms
6 ms
20 ms
Tot PDV
5 ms
BFD
Decimal
Hex
Decimal
Hex
14
14
1
Decimal
22
Hex
16
8
48
8
30
A0
80
80
1
11 ms
16 ms
40 ms
“No Discard”
125 us
125 us
125 us
T1
or
E1
“Limited Overrun”
“Limited Underrun”
10 ms
20 ms
32
20
160
80
50
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DS34S132 DATA SHEET
10.4.2.4 Unstructured HDLC Bundle (any Line Rate) Settings
Table 10-49. Unstructured HDLC Bundle (any Line Rate) Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
RT
R
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Payload Max Size
NA
0
x
0
x
0
x
0
x
0 = HDLC Payload Machine Type
Maximum # of bytes in RXP Packet Payload (not incl. FCS)
9
8
SCSCFPD
NA
RT
RT
RT
NA
T
0
0
0
0
SAT/CES Sanity Check
HDLC Bit Reorder Enable
HDLC FCS Disable
NA
SCSNRE
SCRXBCSS
SCTXBCSS
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
0 = transmit MS bit first; 1 = transmit LS bit first
0 = FCS enabled; 1 = FCS disabled
0 = 16-bit; 1 = 32-bit
7
6
HDLC RXP FCS bit Width
Reorder Seq Number Select
HDLC frame Seq # Mode
5
RSNS
NA
SCTXCE/
SCTXDFSE
4:3
x
x
x
x
0 = Seq Num always 0;
3 = Wrap around skipping “0”
1 = Wrap around using “0”
2:0 SCTXCOS
BCDR2
31:0 ATSS1
BCDR3
RT
RT
0
1
0
1
0
1
0
1
HDLC Channel Width Select
Active Timeslot Select
0 = Nx8-bit (Nx64 Kb/s)
0x0000.0001
4:3 TXPMS
2:1 TXBTS
T
T
x
0
0
x
0
0
x
0
0
x
0
0
TXP Packet Mode Select
TXP Bundle TDM Port Mode
TXP Bundle Priority
0 = Disable TXP Bundle; 1 = Enable TXP HDLC Bundle
0 = HDLC for Unstructured TDM Port
NA
0
TXBPS
NA
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
[1]
0
x
[1]
1
x
[1]
2
x
[1]
3
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
0 = Control Word is not included; 1 = CW is required
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
0 = HDLC for Unstructured TDM Port
RXP Control Word Enable
RXP Header Type Select
RXP Bundle TDM Port Mode
RXP Label/Cookie Select
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
0
0
0
0
x
0
x
0
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
0
[1]
[0]
0
0
[0]
0
0
[0]
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = 0x7E Inter-frame Fill; 1 = 0xFF Inter-frame Fill
NA
HDLC Inter-frame Fill
11:9 RXCOS
NA
R
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
8
RXOICWE
[1]
x
[0]
x
[1]
x
[1]
x
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard packet
Select TDM Port #0 - #31
7:6 RXBDS
5:1 PNS1
R
R
x
x
x
x
0
PCRE
R
0
0
0
0
0 = do not use for Ck Recov
BCDR5
24:10 PDVT
NA
R
0
0
0
0
Packet Delay Variation Time
NA
NA
9:0 MJBS
NA NA NA NA Max Jitter Buffer Size
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
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DS34S132 DATA SHEET
10.4.2.5 Structured Nx64 Kb/s HDLC Bundle Settings
Table 10-50. Structured Nx64 Kb/s HDLC Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
RT
R
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Payload Max Size
NA
0
x
0
x
0
x
0
x
0 = HDLC Payload Machine Type
Maximum # of bytes in RXP Packet Payload (not incl. FCS)
9
8
SCSCFPD
NA
RT
RT
RT
NA
T
0
0
0
0
SAT/CES Sanity Check
HDLC Bit Reorder Enable
HDLC FCS Disable
NA
SCSNRE
SCRXBCSS
SCTXBCSS
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
0 = transmit MS bit first; 1 = transmit LS bit first
0 = FCS enabled; 1 = FCS disabled
0 = 16-bit; 1 = 32-bit
7
6
HDLC RXP FCS bit Width
Reorder Seq Number Select
HDLC frame Seq # Mode
5
RSNS
NA
SCTXCE/
SCTXDFSE
4:3
x
x
x
x
0 = Seq Num always 0;
3 = Wrap around skipping “0”
1 = Wrap around using “0”
2:0 SCTXCOS
BCDR2
31:0 ATSS1
BCDR3
RT
RT
0
x
0
x
0
x
0
x
HDLC Channel Width Select
Active Timeslot Select
0 = Nx8-bit (Nx64 Kb/s)
1b = included in Bundle (T1: TS #0 - 23; E1: TS #1 - 31)
4:3 TXPMS
2:1 TXBTS
T
T
x
1
0
x
1
0
x
1
0
x
1
0
TXP Packet Mode Select
TXP Bundle TDM Port Mode
TXP Bundle Priority
0 = Disable TXP Bundle; 1 = Enable TXP HDLC Bundle
1 = HDLC for Structured T1/E1 Port
NA
0
TXBPS
NA
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
[1]
0
x
[1]
1
x
[1]
2
x
[1]
3
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
0 = Control Word is not included; 1 = CW is required
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
1 = HDLC for Structured T1/E1 Port
RXP Control Word Enable
RXP Header Type Select
RXP Bundle TDM Port Mode
RXP Label/Cookie Select
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
1
1
1
1
x
0
x
0
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
0
[1]
[0]
0
0
[0]
0
0
[0]
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = 0x7E Inter-frame Fill; 1 = 0xFF Inter-frame Fill
NA
HDLC Inter-frame Fill
11:9 RXCOS
NA
R
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
8
RXOICWE
[1]
x
[0]
x
[1]
x
[1]
x
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard packet
Select TDM Port #0 - #31
7:6 RXBDS
5:1 PNS1
R
R
x
x
x
x
0
PCRE
R
0
0
0
0
0 = do not use for Ck Recov
BCDR5
24:10 PDVT
NA
R
0
0
0
0
Packet Delay Variation Time
NA
NA
9:0 MJBS
NA NA NA NA Max Jitter Buffer Size
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
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DS34S132 DATA SHEET
10.4.2.6 Structured 16 Kb/s or 56 Kb/s HDLC Bundle Settings
Table 10-51. Structured 16 Kb/s or 56 Kb/s HDLC Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
RT
R
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Payload Max Size
NA
0
x
0
x
0
x
0
x
0 = HDLC Payload Machine Type
Maximum # of bytes in RXP Packet Payload (not incl. FCS)
9
8
SCSCFPD
NA
RT
RT
RT
NA
T
0
0
0
0
SAT/CES Sanity Check
HDLC Bit Reorder Enable
HDLC FCS Disable
NA
SCSNRE
SCRXBCSS
SCTXBCSS
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
[0]
[1]
[1]
0
0 = transmit MS bit first; 1 = transmit LS bit first
0 = FCS enabled; 1 = FCS disabled
0 = 16-bit; 1 = 32-bit
7
6
HDLC RXP FCS bit Width
Reorder Seq Number Select
HDLC frame Seq # Mode
5
RSNS
NA
SCTXCE/
SCTXDFSE
4:3
x
x
x
x
0 = Seq Num always 0;
3 = Wrap around skipping “0”
1 = Wrap around using “0”
2:0 SCTXCOS
RT
x
x
x
x
HDLC Channel Width Select
1 = 7-bit + 1 unused bit (56 Kb/s);
2 = 2-bit coding in 2 LSbit position + 6 unused bits (16 Kb/s)
3 = 2-bit coding in 2 MSbit position + 6 unused bits (16 Kb/s)
BCDR2
31:0 ATSS1
BCDR3
RT
x
x
x
x
Active Timeslot Select
1b = included in Bundle (T1: TS #0 - 23; E1: TS #1 - 31)
4:3 TXPMS
2:1 TXBTS
T
T
x
1
0
x
1
0
x
1
0
x
1
0
TXP Packet Mode Select
TXP Bundle TDM Port Mode
TXP Bundle Priority
0 = Disable TXP Bundle; 1 = Enable TXP HDLC Bundle
1 = HDLC for Structured T1/E1 Port
NA
0
TXBPS
NA
BCDR4
21 RXRE
20 RXCWE
R
R
R
R
R
x
[1]
0
x
[1]
1
x
[1]
2
x
[1]
3
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
0 = Control Word is not included; 1 = CW is required
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
1 = HDLC for Structured T1/E1 Port
RXP Control Word Enable
RXP Header Type Select
RXP Bundle TDM Port Mode
RXP Label/Cookie Select
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
1
1
1
1
x
0
x
0
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
R
0
[0]
0
[1]
[0]
0
0
[0]
0
0
[0]
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
0 = 0x7E Inter-frame Fill; 1 = 0xFF Inter-frame Fill
NA
HDLC Inter-frame Fill
11:9 RXCOS
NA
R
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
8
RXOICWE
[1]
x
[0]
x
[1]
x
[1]
x
0 = ignore CW OAM indication; 1 = look for OAM indication
0 = TDM Port; 3 = Discard packet
Select TDM Port #0 - #31
7:6 RXBDS
5:1 PNS1
R
R
x
x
x
x
0
PCRE
R
0
0
0
0
0 = do not use for Ck Recov
BCDR5
24:10 PDVT
NA
R
0
0
0
0
Packet Delay Variation Time
NA
NA
9:0 MJBS
NA NA NA NA Max Jitter Buffer Size
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
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DS34S132 DATA SHEET
10.4.2.7 Clock Only Bundle Settings
10.4.2.7.1 Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings
Table 10-52. Combined RXP and TXP (Bidirectional) Clock Only Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
RT
RT
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Ck Only Packet Rate
NA
3
x
3
x
3
x
3
x
3 = SAT/CES Payload Machine Type
SAT Packet rate (# TDM Port bytes per pkt)
For T1, PCT = 1 ms: PMS = 0x0C1 (193 bytes decimal)
For E1, PCT = 1 ms: PMS = 0x100 (256 bytes decimal)
For 256 Kb/s, PCT = 1 ms: PMS = 0x020 (32 bytes dec.)
CES Packet rate (# TDM Port frames per pkt)
For PCT = 1 ms: PMS = 0x008 (8 frames)
For PCT = 8 ms: PMS = 0x040 (64 frames)
9
8
7
6
5
4
3
SCSCFPD
R
0
[1]
0
0
[1]
0
0
[1]
0
0
[1]
0
Sanity Check
0 = do not discard based on PMS setting
SCSNRE
SCRXBCSS
SCTXBCSS
R
Seq # Reorder En
0 = Disable Reordering; 1 = Enable Reordering
NA
NA
R
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Condition En
CES T1 TXP Framing
NA
0
0
0
0
NA
RSNS
[0]
0
[0]
0
[0]
0
[0]
0
0 = Control Word Sequence #; 1 = RTP Sequence #
SCTXCE
SCTXDFSE
NA
NA
NA
NA
NA
NA
0
0
0
0
2:0 SCTXCOS
BCDR2
31:0 ATSS1
0
0
0
0
SAT/CES TXP Cond. Octet
RT
x
x
x
x
Active Timeslot Select
SAT: 0x0000.0001
CES with out CAS: 1 = enable TS (T1: 0-23; E1: 1-31)
CES with CAS: 1 = enable TS (T1: 0-23; E1: 1-15 & 17-31)
BCDR3
1 = HDLC for Structured T1/E1 Port
4:3 TXPMS
2:1 TXBTS
T
T
x
x
x
x
x
x
x
x
TXP Packet Mode Select
RXP Bundle Type
0 = Disable; 2 = Transmit without payload (Clock Only)
0 = SAT for Unstructured TDM Port
1 = CES without CAS for Structured T1/E1 Port
0 = low priority; 1 = high (for PW Timing Connections)
0
TXBPS
T
[1]
[1]
[1]
[1]
TXP Bundle Priority
BCDR4
21 RXRE
20 RXCWE
19:18 RXHTS
17:16 RXBTS
R
R
R
R
x
1
0
x
x
1
1
x
x
1
2
x
x
1
3
x
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
1 = Control Word is required
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
0 = SAT for Unstructured TDM Port
1 = CES without CAS for Structured T1/E1 Port
15:14 RXLCS
R
x
0
x
0
RXP Label/Cookie Select
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
NA
NA
R
0
0
[1]
0
0
0
0
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
NA
11:9 RXCOS
0
0
0
0
NA
8
RXOICWE
[1]
3
[0]
3
[1]
3
[1]
3
0 = ignore CW OAM indication; 1 = look for OAM indication
3 = Discard (timing information is still available for ck recov)
Select TDM Port #0 - #31
7:6 RXBDS
5:1 PNS1
R
RT
R
x
x
x
x
0
PCRE
1
1
1
1
1 = use for Ck Recovery
BCDR5
24:10 PDVT
NA
NA
0
0
0
0
0
0
0
0
Packet Delay Variation Time
Max Jitter Buffer Size
NA
NA
9:0 MJBS
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
The Datapath for an RXP Clock Only Bundle should not be released from Reset (B.BRCR2.RXBRE = 1). The Clock
Only Bundle does not include payload data. Holding the Bundle’s Datapath in Reset prevents the S132 from
attempting to process the packet after the packet header has been fully interpreted.
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DS34S132 DATA SHEET
10.4.2.7.2 RXP (Unidirectional) Clock Only Bundle Settings
Table 10-53. RXP (Unidirectional) Clock Only Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
R
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Ck Only Packet Rate
NA
3
x
3
x
3
x
3
x
3 = SAT/CES Payload Machine Type
R
SAT Packet rate (# TDM Port bytes per pkt)
For T1, PCT = 1 ms: PMS = 0x0C1 (193 bytes decimal)
For E1, PCT = 1 ms: PMS = 0x100 (256 bytes decimal)
For 256 Kb/s, PCT = 1 ms: PMS = 0x020 (32 bytes dec.)
CES Packet rate (# TDM Port frames per pkt)
For PCT = 1 ms: PMS = 0x008 (8 frames)
For PCT = 8 ms: PMS = 0x040 (64 frames)
9
8
7
6
5
4
3
SCSCFPD
R
0
[1]
0
0
[1]
0
0
[1]
0
0
[1]
0
Sanity Check
0 = do not discard based on PMS setting
SCSNRE
SCRXBCSS
SCTXBCSS
R
Seq # Reorder En
0 = Disable Reordering; 1 = Enable Reordering
NA
NA
R
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Condition En
CES T1 TXP Framing
NA
0
0
0
0
NA
RSNS
[0]
0
[0]
0
[0]
0
[0]
0
0 = Control Word Sequence #; 1 = RTP Sequence #
SCTXCE
SCTXDFSE
NA
NA
NA
NA
NA
NA
0
0
0
0
2:0 SCTXCOS
BCDR2
31:0 ATSS1
0
0
0
0
SAT/CES TXP Cond. Octet
R
x
x
x
x
Active Timeslot Select
SAT: 0x0000.0001
CES with out CAS: 1 = enable TS (T1: 0-23; E1: 1-31)
CES with CAS: 1 = enable TS (T1: 0-23; E1: 1-15 & 17-31)
BCDR3
4:3 TXPMS
2:1 TXBTS
NA
NA
NA
0
0
0
0
0
0
0
0
0
0
0
0
TXP Packet Mode Select
RXP Bundle Type
NA
NA
NA
0
TXBPS
TXP Bundle Priority
BCDR4
21 RXRE
20 RXCWE
19:18 RXHTS
17:16 RXBTS
R
R
R
R
x
1
0
x
x
1
1
x
x
1
2
x
x
1
3
x
RXP RTP Enable
0 = RTP is not included; 1 = RTP is required
1 = Control Word is required
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
0 = SAT for Unstructured TDM Port
1 = CES without CAS for Structured T1/E1 Port
15:14 RXLCS
R
x
0
x
0
RXP Label/Cookie Select
MPLS: 0x1 = 1 Label; 0x2 = 2 Labels; 0x3 = 3 Labels
L2TPV3: 0x0 = 0 Cookies; 0x1 = 1 Cookie; 0x2 = 2 Cookies
13 RXUBIDLS
12 SCLVI
R
NA
NA
R
0
0
[1]
0
0
0
0
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
NA
11:9 RXCOS
0
0
0
0
NA
8
RXOICWE
[1]
3
[0]
3
[1]
3
[1]
3
0 = ignore CW OAM indication; 1 = look for OAM indication
3 = Discard (timing still available for ck recov)
Select TDM Port #0 - #31
7:6 RXBDS
5:1 PNS1
R
R
x
x
x
x
0
PCRE
R
1
1
1
1
1 = use for Ck Recovery
BCDR5
24:10 PDVT
NA
NA
0
0
0
0
0
0
0
0
Packet Delay Variation Time
Max Jitter Buffer Size
NA
NA
9:0 MJBS
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
The Datapath for an RXP Clock Only Bundle should not be released from Reset (B.BRCR2.RXBRE = 1). The Clock
Only Bundle does not include payload data. Holding the Bundle’s Datapath in Reset prevents the S132 from
attempting to process the packet after the packet header has been fully interpreted.
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DS34S132 DATA SHEET
10.4.2.7.3 TXP (Unidirectional) Clock Only Bundle Settings
Table 10-54. TXP (Unidirectional) Clock Only Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
23 LBCAI
22:21 PMT
20:10 PMS
NA
T
0
0
0
0
L Bit Conditioning Auto Insert
Payload Machine Type
Ck Only Packet Rate
NA
3
x
3
x
3
x
3
x
3 = SAT/CES Payload Machine Type
T
SAT Packet rate (# TDM Port bytes per pkt)
For T1, PCT = 1 ms: PMS = 0x0C1 (193 bytes decimal)
For E1, PCT = 1 ms: PMS = 0x100 (256 bytes decimal)
For 256 Kb/s, PCT = 1 ms: PMS = 0x020 (32 bytes dec.)
CES Packet rate (# TDM Port frames per pkt)
For PCT = 1 ms: PMS = 0x008 (8 frames)
For PCT = 8 ms: PMS = 0x040 (64 frames)
9
8
7
6
5
4
3
SCSCFPD
NA
NA
NA
NA
NA
NA
NA
NA
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Sanity Check
NA
NA
NA
NA
NA
NA
NA
NA
SCSNRE
SCRXBCSS
SCTXBCSS
Seq # Reorder En
CES RXP CAS Source Select
CES TXP CAS Source Select
Reorder Seq Number Select
SAT/CES TXP Condition En
CES T1 TXP Framing
RSNS
SCTXCE
SCTXDFSE
2:0 SCTXCOS
BCDR2
31:0 ATSS1
SAT/CES TXP Cond. Octet
T
x
x
x
x
Active Timeslot Select
SAT: 0x0000.0001
CES with out CAS: 1 = enable TS (T1: 0-23; E1: 1-31)
CES with CAS: 1 = enable TS (T1: 0-23; E1: 1-15 & 17-31)
BCDR3
4:3 TXPMS
2:1 TXBTS
T
T
x
x
x
x
x
x
x
x
TXP Packet Mode Select
RXP Bundle Type
0 = Disable; 2 = Transmit without payload (Clock Only)
0 = SAT for Unstructured TDM Port
1 = CES without CAS for Structured T1/E1 Port
0 = low priority; 1 = high (for PW Timing Connections)
0
TXBPS
T
[1]
[1]
[1]
[1]
TXP Bundle Priority
BCDR4
21 RXRE
20 RXCWE
NA
NA
NA
NA
NA
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
x
RXP RTP Enable
NA
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
NA
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
NA
NA
RXP Label/Cookie Select
RXP UDP BID Location
SAT/CES Last Value Insert
Xmt (RXP) Conditioning Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
NA
13 RXUBIDLS NA
NA
12 SCLVI
NA
NA
NA
NA
T
NA
11:9 RXCOS
NA
8
RXOICWE
NA
7:6 RXBDS
5:1 PNS1
NA
Select TDM Port #0 - #31
NA
0
PCRE
NA
0
0
0
0
BCDR5
24:10 PDVT
NA
NA
0
0
0
0
0
0
0
0
Packet Delay Variation Time
Max Jitter Buffer Size
NA
NA
9:0 MJBS
1
Note:
TSAn.m must be programmed to enable the port and timeslots selected by PNS (n = PNS) and ATSS (m = Timeslot).
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DS34S132 DATA SHEET
10.4.2.8 “CPU RXP PW Debug” Bundle Settings
The minimum Bundle settings that must be configured to properly detect packets for CPU Debug RXP PW Bundles
are provided in Table 10-55. In the table, “NR” indicates “Not Required”. An “NR” value can be set according to the
“normal” CES, SAT, HDLC or Clock Only Bundle setting but is not required by a CPU Debug RXP PW Bundle.
Table 10-55. “CPU RXP PW Debug” Bundle Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
31:0
-
NR
NR
NR
NR
NR
NR
BCDR2
31:0
-
NR
[0]
NR
[0]
NR
[0]
NR
[0]
BCDR3
4:3 TXPMS
T
TXP Packet Mode Select
0 = Disable; 1 = Transmit with payload; 2 = Transmit
without payload (for TDM Port faults)
2:1 TXBTS
-
-
NR
NR
NR
NR
NR
NR
NR
NR
RXP Bundle Type
TXP Bundle Priority
NR
NR
0
TXBPS
BCDR4
21 RXRE
20 RXCWE
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
13 RXUBIDLS
12 SCLVI
-
-
NR
NR
0
NR
NR
1
NR
NR
2
NR
NR
3
RXP RTP Enable
NR
RXP Control Word Enable
RXP Header Type Select
RXP Bundle Type
NR
R
-
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
NR
NR
NR
NR
NR
NR
x
NR
NR
[1]
NR
NR
NR
NR
NR
NR
x
NR
NR
NR
NR
NR
NR
x
NR
-
RXP Label/Cookie Select
RXP UDP BID Location
SAT/CES Last Value Insert
Xmt (RXP) Condition Octet
RXP OAM in CW Enable
RXP Bundle Data Destination
TDM Port Number Select
TDM Port Ck Recov. Enable
NR
R
-
0 = UDP Source Port; 1 = UDP Destination Port
NR
NR
NR
x
NR
11:9 RXCOS
-
NR
8
RXOICWE
-
NR
7:6 RXBDS
5:1 PNS
R
-
1 = forward to CPU; 3 = discard
NR
NR
NR
NR
NR
NR
NR
NR
NR
NR
0
BCDR5
31:0
PCRE
-
-
NR
NR
NR
NR
NR
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DS34S132 DATA SHEET
10.4.2.9 In-band VCCV OAM Connection Settings
When In-band VCCV OAM is used it is always part of a CES, SAT, HDLC or Clock Only Bundle. The In-band
VCCV connection can be to be enabled before all of the Bundle function/settings are known/programmed for the
CES, SAT, HDLC, Clock Only Bundle. The minimum Bundle settings that must be configured to properly detect In-
band VCCV are provided in Table 10-56. In the table, “NR” indicates “Not Required”. An “NR” value can be set
according to the “normal” CES, SAT, HDLC or Clock Only Bundle setting but is not required by an In-band VCCV
Connection.
Table 10-56. In-band VCCV OAM Connection Settings
Reg-bit Bit Abbrev RT
BCDR1
M
U
L
E
Bit Name Description
Comments
31:0
-
-
-
NR NR NR NR
NR NR NR NR
NR NR NR NR
NR
NR
NR
BCDR2
31:0
BCDR3
31:0
BCDR4
21 RXRE
-
R
R
-
NR NR NR NR RXP RTP Enable
NR
20 RXCWE
19:18 RXHTS
17:16 RXBTS
15:14 RXLCS
13 RXUBIDLS
12 SCLVI
1
0
1
1
1
2
1
3
RXP Control Word Enable
RXP Header Type Select
1 = Control Word is required
0 = MPLS; 1 = UDP; 2 = L2TPv3; 3 = MEF
NR NR NR NR RXP Bundle Type
NR
-
NR NR NR NR RXP Label/Cookie Select
NR
R
-
0
[1]
0
0
RXP UDP BID Location
0 = UDP Source Port; 1 = UDP Destination Port
NR NR NR NR SAT/CES Last Value Insert
NR NR NR NR Xmt (RXP) Conditioning Octet
NR
11:9 RXCOS
-
NR
8
RXOICWE
R
R
-
1
x
[0]
x
1
x
1
x
RXP OAM in CW Enable
1 = look for OAM indication
7:6 RXBDS
5:1 PNS
RXP Bundle Data Destination
0 = TDM Port; 3 = Discard packet
NR NR NR NR TDM Port Number Select
NR NR NR NR TDM Port Ck Recov. Enable
NR
NR
0
BCDR5
31:0
PCRE
-
-
NR NR NR NR
NR
The B.BCDR4.RXCWE setting is ignored if PC.CR1.DPS7 = 1 (discard all In-band VCCV packets).
10.4.2.10OAM Bundle (Out-band VCCV OAM) Settings
OAM Bundles only include programmable settings for the OAM BID and for the Activate state of the OAM Bundle.
OAM Bundles do not included the other register/functions that are provided for the “normal” Bundles (described in
the previous sections).
Table 10-57. OAM Bundle PWID and Activation Control Registers (B.)
Register
Bits
OBS
WE
RE
Functional Description
OAM Bundle Select
Write Enable
Comments
BACR
Assign Bundle ID (PWID): To assign an OAM Bundle ID to an OAM Bundle, first
program the OAM Bundle ID using BIDV. Then use OBS = 1 and BS to select the
OAM Bundle Number (0 to 31). The BIDV value for that OAM Bundle will be
Written when the WE transitions from “0 to 1”.
Read Enable
Bundle Activate State: To Activate or De-activate an OAM Bundle, first program
the Activate state using ABE. Then use OBS = 1 and BS to select the OAM
Bundle Number (0 to 31). The Activate state for that OAM Bundle will be Written
when WE transitions from “0 to 1”.
BS
Bundle Number
Activate Bundle
Bundle ID
BADR1
BADR2
ABE
BIDV
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DS34S132 DATA SHEET
10.4.3 Send to CPU Settings
There are several RXP packet conditions that can be used to forward packets to the CPU that have been described
in previous Register Guide sections. Table 10-58 provides a Quick Reference list for each of these “send to CPU”
conditions using an abbreviated detected condition description.
Table 10-58. “Send to CPU” Quick Reference Settings
Send to CPU Type
Detected RX Packet Condition
“Send to CPU” Program Settings
CPU Debug RXP PW Bundle
In-band VCCV OAM
PW-ID = Activated BID
B.BCDR4.RXBDS = 1
B.BCDR4.RXIOCWE=1 & PC.CR1.DPS7 = 0
PC.CR4.MOET & PC.CR1.DPS7 = 0
PC.CR1.DPS10 = 0
PW-ID = Activated BID
MEF OAM
Ethernet Type = PC.CR4.MOET
# MPLS outer labels > 2
Too many MPLS Labels
Unknown Ethernet DA
CPU Destination Ethernet Type
OAM Bundle (Out-band VCCV)
Unknown PW-ID
Ethernet DA ≠ PC.CR17 – PC.CR19
Ethernet Type = PC.CR20.CDET
PW-ID = Activated OAM BID
PW-ID ≠ PC.CR6 – PC.CR16
Unknown UDP Protocol Type
IP Protocol ≠ UDP or L2TPv3
ARP IP DA = PC.CR6 – PC.CR8
PC.CR1.DPS9 = 0
PC.CR1.DPS8=0
PC.CR1.DPS7 = 0
PC.CR1.DPS6 = 0
Unknown UDP Protocol
Unknown IP Protocol
ARP with known IP DA
Unknown Ether Type
PC.CR1.DPS5 = 0
PC.CR1.DPS4 = 0
PC.CR1.DPS3 = 0
Ethernet Type ≠ ARP, IPv4, IPv6, Multicast MPLS, Unicast
PC.CR1.DPS2 = 0
MPLS, PC.CR20.CDET, PC.CR4.MET or PC.CR4.MOET
Unknown IP DA
IP DA ≠ PC.CR6 – PC.CR16
PC.CR1.DPS1 = 0
PC.CR1.DPS0 = 0
ARP w/ unknown IP DA
ARP IP DA ≠ PC.CR6 – PC.CR8
10.4.4 TDM Port Settings
Table 10-59. Global TDM Port Settings
Register
Functional Description
Comments
G.ECCR1 - G.ECCR2
G.TCCR1 - G.TCCR2
TXP TDM Conditioning Octets A – H
RXP TDM Conditioning Octets A –H
Data transmitted in TXP TDM Bundle (in place of received TDM port data).
Data transmitted at TDM Port (in place of RXP TDM Bundle data).
The tables that follow provide most of the settings for T1/E1 and slower TDM Port applications. When a TDM Port
uses a Clock Recovery Engine there are some Clock Recovery Engine Registers that must be set that are not
identified in this section (e.g. selection between Adaptive Clock Recovery and Differential Clock Recovery). These
are defined by the S132 DSP Firmware load.
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DS34S132 DATA SHEET
Table 10-60. TDM Port “n” Register Settings for T1 Applications (Pn.; n = 0 to 31)
Reg-bit Bit Name
RT SAT
CES no CES w/ Bit Name Description
Comments
CAS
CAS
TXSCn.CR1 - CR4
31:0
RXSCn.CR1 - CR4
T
0
0
0
0
x
x
CTS0-CTS23
TXP SW CAS (TS 0 – 23)
SW CAS transmitted in TXP TDM Bundle.
31:0
PTCR1.
31
R
CTS0-CTS23
Xmt (RXP) SW CAS (TS0-23) SW CAS transmitted at TDM Port.
DR
R
R
R
R
R
R
R
R
x
x
x
1
Data path Reset
0 = Normal; 1 = Hold all data path registers in reset value
28
SFS
FFS
MFS
BFD
BPF
DP
0
1
Structure Format Select
Frame Format
Unstructured (0) or Structured (1)
27
0
1
1
1 = T1
26:25
24:23
22:18
17
0
[3]
0
[3]
x
CAS Multi-frame Format
# Frame(Block) per Buffer
0 = no CAS or multi-frame; 2 = T1 SF; 3 = T1 ESF
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
0x17 (24 bytes; 0x00 = 1 byte/frame; BPF ≤ PMS)
Low priority (0) or High priority (1)
[3]
[0x17]
x
[0x17]
x
[0x17] Bytes per Frame(Block)
x
x
Decap Priority
16
DOSOT
0
0
Disable CAS on TDAT
Overwrite CAS on TDAT (0) or do not overwrite TDAT (1)
PTCR2.
9
PRPTLL
TIOE
TCE
RT
R
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Port Rcv to Xmt Line Loopbk 0 = loopback disabled (normal); 1 = loopback enabled
Transmit Input/Output Enable 0 = TDAT/TSYNC/TSIG disabled (high Z); 1 = enabled
8
7
R
Transmit Clock Enable
Transmit Framing Source
TSYNC Direction Select
0 = TCLKO disabled (high Z); 1 = enabled
Synchronize transmit timing to RSYNC (0) or TSYNC (1)
Input (0) or output (1).
6
TSRS
TDS
R
5
R
4
TOES
TIES
R
Transmit Output Edge Select 0 = positive edge; 1 = negative edge
3
R
Transmit Input Edge Select
TCLKO Source Select
0 = positive edge; 1 = negative edge
2:0
TSS
R
0 = RCLK; 1 = aclk; 2 = grclk; 4 = EXTCLK0; 5 = EXTCLK1
PTCR3.
31:0
PRCR1.
31
PRPTTSL
RT
0
x
x
Port Rcv to Xmt TS Loopback 0 = loopback disabled (normal); 1 = enabled (1 bit per TS)
DR
T
T
T
T
T
T
T
T
T
T
T
T
T
x
x
x
1
Data path Reset
0 = Normal; 1 = Hold all data path registers in reset value
Unstructured (0) or Structured (1)
28
SFS
FFS
MFS
BFD
BPF
EP
0
1
Structure Format Select
Frame Format
27
0
1
1
1 = T1
26:25
24:23
22:18
17
0
0
x
CAS Multi-frame Format
# Frame(Block) per Buffer
0 = no CAS multi-frame; 2 = T1 SF; 3 = T1 ESF
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
0x17 (24 bytes; 0x00 = 1 byte/frame; BPF ≤ PMS)
Low priority (0) or High priority (1)
[3]
[3]
[3]
[0x17]
[0x17]
[0x17] Bytes per Frame(Block)
x
x
0
0
0
x
x
0
x
x
x
x
x
x
0
Encap Priority
CAS Source
C-bit Value
D-bit Value
L-bit Value
16
CS
0
RDAT (0) or RSIG (1)
15
CBVSE
DBVSE
LB
0
CAS C-bit value (T1 ESF only)
14
0
CAS D-bit value (T1 ESF only)
13
x
x
L-bit Value for all TXP Bundles associated with Port “n“
12
LBSS
SPL
L-bit Source (all Pn Bundles) TXP Bundle L-bit source: LB (0); TXP Bundle Descriptor (1)
11:1
PRCR2.
6
[0x17]
SAT Packet Payload Length
SPL = B.BCDR1.PMS ≥ BPF (T1: 0x17)
RSTS
RDS
RIES
RSS
T
T
0
0
x
x
x
x
x
x
x
x
x
x
Receive Framing Source
RSYNC Direction Select
RCLK Edge Select
0 = RSYNC input; 1 = synchronize to Transmit Port timing
Input (0) or output (1).
5
3
T
Positive edge (0) or negative edge (1)
0
T
Receive clock Source Select RCLK (0) or TCLKO (1)
PRCR3.
31:0
PRCR4.
16
T
PTPRTSL
RT
0
x
x
Port Xmt to Rcv TS Loopback 0 = loopback disabled (normal); 1 = enabled (1 bit per TS)
TSGMS
TSGMC
T
T
x
x
x
x
x
x
TXP Timestamp Gen Mode
0=Differential (CMNCLK); 1=Absolute (RSS selects Rcv ck)
15:0
PRCR5.
28:16
12:0
TXP Timestamp Gen M Coeff M = INT(637009920000 / CMNCLK)
TSGN1C
TSGN0C
T
T
x
x
x
x
x
x
TXP T-stamp Gen N1 Coeff
TXP T-stamp Gen N0 Coeff
N1 = 79626240 + (M * CMNCLK / 8000)
N0 = N1 + (CMNCLK / 8000)
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DS34S132 DATA SHEET
Table 10-61. TDM Port “n” Register Settings for E1 Applications (Pn.; n = 0 to 31)
Reg-bit Bit Name
RT SAT
CES no CES w/ Bit Name Description
Comments
CAS
CAS
TXSCn.CR1 - CR4
31:0
RXSCn.CR1 - CR4
T
0
0
0
0
x
x
CTS0-CTS23
TXP SW CAS (TS 0 – 31)
SW CAS transmitted in TXP TDM Bundle.
31:0
R
CTS0-CTS23
Xmt (RXP) SW CAS (TS0-23) SW CAS transmitted at TDM Port.
PTCR1.
31 DR
R
R
R
R
R
R
R
R
x
0
x
1
x
1
Data path Reset
0 = Normal; 1 = Hold all data path registers in reset value
28 SFS
27 FFS
Structure Format Select
Frame Format
Unstructured (0) or Structured (1)
0
0
0
0 = E1
26:25 MFS
24:23 BFD
22:18 BPF
17 DP
0
0
x
CAS Multi-frame Format
# Frame(Block) per Buffer
0 = no CAS multi-frame; 1 = E1
[3]
[3]
[3]
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
0x1F (32 bytes; 0x00 = 1 byte/frame; BPF ≤ PMS)
Low priority (0) or High priority (1)
[0x1F] [0x1F]
[0x1F] Bytes per Frame(Block)
x
x
x
x
Decap Priority
16 DOSOT
PTCR2.
0
0
Disable CAS on TDAT
Overwrite CAS on TDAT (0) or do not overwrite TDAT (1)
9
8
7
6
5
4
3
PRPTLL
TIOE
TCE
RT
R
x
x
x
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Port Rcv to Xmt Line Loopbk 0 = loopback disabled (normal); 1 = loopback enabled
Transmit Input/Output Enable 0 = TDAT/TSYNC/TSIG disabled (high Z); 1 = enabled
R
Transmit Clock Enable
Transmit Framing Source
TSYNC Direction Select
0 = TCLKO disabled (high Z); 1 = enabled
Synchronize transmit timing to RSYNC (0) or TSYNC (1)
Input (0) or output (1).
TSRS
TDS
R
R
TOES
TIES
R
Transmit Output Edge Select 0 = positive edge; 1 = negative edge
R
Transmit Input Edge Select
TCLKO Source Select
0 = positive edge; 1 = negative edge
2:0 TSS
PTCR3.
31:0 PRPTTSL
PRCR1.
R
0 = RCLK; 1 = aclk; 2 = grclk; 4 = EXTCLK0; 5 = EXTCLK1
RT
0
x
x
Port Rcv to Xmt TS Loopback 0 = loopback disabled (normal); 1 = enabled (1 bit per TS)
31 DR
28 SFS
T
T
x
0
x
1
x
1
Data path Reset
0 = Normal; 1 = Hold all data path registers in reset value
Unstructured (0) or Structured (1)
0 = E1
Structure Format Select
Frame Format
27 FFS
T
0
0
0
26:25 MFS
24:23 BFD
22:18 BPF
17 EP
T
0
0
x
CAS Multi-frame Format
# Frame(Block) per Buffer
0 = no CAS multi-frame; 1 = E1
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
0x1F (32 bytes; 0x00 = 1 byte/frame; BPF ≤ PMS)
Low priority (0) or High priority (1)
RDAT (0) or RSIG (1)
T
[3]
[3]
[3]
T
[0x1F] [0x1F]
[0x1F] Bytes per Frame(Block)
T
x
x
0
0
0
x
x
0
x
x
0
0
x
x
0
Encap Priority
CAS Source
C-bit Value
D-bit Value
L-bit Value
16 CS
T
0
15 CBVSE
14 DBVSE
13 LB
NA
NA
T
0
NA
0
NA
x
x
L-bit Value for all TXP Bundles associated with Port “n“
12 LBSS
11:1 SPL
T
L-bit Source (all Pn Bundles) TXP Bundle L-bit source: LB (0); TXP Bundle Descriptor (1)
T
[0x1F]
SAT Packet Payload Length
SPL = B.BCDR1.PMS ≥ BPF (E1: 0x1F)
PRCR2.
6
RSTS
RDS
RIES
RSS
T
T
0
0
x
x
x
x
x
x
x
x
x
x
Receive Framing Source
RSYNC Direction Select
RCLK Edge Select
0 = RSYNC input; 1 = synchronize to Transmit Port timing
Input (0) or output (1).
5
3
0
T
Positive edge (0) or negative edge (1)
T
Receive clock Source Select RCLK (0) or TCLKO (1)
PRCR3.
31:0 PTPRTSL
PRCR4.
T
RT
0
x
x
Port Xmt to Rcv TS Loopback 0 = loopback disabled (normal); 1 = enabled (1 bit per TS)
16 TSGMS
T
T
x
x
x
x
x
x
TXP Timestamp Gen Mode
0=Differential (CMNCLK); 1=Absolute (RSS select Rcv ck)
15:0 TSGMC
TXP Timestamp Gen M Coeff M = INT(637009920000 / CMNCLK)
PRCR5.
28:16 TSGN1C
T
T
x
x
x
x
x
x
TXP T-stamp Gen N1 Coeff
TXP T-stamp Gen N0 Coeff
N1 = 79626240 + (M * CMNCLK / 8000)
N0 = N1 + (CMNCLK / 8000)
12:0 TSGN0C
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DS34S132 DATA SHEET
Table 10-62. TDM Port “n” Register Settings for non-T1/E1 Applications (Pn.; n = 0 to 31)
Reg-bit Bit Name
PTCR1.
RT SAT
Bit Name Description
Comments
31 DR
R
R
R
R
R
R
R
R
x
0
Data path Reset
0 = Normal; 1 = Hold all data path registers in reset value
28 SFS
Structure Format Select
Frame Format
Unstructured = 0
27 FFS
0
NA
26:25 MFS
24:23 BFD
22:18 BPF
17 DP
0
CAS Multi-frame Format
# Frame(Block) per Buffer
Bytes per Frame(Block)
Decap Priority
NA
[3]
x
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
# bytes per Frame(Block) “pseudo frame period” (0x00 = 1 byte; BPF ≤ PMS)
Low priority (0) or High priority (1)
x
16 DOSOT
PTCR2.
0
Disable CAS on TDAT
NA
9
8
7
6
5
4
3
PRPTLL
TIOE
TCE
RT
R
x
x
x
0
0
x
x
x
Port Rcv to Xmt Line Loopbk 0 = loopback disabled (normal); 1 = loopback enabled
Transmit Input/Output Enable 0 = TDAT/TSYNC/TSIG disabled (high Z); 1 = enabled
R
Transmit Clock Enable
Transmit Framing Source
TSYNC Direction Select
0 = TCLKO disabled (high Z); 1 = enabled
TSRS
TDS
R
NA
NA
R
TOES
TIES
R
Transmit Output Edge Select 0 = positive edge; 1 = negative edge
R
Transmit Input Edge Select
TCLKO Source Select
0 = positive edge; 1 = negative edge
2:0 TSS
PTCR3.
31:0 PRPTTSL
PRCR1.
R
0 = RCLK; 1 = aclk; 2 = grclk; 4 = EXTCLK0; 5 = EXTCLK1
RT
0
Port Rcv to Xmt TS Loopback NA
31 DR
28 SFS
T
T
T
T
T
T
T
T
T
T
T
T
T
x
0
0
0
[3]
x
Data path Reset
Structure Format Select
Frame Format
0 = Normal; 1 = Hold all data path registers in reset value
Unstructured (0) or Structured (1)
27 FFS
NA
26:25 MFS
24:23 BFD
22:18 BPF
17 EP
CAS Multi-frame Format
# Frame(Block) per Buffer
Bytes per Frame(Block)
Encap Priority
NA
0 = disable port rcv; 1 = 1 block; 2 = 2 blocks; 3 = 4 blocks
# bytes per Frame(Block) “pseudo frame period” (0x00 = 1 byte; BPF ≤ PMS)
x
Low priority (0) or High priority (1)
16 CS
0
0
0
x
CAS Source
NA
15 CBVSE
14 DBVSE
13 LB
C-bit Value
NA
D-bit Value
NA
L-bit Value
L-bit Value for TXP Bundle
12 LBSS
11:1 SPL
x
L-bit Source
TXP Bundle L-bit source: LB (0); TXP Bundle Descriptor (1)
Payload length in bytes where SPL = B.BCDR1.PMS ≥ BPF.
x
SAT Packet Payload Length
PRCR2.
6
RSTS
RDS
RIES
RSS
T
T
T
T
0
0
x
x
Receive Framing Source
RSYNC Direction Select
RCLK Edge Select
NA
5
3
0
NA
Positive edge (0) or negative edge (1)
RCLK (0) or TCLKO (1)
RCLK Source Select
PRCR3.
31:0 PTPRTSL
PRCR4.
RT
0
Port Xmt to Rcv TS Loopback NA
16 TSGMS
T
T
x
x
TXP Timestamp Gen Mode
0= Differential (CMNCLK); 1= Absolute (RSS selected RCLK)
15:0 TSGMC
TXP Timestamp Gen M Coeff M = INT(637009920000 / CMNCLK)
PRCR5.
28:16 TSGN1C
12:0 TSGN0C
T
T
x
x
TXP T-stamp Gen N1 Coeff
TXP T-stamp Gen N0 Coeff
N1 = - FCMN x ((2^12 x FOUT/FCMN) - M)
N0 = FCMN + N1
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DS34S132 DATA SHEET
10.4.5 Status Monitoring
10.4.5.1 Ethernet Port Monitoring
Table 10-63. Ethernet MAC Status Registers (M.)
Bit # Register Bit Name
r/w Default Comments
- Network Control Register
NET_CONTROL
14 RD_SNAP
rw
wo
wo
0
0
0
Read Snapshot – 1 = Read latched register; 0 = Read current (real-time/raw) statistics
Take Snapshot – “0 to 1” = store current statistics values in latched registers
Clear Statistics Register - When set, clears the statistics registers.
13 TAKE_SNAP
5
STATS_CLR
NET_STATUS
- Network Status Register
2
1
PHY_MAN_IDLE
MDIOS
ro
ro
-
-
PHY Management Idle - The PHY management logic is idle (i.e. has completed).
MDIO Status - Returns status of the MDIO signal
IRQ_STATUS
- Interrupt Status Register
ro PHY Management Operation Done status. Cleared on read.
- Interrupt Enable Register
wo Enable PHY Management Operation Done Interrupt
- Interrupt Disable Register
wo Disable PHY Management Done interrupt
- Interrupt Mask Register
ro Mask PHY Management Complete - 0 = Interrupt is enabled (1 = disabled).
0
IRQ_MAN_DONE
-
IRQ_ENABLE
0
EN_IRQ_MAN_DONE
0
IRQ_DISABLE
0
DIS_IRQ_MAN_DONE
0
IRQ_MASK
0
MSK_IRQ_MAN_DONE
0
Table 10-64. Ethernet RMON Count Registers (M.; all are Read Only)
Register Name
Bits Bit Name
Description
OCT_TX_BOT
31:0 TX_OCTETS_FRM
15:0 TX_OCTETS_FRM
31:0 FRMS_TX
Transmitted Octets in Frame without errors [31:0].
Transmitted Octets in Frame without errors [47:32].
Frames transmitted without error.
OCT_TX_TOP
STATS_FRAMES_TX
BROADCAST_TX
MULTICAST_TX
STATS_PAUSE_TX
FRAME64_TX
31:0 BRDCST_TX
31:0 MLTCST_TX
15:0 PAUSE_TX
Broadcast Frames Transmitted without error.
Multicast Frames Transmitted without error.
Pause Frames Transmitted
31:0 64B_TX
64 Byte Frames Transmitted without error.
FRAME65_TX
31:0 65TO127B_TX
31:0 128TO255B_TX
31:0 256TO511B_TX
31:0 512TO1023B_TX
31:0 1024TO1518B_TX
31:0 1519B_OR_MORE
31:0 OCT_RX_BOT
15:0 OCT_RX_TOP
31:0 FRMS_RX
65 to 127 Byte Frames Transmitted without error.
128 to 255 Byte Frames Transmitted without error.
256 to 511 Byte Frames Transmitted without error.
512 to 1023 Byte Frames Transmitted without error.
1024 to 1518 Byte Frames Transmitted without error.
1519 Bytes or More Frames Transmitted without error.
Octets (bottom) received without errors and passed filter [31:0]
Octets (top) received without errors and passed filter [47:32]
Frames Received without error and passed filter.
Broadcast Frames Received without errors and passed filter.
Multicast Frames Received without errors and passed filter.
Pause Frames Received
FRAME128_TX
FRAME256_TX
FRAME512_TX
FRAME1024_TX
FRAME1519_TX
OCT_RX_BOT
OCT_RX_TOP
STATS_FRAMES_RX
BROADCAST_RX
MULTICAST_RX
STATS_PAUSE_RX
FRAME64_RX
31:0 BRDCST_RX
31:0 MLTCST_RX
15:0 PAUSE_RX
31:0 64B_RX
64 Byte Frames Received without errors and passed filter.
65 to 127 Byte Frames Rcvd without errors and passed filter.
128 to 255 Byte Frames Rcvd without errors and passed filter.
256 to 511 Byte Frames Rcvd without errors and passed filter.
512 to 1023 Byte Frames Rcvd without errors and passed filter.
1024 to 1518 Byte Frames Rcvd without errors and passed filter.
FRAME65_RX
31:0 65TO127B_RX
31:0 128TO255B_RX
31:0 256TO511B_RX
31:0 512TO1023B_RX
31:0 1024TO1518B_RX
FRAME128_RX
FRAME256_RX
FRAME512_RX
FRAME1024_RX
FRAME1519_RX
STATS_USIZE_FRAMES
STATS_EXCESS_LEN
STATS_JABBERS
STATS_FCS_ERRORS
STATS_LENGTH_ERRORS
STATS_RX_SYM_ERR
STATS_ALIGN_ERRORS
31:0 1519B_OR_MORE_RX 1519 Bytes or More Frames Rcvd without errors and passed filter.
9:0 USIZE_RX
9:0 OSIZE_RX
9:0 JAB_RX
Frames received with < 64 bytes in length
Oversized Frames Received
Jabbers Received
9:0 FCS_ERR
10-bit count of frames discarded with Ether FCS errors.
10-bit count of frames with Length field not equal to measured length
10-bit count of frames with RX_ER = 1 during reception.
10 bit count of frames discarded with non-integral byte count.
9:0 LGTH_FRM_ERR
9:0 RX_SYM_ERR
9:0 ALIGN_ERR
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DS34S132 DATA SHEET
10.4.5.2 Global Packet Classifier Monitoring Control
Table 10-65. Global Packet Classifier Monitoring Settings (PC.)
Register
Packet Classifier Function
Description
CPCR.CPC
Good Packet Count
# received packets forwarded toward a TDM Port or CPU
PCECR.UICPEC UDP & IP Pkt FCS Error Count
# received packets with UDP & IP checksum errors (see UICECS)
CR1.UICECS
SPCR.SPC
UDP & IP FCS Error Select
Stray Packet Count
Selects whether UICPEC counts UDP, IP or “UDP and IP” checksum errors
# received packets with PW header, but unknown PWID (no BID or OAM BID match)
10.4.5.3 Global RXP Bundle Monitoring Control
Table 10-66. Global RXP Bundle Control Word Change Monitor Settings(G.)
Register
Control Word Function
SAT/CES SAT
HDLC Bundle
Clock-only
Bundle
CPU Debug
Bundle1
Bundle
Bundle
GCR.LBCDE
GCR.RBCDE
GCR.MBCDE
L-bit Change Detect Enable
R-bit Change Detect Enable
M-bit Change Detect Enable
Frag-bit Change Detect Enable
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA
NA
NA
NA
NA
NA
Yes
Yes
Yes
Yes
Yes
Yes
NA
GCR.FBCDE
1
Notes:
When an intended SAT/CES Bundle is programmed to be sent to the CPU the Control Word Change Detect bits can
be monitored for debug purposes (this is not a normal CPU Bundle function).
10.4.5.4 Global TXP Packet Queue Monitoring
Table 10-67. Global TXP Output Queue Status Registers (G.)
Status Register
Functional Description
SAT/CES
Bundle
HDLC
Bundle
Clock-only
Bundle
All CPU connection
types
TPISR1.TXHPQML
TPISR2.TXLPQML
TXP High Priority Queue Max Level1
TXP Low Priority Queue Max Level
TXP CPU Queue Max Level
Yes
Yes
NA
Yes
Yes
NA
Yes
Yes
NA
NA
NA
Yes
TPISR3.TXCQML
1
Notes:
High priority normally is only assigned to SAT/CES/Clock Only Bundles used for Clock Recovery at PW far end.
10.4.5.5 PW Bundle Monitoring
Table 10-68. TXP Bundle Status/Statistics Registers
Bundle/Port
Select
Status
Register
Status
Bits
Functional Description
SAT/CES
Bundle
HDLC
Bundles
Clock-only
Bundles
CPU Debug
Bundles
B.BESCR
Pn.
BESR1
BESR2
BESR3
PTSR1-4
PRHEFC
GPTXC
TXPSFSL
CTSx
Bad Rcv HDLC Frame Count
Good TXP Packet (Ethernet) Count
TXP Queue Overflow
NA
Yes
Yes
Yes
NA
NA
NA
NA
NA
NA
Yes
Yes
Yes
Yes
Yes
NA
TXP CAS in Time Slot x
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DS34S132 DATA SHEET
Table 10-69. RXP Bundle Status/Statistics Registers3
Bundle
Select
Register
Status Bits
Function
SAT/CES
Bundles
HDLC
Bundles
Clock-only
Bundles
CPU Debug
Bundles
B.BDSCR B.BDSR1
JBLPDSL
PDC
Jitter Buffer Late Packet Discard
RXP Pkt Discard Count1
Jitter Buffer Event Count1
Jitter Buffer Low Level
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NA
NA
NA
NA
NA
Yes
Yes
Yes
Yes
Yes
Yes
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Yes
NA
NA
NA
NA
NA
NA
Yes
Yes
Yes
NA
Yes
Yes
Yes
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
B.BDSR2
B.BDSR3
JBEC
JBLL
JBHL
Jitter Buffer High Level
Ethernet Good RXP Packet Count
Jumped/Lost Packet Count
Reorder/Out-of-Window Count
Payload Size/Sequence Error
Packet Length Error
B.BDSR4
B.BDSR5
B.BDSR6
B.BDSR7
GPRXC
SCJPC
SCRPC
SCPSESL
PLESL
SCJBEPDSL
JBCL
Early Pkt/Buffer overflow Discard
Jitter Buffer Current Level
Control Word L-bit
LBD
RBD
Control Word R-bit
DMD
Control Word M-bits
FBD
Control Word Frag-bits
Malformed Packet Count
R-bit Packet Count
B.BDSR8
B.BDSR9
SCMPC
SCRBPC
CWCDSL
JBU
-
B.GxSRL
Control Word Change
-
JB.GxSRL
Pn.PRSR1-4
Group Jitter Buffer Underrun/Playout Yes
RXP CAS in Time Slot x Yes
-
CTSx
1
2
3
Notes:
PC.CR1.PDCC and PC.CR1.JBECC select what conditions are counted by PDC and JBEC (respectively).
G.GCR.IPSE selects whether JB.GxSRL.JBU indicates Underrun or “Underrun and Start of Playout”.
The Bundle Status Registers do not function until a Bundle is released from Reset.
10.4.6 SDRAM Settings
Table 10-70. SDRAM Settings (EMI.)
Register
bits
Functional
Description
Total SDRAM Memory Size
Comments
128 Mbit
256 Mbit
512 Mbit
1024 Mbit
DCR2.TRFC
DCR2.DCL
DCR2.DCW
DCR2.DMS
DCR2.DRRS
Refresh Pulse Period
CAS Latency
0x1F
0x1F
0x1F
0x1F
TRFC * 8ns (0x1F = 248 ns)
CAS Latency = 2
2
2
2
2
2
1
2
0
Column Width
512 = 2; 1024 = 1; 2048 = 0
128= 3; 256= 2; 512= 1; 1024= 0
DRRS * 512ns (0x10 = 8.192 us)
Total External Memory
Repeat Refresh Time
3
2
1
0
0x10
0x10
0x10
0x10
Table 10-71. SDRAM Starting Address Assignments (EMI.; all SDRAM sizes)
EMI Register
Description
Contents
Block size
Start Addr (Hex)
BMCR3.PRSO
BMCR3.PTSO
BMCR1.TXPSO
BMCR1.TXHSO
BMCR2.JBSO
RXP CPU Queue
TXP CPU Queue
TXP Payload Queue
TXP Header Descriptors
Jitter Buffer
512 RXP CPU Packets
8 Mbit
000.0000
080.0000
100.0000
200.0000
210.0000
512 TXP CPU Packets
8 Mbit
256 TXP Bundle Packet Payloads
256 TXP Bundle Header Descriptors
256 RXP Bundle Jitter Buffers
16 Mbit
1 Mbit
to end of SDRAM
Table 10-72. Example Max PDV (ms) for various PCT, JBMD and # of TS Combinations
JBMD
Setting
Number of Timeslots per Bundle
PCT
(Kbytes)
32
16
12
8
4
2
1
256
451
224
110
53
812
403
198
96
1016
504
248
120
1354
672
330
160
2032
1008
496
2709
1344
661
3251
1612
793
128
0.125 ms
64
32
240
320
384
19-4750; Rev 1; 07/11
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DS34S132 DATA SHEET
256
128
64
500
248
122
59
985
489
240
116
1300
645
317
154
1912
949
467
226
3612
1792
882
6502
3226
1587
768
10837
5376
2645
1280
1 ms
5 ms
32
427
256
128
64
507
252
125
60
1010
502
247
120
1345
667
330
160
2007
997
490
237
3965
1967
970
7742
3842
1890
915
14780
7332
3607
1747
32
470
256
128
64
INVALID
INVALID
INVALID
INVALID
1015
505
250
120
1350
670
330
160
2020
1005
495
4015
1995
980
7930
3935
1940
940
15485
7685
3780
1830
10 ms
32
240
475
Note: “INVALID” means that the packet size would exceed the 2 Kbyte maximum packet size.
It is expected that a 256 Mbit DDR SDRAM will support most applications. With a 256 Mbit device and a JBMD
setting of 64 KByte, the system can support up to 110 ms of PDV on any combination of Bundle sizes (1 Timeslot
to 32 Timeslots per Bundle). The Packet Creation Time (PCT) and BFD can be set to any valid values. To minimize
the S132 process latency the BFD can be set to a 1 frame period. Larger SDRAM devices can be used to support
this same application description (e.g. if pricing or availability makes a larger device more desirable). If the
maximum PDV can be decreased, for example to 53 ms then the smaller 128 Mbit could be used.
The SDRAM size selection can be complicated because there are so many variables. One approach is to begin by
knowing the maximum PDV and the maximum number of Timeslots in a Bundle. With this information Table 10-72
indicates the minimum JBMD. The SDRAM size can then be calculated from:
DDR SDRAM size = (JBMD in Kbytes) * # Bundles + total memory for other queues (e.g. TXP CPU queue)
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DS34S132 DATA SHEET
11
JTAG INFORMATION
This device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public
instructions included are HIGHZ, CLAMP, and IDCODE. The device contains the following items, which meet the
requirements set by the IEEE 1149.1 Standard Test Access Port (TAP) and Boundary Scan Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The Test Access Port has the necessary interface pins, namely JTCLK, JTDI, JTDO, JTMS and JTRST_N. Details
about the boundary scan architecture and the TAP can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and
IEEE 1149.1b-1994.
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. The
bypass register is a 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions to provide a short
path between JTDI and JTDO. The boundary scan register contains a shift register path and a latched parallel
output for control cells and digital I/O cells. DS34S132 BSDL files are available at http://www.maxim-
ic.com/tools/bsdl/. An optional test register, the identification register, has also been included in the device design.
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. Table 11-1 shows the
identification register contents for the DS34S132 device.
Table 11-1. JTAG ID Code
REVISION
ID[31:28]
4’b0001
DEVICE CODE
ID[27:12]
MANUFACTURER’S CODE
STD
Bit[0]
1
DEVICE
ID[11:0]
0A1h
DS34S132
009Fh
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DS34S132 DATA SHEET
12
DC ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Input, Bi-directional or Open Drain
Output Lead with Respect to VSS (except VDD)
Supply Voltage (VDD33) with Respect to VSS
Supply Voltage (VDD18) with Respect to VSS
Ambient Operating Temperature Range
Junction Operating Temperature Range
Storage Temperature Range
-0.5V to +5.5V
-0.5V to +3.6V
-0.5V to +2.0V
-40°C to +85°C
-40°C to +125°C
-55°C to +125°C
See IPC/JEDEC J-STD-020A
Soldering Temperature Range
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect reliability. Ambient Operating Temperature Range is assuming the
device is mounted on a JEDEC standard test board in a convection cooled JEDEC test enclosure.
Note 1: The “typ” (typical) values listed below are not production tested.
Note 2: Production tests are done at room temperature and at TA=+85°C. All functionality and parametric values
through temperature range are guaranteed by design.
Table 12-1. Recommended DC Operating Conditions (Tj = -40°C to +85°C.)
Symbol
VIH
Notes
Min
2.40
Typ
Max
5.50
Units
V
Parameter
Input Logic 1
VIL
-0.30
+0.80
V
Input Logic 0
VRF
VIL
VIH
VDD33
VDDP
VDDQ
VDD18
AVDD
CVDD
1
1.188
-0.30
1.25
1.313
V
V
V
V
V
V
V
V
SDRAM Input Reference +/- 5%
Input Voltage DDR SDRAM Logic 0
Input Voltage DDR SDRAM Logic 1
Core Digital 3.3V Supply +/- 5%
SDRAM Core 2.5V Supply +/- 5%
SDRAM Output 2.5V Supply +/- 5%
Core Digital 1.8 V Supply +/- 5%
SDRAM 1.8 V PLL Supply +/- 5%
VRF - 0.15
VDDQ + 0.3
3.465
VRF + 0.15
3.135
2.375
2.375
1.710
1.710
1.710
3.300
2.500
2.500
1.800
1.800
1.800
2.625
2.625
1.890
1.890
1.890
V
CLAD 1.8 V PLL Supply +/- 5%
1
Notes:
The value of VRF can be selected by the user to provide optimum noise margins in the system. Typically, the value of
VRF is expected to be about 0.5 x VDDQ of the transmitting device and VRF is expected to track variations in VDDQ.
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DS34S132 DATA SHEET
Table 12-2. DC Electrical Characteristics (Tj = -40°C to +85°C.)
Parameter
Symbol Note
Min
Typ
60
100
250
5
1
1
7
Max Units
100
120
350
10
Idd33
Iddq
Idd18
Iadd
Icdd
IDDD
CIO
IIL
1
mA
mA
mA
mA
mA
mA
pF
µA
µA
µA
V
VDD33 I/O Supply Current (VDD33 = 3.465V)
VDDQ I/O + VDDP I/O Supply Current (VDD = 2.625)
VDD18 Supply Current (VDD18 = 1.89)
AVDD Supply Current ( AVDD = 1.89)
CVDD Supply Current ( CVDD = 1.89)
Power-Down Current (All DISABLE and power down bits set)
Lead Capacitance
Input Leakage
Input Leakage
Output Leakage (when Hi-Z)
Output Voltage (IOH = -8.0mA)
5
1
-10
-100
-10
+10
+10
+10
IILP
ILO
VOH
VOL
VOH
VOL
VOH
VOL
2.4
0.4
0.4
0.4
V
V
V
V
Output Voltage (IOL = +8.0mA)
Output Voltage (IOH = -16.0mA)
Output Voltage (IOL = +16.0mA)
Output Voltage DDR SDRAM (IOH = -8.0mA)
2.4
1.9
0.2
V
Output Voltage DDR SDRAM (IOL = +8.0mA)
1
Notes:
All outputs loaded with rated capacitance; all inputs between DVDD33 and DVSS; inputs with pull-ups connected to
VDD33.
13
AC TIMING CHARACTERISTICS
13.1 CPU Interface
Table 13-1. CPU Interface Timing (VDD = 3.3V ±5%, Tj = -40°C to 125°C.)
SIGNAL
SYMBOL
MIN TYP MAX UNITS NOTES
DESCRIPTION
System Clock Frequency
SYSCLK
PCS_N,
PA, PWR
PCS_N,
PA, PWR
50
85
MHz
ns
t1
t2
Setup Time to SYSCLK active edge
Hold Time from SYSCLK active edge
3.5
1,2,4
1,2,4
1
ns
t3
t4
PD[31:0]
PD[31:0]
PD[31:0]
PD[31:0]
PTA_N
Input Setup Time to SYSCLK active edge
Input Hold Time from SYSCLK active edge
Output Delay from SYSCLK active edge
Output Hold from SYSCLK active edge
Output Delay from SYSCLK active edge
Output Tristate from SYSCLK active edge
3.5
1
ns
ns
ns
ns
ns
ns
1,2,4
1,2,4
t7
6
1,2,4
t8
1
1,2,4
t9
6
6
1,2,3,4
1,2,3,4
PTA_N
t10
clock
period
t11
PCS_N
Delay between Consecutive Accesses
1
t12
t13
t15
PA
PA
Setup Time to PALE falling edge
Hold Time from PALE falling edge
Width
11
1.5
4
ns
ns
ns
PALE
Notes:
1
The input/output timing reference level for all signals is VDD/2.
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DS34S132 DATA SHEET
Figure 13-1. MPC870-like processor CPU Interface Write Cycle
SYSCLK
t1
t2
t11
PCS_N
t1
t2
PA[13:2]
PD[31:0]
PRW_N
t3
t4
t1
t2
t9
t9
t10
PTA_N
Figure 13-2. MPC870-like processor CPU Interface Read Cycle
SYSCLK
t1
t2
t11
PCS_N
t1
t2
PA[13:2]
PD[31:0]
t7
t8
t1
t2
PRW_N
PTA_N
t9
t9
t10
Figure 13-3. MPC8313-like processor CPU Interface Write Cycle
SYSCLK
t1
t2
t11
PCS_N
t15
PALE
t12
t13
t1
t3
t1
PA[13:2]
PD[15:0]
PRW_N
t4
t2
t9
t9
t10
PTA_N
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DS34S132 DATA SHEET
Figure 13-4. MPC8313-like processor CPU Interface Read Cycle
SYSCLK
t1
t2
t11
PCS_N
t15
PALE
t12
t13
t1
PA[13:2]
PD[15:0]
t7
t8
t1
t2
PRW_N
t9
t9
t10
PTA_N
13.2 TDM Interface
Table 13-2. TDM Ports
PARAMETER
TCLKO Output Period
SYMBOL
MIN
TYP
648
488
MAX
UNITS
ns
ns
NOTES
t1
t1
t2
1
2
3
4
3
4
8
2
0
ns
TSYNC, RSYNC, RDAT, RSIG input setup
to TCLKO
TSYNC, RSYNC, RDAT, RSIG input hold
from TCLKO
TCLKO to TDAT, TSIG output hold
TCLKO to TDAT, TSIG output valid
TCLKO to TSYNC output valid
TCLKO to TSYNC output hold
RCLK Input Period
t3
ns
t4
t5
t6
t7
t8
t8
t9
t10
ns
ns
ns
ns
ns
ns
ns
ns
10
10
6
6
1
2
5
5
0
648
488
8
2
RSYNC, RDAT, RSIG input setup to RCLK
RSYNC, RDAT, RSIG input hold from RCLK
1
Notes:
T1 Mode
E1 Mode
TSYNC is in input mode
RSYNC, RDAT and RSIG are timed relative to TCLKO when using a single clock for the port.
RSYNC, RDAT and RSIG are timed relative to RCLK when using two clocks for the port.
TSYNC is in output mode
2
3
4
5
6
7
The output timing specification for each port signal is with a 30pF load.
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DS34S132 DATA SHEET
Figure 13-5. TDM Port using Single Clock (TCLKO), positive edge timing (RSS = 1, TIES = RIES = 0)
t1
TCLKOn
RDATn,RSYNCn,RSIGn
TSYNCn1
t2
t3
t3
t2
t6
t5
t7
TSYNCn2
t4
TDATn, TSIGn
1
2
Notes:
TSYNC programmed to be an Output
TSYNC programmed to be an Input
Figure 13-6. TDM Port using Two Clock, negative edge timing (RSS = 0, TIES = RIES = 1)
t8
RCLKn
t9
t10
RDATn, RSIGn, RSYNCn
TCLKOn
t1
t5
t4
TDATn,TSIGn
TSYNCn1
t2
t3
t6
t7
TSYNCn2
1
Notes:
TSYNC programmed to be an Output
2 TSYNC programmed to be an Input
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DS34S132 DATA SHEET
13.3 MAC Interface
13.3.1 GMII Interface
Table 13-3. GMII Transmit Timing
PARAMETER
GTXCLK Output Period
GTXCLK Stability
GTXCLK Duty Cycle
TXD,TXEN, & TXER valid after rising edge
GTXCLK
SYMBOL
MIN
TYP
8
MAX
UNITS
ns
ppm
%
NOTES
t1
t1
t4
t2
1
-100
40
+100
60
5.5
ns
TXD,TXEN, & TXER hold after rising edge
t3
0.5
ns
GTXCLK
Notes:
1
The rise time and the fall time shall be 1ns measured from VIL_AC(MAX) = 0.7V to VHI_AC(MIN) = 1.9V.
The output timing specification for each signal is with a 5 pF load.
Figure 13-7. GMII Transmit Timing
GTXCLK
t1
t4
t2
t3
TXD, TXEN, TXER
Table 13-4. GMII Receive Timing
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
RXCLK input Period
t1
8
ns
1
RXCLK Duty Cycle
t4
t2
t3
40
60
%
ns
ns
RXDV,& RXD setup prior to RXCLK
2.0
RXDV, & RXD hold after RXCLK
0
1
Notes:
The rise time and the fall time shall be 1ns measured from VIL_AC(MAX) = 0.7V to VHI_AC(MIN) = 1.9V.
2 The output timing specification for each signal is with a 5pF load.
Figure 13-8. GMII Receive Timing
t1
t4
RXCLK
t3
t2
RXDV, RXD, RXER
13.3.2 MII Interface
Table 13-5. MII Transmit Timing
PARAMETER
TXCLK input Period
TXCLK Duty Cycle
TXD,TXEN, & TXER valid after rising edge TXCLK
SYMBOL
MIN
40
0
TYP MAX UNITS NOTES
t1
t4
t2
t3
40
ns
%
2
60
25
ns
ns
1
1
TXD,TXEN, & TXER hold after rising edge TXCLK
1
Notes:
The output timing specification for each signal is with a 20pF load.
Input low and input high are from VIL_AC(MAX) = 0.8V to VHI_AC(MIN) = 2.0V.
2
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DS34S132 DATA SHEET
Figure 13-9. MII Transmit Timing
t1
t4
TXCLK
t2
t3
TXD, TXEN, TXER
Table 13-6. MII Receive Timing
PARAMETER
RXCLK input Period
TXCLK Duty Cycle
RXDV,RXD, & RXER setup prior to RXCLK
SYMBOL
MIN
TYP
8
MAX
60
UNITS
ns
%
ns
NOTES
t1
t4
t2
t3
1
40
10
1
1
RXDV, RXD, RXER hold after RXCLK
0
ns
1
Notes:
Input low and input high are from VIL_AC(MAX) = 0.8V to VHI_AC(MIN) = 2.0V.
Figure 13-10. MII Receive Timing
t1
t4
RXCLK
RXDV, RXD, RXER
t3
t2
13.4 DDR SDRAM Timing
Table 13-7. DDR SDRAM Interface Timing
Parameter
Symbol
Min
7.5
3.6
3.6
3
0.8
0.8
6
3.2
1
Typ
Max
8.5
Units
t1
t2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SD_CLK Output Period
SD_CLK Output High Period
SD_CLK Output Low Period
4.4
4.4
5
t3
t4
t5
t6
Address and Control Output Hold Time
SDDQ Setup to SDUDQS, SDLDQS
SDDQ Output hold to SDUDQS, SDLDQS
SDUDQS, SDLDQS Write Preamble
SDUDQS, SDLDQS Write Postamble
SDUDQS, SDLDQS to SDUDM, SDLDM Hold Time
SDUDM, SDLDM to SDUDQS, SDLDQS Setup Time
SDUDQS, SDLDQS to SDDQ (Read)
SD_CLK to SDLDQS, SDUDQS (Read)
SDLDQS, SDUDQS High Pulse Width (Read)
SDLDQS, SDUDQS Low Pulse Width (Read)
t7
t8
t9
10
5.0
t10
t11
t12
t13
t14
1
-1
-1
+1
+1
3.4
3.4
4.5
4.5
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DS34S132 DATA SHEET
Figure 13-11. DDR SDRAM Timing
P0
SD_CLK
P1
P2
P3
SD_CLK
t1
t2
t3
WRITE
t4
Address /
Control
t5 t6
SDATA
t14
SD_UDQS
SD_LDQS
t7
t8
t13
t9
SD_UDM
SD_LDM
t10
READ
SD_CLK
SD_CLK
SD_UDQS
SD_LDQS
t12
SDATA
t11
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DS34S132 DATA SHEET
14
PIN ASSIGNMENT
Table 14-1. Pins Sorted by Signal Name
Signal
AVDD
Ball#
A6
Signal
PA[13]
PA[2]
Ball#
AB24
Y25
Y24
Y23
Y22
AA26
AA25
AA24
AA23
AB23
W25
N23
N24
R23
R24
R25
R26
T21
T22
T23
T24
T25
T26
P21
U21
U22
U23
U24
U25
U26
V21
V22
V23
V24
P22
V25
V26
P23
P24
P25
P26
R21
R22
Signal
Ball#
N25
W23
W26
W24
W22
D6
Signal
Ball#
T6
PINT_N
PRW
RDAT14
RDAT15
RDAT16
RDAT17
RDAT18
RDAT19
RDAT2
RDAT20
RDAT21
RDAT22
RDAT23
RDAT24
RDAT25
RDAT26
RDAT27
RDAT28
RDAT29
RDAT3
RDAT30
RDAT31
RDAT4
RDAT5
RDAT6
RDAT7
RDAT8
RDAT9
REFCLK
RSIG0
AVSS
A7
U6
CMNCLK
COL
AC10
H24
H25
AF9
AF8
B7
PA[3]
PRWCTRL
PTA_N
V6
PA[4]
Y7
CRS
PA[5]
PWIDTH
RCLK0
AB6
AA8
G7
CVDD
CVSS
PA[6]
PA[7]
RCLK1
D5
DDRCLK
EPHYRST_N
ETHCLK
EXTCLK[0]
EXTCLK[1]
EXTINT
GTXCLK
HIZ_N
JTCLK
JTDI
PA[8]
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
RCLK16
RCLK17
RCLK18
RCLK19
RCLK2
R2
AA9
AB9
AA11
AA13
AA14
AA15
AA16
AA17
Y18
AA20
J6
H26
B26
PA[9]
U3
PALE
PCS_N
PD[0]
R5
AA10
Y11
U4
V4
H23
K26
PD[1]
W5
PD[10]
PD[11]
PD[12]
PD[13]
PD[14]
PD[15]
PD[16]
PD[17]
PD[18]
PD[19]
PD[2]
Y5
D24
A22
AA5
AD4
AC6
F5
C22
D22
B22
JTDO
JTMS
RCLK20
RCLK21
RCLK22
RCLK23
RCLK24
RCLK25
RCLK26
RCLK27
RCLK28
RCLK29
RCLK3
AC7
AC9
AB11
AB12
AB13
AC15
AC16
AC17
AB18
AB19
G5
AA21
AD22
K6
JTRST_N
LIUCLK
MDC
B23
AF10
D26
D25
AF23
AE23
V20
L6
MDIO
M6
MT[0]
N6
MT[1]
PD[20]
PD[21]
PD[22]
PD[23]
PD[24]
PD[25]
PD[26]
PD[27]
PD[28]
PD[29]
PD[3]
M4
MT[10]
MT[11]
MT[12]
MT[13]
MT[14]
MT[15]
MT[2]
M3
U20
T20
AE9
F8
R20
N22
N21
AD23
AF24
AE24
AF25
AD26
AD25
W21
W20
Y26
RSIG1
F7
RCLK30
RCLK31
RCLK4
AB20
AF22
H5
RSIG10
RSIG11
RSIG12
RSIG13
RSIG14
RSIG15
RSIG16
RSIG17
RSIG18
RSIG19
RSIG2
P3
P4
P7
MT[3]
RCLK5
J4
R7
MT[4]
RCLK6
K4
T7
MT[5]
RCLK7
M5
U7
MT[6]
PD[30]
PD[31]
PD[4]
RCLK8
K3
V7
MT[7]
RCLK9
M2
W7
MT[8]
RDAT0
RDAT1
RDAT10
RDAT11
RDAT12
RDAT13
E8
AA7
Y8
MT[9]
PD[5]
E7
PA[1]
PD[6]
R3
H7
PA[10]
PA[11]
PA[12]
AA22
AB26
AB25
PD[7]
R4
RSIG20
RSIG21
RSIG22
Y9
PD[8]
P6
Y10
Y12
180 of 194
PD[9]
R6
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DS34S132 DATA SHEET
Signal
Ball#
Y13
Y14
Y15
Y16
Y17
Y19
Y20
J7
Signal
Ball#
N5
Signal
Ball#
C12
D12
D13
A13
B12
B14
C13
C16
A14
B13
C15
B8
Signal
Ball#
B5
RSIG23
RSYNC7
RSYNC8
RSYNC9
RXCLK
SDDQ[5]
SDDQ[6]
SDDQ[7]
SDDQ[8]
SDDQ[9]
SDLDM
TDAT0
TDAT1
TDAT10
TDAT11
TDAT12
TDAT13
TDAT14
TDAT15
TDAT16
TDAT17
TDAT18
TDAT19
TDAT2
TDAT20
TDAT21
TDAT22
TDAT23
TDAT24
TDAT25
TDAT26
TDAT27
TDAT28
TDAT29
TDAT3
TDAT30
TDAT31
TDAT4
TDAT5
TDAT6
TDAT7
TDAT8
TDAT9
TEST_N
TSIG0
RSIG24
L3
B3
RSIG25
N2
P1
RSIG26
G26
F26
F25
F24
F23
E26
E25
E24
E23
G25
G24
D19
C19
C18
B17
A17
B16
C20
B20
A20
B19
A19
B18
A18
D18
C17
D17
D15
A16
A15
B15
D16
C9
V2
RSIG27
RXD[0]
V3
RSIG28
RXD[1]
Y2
RSIG29
RXD[2]
SDLDQS
SDRAS_N
SDUDM
Y3
RSIG3
RXD[3]
AA3
AB3
AC3
AE3
AE5
D3
RSIG30
Y21
AC22
K7
RXD[4]
RSIG31
RXD[5]
SDUDQS
SDWE_N
SMTI
RSIG4
RXD[6]
RSIG5
L7
RXD[7]
RSIG6
M7
RXDV
SMTO
C7
RSIG7
N7
RXERR
SDA[0]
SYSCLK
TCLKO0
TCLKO1
TCLKO10
TCLKO11
TCLKO12
TCLKO13
TCLKO14
TCLKO15
TCLKO16
TCLKO17
TCLKO18
TCLKO19
TCLKO2
TCLKO20
TCLKO21
TCLKO22
TCLKO23
TCLKO24
TCLKO25
TCLKO26
TCLKO27
TCLKO28
TCLKO29
TCLKO3
TCLKO30
TCLKO31
TCLKO4
TCLKO5
TCLKO6
TCLKO7
TCLKO8
TCLKO9
N26
A4
AD6
AE7
AE11
AD12
AD13
AD14
AD15
AE17
AD18
AD19
E3
RSIG8
N4
RSIG9
N3
SDA[1]
A2
RST_N
A23
D7
SDA[10]
SDA[11]
SDA[12]
SDA[13]
SDA[2]
T1
RSYNC0
RSYNC1
RSYNC10
RSYNC11
RSYNC12
RSYNC13
RSYNC14
RSYNC15
RSYNC16
RSYNC17
RSYNC18
RSYNC19
RSYNC2
RSYNC20
RSYNC21
RSYNC22
RSYNC23
RSYNC24
RSYNC25
RSYNC26
RSYNC27
RSYNC28
RSYNC29
RSYNC3
RSYNC30
RSYNC31
RSYNC4
RSYNC5
RSYNC6
V1
E6
W1
P2
AA1
AB1
AC1
AD1
AE1
AF2
AF4
B1
T3
P5
SDA[3]
T5
SDA[4]
U5
SDA[5]
V5
SDA[6]
AD20
AD21
F3
W6
SDA[7]
Y6
SDA[8]
AC5
AB7
G6
SDA[9]
AF6
AF7
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
C1
G3
SDBA[0]
SDBA[1]
SDCAS_N
SDCLK
G2
J3
AB8
AD8
AB10
AA12
AB14
AB15
AB16
AB17
AA18
AA19
H6
J2
N1
SDCLK_N
SDCLKEN
SDCS_N
SDDQ[0]
SDDQ[1]
SDDQ[10]
SDDQ[11]
SDDQ[12]
SDDQ[13]
SDDQ[14]
SDDQ[15]
SDDQ[2]
SDDQ[3]
SDDQ[4]
G23
C5
TSIG1
C4
TSIG10
TSIG11
TSIG12
TSIG13
TSIG14
TSIG15
TSIG16
TSIG17
TSIG18
TSIG19
TSIG2
T2
C10
A12
A11
B11
B10
A10
A9
U2
T4
AF20
AF21
D1
W3
W4
Y4
AB21
AE22
J5
E1
AA4
AB4
AE4
AD5
E4
F1
D10
C11
D11
H1
K5
J1
L5
L1
19-4750; Rev 1; 07/11
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DS34S132 DATA SHEET
Signal
Ball#
AD7
AC8
AD11
AC12
AC13
AC14
AD16
AD17
AC18
AC19
F4
Signal
TSYNC5
TSYNC6
TSYNC7
TSYNC8
TSYNC9
TXCLK
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXEN
Ball#
F2
Signal
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDDP
Ball#
V19
V8
Signal
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball#
D9
TSIG20
TSIG21
G1
E12
E16
E19
F14
E14
A25
A5
TSIG22
H2
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W8
TSIG23
K1
TSIG24
M1
TSIG25
J26
L26
L25
L24
L23
K25
K24
J25
J24
J23
K23
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H8
TSIG26
TSIG27
TSIG28
AD10
AD9
AE10
AE26
AF11
B6
TSIG29
TSIG3
TSIG30
AC20
AC21
G4
TSIG31
TSIG4
W9
TSIG5
H4
A1
C25
C26
C6
TSIG6
H3
TXERR
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
A26
AA6
AB22
AB5
AC23
AC4
AD24
AD3
AE2
AE25
AF1
AF26
B2
TSIG7
L4
TSIG8
K2
D8
TSIG9
L2
E21
F12
F18
F22
J10
J11
J12
J13
J14
J15
J16
J17
J18
J22
J9
TSYNC0
TSYNC1
TSYNC10
TSYNC11
TSYNC12
TSYNC13
TSYNC14
TSYNC15
TSYNC16
TSYNC17
TSYNC18
TSYNC19
TSYNC2
TSYNC20
TSYNC21
TSYNC22
TSYNC23
TSYNC24
TSYNC25
TSYNC26
TSYNC27
TSYNC28
TSYNC29
TSYNC3
TSYNC30
TSYNC31
TSYNC4
B4
A3
R1
U1
W2
Y1
AA2
AB2
AC2
AD2
AF3
AF5
C2
H9
J19
J8
B25
C24
C3
K19
K8
D23
D4
AE6
AE8
AC11
AE12
AE13
AE14
AE15
AE16
AE18
AE19
D2
L19
L8
E22
E5
K10
K11
K12
K13
K14
K15
K16
K17
K18
K22
K9
M19
M8
F6
N19
N8
M25
M26
E11
E15
E18
A21
B9
P19
P8
VDDP
R19
R8
VDDP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
T19
T8
AE20
AE21
E2
C21
D14
D20
U19
U8
L10
L11
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DS34S132 DATA SHEET
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball#
L12
L13
L14
L15
L16
L17
L18
L22
L9
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball#
N12
N13
N14
N15
N16
N17
N18
N9
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Ball#
R16
R17
R18
R9
Signal
VSS
Ball#
V10
V11
V12
V13
V14
V15
V16
V17
V18
V9
VSS
VSS
VSS
T10
T11
T12
T13
T14
T15
T16
T17
T18
T9
VSS
VSS
VSS
VSS
P10
P11
P12
P13
P14
P15
P16
P17
P18
P9
VSS
M10
M11
M12
M13
M14
M15
M16
M17
M18
M22
M23
M24
M9
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A8
B21
C14
C8
U10
U11
U12
U13
U14
U15
U16
U17
U18
U9
D21
E10
E13
E17
E20
F15
R10
R11
R12
R13
R14
R15
N10
N11
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DS34S132 DATA SHEET
Table 14-2. Pins Sorted by Ball Grid Array - Ball Number
Ball#
A1
Signal
VDD33
Ball#
AA7
AA8
AA9
AB1
Signal
Ball#
AC4
AC5
AC6
AC7
AC8
AC9
AD1
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD2
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AE1
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE2
AE20
AE21
AE22
AE23
AE24
Signal
VDD33
Ball#
AE25
AE26
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AF1
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF2
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AF3
AF4
AF5
AF6
AF7
AF8
AF9
B1
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B2
B20
B21
Signal
VDD33
VSS
RSIG18
RDAT19
RDAT20
TCLKO14
RSYNC22
RCLK22
RCLK23
RCLK24
RSYNC24
RSYNC25
RSYNC26
RSYNC27
RCLK28
RCLK29
TSYNC15
RCLK30
RSYNC30
VDD33
PALE
PA[13]
PA[12]
PA[11]
TDAT16
TSIG17
VDD33
RDAT18
RSYNC19
RSYNC20
RDAT21
TCLKO15
CMNCLK
TSYNC22
TSIG23
TSIG24
TSIG25
RCLK25
RCLK26
RCLK27
TSIG28
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A2
A20
A21
A22
A23
A24
A25
A26
A3
SDDQ[14]
SDDQ[11]
SDDQ[10]
SDDQ[8]
SDUDM
SDCLK_N
SDCLK
SDA[12]
SDA[8]
SDA[6]
TCLKO1
SDA[4]
VDDQ
JTCLK
RSYNC18
RCLK19
RCLK20
TSIG21
RCLK21
TCLKO16
VSS
TSIG22
TDAT23
TDAT24
TDAT25
TDAT26
TSIG26
TSIG27
TDAT28
TDAT29
TSYNC17
TDAT30
TDAT31
RDAT31
MT[2]
VDD33
MT[7]
MT[6]
VDD33
RCLK18
TSIG19
TDAT20
TSIG20
RSYNC21
VSS
TDAT18
TSIG18
TDAT19
TSYNC20
TDAT21
TSYNC21
REFCLK
VDD33
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB2
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB3
LIUCLK
VSS
TCLKO22
TCLKO23
TCLKO24
TCLKO25
TCLKO26
TCLKO27
TCLKO28
TCLKO29
TCLKO18
TCLKO30
TCLKO31
RCLK31
MT[0]
MT[3]
MT[5]
VDD33
TSYNC18
TCLKO19
TSYNC19
TCLKO20
TCLKO21
CVSS
RST_N
VSS
VDD33
TSYNC1
TCLKO0
VSS
AVDD
AVSS
VSSQ
SDDQ[15]
TCLKO13
EXTCLK[0]
RDAT22
RSYNC23
RDAT23
RDAT24
RDAT25
RDAT26
RDAT27
RSYNC28
RSYNC29
TSYNC14
RDAT29
RDAT30
PA[10]
A4
A5
A6
A7
A8
A9
AB4
AB5
AB6
AB7
AB8
AB9
AC1
AA1
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA2
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA3
AA4
AA5
AA6
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC2
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC3
TCLKO17
VSS
TDAT22
TSYNC23
TSYNC24
TSYNC25
TSYNC26
TSYNC27
TDAT27
TSYNC28
TSYNC29
VDD33
CVDD
TCLKO2
SDDQ[13]
SDDQ[12]
SDDQ[9]
SDUDQS
SDLDM
SDCLKEN
SDA[13]
SDA[11]
SDA[7]
TSIG29
TSYNC16
TSIG30
TSIG31
RSIG31
VDD33
PA[9]
PA[8]
PA[7]
PA[6]
TDAT15
TSIG16
RCLK17
VDD33
TSYNC30
TSYNC31
RSYNC31
MT[1]
SDA[5]
VDD33
SDA[3]
VSSQ
TDAT17
MT[4]
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DS34S132 DATA SHEET
Ball#
B22
B23
B24
B25
B26
B3
B4
B5
B6
B7
Signal
JTMS
JTRST_N
Ball#
D21
D22
D23
D24
D25
D26
D3
D4
D5
D6
D7
Signal
VSSQ
JTDO
VDD33
HIZ_N
MDIO
Ball#
F20
F21
F22
F23
F24
F25
F26
F3
F4
F5
F6
F7
Signal
Ball#
H2
Signal
TSYNC7
H20
H21
H22
H23
H24
H25
H26
H3
H4
H5
H6
H7
VSS
VDD33
ETHCLK
TDAT1
TSYNC0
TDAT0
VSS
DDRCLK
SMTI
VDDQ
TCLKO3
SDDQ[1]
SDDQ[3]
SDDQ[5]
SDLDQS
VSSQ
SDWE_N
SDRAS_N
SDBA[0]
SDA[10]
SDA[1]
TSYNC2
SDA[2]
VDDQ
RXD[3]
RXD[2]
RXD[1]
RXD[0]
TDAT4
TSIG3
RCLK2
VDD33
RSIG1
RSIG0
EXTINT
COL
CRS
MDC
TDAT2
VDD33
RCLK1
RCLK0
RSYNC0
VSS
VDDQ
TCLKO5
VSSQ
VDDP
VDDQ
VSSQ
VREF
VDDP
VDDQ
VSSQ
VDDP
VDDQ
TSYNC4
VSSQ
VSS
VDD33
RXD[7]
RXD[6]
RXD[5]
RXD[4]
TDAT3
TSIG2
VDD33
RSYNC1
RDAT1
RDAT0
EPHYRST_N
TSIG6
TSIG5
RCLK4
RSYNC3
RSIG2
VDD18
VDD18
TCLKO8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B8
B9
C1
D8
D9
E1
F8
F9
G1
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C2
C20
C21
C22
C23
C24
C25
C26
C3
C4
C5
C6
C7
C8
C9
D1
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D2
H8
H9
J1
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E2
E20
E21
E22
E23
E24
E25
E26
E3
E4
E5
E6
E7
E8
E9
F1
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F2
TSYNC6
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G2
G20
G21
G22
G23
G24
G25
G26
G3
G4
G5
G6
G7
G8
G9
H1
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J2
J20
J21
J22
J23
J24
J25
J26
J3
J4
J5
J6
J7
J8
J9
K1
K10
K11
K12
K13
K14
K15
K16
K17
K18
TDAT6
VDD18
TDAT8
JTDI
VDD33
VSS
VSS
VDD33
TSIG1
TSIG0
VSS
SMTO
VSSQ
SDDQ[0]
TCLKO4
SDDQ[2]
SDDQ[4]
SDDQ[6]
SDDQ[7]
VDDQ
SDCAS_N
SDCS_N
SDBA[1]
SDA[9]
SDA[0]
TSYNC3
VDDQ
TEST_N
RXERR
RXDV
RXCLK
TDAT5
TSIG4
RCLK3
RSYNC2
RDAT2
VSS
TXEN
TXD[7]
TXD[6]
TXCLK
TDAT7
RCLK5
RSYNC4
RDAT3
RSIG3
VDD18
VSS
TSYNC8
VSS
VSS
VSS
VSS
TCLKO6
VSS
TCLKO7
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDDQ
VSSQ
VSS
VSS
VSS
VSS
VSS
D20
TSYNC5
VSS
19-4750; Rev 1; 0711
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DS34S132 DATA SHEET
Ball#
K19
K2
Signal
VDD18
TSIG8
Ball#
M18
M19
M2
M20
M21
M22
M23
M24
M25
M26
M3
M4
M5
M6
M7
M8
M9
N1
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N2
N20
N21
N22
N23
N24
N25
N26
N3
Signal
VSS
VDD18
RCLK9
Ball#
P17
P18
P19
P2
P20
P21
P22
P23
P24
P25
P26
P3
P4
P5
P6
P7
P8
P9
R1
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R2
R20
R21
R22
R23
R24
R25
R26
R3
Signal
VSS
VSS
VDD18
RSYNC10
Ball#
T16
T17
T18
T19
T2
T20
T21
T22
T23
T24
T25
T26
T3
T4
T5
T6
T7
T8
T9
U1
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U2
U20
U21
U22
U23
U24
U25
U26
U3
Signal
VSS
VSS
K20
K21
K22
K23
K24
K25
K26
K3
K4
K5
K6
K7
VSS
VDD18
TSIG10
MT[12]
PD[14]
PD[15]
PD[16]
PD[17]
PD[18]
PD[19]
RSYNC11
TSIG12
RSYNC13
RDAT14
RSIG14
VDD18
VSS
TSYNC11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TXERR
TXD[5]
TXD[4]
GTXCLK
RCLK8
RCLK6
RSYNC5
RDAT4
RSIG4
VDD18
VSS
TCLKO9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD18
TSIG9
VSS
VSS
VSS
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
RSIG10
RSIG11
RSYNC12
RDAT12
RSIG12
VDD18
VSS
TSYNC10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD18
RCLK10
MT[13]
PD[8]
VDD33
VDD33
RDAT9
RDAT8
RCLK7
RDAT6
RSIG6
VDD18
VSS
TDAT9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD18
RSYNC9
K8
K9
L1
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L2
L20
L21
L22
L23
L24
L25
L26
L3
L4
L5
L6
L7
L8
L9
M1
M10
M11
M12
M13
M14
M15
M16
M17
VSS
VDD18
TSIG11
MT[11]
PD[20]
PD[21]
PD[22]
PD[23]
PD[24]
PD[25]
RCLK11
RCLK13
RSYNC14
RDAT15
RSIG15
VDD18
VSS
VSS
MT[15]
MT[14]
PD[0]
TXD[3]
TXD[2]
TXD[1]
TXD[0]
RSYNC8
TSIG7
RSYNC6
RDAT5
RSIG5
VDD18
VSS
TSYNC9
VSS
VSS
VSS
VSS
PD[9]
PD[1]
PD[10]
PD[11]
PD[12]
PD[13]
RDAT10
RDAT11
RCLK12
RDAT13
RSIG13
VDD18
VSS
TCLKO10
VSS
VSS
VSS
VSS
PINT_N
SYSCLK
RSIG9
RSIG8
RSYNC7
RDAT7
RSIG7
VDD18
VSS
TDAT10
VSS
VSS
VSS
VSS
N4
N5
N6
N7
N8
N9
P1
P10
P11
P12
P13
P14
P15
P16
R4
R5
R6
R7
R8
R9
T1
T10
T11
T12
T13
T14
T15
U4
U5
U6
U7
U8
U9
V1
V10
V11
V12
V13
V14
TCLKO11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
19-4750; Rev 1; 0711
186 of 194
DS34S132 DATA SHEET
Ball#
V15
V16
V17
V18
V19
V2
V20
V21
V22
V23
V24
V25
V26
V3
Signal
VSS
VSS
VSS
VSS
Ball#
V8
V9
Signal
VDD18
VSS
Ball#
W24
W25
W26
W3
W4
W5
W6
W7
W8
W9
Y1
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Signal
PTA_N
PCS_N
PRWCTRL
TSIG13
TSIG14
RCLK15
RSYNC16
RSIG17
VDD18
Ball#
Y17
Y18
Y19
Y2
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Signal
RSIG27
RDAT28
RSIG28
TDAT13
RSIG29
RSIG30
PA[5]
PA[4]
PA[3]
PA[2]
PA[1]
TDAT14
TSIG15
RCLK16
RSYNC17
RDAT17
RSIG19
RSIG20
W1
TCLKO12
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
VDD18
TSYNC12
MT[9]
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W2
VDD18
TDAT11
MT[10]
PD[26]
PD[27]
PD[28]
PD[29]
PD[30]
PD[31]
TDAT12
RCLK14
RSYNC15
RDAT16
RSIG16
VDD18
TSYNC13
RSIG21
EXTCLK[1]
RSIG22
RSIG23
RSIG24
RSIG25
RSIG26
V4
V5
V6
V7
W20
W21
W22
W23
MT[8]
PWIDTH
PRW
19-4750; Rev 1; 0711
187 of 194
DS34S132 DATA SHEET
Table 14-3. Pin Assignments according to Device Outline
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
1
2
3
4
5
6
7
8
9
V
D
D
3
T
C
L
K
O
1
T
S
Y
N
C
1
T
C
L
K
O
0
V
S
S
A
V
D
D
A
V
S
S
V
S
S
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
[
S
D
U
D
M
S
D
C
L
K
_
S
D
C
L
S
D
A
[
1
2
]
S
D
A
[
8
]
S
D
A
[
6
]
S
D
A
[
4
]
V
D
D
Q
J
T
C
L
R
S
T
_
V
S
S
V
D
D
3
A
B
C
D
E
F
A
B
C
D
E
F
3
[1 [1 [1 [1
5] 4] 1] 0]
K
K
N
3
8
]
N
T
C
L
K
O
2
V
D
D
3
T
D
A
T
1
T
S
Y
N
C
0
T
D
A
T
0
V
S
S
D
D
R
C
L
S
M
T
I
V
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
U
D
Q
S
S
D
L
D
M
S
D
C
L
K
E
N
S
D
A
[
1
3
]
S
D
A
[
1
1
]
S
D
A
[
7
]
S
D
A
[
5
]
S
D
A
[
3
]
V
S
S
Q
J
T
M
S
J
T
R
S
T
_
V
D
D
3
E
T
H
C
L
3
[1 [1 [9
3] 2]
3
K
]
K
N
T
C
L
K
O
3
T
S
Y
N
C
2
V
D
D
3
T
S
I
G
1
T
S
I
G
0
V
S
S
S
M
T
V
S
S
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
L
D
Q
S
V
S
S
Q
S
D
W
E
_
S
D
R
A
S
_
S
D
B
A
[
S
D
A
[
1
0
]
S
D
A
[
1
]
S
D
A
[
2
]
V
D
D
Q
J
T
D
I
V
D
D
3
V
S
S
V
S
S
O
3
[0 [1 [3 [5
]
3
]
]
]
N
0
]
N
T
C
L
K
O
4
T
S
Y
N
C
3
T
D
A
T
2
V
D
D
3
R
C
L
K
1
R
C
L
K
0
R
S
Y
N
C
0
V
S
S
V
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
S
D
D
Q
[
V
D
D
Q
S
D
C
A
S
_
S
D
C
S
_
S
D
B
A
[
S
D
A
[
9
]
S
D
A
[
0
]
V
D
D
Q
V
S
S
Q
J
T
D
O
V
D
D
3
H
I
Z
_
N
M
D
I
M
D
C
O
3
[2 [4 [6
]
3
]
]
7
]
N
1
]
N
T
C
L
K
O
5
T
S
Y
N
C
4
T
D
A
T
3
T
S
I
G
2
V
D
D
3
R
S
Y
N
C
1
R
D
A
T
1
R
D
A
T
0
V
S
S
Q
V
D
D
P
V
D
D
Q
V
S
S
Q
V
R
E
F
V
D
D
P
V
D
D
Q
V
S
S
Q
V
D
D
P
V
D
D
Q
V
S
S
Q
V
S
S
V
D
D
3
R
X
D
[
7
]
R
X
D
[
6
]
R
X
D
[
5
]
R
X
D
[
4
]
3
3
T
C
L
K
O
6
T
S
Y
N
C
5
T
D
A
T
4
T
S
I
G
3
R
C
L
K
2
V
D
D
3
R
S
I
G
1
R
S
I
G
0
V
S
S
V
D
D
Q
V
S
S
Q
V
S
S
V
S
S
R
X
D
[
3
]
R
X
D
[
2
]
R
X
D
[
1
]
R
X
D
[
0
]
3
T
S
Y
N
C
6
T
D
A
T
6
T
D
A
T
5
T
S
I
G
4
R
C
L
K
3
R
S
Y
N
C
2
R
D
A
T
2
T
E
S
T
_
R
X
E
R
R
R
X
D
V
R
X
C
L
G
G
K
N
T
C
L
K
O
7
T
S
Y
N
C
7
T
S
I
G
6
T
S
I
G
5
R
C
L
K
4
R
S
Y
N
C
3
R
S
I
G
2
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
E
X
T
I
N
T
C
O
L
C
R
S
E
P
H
Y
R
S
T
_
8
8
8
8
8
8
8
8
8
8
8
8
H
H
N
19-4750; Rev 1; 0711
188 of 194
DS34S132 DATA SHEET
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
1
2
3
4
5
6
7
8
9
T
C
L
K
O
8
T
D
A
T
8
T
D
A
T
7
R
C
L
K
5
R
S
Y
N
C
4
R
D
A
T
3
R
S
I
G
3
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
V
S
S
T
X
E
N
T
X
D
[
7
]
T
X
D
[
6
]
T
X
C
L
J
J
8
8
K
T
S
Y
N
C
8
T
S
I
G
8
R
C
L
K
8
R
C
L
K
6
R
S
Y
N
C
5
R
D
A
T
4
R
S
I
G
4
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
V
S
S
T
X
E
R
R
T
X
D
[
5
]
T
X
D
[
4
]
G
T
X
C
L
K
L
K
L
8
8
K
T
C
L
K
O
9
T
S
I
G
9
R
S
Y
N
C
8
T
S
I
G
7
R
S
Y
N
C
6
R
D
A
T
5
R
S
I
G
5
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
V
S
S
T
X
D
[
3
]
T
X
D
[
2
]
T
X
D
[
1
]
T
X
D
[
0
]
8
8
T
S
Y
N
C
9
R
C
L
K
9
R
D
A
T
9
R
D
A
T
8
R
C
L
K
7
R
D
A
T
6
R
S
I
G
6
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
V
S
S
V
S
S
V
S
S
V
D
D
3
V
D
D
3
M
N
P
R
T
M
N
P
R
T
8
8
3
3
T
D
A
T
9
R
S
Y
N
C
9
R
S
I
G
9
R
S
I
G
8
R
S
Y
N
C
7
R
D
A
T
7
R
S
I
G
7
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
M
T
[
1
5
]
M
T
[
1
4
]
P
D
[
0
]
P
D
[
1
]
P
I
N
T
_
N
S
Y
S
C
L
8
8
K
T
D
A
T
1
R
S
Y
N
C
1
R
S
I
G
1
0
R
S
I
G
1
1
R
S
Y
N
C
1
R
D
A
T
1
R
S
I
G
1
2
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
P
D
[
2
]
P
D
[
3
]
P
D
[
4
]
P
D
[
5
]
P
D
[
6
]
P
D
[
7
]
8
8
0
2
0
2
T
S
Y
N
C
1
R
C
L
K
1
R
D
A
T
1
R
D
A
T
1
R
C
L
K
1
R
D
A
T
1
R
S
I
G
1
3
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
M
T
[
1
3
]
P
D
[
8
]
P
D
[
9
]
P
D
[
1
0
]
P
D
[
1
1
]
P
D
[
1
2
]
P
D
[
1
3
]
8
8
0
0
1
2
3
0
T
C
L
K
O
1
T
S
I
G
1
0
R
S
Y
N
C
1
T
S
I
G
1
2
R
S
Y
N
C
1
R
D
A
T
1
R
S
I
G
1
4
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
M
T
[
1
2
]
P
D
[
1
4
]
P
D
[
1
5
]
P
D
[
1
6
]
P
D
[
1
7
]
P
D
[
1
8
]
P
D
[
1
9
]
8
8
4
0
1
3
19-4750; Rev 1; 0711
189 of 194
DS34S132 DATA SHEET
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
1
2
3
4
5
6
7
8
9
T
S
Y
N
C
1
T
S
I
G
1
1
R
C
L
K
1
R
C
L
K
1
R
S
Y
N
C
1
R
D
A
T
1
R
S
I
G
1
5
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
M
T
[
1
1
]
P
D
[
2
0
]
P
D
[
2
1
]
P
D
[
2
2
]
P
D
[
2
3
]
P
D
[
2
4
]
P
D
[
2
5
]
U
V
U
V
8
8
1
3
5
1
4
T
C
L
K
O
1
T
D
A
T
1
T
D
A
T
1
R
C
L
K
1
R
S
Y
N
C
1
R
D
A
T
1
R
S
I
G
1
6
V
D
D
1
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
S
S
V
D
D
1
M
T
[
1
0
]
P
D
[
2
6
]
P
D
[
2
7
]
P
D
[
2
8
]
P
D
[
2
9
]
P
D
[
3
0
]
P
D
[
3
1
]
8
8
1
2
4
6
1
5
T
C
L
K
O
1
T
S
Y
N
C
1
T
S
I
G
1
3
T
S
I
G
1
4
R
C
L
K
1
R
S
Y
N
C
1
R
S
I
G
1
7
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
V
D
D
1
M
T
[
9
]
M
T
[
8
]
P
W
I
D
T
P
R
W
P
T
A
_
P
C
S
_
P
R
W
C
T
W
W
8
8
8
8
8
8
8
8
8
8
8
8
N
N
5
H
R
L
2
2
6
T
S
Y
N
C
1
T
D
A
T
1
T
D
A
T
1
T
S
I
G
1
5
R
C
L
K
1
R
S
Y
N
C
1
R
D
A
T
1
R
S
I
G
1
9
R
S
I
G
2
0
R
S
I
G
2
1
E
X
T
C
L
K
[1
]
R
S
I
G
2
2
R
S
I
G
2
3
R
S
I
G
2
4
R
S
I
G
2
5
R
S
I
G
2
6
R
S
I
G
2
7
R
D
A
T
2
R
S
I
G
2
8
R
S
I
G
2
9
R
S
I
G
3
0
P
A
[
5
]
P
A
[
4
]
P
A
[
3
]
P
A
[
2
]
P
A
[
1
]
Y
Y
3
4
6
7
8
3
7
T
C
L
K
O
1
T
S
Y
N
C
1
T
D
A
T
1
T
S
I
G
1
6
R
C
L
K
1
V
D
D
3
R
S
I
G
1
8
R
D
A
T
1
R
D
A
T
2
E
X
T
C
L
K
[0
]
R
D
A
T
2
R
S
Y
N
C
2
R
D
A
T
2
R
D
A
T
2
R
D
A
T
2
R
D
A
T
2
R
D
A
T
2
R
S
Y
N
C
2
R
S
Y
N
C
2
R
D
A
T
2
R
D
A
T
3
P
A
[
1
0
]
P
A
[
9
]
P
A
[
8
]
P
A
[
7
]
P
A
[
6
]
A
A
A
A
3
5
7
9
0
2
3
4
5
6
7
9
0
3
4
3
8
9
T
C
L
K
O
1
T
S
Y
N
C
1
T
D
A
T
1
T
S
I
G
1
7
V
D
D
3
R
D
A
T
1
R
S
Y
N
C
1
R
S
Y
N
C
2
R
D
A
T
2
R
S
Y
N
C
2
R
C
L
K
2
R
C
L
K
2
R
C
L
K
2
R
S
Y
N
C
2
R
S
Y
N
C
2
R
S
Y
N
C
2
R
S
Y
N
C
2
R
C
L
K
2
R
C
L
K
2
R
C
L
K
3
R
S
Y
N
C
3
V
D
D
3
P
A
L
P
A
[
1
3
]
P
A
[
1
2
]
P
A
[
1
1
]
A
B
A
B
E
3
3
6
8
1
2
3
4
8
9
0
4
5
9
0
2
4
5
6
7
0
T
C
L
K
O
1
T
S
Y
N
C
1
T
D
A
T
1
V
D
D
3
R
S
Y
N
C
1
R
C
L
K
1
R
C
L
K
2
T
S
I
G
2
1
R
C
L
K
2
C
M
N
C
L
T
S
Y
N
C
2
T
S
I
G
2
3
T
S
I
G
2
4
T
S
I
G
2
5
R
C
L
K
2
R
C
L
K
2
R
C
L
K
2
T
S
I
G
2
8
T
S
I
G
2
9
T
S
I
G
3
0
T
S
I
G
3
1
R
S
I
G
3
1
V
D
D
3
A
C
A
C
3
3
7
9
0
1
K
5
6
7
5
6
8
2
T
C
L
K
O
1
T
S
Y
N
C
1
V
D
D
3
R
C
L
K
1
T
S
I
G
1
9
T
D
A
T
2
T
S
I
G
2
0
R
S
Y
N
C
2
V
S
S
V
S
S
T
S
I
G
2
2
T
D
A
T
2
T
D
A
T
2
T
D
A
T
2
T
D
A
T
2
T
S
I
G
2
6
T
S
I
G
2
7
T
D
A
T
2
T
D
A
T
2
T
D
A
T
3
T
D
A
T
3
R
D
A
T
3
M
T
[
2
]
V
D
D
3
M
T
[
7
]
M
T
[
6
]
A
D
A
D
3
3
8
0
3
4
5
6
8
9
0
1
1
6
7
1
19-4750; Rev 1; 0711
190 of 194
DS34S132 DATA SHEET
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
1
2
3
4
5
6
7
8
9
T
C
L
K
O
1
V
D
D
3
T
D
A
T
1
T
S
I
G
1
8
T
D
A
T
1
T
S
Y
N
C
2
T
D
A
T
2
T
S
Y
N
C
2
R
E
F
C
L
V
S
S
T
D
A
T
2
T
S
Y
N
C
2
T
S
Y
N
C
2
T
S
Y
N
C
2
T
S
Y
N
C
2
T
S
Y
N
C
2
T
D
A
T
2
T
S
Y
N
C
2
T
S
Y
N
C
2
T
S
Y
N
C
3
T
S
Y
N
C
3
R
S
Y
N
C
3
M
T
[
1
]
M
T
[
4
]
V
D
D
3
V
S
S
A
E
A
E
3
3
8
9
1
K
2
7
7
0
1
3
4
5
6
7
8
9
0
1
1
V
D
D
3
T
C
L
K
O
1
T
S
Y
N
C
1
T
C
L
K
O
1
T
S
Y
N
C
1
T
C
L
K
O
2
T
C
L
K
O
2
C
V
S
S
C
V
D
D
LI
U
C
L
V
S
S
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
2
T
C
L
K
O
3
T
C
L
K
O
3
R
C
L
K
3
M
T
[
0
]
M
T
[
3
]
M
T
[
5
]
V
D
D
3
A
F
A
F
3
K
3
1
8
8
9
9
0
1
2
3
4
5
6
7
8
9
0
1
19-4750; Rev 1; 0711
191 of 194
DS34S132 DATA SHEET
15
PACKAGE INFORMATION
The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package
outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
90-0269
676 TEPBGA
(27mm x 27mm)
21-0311
V676H+1
Figure 15-1. 676-Ball TEPBGA
19-4750; Rev 1; 0711
192 of 194
DS34S132 DATA SHEET
16
THERMAL INFORMATION
Table 16-1. Thermal Package Information
Parameter
Value
Target Ambient Temperature Range
Die Junction Temperature Range
Theta-JA, Still Air
-40°C to +85°C
-40°C to +125°C
14.5°C/W (Note 1)
3.9°C/W
Theta-JC, Still Air
Psi Jt (Junction to Top of Case)
Note 1: Theta-JA is based on the package mounted on a four-layer JEDEC board and measured in a JEDEC test chamber.
0.23°C/W
19-4750; Rev 1; 0711
193 of 194
DS34S132 DATA SHEET
17
DATA SHEET REVISION HISTORY
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
7/09
Initial release.
—
1
7/11
Rev A2 – DCR bug fixed.
1,83,127,171
19-4750; Rev 1; 7/11
194 of 194
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses
are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products.
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