DS3690 [MAXIM]

3.3V 26-Channel, Three-Stateable Transmission Gate; 3.3V 26通道,三Stateable传输门
DS3690
型号: DS3690
厂家: MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述:

3.3V 26-Channel, Three-Stateable Transmission Gate
3.3V 26通道,三Stateable传输门

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Rev 0; 10/07  
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
DS3690  
General Description  
Features  
The DS3690 is a 26-channel, three-stateable transmis-  
sion gate designed for transparent digital signal trans-  
fer when enabled and fast-gated bus isolation when the  
device is disabled. Each of the 26 independent chan-  
nels can be used for input, output, or I/O signal appli-  
cations, with a typical signal propagation delay of less  
than 10ns. Using the logic-control input, all channels  
can be simultaneously enabled for bus transmission or  
forced to a high-impedance condition to isolate a criti-  
cal component on that bus.  
26 Bidirectional Channels  
Low Propagation Delay (< 10ns typ)  
High-Speed On/Off Time (< 20ns typ)  
2.7V to 3.6V Supply  
Wide Temperature Range: -55°C to +85°C  
TQFN Package (5mm x 11mm x 0.8mm)  
The DS3690 operates on a single 3.3V (typical) power  
supply and is available in a space-saving 56-pin lead-  
free TQFN package.  
Ordering Information  
Applications  
POS Terminals  
PART  
DS3690T+  
TEMP RANGE  
-55°C to +85°C  
-55°C to +85°C  
PIN-PACKAGE  
56 TQFN  
PIN Pads  
DS3690T+TRL  
56 TQFN  
Cryptographic Processors  
Gaming  
+Denotes a lead-free package.  
TRL = Tape and reel.  
Lottery Terminals  
Industrial Controls and Monitoring  
Pin Configuration  
TOP VIEW  
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29  
49  
50  
51  
28  
CH24B  
CH25B  
CH26B  
CH21B  
CH22B  
CH23B  
GND  
27  
26  
25  
24  
CE 52  
53  
DS3690  
GND  
V
CC  
CH26A 54  
CH25A 55  
CH24A 56  
23 CH23A  
22 CH22A  
21 CH21A  
EXPOSED PAD (ON BOTTOM)  
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
TQFN  
(5mm × 11mm × 0.8mm)  
Typical Operating Circuit appears at end of data sheet.  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,  
or visit Maxim’s website at www.maxim-ic.com.  
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
ABSOLUTE MAXIMUM RATINGS  
Voltage Range on Any Pin Relative to Ground......-0.5V to +6.0V  
Operating Temperature Range ...........................-55°C to +85°C  
Storage Temperature Range.............................-55°C to +125°C  
Soldering Temperature...................Refer to IPC/JEDEC J-STD-020  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
DS3690  
RECOMMENDED OPERATING CONDITIONS  
(T = -55°C to +85°C)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Supply Voltage  
V
(Note 1)  
(Note 1)  
2.7  
3.3  
3.6  
V
CC  
0.7 x  
V
+
CC  
0.3  
Input Logic 1  
Input Logic 0  
V
V
V
IH  
V
CC  
0.3 x  
V
(Note 1)  
-0.3  
IL  
V
CC  
DC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= +2.7V to +3.6V, T = -55°C to +85°C, unless otherwise noted.)  
A
PARAMETER  
Standby Current  
SYMBOL  
CONDITIONS  
CE = CH1 CH26 = V , I  
MIN  
TYP  
MAX  
1
UNITS  
μA  
I
= 0mA  
CC OUT  
CC  
Input Leakage Current (CE)  
I
V
= 0V to V , T = +25°C  
-0.1  
-1.0  
+0.1  
+1.0  
μA  
I
IN  
CC  
A
I/O Leakage Current  
I
CE = V  
μA  
IO  
IH  
AC ELECTRICAL CHARACTERISTICS  
(V  
CC  
= +2.7V to +3.6V, T = -55°C to +85°C, unless otherwise noted.)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
Propagation Delay  
(A to B or B to A)  
t
CE = V (Note 2)  
10  
ns  
PD  
IL  
Chip Enable to Output Valid  
Chip Enable to Output Deselect  
Input to CE Setup Time  
t
t
(Notes 2, 3)  
(Notes 2, 3)  
(Note 4)  
20  
20  
ns  
ns  
ns  
ns  
CEV  
CEZ  
t
0
IS  
Skew Between Channels  
t
(Notes 5, 6)  
1
S
AC TEST CONDITIONS  
Input Pulse Levels:  
V
IL  
= 0.0V, V = 2.7V  
IH  
Input Pulse Rise and Fall Times:  
5ns  
Input and Output Timing Reference Level:  
Output Load:  
V
/2  
CC  
C (100pF)  
L
2
_______________________________________________________________________________________  
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
DS3690  
CAPACITANCE  
(T = +25°C)  
A
PARAMETER  
SYMBOL  
CONDITIONS  
Not production tested  
Not production tested  
MIN  
TYP  
MAX  
UNITS  
pF  
Input Capacitance (CE)  
C
IN  
C
IO  
5
8
I/O Capacitance  
pF  
Note 1: All voltages referenced to ground.  
Note 2: Typical waveform shown is labeled CHxxA (input) to CHxxB (output), and is identical in function when selecting pin CHxxB  
(as the input) to pin CHxxA (as the output).  
Note 3: Output reference level is V /2.  
CC  
Note 4: Input transitions prior to the CE falling edge are ignored (don’t care).  
Note 5: Propagation delay differential between any two channels when using a common input signal source.  
Note 6: Guaranteed by design and not 100% tested.  
Timing Diagrams  
CHxxA  
t
t
t
PD  
PD  
PD  
CHxxB  
Figure 1. Digital Channel Propagation Delay  
CE  
CE  
t
IS  
DON'T  
CARE  
CHxxA  
CHxxB  
DON'T CARE  
CHxxA  
CHxxB  
t
CEZ  
t
CEV  
HIGH IMPEDANCE  
HIGH IMPEDANCE  
Figure 2. Digital Channels Enabled by CE  
Figure 3. Digital Channels Disabled by CE  
_______________________________________________________________________________________  
3
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
Typical Operating Characteristics  
(V  
CC  
= 3.3V, T = +25°C, unless otherwise noted.)  
A
POWER-SUPPLY CURRENT  
vs. INPUT VOLTAGE  
CHANNEL ON-RESISTANCE CHANGE  
vs. INPUT VOLTAGE  
1.E-02  
25  
CE = CH1A–CH26A,  
CH1B–CH26B = FLOAT  
DS3690  
I
= -0.1mA, CH1  
OUT  
1.E-03  
1.E-04  
1.E-05  
1.E-06  
1.E-07  
1.E-08  
1.E-09  
1.E-10  
20  
15  
10  
5
T
A
= +85°C  
T
A
= +25°C  
T
A
= -55°C  
0
2.0  
2.3  
2.6  
2.9  
3.2  
0.0  
0.7  
1.3  
2.0  
2.6  
3.3  
INPUT VOLTAGE (V)  
INPUT VOLTAGE (V)  
OUTPUT-VOLTAGE HIGH  
vs. OUTPUT CURRENT  
OUTPUT-VOLTAGE LOW  
vs. OUTPUT CURRENT  
3.2  
3.1  
3.0  
2.9  
2.8  
2.7  
2.6  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0.0  
V
IN  
= +3.0V, CH1A–CH1B  
V
IN  
= +0.3V, CH1A–CH1B  
-5  
-4  
-3  
-2  
-1  
0
0
1
2
3
4
5
OUTPUT CURRENT (mA)  
OUTPUT CURRENT (mA)  
4
_______________________________________________________________________________________  
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
DS3690  
Pin Description  
PIN  
1
NAME  
CH01A  
CH02A  
CH03A  
CH04A  
CH05A  
CH06A  
CH07A  
CH08A  
CH09A  
CH10A  
CH11A  
CH12A  
CH13A  
CH14A  
CH15A  
CH16A  
CH17A  
CH18A  
CH19A  
CH20A  
CH21A  
CH22A  
CH23A  
FUNCTION  
Channel 1 Terminal A  
Channel 2 Terminal A  
Channel 3 Terminal A  
Channel 4 Terminal A  
Channel 5 Terminal A  
Channel 6 Terminal A  
Channel 7 Terminal A  
Channel 8 Terminal A  
Channel 9 Terminal A  
Channel 10 Terminal A  
Channel 11 Terminal A  
Channel 12 Terminal A  
Channel 13 Terminal A  
Channel 14 Terminal A  
Channel 15 Terminal A  
Channel 16 Terminal A  
Channel 17 Terminal A  
Channel 18 Terminal A  
Channel 19 Terminal A  
Channel 20 Terminal A  
Channel 21 Terminal A  
Channel 22 Terminal A  
Channel 23 Terminal A  
Supply Voltage  
PIN  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
54  
55  
56  
NAME  
CH19B  
CH18B  
CH17B  
CH16B  
CH15B  
CH14B  
CH13B  
CH12B  
CH11B  
CH10B  
CH09B  
CH08B  
CH07B  
CH06B  
CH05B  
CH04B  
CH03B  
CH02B  
CH01B  
CH24B  
CH25B  
CH26B  
CE  
FUNCTION  
Channel 19 Terminal B  
Channel 18 Terminal B  
Channel 17 Terminal B  
Channel 16 Terminal B  
Channel 15 Terminal B  
Channel 14 Terminal B  
Channel 13 Terminal B  
Channel 12 Terminal B  
Channel 11 Terminal B  
Channel 10 Terminal B  
Channel 9 Terminal B  
Channel 8 Terminal B  
Channel 7 Terminal B  
Channel 6 Terminal B  
Channel 5 Terminal B  
Channel 4 Terminal B  
Channel 3 Terminal B  
Channel 2 Terminal B  
Channel 1 Terminal B  
Channel 24 Terminal B  
Channel 25 Terminal B  
Channel 26 Terminal B  
Chip-Enable Input (Active Low)  
Channel 26 Terminal A  
Channel 25 Terminal A  
Channel 24 Terminal A  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25, 53  
26  
27  
28  
29  
V
CC  
CH26A  
CH25A  
CH24A  
GND  
Ground  
CH23B  
CH22B  
CH21B  
CH20B  
Channel 23 Terminal B  
Channel 22 Terminal B  
Channel 21 Terminal B  
Channel 20 Terminal B  
Exposed Paddle. Must be  
connected to ground.  
EP  
_______________________________________________________________________________________  
5
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
Detailed Description  
Applications Information  
The DS3690 is a 26-channel, noninverting, bidirectional  
CMOS transmission gate, and is intended for use in  
applications where a downstream component must be  
isolated from a common control, address, or data bus in  
a timely fashion. Each of the 26 independent channels  
can be used for input, output, or I/O signal applications.  
The chip-enable input (CE) allows gated bus control for  
either signal transmission or bus isolation.  
Power-Supply Decoupling  
To achieve the best results when using the DS3690,  
decouple the power supply with a 0.1µF capacitor.  
Use a high-quality, ceramic surface-mount capacitor if  
possible. Surface-mount components minimize lead  
inductance, which improves performance, while ceram-  
ic capacitors have adequately high-frequency  
response for decoupling applications.  
DS3690  
Each independent channel consists of two pins  
(“CHxxA” and “CHxxB” where xx is 01–26). Since all 26  
channels are capable of bidirectional function, either  
CHxxA or CHxxB can be selected as the input pin for  
any unidirectional signal requirements. A change of  
logic state on one side of any channel is directly reflect-  
ed on the other side of that channel. Signal  
propagation delay (CHxxA to CHxxB, or CHxxB to  
Pin Connections  
For optimum circuit operation, connect pins 25 and 53 to  
a common ground. The exposed pad on the package  
bottom side should be connected to ground.  
To prevent an unused transmission channel from gener-  
ating any undesired activity, it is recommended that one  
side of that unused channel be connected to ground  
(either the A or B terminal, at the designer’s discretion).  
CHxxA) is illustrated in Figure 1 as t  
.
PD  
All channels can be simultaneously enabled or forced  
to a high-impedance state using the CE input. When CE  
becomes a logic zero, all channels are enabled for  
signal transmission within t  
(see Figure 2). When CE  
CEV  
becomes a logic one, all channels are forced to a  
high-impedance state within t  
(see Figure 3).  
CEZ  
Typical Operating Circuit  
+3.3V  
R/W CONTROL  
R/W CONTROL  
ADDRESS (A  
I/O (DQ  
)
ADDRESS (A  
I/O (DQ  
)
0–X  
0–X  
EXTERNAL  
MEMORY  
MICRO  
)
)
0–X  
0–X  
DS3690  
BUS ENABLE  
CE  
6
_______________________________________________________________________________________  
3.3V 26-Channel, Three-Stateable  
Transmission Gate  
DS3690  
Functional Diagram  
Package Information  
(For the latest package outline information, go to  
www.maxim-ic.com/DallasPackInfo.)  
PACKAGE TYPE  
DOCUMENT NO.  
21-0187  
V
CC  
56 TQFN  
V
CC  
CE  
CH01A  
CH02A  
CH03A  
CH01B  
CH02B  
CH03B  
GND  
CH26A  
CH26B  
DS3690  
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7  
© 2007 Maxim Integrated Products  
is a registered trademark of Maxim Integrated Products, Inc.  

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