DS4026S3+BCN [MAXIM]
CMOS Output Clock Oscillator, 10MHz Min, 51.84MHz Max, 12.8MHz Nom, ROHS COMPLIANT, SOP-16;
| 型号： | DS4026S3+BCN |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CMOS Output Clock Oscillator, 10MHz Min, 51.84MHz Max, 12.8MHz Nom, ROHS COMPLIANT, SOP-16 |
| 文件： | 总14页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 2; 4/08
10MHz to 51.84MHz TCXO
DS4026
General Description
Features
The DS4026 is a temperature-compensated crystal
oscillator (TCXO) that provides ±±ppm ꢀreꢁuency staꢂili-
ty over the -40°C to +85°C industrial temperature range.
The DS4026 is also availaꢂle in Stratum 3 versions (see
the Ordering Inꢀormation—Stratum 3 taꢂle). Each device
is ꢀactory caliꢂrated over temperature to achieve the
±±ppm ꢀreꢁuency staꢂility. Standard ꢀreꢁuencies ꢀor the
device include ±0, ±2.8, ±9.44, 20, 38.88, 40, and
5±.84MHz. Contact the ꢀactory ꢀor custom ꢀreꢁuencies.
♦ ±±11pm FreqrꢀncmꢁnnqFꢂncmꢃOrFmꢄ-40°mꢅtmꢆ+80°
♦ SꢅꢂꢀdꢂFdm Freqrꢀnirs:m±4,m±2.+,m±9.--,m24,m3+.++,
-4,m8±.+-MHz
♦ SꢅFꢂꢅqpm3m Freqrꢀnirs:m±4,m±2.+,m±9.2,m24MHz
♦ Mꢂxipqpm±-.ꢇ11pmꢈrOiꢂꢅitꢀmꢃOrFm24mꢉrꢂFs
♦ Miꢀipqpm±+11pmꢊ±811pmꢋtFm±4MHzꢌmꢈiDiꢅꢂꢍ
2
FreqrꢀncmTqꢀiꢀDmThFtqDhmI °mIꢀꢅrFꢋꢂnr
The DS4026 provides excellent phase-noise characteris-
tics. The output is a push-pull CMOS sꢁuare wave with
symmetrical rise and ꢀall times. In addition, the DS4026
is designed to provide a maximum ꢀreꢁuency deviation
oꢀ less than ±4.6ppm over 20 years. The device also
♦ SqFꢋꢂnrꢄMtqꢀꢅm±ꢇꢄPiꢀmSꢃmPꢂnkꢂDr
♦ Pbm Frr/RtHSm°tp1ꢍiꢂꢀꢅ
2
provides an I C interꢀace to allow pushing and pulling
Pin Configuration
oꢀ the output ꢀreꢁuency ꢂy a minimum oꢀ ±8ppm
(±5ppm ꢀor ±0MHz) with typical ±ppꢂ resolution.
TOP VIEW
The DS4026 implements a temperature-to-voltage con-
version with a nonlinear relationship. The output ꢀrom
the temperature-to-voltage converter is used to drive
the voltage-controlled crystal oscillator to compensate
ꢀor ꢀreꢁuency change.
+
GNDA
1
2
3
4
5
6
7
8
16 V
CCD
V
REF
15 FOUT
14 GNDD
13 SCL
12 SDA
11 GND
10 N.C.
V
CC
The device implements an on-chip temperature sensor
lookup taꢂle, and a digital-to-analog converter (DAC) to
V
OSC
DS4026
2
GNDOSC
N.C.
adjust the ꢀreꢁuency. An I C interꢀace used to commu-
nicate with the DS4026 perꢀorms temperature readings
and ꢀreꢁuency push-pull.
N.C.
Applications
N.C.
9
N.C.
Reꢀerence Clock Generation
Telecom/Datacom/SATCOM
Wireless
Test and Measurement
Ordering Information
OUTPUT (f )
(MHz, CMOS)
C
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
0°C to +70°C
-40°C to +85°C
0°C to +70°C
10.00
10.00
12.80
12.80
16 SO
16 SO
16 SO
16 SO
DS4026-ACC
DS4026-ACN
DS4026-BCC
DS4026-BCN
DS4026S+ACC
DS4026S+ACN
DS4026S+BCC
DS4026S+BCN
-40°C to +85°C
DS4026S+ECC
DS4026S+ECN
DS4026S+FCC
DS4026S+FCN
0°C to +70°C
-40°C to +85°C
0°C to +70°C
16.80
16.80
16 SO
16 SO
16 SO
16 SO
DS4026-ECC
DS4026-ECN
DS4026-FCC
DS4026-FCN
16.384
16.384
-40°C to +85°C
ꢃFdrFiꢀDmIꢀꢋtFpꢂꢅitꢀmntꢀꢅiꢀqrdmꢂꢅmrꢀdmtꢋmdꢂꢅꢂmshrrꢅ.
+Denotes a lead-ꢀree package.
*The top mark will include a “+” ꢀor a lead-ꢀree/RoHS-compliant device.
________________________________________________________________ MꢂxipmIꢀꢅrDFꢂꢅrdmPFtdqnꢅs
±
tFm1FiniꢀD,mdrꢍiOrFc,mꢂꢀdmtFdrFiꢀDmiꢀꢋtFpꢂꢅitꢀ,m1ꢍrꢂsrmntꢀꢅꢂnꢅmMꢂxipmꢈiFrnꢅmꢂꢅm±ꢄ+++ꢄꢇ29ꢄ-ꢇ-2,
tFmOisiꢅmMꢂxip’smwrbsiꢅrmꢂꢅmwww.pꢂxipꢄin.ntp.
10MHz to 51.84MHz TCXO
ꢁBSꢃLUTEmMꢁXIMUMmRꢁTINGS
Voltage Range on V
V
, and V
Operating Temperature Range (noncondensing)....-40°C to +85°C
Storage Temperature Range...............................-40°C to +85°C
Soldering Temperature...........................Reꢀer to the IPC/JEDEC
J-STD-020 Speciꢀication.
CC CCD
OSC
,
Relative to Ground..............................................-0.3V to +3.8V
Voltage Range on SDA, SCL, and FOUT
Relative to Ground...................................-0.3V to (V
+ 0.3V)
CC
Stresses ꢂeyond those listed under “Aꢂsolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and ꢀunctional
operation oꢀ the device at these or any other conditions ꢂeyond those indicated in the operational sections oꢀ the speciꢀications is not implied. Exposure to
aꢂsolute maximum rating conditions ꢀor extended periods may aꢀꢀect device reliaꢂility.
DS4026
RE°ꢃMMENꢈEꢈmꢈ°mꢃPERꢁTINGm°ꢃNꢈITIꢃNSm
(T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
Power-Supply Voltage
Oscillator Power Supply
Driver Power Supply
SYMBOL
CONDITIONS
MIN
TYP
3.3
3.3
3.3
MAX
3.465
3.465
3.465
UNITS
V
CC
3.135
3.135
3.135
V
V
V
V
OSC
CCD
V
ꢈ°mELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Notes ±, 2, 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Active-Supply Current
I
(Note 4)
1.5
2.5
mA
CC
CC
FOUT CMOS output on, CL = 10pF,
frequency < 25MHz
3
5
2
3
4
9
3
5
Oscillator Active-Supply
OSC
I
mA
mA
OSC
Current
FOUT CMOS output on, CL = 10pF,
frequency ꢀ 25MHz
FOUT CMOS output on, CL = 10pF,
frequency < 25MHz
V
CCD
Driver Active-Supply
I
CCD
Current
FOUT CMOS output on, CL = 10pF,
frequency ꢀ 25MHz
SCL Input Leakage
SDA Leakage
I
-1
-1
+1
+1
μA
μA
LI
I
Output off
LO
0.7 x
V
CC
+ 0.3
SCL, SDA High Input Voltage
SCL, SDA Low Input Voltage
V
V
V
IH
V
CC
+0.3 x
V
-0.3
2.4
IL
V
CC
SDA Logic 0 Output
I
V
V
V
= 3.0V, V = 0.4V
3
mA
V
OL
CC
OL
FOUT High Output Voltage
FOUT Low Output Voltage
FOUT Rise/Fall Time
FOUT Duty Cycle
V
= 3V, I
= -2mA
OH
OH
CCD
CCD
V
= 3V, I = 2.0mA
0.4
55
V
OL
OL
t /t
R F
(0.1 x V
) - (0.9 x V
(Note 5)
)
CCD
2
ns
%
CCD
t
0.5 x V
45
D
CCD
2
_______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
ꢁ°mELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S—T°Xꢃ
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note ±)
A
PARAMETER
SYMBOL
ꢀf/f
CONDITIONS
CL = 10pF to ground
MIN
TYP
MAX
UNITS
Frequency Stability vs.
Temperature
f
C
f
C
+ 1ppm
f
C
ppm
C
– 1ppm
ꢀf
VOLTAGE
Frequency Stability vs. Voltage
CL = 10pF to ground, +25°C
(Note 5)
-2
+2
ppm/V
ppm
/f
C
First Year
Aging
-1
-2
8
+1
+2
ꢀf
/f
AGING C
Years 2–20
Except 10MHz
10MHz
15
10
1
Frequency Pull
Range
FTUNEH = 3Fh and FTUNEL = FFh;
FTUNEH = 40h and FTUNEL = 00h at +25°C
ꢀf/f
ppm
ppb
C
5
Frequency Pull Resolution
ꢀf
/f
RES C
ꢁ°mELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S—STRꢁTUMm3
(V
CC
= +3.±35V to +3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note ±)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STRATUM 3 FREQUENCY STABILITY
Frequency Stability vs.
Temperature
ꢀf
/f
-40°C to +85°C (Note 6)
T = +25°C, 3°C and V = 3.3V
C A
-0.28
-0.8
+0.28
+0.8
ppm
ppm
ppm
TEMP C
Initial Tolerance and Reflow
ꢀf
/f
INITIAL
DD
ꢀf
V = 3.3V 5%, C = 10pF to ground,
CC L
VOLTAGE
Frequency Stability vs. Voltage
-0.33
+0.33
/f
C
+25°C (Note 7)
Frequency Stability vs.
Aging/20 Years
ꢀf
/f
f
= Nominal (Note 8)
-3.0
-0.1
+3.0
+0.1
ppm
ppm
ppm
ppm
AGING C
C
Frequency Stability vs. Load
Change
ꢀf
/f
Load = 10pF 5%, +25°C (Note 5)
LOAD C
Operating temperature, load, supply, and
initial tolerance, aging (20 years) (Notes 5, 8)
Free-Run Accuracy
-4.6
+4.6
ꢀf
24HOURS
Holdover Stability (24 Hours)
24-hour elapsed time (Notes 5, 9)
-0.32
+0.32
/f
C
PHꢁSEmNꢃISE
PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, 3.3V)
OFFSET (MHz)
12.80
10Hz
100Hz
-130.16
-125.12
-120.76
-120.06
-115.44
-120.39
-134.83
-128.53
-126.20
-119.45
1kHz
10kHz
-150.84
-146.87
-150.96
-150.59
-151.59
-151.14
-150.84
-150.78
-151.90
-150.33
100kHz
-151.71
-151.69
-151.18
-152.50
-152.37
-153.21
-151.25
-152.72
-152.28
-150.34
1MHz
-88.41
-82.63
-83.71
-79.01
-80.80
-74.09
-92.52
-87.44
-89.6
-147.84
-145.03
-145.44
-141.75
-141.17
-142.33
-147.22
-147.67
-146.88
-143.08
-151.87
-151.52
-151.45
-153.06
-153.00
-153.94
-150.84
-151.75
-151.93
-150.67
19.44
20.00
CARRIER
FREQUENCY
38.88
40.00
51.84
10.0
16.384
16.8
24.0
-83.98
_______________________________________________________________________________________
3
10MHz to 51.84MHz TCXO
TEMPERꢁTUREmSENSꢃRmELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note ±)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Temperature Sensor Accuracy
ꢀT
-3
+3
°C
Temperature Sensor Conversion
Time
t
11
12
ms
CONVT
DS4026
Temperature Sensor Resolution
N2
Bits
2
ꢁ°mELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S—I °mSERIꢁLmINTER ꢁ°E
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
100
UNITS
Standard mode
Fast mode
0
100
SCL Clock Frequency
f
kHz
SCL
BUF
400
Standard mode
Fast mode
4.7
Bus Free Time Between STOP
and START Conditions
t
μs
μs
μs
μs
μs
ns
μs
ns
ns
μs
pF
1.3
Standard mode
Fast mode
4.0
Hold Time (Repeated) START
Condition (Note 10)
t
HD:STA
0.6
Standard mode
Fast mode
4.7
Low Period of SCL Clock
High Period of SCL Clock
t
LOW
1.3
Standard mode
Fast mode
4.0
t
HIGH
0.6
Standard mode
Fast mode
0
0.9
0.9
Data Hold Time
(Notes 11, 12)
t
t
t
HD:DAT
SU:DAT
SU:STA
0
Standard mode
Fast mode
250
Data Setup Time (Note 13)
START Setup Time
100
Standard mode
Fast mode
4.7
0.6
Standard mode
Fast mode
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
4.7
1000
300
300
300
Rise Time of Both SDA and SCL
Signals (Note 14)
B
t
R
B
B
B
Standard mode
Fast mode
Fall Time of Both SDA and SCL
Signals (Note 14)
t
F
Standard mode
Fast mode
Setup Time for STOP Condition
t
SU:STO
0.6
Pin Capacitance SDA, SCL
(Note 5)
C
10
I/O
-
_______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
2
ꢁ°mELE°TRI°ꢁLm°HꢁRꢁ°TERISTI°S—I °mSERIꢁLmINTER ꢁ°Emꢊntꢀꢅiꢀqrdꢌ
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Capacitive Load for Each Bus
Line (Note 14)
C
400
pF
B
Pulse Width of Spikes That Must
Be Suppressed by the Input
Filter
t
Fast mode
30
ns
SP
Ntꢅrm±: Typical values are at +25°C, nominal supply voltages, unless otherwise indicated.
Ntꢅrm2: Voltages reꢀerenced to ground.
Ntꢅrm3: Limits at -40°C are guaranteed ꢂy design and not production tested.
2
Ntꢅrm-: Speciꢀied with I C ꢂus inactive.
Ntꢅrm8: Guaranteed ꢂy design and not production tested.
Ntꢅrmꢇ: Freꢁuency staꢂility vs. temperature is deꢀined as (Δꢀ
- Δꢀ )/2.
MIN
MAX
Ntꢅrm7: Maximum power-supply variations to meet the speciꢀication are 5%.
Ntꢅrm+: Crystal vendor speciꢀication.
Ntꢅrm9: Holdover is deꢀined as (ꢀ
- ꢀ
)/2 as measured within a 24-hour period. Warmup time = ± hour.
MAX MIN
Ntꢅrm±4: Aꢀter this period, the ꢀirst clock pulse is generated.
Ntꢅrm±±: A device must internally provide a hold time oꢀ at least 300ns ꢀor the SDA signal (reꢀerred to the V
to ꢂridge the undeꢀined region oꢀ the ꢀalling edge oꢀ SCL.
oꢀ the SCL signal)
IH(MIN)
Ntꢅrm±2: The maximum t
need only ꢂe met iꢀ the device does not stretch the low period (t
) oꢀ the SCL signal.
LOW
HD:DAT
Ntꢅrm±3: A ꢀast-mode device can ꢂe used in a standard-mode system, ꢂut the reꢁuirement that t
≥ 250ns must then ꢂe met.
SU:DAT
This is automatically the case iꢀ the device does not stretch the low period oꢀ the SCL signal. Iꢀ such a device does not
stretch the low period oꢀ the SCL signal, it must output the next data ꢂit to the SDA line t
±250ns ꢂeꢀore the SCL line is released.
+ t
= ±000 + 250 =
R(MAX)
SU:DAT
Ntꢅrm±-: C —total capacitance oꢀ one ꢂus line in pF.
B
2
Data Transfer on I C Serial Bus
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
R
t
F
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
SU:STO
t
REPEATED
START
SU:DAT
STOP
START
t
HD:DAT
_______________________________________________________________________________________
8
10MHz to 51.84MHz TCXO
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
ACTIVE-SUPPLY CURRENT
vs. DRIVER POWER SUPPLY
ACTIVE-SUPPLY CURRENT
vs. OSCILLATOR POWER SUPPLY
ACTIVE-SUPPLY CURRENT
vs. POWER-SUPPLY CURRENT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.6
2
10.0
8.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
51.84
51.84
12.8
51.84
6.0
4.0
12.8
12.8
2.0
-0.1
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
V
V
V
OSC
CCD
CC
FREQUENCY vs. FTUNE
PHASE NOISE (TYP)
FREQUENCY vs. TEMPERATURE
20
15
20
18
15
13
10
8
5
3
0
-3
-5
-8
-10
-13
-5.0
-30.0
DCOMP = 1
51.84
10
5
-55.0
51.84MHz
12.8
0
19.44MHz
-80.0
-5
DCOMP = 0
-105.0
-130.0
-155.0
-180.0
-10
-15
-20
-25
-30
38.88MHz
12.8MHz
100
-15
4000h
000h
3FFFh
10
1000
10,000 100,000 1,000,000
-20
40
TEMPERATURE (°C)
60
80
-40
0
20
VC (V)
OFFSET (Hz)
ꢇ
_______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
Pin Description
PIN
1
NAME
FUNCTION
GNDA
Ground for DAC
2
V
REF
Voltage Reference Output. This pin must be decoupled with a 100μF ceramic capacitor to ground.
Power Supply for Digital Control and Temperature Sensor. This pin must be decoupled with a
100nF capacitor to ground.
3
V
CC
4
5
V
Power Supply for Oscillator Circuit. This pin must be decoupled with a 0.1μF capacitor to ground.
Ground for Oscillator Circuit
OSC
GNDOSC
N.C.
6–10
11
No Connection. Must be connected to ground.
GND
Ground for Digital Control, Temperature Sensor, and Controller Substrate
2
Serial Data Input/Output. SDA is the data input/output for the I C interface. This open-drain pin
requires an external pullup resistor.
12
13
SDA
SCL
2
Serial Clock Input. SCL is the clock input for the I C Interface and is used to synchronize data
movement on the serial interface.
14
15
GNDD
FOUT
Ground for Oscillator Output Driver
Frequency Output, CMOS Push-Pull
Power Supply for Oscillator Output Driver. This pin must be decoupled with a 0.1μF capacitor to
16
V
CCD
ground. A 20ꢀ resistor must be placed in series between the power supply and V
.
CCD
20Ω
GNDA
V
CCD
100μF 20%
CERAMIC
0.1μF
3.3V 5%
FOUT
V
GNDD
REF
CC
DS4026
V
SCL
SDA
0.1μF
3.3V
V
OSC
0.1μF
3.3V
GNDOSC
N.C.
GND
N.C.
N.C.
N.C.
N.C.
Figure ±. Typical Operating Circuit
_______________________________________________________________________________________
7
10MHz to 51.84MHz TCXO
V
CC
V
CC
EEPROM
ARRAY
TEMP
SENSOR
A/D
DS4026
GND
GND
V
CC
V
CC
V
REF
SCL
SDA
2
I C
CONTROLLER
DAC
INTERFACE
DS4026
GNDA
GND
GND
V
CCD
V
OSC
CMOS
BUFFER
FOUT
GNDOSC
GNDD
Figure 2. Functional Diagram
• Controller to read the temperature, control lookup
taꢂle, and adjust the DAC input
Detailed Description
The DS4026 is a TCXO capaꢂle oꢀ operating at 3.3V
±5%, and it allows digital tuning oꢀ the ꢀundamental ꢀre-
ꢁuency. The device is caliꢂrated in the ꢀactory to
achieve an accuracy oꢀ ±±ppm over the industrial tem-
perature range, and its minimum pullaꢂility is ±8ppm
with a typical resolution oꢀ ±ppꢂ (typ) per LSB.
• DAC output to adjust the capacitive load
2
• I C interꢀace to communicate with the chip
The oscillator ꢂlock consists oꢀ an ampliꢀier and variaꢂle
capacitor in a Pierce crystal oscillator with a crystal res-
onator oꢀ ꢀundamental mode. The oscillator ampliꢀier is a
single transistor ampliꢀier and its transconductance is
temperature compensated. The variaꢂle capacitor is
adjusted ꢂy the DAC to provide temperature compensa-
tion. With the FTUNEH and FTUNEL registers, a minimum
pullaꢂility oꢀ ±8ppm (±5ppm ꢀor ±0MHz) is achieved with
a typical resolution oꢀ ±ppꢂ (typ) per LSB.
The DS4026 contains the ꢀollowing ꢂlocks:
• Oscillator ꢂlock with variaꢂle capacitor ꢀor compen-
sation
• Output driver ꢂlock
• Temperature sensor
+
_______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
The output driver is a CMOS sꢁuare-wave output with
symmetrical rise and ꢀall time.
Address Map
Disable Compensation Update (DCOMP)
DCOMP is ꢂit 7 oꢀ the ꢀreꢁuency tuning register (see
the Freꢁuency Tuning Register (00h–0±h), POR = 00h
taꢂle). When set to logic ±, this ꢂit’s temperature-com-
pensation ꢀunction is disaꢂled. This disaꢂling prevents
the variaꢂle capacitor in the oscillator ꢂlock ꢀrom
changing. However, the temperature register still per-
ꢀorms temperature conversions. The temperature trim
code ꢀrom the last temperature conversion ꢂeꢀore
DCOMP is enaꢂled is used ꢀor temperature compensa-
tion. The FTUNE registers are still ꢀunctional when
DCOMP is disaꢂled.
The temperature sensor provides a ±2-ꢂit temperature
reading with a resolution oꢀ 0.0625°C. The sensor is in
continuous conversion mode. Iꢀ DCOMP is set, conver-
sions continue ꢂut temperature updates are inhiꢂited.
The controller coordinates the conversion oꢀ tempera-
ture into digital codes. When the temperature reading is
diꢀꢀerent ꢀrom the previous one or the ꢀreꢁuency tuning
register is changed, the controller looks up the two cor-
responding capacitance trim codes ꢀrom the lookup
taꢂle at a 0.5°C increment. The trim codes are interpo-
lated to 0.0625°C resolution.
The result is added with the tuning value ꢀrom the ꢀre-
ꢁuency tuning register and loaded into the DAC regis-
ters to adjust voltage output. The monotonic DAC
provides an analog voltage ꢂased on temperature
compensation to drive the variaꢂle capacitor.
The ꢀreꢁuency tuning registers adjust the ꢂase ꢀreꢁuen-
cy. The ꢀreꢁuency tuning value is represented in two’s
complement data. Bit 6 oꢀ FTUNEH is the sign, ꢂit 5 is
the MSB, and ꢂit 0 oꢀ FTUNEL is the LSB (see Taꢂle ±).
When the tuning register low (0±h) is programmed with
a value, the next temperature update cycle sums the
programmed value with the ꢀactory compensated
value. This allows the user to digitally control the ꢂase
The DS4026 operates as a slave device on the serial
ꢂus. Access is oꢂtained ꢂy implementing a START
condition and providing a device identiꢀication code ꢀol-
lowed ꢂy data. Suꢂseꢁuent registers can ꢂe accessed
seꢁuentially until a STOP condition is executed.
2
ꢀreꢁuency using the I C protocol.
These ꢀreꢁuency tuning register ꢂits allow the tuning oꢀ
the ꢂase ꢀreꢁuency. Each ꢂit typically represents
aꢂout ±ppꢂ (typ). For FTUNEH = 3Fh and FTUNEL =
FFh, the device pushes the ꢂase ꢀreꢁuency ꢂy approx-
imately +±5ppm.
Frequency Tuning Register (00h–01h), POR = 00h
ADDRESS
00h
BIT 7
DCOMP
0
BIT 6
Sign
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
Data
0
BIT 2
Data
0
BIT 1
Data
0
BIT 0
Data
0
POR
01h
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
POR
Temperature Register (02h–03h)
ADDRESS
02h
BIT 7
Sign
0
BIT 6
Data
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
BIT 2
BIT 1
BIT 0
Data
Data
Data
Data
POR
0
0
0
0
0
0
0
0
0
0
0
0
03h
Data
0
Data
0
Data
0
Data
0
POR
_______________________________________________________________________________________
9
10MHz to 51.84MHz TCXO
Tꢂbꢍrm±.mRrDisꢅrFmMꢂ1
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FTUNEH
FTUNEL
TREGH
TREGL
BIT 2
BIT 1
BIT 0
FUNCTION
00
01
02
03
DCOMP
SIGN
Frequency Tuning High
Frequency Tuning Low
Temperature MSB
SIGN
DS4026
Temperature LSB
2
Read Mode
I C Serial Data Bus
In the temperature register (see the Temperature
Register (02h–03h) taꢂle), temperature is represented
as a ±2-ꢂit code and is accessiꢂle at location 02h and
03h. The upper 8 ꢂits are at location 02h and the lower
4 ꢂits are in the upper niꢂꢂle oꢀ the ꢂyte at location
03h. Upon power reset, the registers are set to a +25°C
deꢀault temperature and the controller starts a tempera-
ture conversion. The temperature register stores new
temperature readings.
2
The DS4026 supports a ꢂidirectional I C ꢂus and data
transmission protocol. A device that sends data onto
the ꢂus is deꢀined as a transmitter and a device receiv-
ing data is deꢀined as a receiver. The device that con-
trols the message is called a master. The devices that
are controlled ꢂy the master are slaves. The ꢂus must
ꢂe controlled ꢂy a master device that generates the
serial clock (SCL), controls the ꢂus access, and gener-
ates the START and STOP conditions. The DS4026
2
The current temperature is loaded into the (user) tem-
perature registers when a valid I C slave address and
write is received and when a word address is received.
Conseꢁuently, iꢀ the two temperature registers are read
in individual I C transactions, it is possiꢂle ꢀor a tem-
operates as a slave on the I C ꢂus. Connections to the
2
ꢂus are made through the open-drain I/O lines SDA
and SCL. Within the ꢂus speciꢀications, a standard
mode (±00kHz maximum clock rate) and a ꢀast mode
(400kHz maximum clock rate) are deꢀined. The DS4026
works in ꢂoth modes.
2
perature conversion to occur ꢂetween reads, and the
results can ꢂe inaccurate. To prevent this ꢀrom occur-
ring, the registers should ꢂe read using a single, multi-
The ꢀollowing ꢂus protocol has ꢂeen deꢀined (Figure 3):
2
• Data transꢀer can ꢂe initiated only when the ꢂus is
not ꢂusy.
ꢂyte read operation (Figure 5). I C reads do not aꢀꢀect
the internal temperature registers.
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERED
CONDITION
2
Figure 3. I C Data Transꢀer Overview
±4 ______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
• During data transꢀer, the data line must remain staꢂle
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is staꢂle low during the high
period oꢀ the acknowledge-related clock pulse. Oꢀ
course, setup and hold times must ꢂe taken into
account. A master must signal an end oꢀ data to the
slave ꢂy not generating an acknowledge ꢂit on the
last ꢂyte that has ꢂeen clocked out oꢀ the slave. In
this case, the slave must leave the data line high to
enaꢂle the master to generate the STOP condition.
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the ꢀollowing ꢂus conditions have ꢂeen
deꢀined:
Bqsmꢀtꢅmbqsc: Both data and clock lines remain
high.
STꢁRTmdꢂꢅꢂmꢅFꢂꢀsꢋrF: A change in the state oꢀ the
data line ꢀrom high to low, while the clock line is high,
deꢀines a START condition.
Figures 4 and 5 detail how data transꢀer is accom-
2
plished on the I C ꢂus. Depending upon the state oꢀ
STꢃPmdꢂꢅꢂmꢅFꢂꢀsꢋrF: A change in the state oꢀ the
data line ꢀrom low to high, while the clock line is high,
deꢀines a STOP condition.
the R/W ꢂit, two types oꢀ data transꢀer are possiꢂle:
ꢈꢂꢅꢂmꢅFꢂꢀsꢋrFmꢋFtpmꢂmpꢂsꢅrFmꢅFꢂꢀspiꢅꢅrFmꢅtmꢂmsꢍꢂOr
FrnriOrF.mThe ꢀirst ꢂyte transmitted ꢂy the master is
the slave address. Next ꢀollows a numꢂer oꢀ data
ꢂytes. The slave returns an acknowledge (ACK) ꢂit
aꢀter each received ꢂyte.
ꢈꢂꢅꢂmOꢂꢍid: The state oꢀ the data line represents valid
data when, aꢀter a START condition, the data line is
staꢂle ꢀor the duration oꢀ the high period oꢀ the clock
signal. The data on the line must ꢂe changed during
the low period oꢀ the clock signal. There is one clock
pulse per ꢂit oꢀ data.
ꢈꢂꢅꢂmꢅFꢂꢀsꢋrFmꢋFtpmꢂmsꢍꢂOrmꢅFꢂꢀspiꢅꢅrFmꢅtmꢂmpꢂsꢅrF
FrnriOrF.mThe ꢀirst ꢂyte (the slave address) is trans-
mitted ꢂy the master. The slave then returns an
acknowledge ꢂit. Next ꢀollows a numꢂer oꢀ data
ꢂytes transmitted ꢂy the slave to the master. The
master returns an acknowledge ꢂit aꢀter all received
ꢂytes other than the last ꢂyte. At the end oꢀ the last
received ꢂyte, a not acknowledge (NACK) is
returned.
Each data transꢀer is initiated with a START condition
and terminated with a STOP condition. The numꢂer
oꢀ data ꢂytes transꢀerred ꢂetween the START and the
STOP conditions is not limited, and is determined ꢂy
the master device. The inꢀormation is transꢀerred
ꢂyte-wise and each receiver acknowledges with a
ninth ꢂit.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
ꢀer is ended with a STOP condition or with a repeat-
ed START condition. Because a repeated START
condition is also the ꢂeginning oꢀ the next serial
transꢀer, the ꢂus is not released.
ꢁnkꢀtwꢍrdDr:m Each receiving device, when
addressed, is oꢂliged to generate an acknowledge
(ACK) aꢀter the reception oꢀ each ꢂyte. The master
device must generate an extra clock pulse that is
associated with this acknowledge ꢂit.
<SLAVE
ADDRESS>
<SLAVE
ADDRESS>
<WORD
<DATA (n)>
<DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)>
S 1000001 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S 1000001 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S = START
DATA TRANSFERRED
S = START
DATA TRANSFERRED
A = ACKNOWLEDGE
(X + 1 BYTES + ACKNOWLEDGE)
P = STOP
(X + 1 BYTES + ACKNOWLEDGE)
A = ACKNOWLEDGE
NOTE: LAST DATA BYTE IS FOLLOWED BY
P = STOP
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h
A NOT ACKNOWLEDGE (A) SIGNAL
A = NOT ACKNOWLEDGE
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h
Figure 4. Slave Receiver Mode (Write Mode)
Figure 5. Slave Transmitter Mode (Read Mode)
______________________________________________________________________________________ ±±
10MHz to 51.84MHz TCXO
The DS4026 can operate in the ꢀollowing two modes:
SꢍꢂOrmꢅFꢂꢀspiꢅꢅrFmptdrmꢊFrꢂdmptdrꢌ: The ꢀirst ꢂyte
is received and handled as in the slave receiver
mode. However, in this mode, the direction ꢂit indi-
cates that the transꢀer direction is reversed. Serial
data is transmitted on SDA ꢂy the DS4026 while the
serial clock is input on SCL. START and STOP condi-
tions are recognized as the ꢂeginning and end oꢀ a
serial transꢀer. Address recognition is perꢀormed ꢂy
hardware aꢀter reception oꢀ the slave address and
direction ꢂit. The slave address ꢂyte is the ꢀirst ꢂyte
received aꢀter the master generates a START condi-
tion. The slave address ꢂyte contains the 7-ꢂit
DS4026 address, which is ±00000±, ꢀollowed ꢂy the
direction ꢂit (R/W), which is ± ꢀor a read. Aꢀter receiv-
ing and decoding the slave address ꢂyte, the
DS4026 outputs an acknowledge on SDA. The
DS4026 then ꢂegins to transmit data starting with the
register address pointed to ꢂy the register pointer. Iꢀ
the register pointer is not written to ꢂeꢀore the initia-
tion oꢀ a read mode, the ꢀirst address that is read is
the last one stored in the register pointer. The
DS4026 must receive a not acknowledge to end a
read.
SꢍꢂOrmFrnriOrFmptdrmꢊwFiꢅrmptdrꢌ: Serial data and
clock are received through SDA and SCL. Aꢀter each
ꢂyte is received, an acknowledge ꢂit is transmitted.
START and STOP conditions are recognized as the
ꢂeginning and end oꢀ a serial transꢀer. Address
recognition is perꢀormed ꢂy hardware aꢀter reception
oꢀ the slave address and direction ꢂit. The slave
address ꢂyte is the ꢀirst ꢂyte received aꢀter the mas-
ter generates a START condition. The slave address
ꢂyte contains the 7-ꢂit DS4026 address, which is
±00000±, ꢀollowed ꢂy the direction ꢂit (R/W), which is
0 ꢀor a write. Aꢀter receiving and decoding the slave
address ꢂyte, the DS4026 outputs an acknowledge
on SDA. Aꢀter the DS4026 acknowledges the slave
address and write ꢂit, the master transmits a word
address to the DS4026. This sets the register pointer
on the DS4026, with the DS4026 acknowledging the
transꢀer. The master can then transmit zero or more
ꢂytes oꢀ data, with the DS4026 acknowledging each
ꢂyte received. The register pointer increments aꢀter
each data ꢂyte is transꢀerred. The master generates
a STOP condition to terminate the data write.
DS4026
±2 ______________________________________________________________________________________
10MHz to 51.84MHz TCXO
DS4026
Ordering Information (continued)
OUTPUT (f )
C
(MHz, CMOS)
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
DS4026S+HCC
DS4026S+HCN
DS4026S+JCC
DS4026S+JCN
DS4026S+MCC
DS4026S+MCN
DS4026S+PCC
DS4026S+PCN
DS4026S+QCC
DS4026S+QCN
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
19.44
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
DS4026-HCC
DS4026-HCN
DS4026-JCC
DS4026-JCN
DS4026-MCC
DS4026-MCN
DS4026-PCC
DS4026-PCN
DS4026-QCC
DS4026-QCN
19.44
20.00
20.00
38.88
38.88
40.00
40.00
51.84
51.84
DS4026S+RCC
0°C to +70°C
24.00
24.00
16 SO
16 SO
DS4026-RCC
DS4026-RCN
DS4026S+RCN
-40°C to +85°C
+Denotes a lead-ꢀree package.
*The top mark will include a “+” ꢀor a lead-ꢀree/RoHS-compliant device.
Ordering Information—Stratum 3
OUTPUT (f )
(MHz, CMOS)
C
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
DS4026S3+ACN
DS4026S3+BCN
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10.00
12.80
19.20
20.00
16 SO
16 SO
16 SO
16 SO
DS4026S3-ACN
DS4026S3-BCN
DS4026S3-GCN
DS4026S3-JCN
DS4026S3+GCN
DS4026S3+JCN
+Denotes a lead-ꢀree package.
*The top mark will include a “+” ꢀor a lead-ꢀree/RoHS-compliant device.
Chip Information
TRANSISTOR COUNT: 77, 7±2
Package Information
For the latest package outline inꢀormation, go to
www.pꢂxipꢄin.ntp/ꢈꢂꢍꢍꢂsPꢂnkIꢀꢋt.
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
Pꢁ°KꢁGEmTꢉPE Pꢁ°KꢁGEm°ꢃꢈE ꢈꢃ°UMENTmNꢃ.
±6 SO (300 mils)
—
8ꢇꢄG-449ꢄ44±
______________________________________________________________________________________ ±3
10MHz to 51.84MHz TCXO
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
2/07
Initial release.
—
Changed device from 12.8MHz to 51.84MHz to 10MHz to 51.84MHz; added
5ppm (min, typ) digital frequency tuning for the 10MHz option; added new
ordering information and phase noise data; changed capacitor value
designators from 10nF to 0.1μF; changed push-pull value from 15ppm (typ) to
8ppm (min).
DS4026
1
2
9/07
4/08
1–12
Changed maximum frequency deviation from over 10 years to over 20 years;
Added Stratum 3 electrical characteristics table; added ordering information for
Stratum 3 parts.
1, 5, 13
Maxim cannot assume responsiꢂility ꢀor use oꢀ any circuitry other than circuitry entirely emꢂodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and speciꢀications without notice at any time.
±- ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark oꢀ Maxim Integrated Products, Inc.
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