DS4026S+RCC [MAXIM]
CMOS Output Clock Oscillator, 10MHz Min, 51.84MHz Max, 24MHz Nom, ROHS COMPLIANT, SOP-16;
| 型号： | DS4026S+RCC |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | CMOS Output Clock Oscillator, 10MHz Min, 51.84MHz Max, 24MHz Nom, ROHS COMPLIANT, SOP-16 石英晶振 温度补偿晶振 |
| 文件： | 总12页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 2/07
12.8MHz to 51.84MHz TCXO
DS4026
General Description
Features
The DS4026 is a temperature-compensated crystal
oscillator (TCXO) that provides ±±ppm ꢀreꢁuency sta-
bility over the -40°C to +85°C industrial temperature
range. Each device is ꢀactory calibrated over tempera-
ture to achieve the ±±ppm ꢀreꢁuency stability. Standard
ꢀreꢁuencies ꢀor the device include ±2.8, ±9.44, 20.0,
38.88, 40.0, and 5±.84MHz. Contact the ꢀactory ꢀor cus-
tom ꢀreꢁuencies.
♦
1ppm Frequency Accuracy Over -40°C to +85°C
♦ Standard Frequencies: 12.8, 19.44, 20.0, 38.88,
40.0, 51.84MHz
♦ Maximum 4.6ppm Deviation Over 10 Years
♦ Minimum 8ppm Digital Frequency Tuning
Through I2C Interface
The DS4026 provides excellent phase-noise characteris-
tics. The output is a push-pull CMOS sꢁuare wave with
symmetrical rise and ꢀall times. In addition, the DS4026 is
designed to provide a maximum ꢀreꢁuency deviation oꢀ
less than ±4.6ppm over ±0 years. The device also pro-
vides an I2C interꢀace to allow pushing and pulling oꢀ the
output ꢀreꢁuency by a minimum oꢀ ±±5ppm typical with
typical ±ppb resolution.
♦ Surface-Mount 16-Pin SO Package
♦ Pb Free/RoHS Compliant
Pin Configuration
TOP VIEW
The DS4026 implements a temperature-to-voltage con-
version with a nonlinear relationship. The output ꢀrom the
temperature-to-voltage converter is used to drive the volt-
age-controlled crystal oscillator to compensate ꢀor ꢀre-
ꢁuency change.
GNDA
1
2
3
4
5
6
7
8
16 V
CCD
V
REF
15 FOUT
14 GNDD
13 SCL
12 SDA
11 GND
10 N.C.
V
CC
The device implements an on-chip temperature sensor
lookup table, and a digital-to-analog converter (DAC) to
adjust the ꢀreꢁuency. An I2C interꢀace used to communi-
cate with the DS4026 perꢀorms temperature readings and
ꢀreꢁuency push-pull.
V
OSC
DS4026
GNDOSC
N.C.
N.C.
Applications
N.C.
9
N.C.
Reꢀerence Clock Generation
Telecom/Datacom/SATCOM
Wireless
SO
Test and Measurement
Ordering Information
OUTPUT (f
(MHz, CMOS)
)
NOM
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
12.8
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
DS4026-BCC
DS4026-BCN
DS4026-HCC
DS4026-HCN
DS4026-JCC
DS4026-JCN
DS4026S+BCC
DS4026S+BCN
DS4026S+HCC
DS4026S+HCN
DS4026S+JCC
DS4026S+JCN
12.8
19.44
19.44
20.0
20.0
Ordering Information continued at end of data sheet.
+Lead-ꢀree package.
*The top mark will include a “+” ꢀor a lead-ꢀree/RoHS-compliant device.
______________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12.8MHz to 51.84MHz TCXO
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
V
, and V
Operating Temperature Range (noncondensing)....-40°C to +85°C
Storage Temperature Range.............................-55°C to +±25°C
Soldering Temperature………………………….See IPC/JEDEC
J-STD-020 Speciꢀication
CC CCD
OSC
,
Relative to Ground..............................................-0.3V to +3.8V
Voltage Range on SDA, SCL, and FOUT
Relative to Ground...................................-0.3V to (V
+ 0.3V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and ꢀunctional
operation oꢀ the device at these or any other conditions beyond those indicated in the operational sections oꢀ the speciꢀications is not implied. Exposure to
absolute maximum rating conditions ꢀor extended periods may aꢀꢀect device reliability.
DS4026
RECOMMENDED DC OPERATING CONDITIONS
(T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
Power-Supply Voltage
Oscillator Power Supply
Driver Power Supply
SYMBOL
CONDITIONS
MIN
TYP
3.3
MAX
3.465
3.465
3.465
UNITS
V
3.±35
3.±35
3.±35
V
V
V
CC
V
OSC
V
CCD
3.3
3.3
DC ELECTRICAL CHARACTERISTICS (Note 1)
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Notes 2, 3)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Active-Supply Current
I
(Note 4)
±.5
2.5
mA
CC
CC
FOUT CMOS output on, CL = ±0pF,
ꢀreꢁuency < 25MHz
3
5
2
3
4
9
3
5
Oscillator Active-Supply
OSC
I
mA
mA
OSC
Current
FOUT CMOS output on, CL = ±0pF,
ꢀreꢁuency ≥ 25MHz
FOUT CMOS output on, CL = ±0pF,
ꢀreꢁuency < 25MHz
V
Driver Active-Supply
CCD
I
CCD
Current
FOUT CMOS output on, CL = ±0pF,
ꢀreꢁuency ≥ 25MHz
SCL Input Leakage
SDA Leakage
I
-±
-±
+±
+±
µA
µA
LI
I
Output oꢀꢀ
LO
0.7 x
V
CC
+ 0.3
SCL, SDA High Input Voltage
SCL, SDA Low Input Voltage
V
V
V
IH
V
CC
+0.3 x
V
-0.3
2.4
IL
V
CC
SDA Logic 0 Output
I
V
V
V
= 3.0V, V = 0.4V
3
mA
V
OL
CC
OL
FOUT High Output Voltage
FOUT Low Output Voltage
FOUT Rise/Fall Time
FOUT Duty Cycle
V
= 3V, I
= -2mA
OH
CCD
CCD
OH
V
= 3V, I = 2.0mA
0.4
55
V
OL
OL
t /t
R F
(0.± x V
) - (0.9 x V
)
CCD
2
ns
%
CCD
CCD
t
0.5 x V
(Note 5)
45
D
2
_____________________________________________________________________
12.8MHz to 51.84MHz TCXO
DS4026
AC ELECTRICAL CHARACTERISTICS (Note 1)
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
ꢀf /T
CONDITIONS
CL = 10pF to ground
MIN
TYP
MAX
UNITS
Frequency Stability vs.
Temperature
f
f
NOM
+ 1ppm
NOM
f
ppm
1
A
NOM
– 1ppm
Frequency Stability vs. Voltage
Aging, First Year
ꢀf /V
CL = 10pF
(Note 5)
-2
-1
-2
+2
+1
+2
ppm/V
ppm
1
ꢀf /Yr
1
Aging, Years 2–15
ꢀf /Yr
1
(Note 5)
ppm
FTUNEH = 3Fh and FTUNEL = FFh;
FTUNEH = 40h and FTUNEL = 00h
Frequency Pull Range
ꢀf
8
15
1
ppm
ppb
Frequency Pull Resolution
ꢀf
RES
PHASE NOISE
PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, 3.3V)
OFFSET (MHz)
10Hz
100Hz
-130.16
-125.12
1kHz
10kHz
-150.84
-146.87
100kHz
-151.71
-151.69
1MHz
12.80
-88.41
-82.63
-147.84
-145.03
-151.87
-151.52
19.44
20.00
38.88
40.00
51.84
CARRIER
FREQUENCY
-79.01
-80.80
-74.09
-120.06
-115.44
-120.39
-141.75
-141.17
-142.33
-150.59
-151.59
-151.14
-152.50
-152.37
-153.21
-153.06
-153.00
-153.94
_____________________________________________________________________
3
12.8MHz to 51.84MHz TCXO
TEMPERATURE SENSOR ELECTRICAL CHARACTERISTICS (Note 1)
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Temperature Sensor Accuracy
ꢀT
-3
+3
°C
Temperature Sensor Conversion
Time
t
11
12
ms
CONVT
DS4026
Temperature Sensor Resolution
N2
Bits
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
±00
UNITS
Standard mode
Fast mode
0
±00
SCL Clock Freꢁuency
ꢀ
kHz
SCL
400
Standard mode
Fast mode
4.7
Bus Free Time Between STOP
and START Conditions
t
µs
µs
µs
µs
µs
ns
µs
ns
ns
BUF
±.3
Standard mode
Fast mode
4.0
Hold Time (Repeated) START
Condition (Note 6)
t
HD:STA
0.6
Standard mode
Fast mode
4.7
Low Period oꢀ SCL Clock
High Period oꢀ SCL Clock
t
LOW
±.3
Standard mode
Fast mode
4.0
t
HIGH
0.6
Standard mode
Fast mode
0
0.9
0.9
Data Hold Time
(Notes 7, 8)
t
HD:DAT
0
Standard mode
Fast mode
250
Data Setup Time (Note 9)
Start Setup Time
t
SU:DAT
±00
Standard mode
Fast mode
4.7
t
SU:STA
0.6
Standard mode
Fast mode
20 + 0.±C
20 + 0.±C
20 + 0.±C
20 + 0.±C
±000
300
300
300
B
Rise Time oꢀ Both SDA and SCL
Signals (Note ±0)
t
R
B
B
B
Standard mode
Fast mode
Fall Time oꢀ Both SDA and SCL
Signals (Note ±0)
t
F
4
_____________________________________________________________________
12.8MHz to 51.84MHz TCXO
DS4026
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3.±35V to 3.465V, T = -40°C to +85°C, unless otherwise noted.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
4.7
TYP
MAX
UNITS
Standard mode
Fast mode
Setup Time ꢀor STOP Condition
t
µs
SU:STO
0.6
Pin Capacitance SDA, SCL
(Note 5)
C
±0
pF
pF
ns
I/O
Capacitive Load ꢀor Each Bus
Line (Note ±0)
C
400
B
Pulse Width oꢀ Spikes That Must
Be Suppressed by the Input Filter
t
SP
Fast mode
30
Note 1: Typical values are at +25°C, nominal supply voltages, unless otherwise indicated.
Note 2: Voltages reꢀerenced to ground.
Note 3: Limits at -40°C are guaranteed by design and not production tested.
2
Note 4: Speciꢀied with I C bus inactive.
Note 5: Guaranteed by design and not production tested.
Note 6: Aꢀter this period, the ꢀirst clock pulse is generated.
Note 7: A device must internally provide a hold time oꢀ at least 300ns ꢀor the SDA signal (reꢀerred to the V
oꢀ the SCL signal)
IH(MIN)
to bridge the undeꢀined region oꢀ the ꢀalling edge oꢀ SCL.
Note 8: The maximum tHD:DAT need only be met iꢀ the device does not stretch the low period (t
) oꢀ the SCL signal.
LOW
Note 9: A ꢀast-mode device can be used in a standard-mode system, but the reꢁuirement that t
≥ 250ns must then be met.
SU:DAT
This is automatically the case iꢀ the device does not stretch the low period oꢀ the SCL signal. Iꢀ such a device does not
stretch the low period oꢀ the SCL signal, it must output the next data bit to the SDA line t
±250ns beꢀore the SCL line is released.
+ t
= ±000 + 250 =
R(MAX)
SU:DAT
Note 10: C —total capacitance oꢀ one bus line in pF.
B
2
Data Transfer on I C Serial Bus
SDA
SCL
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
t
SU:STA
t
HD:STA
t
HIGH
t
SU:STO
t
REPEATED
START
SU:DAT
STOP
START
t
HD:DAT
_____________________________________________________________________
5
12.8MHz to 51.84MHz TCXO
Typical Operating Characteristics
(V
CC
= +3.3V, T = +25°C, unless otherwise noted.)
A
ACTIVE-SUPPLY CURRENT
vs. DRIVER POWER SUPPLY
ACTIVE-SUPPLY CURRENT
vs. OSCILLATOR POWER SUPPLY
ACTIVE-SUPPLY CURRENT
vs. POWER-SUPPLY CURRENT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.6
2
10.0
8.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
51.84
51.84
12.8
51.84
6.0
4.0
12.8
12.8
2.0
-0.1
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
3.0
3.1
3.2
3.3
(V)
3.4
3.5
3.6
V
V
V
OSC
CCD
CC
FREQUENCY vs. TEMPERATURE
FREQUENCY vs. FTUNE
20
18
15
13
10
8
20
15
DCOMP = 1
51.84
10
5
12.8
0
5
3
0
-5
DCOMP = 0
-10
-15
-20
-25
-30
-3
-5
-8
-10
-13
-15
-20
40
TEMPERATURE (°C)
60
80
-40
0
20
4000h
000h
3FFFh
VC (V)
6
_____________________________________________________________________
12.8MHz to 51.84MHz TCXO
DS4026
Pin Description
PIN
±
NAME
FUNCTION
GNDA
Ground ꢀor DAC
2
V
Voltage Reꢀerence Output. This pin must be decoupled with a ±00µF ceramic capacitor to ground.
REF
Power Supply ꢀor Digital Control and Temperature Sensor. This pin must be decoupled with a ±00nF
capacitor to ground.
3
V
CC
4
5
V
Power Supply ꢀor Oscillator Circuit. This pin must be decoupled with a ±00nF capacitor to ground.
Ground ꢀor Oscillator Circuit
OSC
GNDOSC
N.C.
6–±0
±±
No Connection. Must be connected to ground.
GND
Ground ꢀor Digital Control, Temperature Sensor, and Controller Substrate
Serial Data Input/Output. SDA is the data input/output ꢀor the I2C interꢀace. This open-drain pin
reꢁuires an external pullup resistor.
Serial Clock Input. SCL is the clock input ꢀor the I2C Interꢀace and is used to synchronize data
movement on the serial interꢀace.
±2
±3
SDA
SCL
±4
±5
GNDD
FOUT
Ground ꢀor Oscillator Output Driver
Freꢁuency Output, CMOS Push-Pull
Power Supply ꢀor Oscillator Output Driver. This pin must be decoupled with a ±00nF capacitor to
±6
V
CCD
ground. A 20Ω resistor must be placed in series between the power supply and V
.
CCD
20Ω
GNDA
V
CCD
100μF 5%
CERAMIC
100nF
FOUT
V
GNDD
REF
CC
DS4026
V
SCL
SDA
100nF
V
OSC
100nF
GNDOSC
N.C.
GND
N.C.
N.C.
N.C.
N.C.
Figure ±. Typical Operating Circuit
_____________________________________________________________________
7
12.8MHz to 51.84MHz TCXO
V
CC
V
CC
EEPROM
ARRAY
TEMP
SENSOR
A/D
DS4026
GND
GND
V
CC
V
CC
V
REF
SCL
SDA
2
I C
CONTROLLER
DAC
INTERFACE
DS4026
GNDA
GND
GND
V
CCD
V
OSC
CMOS
BUFFER
FOUT
GNDOSC
GNDD
Figure 2. Functional Diagram
• Controller to read the temperature, control lookup
table, and adjust the DAC input
Detailed Description
The DS4026 is a TCXO capable oꢀ operating at 3.3V
±±0%, and it allows digital tuning oꢀ the ꢀundamental
ꢀreꢁuency. The device is calibrated in the ꢀactory to
achieve an accuracy oꢀ ±±ppm over the industrial tem-
perature range, and its minimum pullability is ±8ppm
with a typical resolution oꢀ ±ppb (typ) per LSB.
• DAC output to adjust the capacitive load
2
• I C interꢀace to communicate with the chip
The oscillator block consists oꢀ an ampliꢀier and variable
capacitor in a Pierce crystal oscillator with a crystal res-
onator oꢀ ꢀundamental mode. The oscillator ampliꢀier is a
single transistor ampliꢀier and its transconductance is
temperature compensated. The variable capacitor is
adjusted by the DAC to provide temperature compen-
sation. With the FTUNEH and FTUNEL registers, a mini-
mum pullability oꢀ ±±5ppm (typ) is achieved with a
typical resolution oꢀ ±ppb (typ) per LSB.
The DS4026 contains the ꢀollowing blocks:
• Oscillator block with variable capacitor ꢀor compen-
sation
• Output driver block
• Temperature sensor
8
_____________________________________________________________________
12.8MHz to 51.84MHz TCXO
DS4026
The output driver is a CMOS sꢁuare-wave output with
symmetrical rise and ꢀall time.
Address Map
Disable Compensation Update (DCOMP)
DCOMP is bit 7 oꢀ the ꢀreꢁuency tuning register (see
the Freꢁuency Tuning Register (00h–0±h), POR = 00h
table). When set to logic ±, this bit’s temperature-com-
pensation ꢀunction is disabled. This disabling prevents
the variable capacitor in the oscillator block ꢀrom
changing. However, the temperature register still per-
ꢀorms temperature conversions. The temperature trim
code ꢀrom the last temperature conversion beꢀore
DCOMP is enabled is used ꢀor temperature compensa-
tion. The FTUNE registers are still ꢀunctional when
DCOMP is disabled.
The temperature sensor provides a ±2-bit temperature
reading with a resolution oꢀ 0.0625°C. The sensor is in
continuous conversion mode unless the DCOMP bit in the
control register is set to disable temperature updates.
The controller coordinates the conversion oꢀ tempera-
ture into digital codes. When the temperature reading is
diꢀꢀerent ꢀrom the previous one or the ꢀreꢁuency tuning
register is changed, the controller looks up the two cor-
responding capacitance trim codes ꢀrom the lookup
table at a 0.5°C increment. The trim codes are interpo-
lated to 0.0625°C resolution.
The result is added with the tuning value ꢀrom the ꢀre-
ꢁuency tuning register and loaded into the DAC regis-
ters to adjust voltage output. The monotonic DAC
provides an analog voltage based on temperature
compensation to drive the variable capacitor.
The ꢀreꢁuency tuning registers adjust the base ꢀreꢁuen-
cy. The ꢀreꢁuency tuning value is represented in two’s
complement data. Bit 6 oꢀ FTUNEH is the sign, bit 5 is
the MSB, and bit 0 oꢀ FTUNEL is the LSB (see Table ±).
When the tuning register low (0±h) is programmed with
a value, the next temperature update cycle sums the
programmed value with the ꢀactory compensated
value. This allows the user to digitally control the base
ꢀreꢁuency using the I2C protocol.
The DS4026 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identiꢀication code ꢀol-
lowed by data. Subseꢁuent registers can be accessed
seꢁuentially until a STOP condition is executed.
These ꢀreꢁuency tuning register bits allow the tuning oꢀ
the base ꢀreꢁuency. Each bit typically represents
about ±ppb (typ). For FTUNEH = 3Fh and FTUNEL =
FFh, the device pushes the base ꢀreꢁuency by approx-
imately +±5ppm.
Frequency Tuning Register (00h–01h), POR = 00h
ADDRESS
00h
BIT 7
DCOMP
0
BIT 6
Sign
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
Data
0
BIT 2
Data
0
BIT 1
Data
0
BIT 0
Data
0
POR
0±h
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
Data
0
POR
Temperature Register (02h–03h)
ADDRESS
02h
BIT 7
Sign
0
BIT 6
Data
0
BIT 5
Data
0
BIT 4
Data
0
BIT 3
BIT 2
BIT 1
BIT 0
Data
Data
Data
Data
POR
0
0
0
0
0
0
0
0
0
0
0
0
03h
Data
0
Data
0
Data
0
Data
0
POR
_____________________________________________________________________
9
12.8MHz to 51.84MHz TCXO
Table 1. Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
FTUNEH
FTUNEL
TREGH
TREGL
BIT 2
BIT 1
BIT 0
FUNCTION
Freꢁuency Tuning High
Freꢁuency Tuning Low
Temperature MSB
00
0±
02
03
DCOMP
SIGN
SIGN
DS4026
Temperature LSB
2
Read Mode
I C Serial Data Bus
In the temperature register (see the Temperature
Register (02h–03h) table), temperature is represented
as a ±2-bit code and is accessible at location 02h and
03h. The upper 8 bits are at location 02h and the lower
4 bits are in the upper nibble oꢀ the byte at location
03h. Upon power reset, the registers are set to a +25°C
deꢀault temperature and the controller starts a tempera-
ture conversion. The temperature register stores new
temperature readings.
The DS4026 supports a bidirectional I2C bus and data
transmission protocol. A device that sends data onto
the bus is deꢀined as a transmitter and a device receiv-
ing data is deꢀined as a receiver. The device that con-
trols the message is called a master. The devices that
are controlled by the master are slaves. The bus must
be controlled by a master device that generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions. The DS4026
operates as a slave on the I2C bus. Connections to the
bus are made through the open-drain I/O lines SDA
and SCL. Within the bus speciꢀications, a standard
mode (±00kHz maximum clock rate) and a ꢀast mode
(400kHz maximum clock rate) are deꢀined. The DS4026
works in both modes.
The current temperature is loaded into the (user) tem-
perature registers when a valid I2C slave address and
write is received and when a word address is received.
Conseꢁuently, iꢀ the two temperature registers are read
in individual I2C transactions, it is possible ꢀor a temper-
ature conversion to occur between reads, and the
results can be inaccurate. To prevent this ꢀrom occur-
ring, the registers should be read using a single, multi-
The ꢀollowing bus protocol has been deꢀined (Figure 3):
2
• Data transꢀer can be initiated only when the bus is
not busy.
byte read operation (Figure 5). I C reads do not aꢀꢀect
the internal temperature registers.
SDA
MSB
SLAVE ADDRESS
R/W
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
6
7
8
9
1
2
3–7
8
9
ACK
ACK
START
CONDITION
STOP
CONDITION
OR REPEATED
START
REPEATED IF MORE BYTES
ARE TRANSFERED
CONDITION
2
Figure 3. I C Data Transꢀer Overview
10
____________________________________________________________________
12.8MHz to 51.84MHz TCXO
DS4026
• During data transꢀer, the data line must remain stable
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period oꢀ the acknowledge-related clock pulse. Oꢀ
course, setup and hold times must be taken into
account. A master must signal an end oꢀ data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out oꢀ the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
Accordingly, the ꢀollowing bus conditions have been
deꢀined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state oꢀ the data
line ꢀrom high to low, while the clock line is high,
deꢀines a START condition.
Figures 4 and 5 detail how data transꢀer is accom-
plished on the I2C bus. Depending upon the state oꢀ
the R/W bit, two types oꢀ data transꢀer are possible:
Stop data transfer: A change in the state oꢀ the data
line ꢀrom low to high, while the clock line is high,
deꢀines a STOP condition.
Data transfer from a master transmitter to a slave
receiver. The ꢀirst byte transmitted by the master is
the slave address. Next ꢀollows a number oꢀ data
bytes. The slave returns an acknowledge (ACK) bit
aꢀter each received byte.
Data valid: The state oꢀ the data line represents valid
data when, aꢀter a START condition, the data line is
stable ꢀor the duration oꢀ the high period oꢀ the clock
signal. The data on the line must be changed during
the low period oꢀ the clock signal. There is one clock
pulse per bit oꢀ data.
Data transfer from a slave transmitter to a master
receiver. The ꢀirst byte (the slave address) is trans-
mitted by the master. The slave then returns an
acknowledge bit. Next ꢀollows a number oꢀ data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit aꢀter all received
bytes other than the last byte. At the end oꢀ the last
received byte, a not acknowledge (NACK) is
returned.
Each data transꢀer is initiated with a START condition
and terminated with a STOP condition. The number
oꢀ data bytes transꢀerred between the START and the
STOP conditions is not limited, and is determined by
the master device. The inꢀormation is transꢀerred
byte-wise and each receiver acknowledges with a
ninth bit.
The master device generates all the serial clock
pulses and the START and STOP conditions. A trans-
ꢀer is ended with a STOP condition or with a repeat-
ed START condition. Because a repeated START
condition is also the beginning oꢀ the next serial
transꢀer, the bus is not released.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
(ACK) aꢀter the reception oꢀ each byte. The master
device must generate an extra clock pulse that is
associated with this acknowledge bit.
<SLAVE
ADDRESS>
<SLAVE
ADDRESS>
<WORD
<DATA (n)>
<DATA (n + 1)> <DATA (n + 2)> <DATA (n + X)>
ADDRESS (n)> <DATA (n)> <DATA (n + 1)> <DATA (n + X)>
S 1000001 1 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
S 1000001 0 A XXXXXXXX A XXXXXXXX A XXXXXXXX A XXXXXXXX A P
DATA TRANSFERRED
S = START
S = START
DATA TRANSFERRED
A = ACKNOWLEDGE
(X + 1 BYTES + ACKNOWLEDGE)
P = STOP
(X + 1 BYTES + ACKNOWLEDGE)
A = ACKNOWLEDGE
NOTE: LAST DATA BYTE IS FOLLOWED BY
P = STOP
A NOT ACKNOWLEDGE (A) SIGNAL
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 82h
A = NOT ACKNOWLEDGE
R/W = READ/WRITE OR DIRECTION BIT ADDRESS = 83h
Figure 4. Slave Receiver Mode (Write Mode)
Figure 5. Slave Transmitter Mode (Read Mode)
____________________________________________________________________ 11
12.8MHz to 51.84MHz TCXO
The DS4026 can operate in the ꢀollowing two modes:
Slave transmitter mode (read mode): The ꢀirst byte
is received and handled as in the slave receiver
mode. However, in this mode, the direction bit indi-
cates that the transꢀer direction is reversed. Serial
data is transmitted on SDA by the DS4026 while the
serial clock is input on SCL. START and STOP condi-
tions are recognized as the beginning and end oꢀ a
serial transꢀer. Address recognition is perꢀormed by
hardware aꢀter reception oꢀ the slave address and
direction bit. The slave address byte is the ꢀirst byte
received aꢀter the master generates a START condi-
tion. The slave address byte contains the 7-bit
DS4026 address, which is ±00000±, ꢀollowed by the
direction bit (R/W), which is ± ꢀor a read. Aꢀter receiv-
ing and decoding the slave address byte, the
DS4026 outputs an acknowledge on SDA. The
DS4026 then begins to transmit data starting with the
register address pointed to by the register pointer. Iꢀ
the register pointer is not written to beꢀore the initia-
tion oꢀ a read mode, the ꢀirst address that is read is
the last one stored in the register pointer. The
DS4026 must receive a not acknowledge to end a
read.
Slave receiver mode (write mode): Serial data and
clock are received through SDA and SCL. Aꢀter each
byte is received, an acknowledge bit is transmitted.
START and STOP conditions are recognized as the
beginning and end oꢀ a serial transꢀer. Address
recognition is perꢀormed by hardware aꢀter reception
oꢀ the slave address and direction bit. The slave
address byte is the ꢀirst byte received aꢀter the mas-
ter generates a START condition. The slave address
byte contains the 7-bit DS4026 address, which is
±00000±, ꢀollowed by the direction bit (R/W), which is
0 ꢀor a write. Aꢀter receiving and decoding the slave
address byte, the DS4026 outputs an acknowledge
on SDA. Aꢀter the DS4026 acknowledges the slave
address and write bit, the master transmits a word
address to the DS4026. This sets the register pointer
on the DS4026, with the DS4026 acknowledging the
transꢀer. The master can then transmit zero or more
bytes oꢀ data, with the DS4026 acknowledging each
byte received. The register pointer increments aꢀter
each data byte is transꢀerred. The master generates
a STOP condition to terminate the data write.
DS4026
Ordering Information (continued)
OUTPUT (f
(MHz, CMOS)
)
NOM
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK*
DS4026S+MCC
DS4026S+MCN
DS4026S+PCC
DS4026S+PCN
DS4026S+QCC
DS4026S+QCN
+Lead-ꢀree package.
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
38.88
16 SO
16 SO
16 SO
16 SO
16 SO
16 SO
DS4026-MCC
DS4026-MCN
DS4026-PCC
DS4026-MCN
DS4026-QCC
DS4026-QCN
38.88
40.0
40.0
51.84
51.84
*The top mark will include a “+” ꢀor a lead-ꢀree/RoHS-compliant device.
Package Information
Chip Information
TRANSISTOR COUNT: 77, 7±2
For the latest package outline inꢀormation, go to
www.maxim-ic.com/DallasPackInfo.
SUBSTRATE CONNECTED TO GROUND
PROCESS: CMOS
PACKAGE TYPE
DOCUMENT NO.
56-G4009-001
±6-pin SO (300 mils)
Maxim cannot assume responsibility ꢀor use oꢀ any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and speciꢀications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark oꢀ Maxim Integrated Products, Inc.
is a registered trademark oꢀ Dallas Semiconductor Corporation.
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