DS4426 [MAXIM]
Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking; 四通道， I²C ，裕量的IDAC ，具有三路电源跟踪的
| 型号： | DS4426 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking |
| 文件： | 总15页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4541; Rev 1; 7/09
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
General Description
Features
2
The DS4426 contains four I C-adjustable current DACs
♦ Four Current DACs
capable of sinking or sourcing current. External resis-
tors set the full-scale range of each output. Each DAC
output has 127 sink and 127 source steps that are pro-
50µA to 200µA Adjustable Full-Scale Range
127 Settings Each for Sink and Source
2
♦ Power-Supply Tracking
grammed by the I C interface. Power-supply tracking
functionality is provided for three channels using dedi-
cated control inputs. Once power-supply tracking is
accomplished, the current outputs default to zero. Two
address pins allow up to four DS4426 devices to exist
Power-Supply Sequencing
Ramp-Up and Ramp-Down Tracking Control
Ratiometric Tracking Support
♦ +2.7V to +5.5V Operation
2
on the same I C bus.
2
♦ I C-Compatible Serial Interface
Applications
♦ Two Address Input Pins Allow Up to Four Devices
2
Power-Supply Adjustment
Power-Supply Margining
Power-Supply Tracking
on Same I C Bus
♦ Lead-Free, 28-Pin TQFN Package (4mm x 4mm)
with Exposed Pad
♦ Industrial Temperature Range: -40°C to +85°C
Adjustable Current Sink or Source
Ordering Information
Pin Configuration
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 TQFN-EP*
28 TQFN-EP*
TOP VIEW
DS4426T+
DS4426T+T&R
21 20 19 18 17 16 15
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
14
13
FS1 22
FS2 23
INN2
INP2
12 INN1
24
25
26
27
28
FS3
GAIN3
GAIN2
GAIN1
N.C.
INP1
A1
11
10
9
DS4426
*EP
6
A0
Functional Diagram appears at end of data sheet.
+
8
GND
1
2
3
4
5
7
THIN QFN
(4mm × 4mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
ABSOLUTE MAXIMUM RATINGS
Voltage Range on SDA, SCL Relative to GND......-0.5V to +6.0V
Operating Temperature Range ...........................-40°C to +85°C
Voltage Range on V
Relative to GND ...............-0.5V to +6.0V
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
CC
Voltage Range on A0, A1, FS[3:0], GAIN[3:1],
INN[3:1], INP[3:1], THR[3:1], and OUT[3:0]
Relative to GND ......................................-0.5V to (V
+ 0.5V)*
CC
*Not to exceed +6.0V.
DS426
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
TYP
MAX
UNITS
Supply Voltage
V
(Note 1)
5.5
V
CC
Input Logic 1
(SDA, SCL, A0, A1)
0.7 x
V
+
CC
0.3
V
V
IH
V
CC
Input Logic 0
(SDA, SCL, A0, A1)
0.3 x
V
CC
V
-0.3
40
V
IL
Full-Scale Resistor Values
R
(Note 2)
160
kꢀ
FS[3:0]
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= +5.5V (Note 3)
MIN
TYP
MAX
UNITS
Supply Current
I
V
V
0.9
mA
CC
CC
Input Leakage Current
(SDA, SCL)
I
= +5.5V
-1
+1
μA
IL
CC
RFS Voltage
V
T
= +25°C
0.940
0.990
1.24
100
1.040
V
V
RFS
A
Reference Voltage
V
REF
Temperature Coefficient
Output Leakage Current (SDA)
ppm/°C
μA
I
L
-1
3
+1
10
V
V
= +0.4V
= +0.6V
OL
OL
Output-Current Low (SDA)
I/O Capacitance
I
mA
pF
OL
6
C
I/O
DAC OUTPUT CURRENT CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
measured at +1.2V
OUT
MIN
TYP
0.33
0.33
0.15
0.30
MAX
UNITS
DC source, V
Output Current Variation Due to
Power-Supply Change
%/V
DC sink, V
measured at +1.2V
OUT
DC source, V = +3.6V
Output Current Variation Due to
Output-Voltage Change
CC
%/V
DC sink, V = +3.6V
CC
2
_______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
DAC OUTPUT CURRENT CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage for Sinking
Current
V
(Note 4)
(Note 4)
0.5
3.5
V
OUT:SINK
Output Voltage for Sourcing
Current
V
CC
-
V
0
V
OUT:SOURCE
0.75
200
-50
Full-Scale Sink Output Current
Full-Scale Source Output Current
I
(Note 4)
(Note 4)
50
μA
μA
OUT:SINK
I
-200
OUT:SOURCE
Output-Current Full-Scale
Accuracy
I
T
= +25°C
5
%
ppm/°C
%/V
OUT:FS
OUT:TC
A
Output-Current Temperature
Coefficient
I
(Note 5)
130
Output-Current Power-Supply
Rejection Ratio
0.33
Output-Leakage Current at Zero
Current Setting
I
-1
+1
μA
ZERO
Output-Current Differential
Linearity
DNL
INL
(Note 6)
(Note 7)
0.5
1
LSB
LSB
Output-Current Integral Linearity
2
CC
I C ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -40°C to +85°C. Timing referenced to V
and V . See Figure 6.)
IH(MIN)
A
IL(MAX)
PARAMETER
SCL Clock Frequency
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
f
(Note 8)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
μs
μs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
μs
μs
μs
ns
μs
LOW
t
HIGH
t
t
t
0.9
HD:DAT
SU:DAT
SU:STA
Data Setup Time
START Setup Time
100
0.6
20 +
SDA and SCL Rise Time
t
(Note 9)
(Note 9)
300
300
ns
R
0.1C
B
20 +
SDA and SCL Fall Time
STOP Setup Time
t
ns
μs
pF
F
0.1C
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 9)
400
B
_______________________________________________________________________________________
3
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
POWER-SUPPLY TRACKING CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -40°C to +85°C, see Figure 5.)
A
PARAMETER
SYMBOL
CONDITIONS
R /R and R /R
MIN
0.5
1
TYP
MAX
1
UNITS
kꢀ
Input Divider Ratio
Output Load
R
DIV
A
B
C
D
R
L
R = (R x R )/(R +R )
20
4.5
10
5
L
F
E
F
E
Feedback Resistor Ratio
Gain Resistor
R /R
0.5
0.8
1.4
2
F
B
R
kꢀ
G
Gain Setting Ratio
R /R
L
G
R /R = 2, R = 5kꢀ, V = +3.6V,
L
G
L
CC
2.4
6.2
T
A
= +25°C
Power-Supply Tracking Gain
G
mA/V
μA
VI
R /R = 5, R = 5kꢀ, V = +3.6V,
L
G
L
CC
3.8
10
1
T
A
= +25°C
Power-Supply Tracking Input
Bias Current
I
B
Power-Supply Tracking Input
Voltage
V
1.4
-
CC
V
INP[3:1] and INN[3:1]
R /R = 1.4; R = 5kꢀ
0
0
V
MHz
V
IN
Unity Gain Bandwidth
GBW
12
L
G
L
Switch closed, V = +3.0V, measured at
CC
Output Voltage While Tracking
V
1.5
1
OUT:TRK
OUT[3:1], R = 5kꢀ
L
R /R = 1.4, R = 1kꢀ, V = +3.0V,
L
G
G
CC
Output Current While Tracking
I
mA
OUT:TRK
V
FB
= +0.8V
Tracking Accuracy
Output Leakage
600
0.5
1
mV
μA
μA
mV
μs
I
Switch open
BC
Comparator Input Bias Current
Comparator Input Offset
Switch Delay
I
OFF
V
5
5
OS
DC
t
Comparator Hysteresis
V
HYS
12.5
mV
Note 1: All voltages are referenced to GND. Current entering the IC is specified positive, and current exiting the IC is negative.
Note 2: Input resistors (R
) must be between the specified values to ensure the device meets its accuracy and linearity specifi-
FS[3:0]
cations.
Note 3: Supply current specified with all outputs set to zero current setting and with all inputs at V
or GND. SDA and SCL are
CC
connected to V . Excludes current through R resistors (I
). Total current including I
is I
+ (2 x I
).
RFS
CC
FS
RFS
RFS
CC
Note 4: The output-voltage full-scale ranges must be satisfied to ensure the device meets its accuracy and linearity specifications.
Only applies to current DAC operation, not power-supply tracking operation.
Note 5: Temperature drift excludes drift caused by external resistors.
Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position
and the actual increase. The expected incremental increase is the full-scale range divided by 127.
Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value.
The expected value is a straight line between the zero and the full-scale values proportional to the setting.
2
Note 8: Timing shown is for fast-mode operation (400kHz). This device is also backward-compatible with I C standard-mode timing.
Note 9: C —Total capacitance of one bus line in pF.
B
4
_______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
VOLTCO (SOURCE)
-150
-175
-200
-225
-250
600
575
550
525
500
475
450
425
400
600
575
550
525
500
475
450
425
400
SDA = SCL = THR[3:1] = V
GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
40kΩ LOAD ON FS[3:0].
= +5.5V
CC
V
CC
V
= +5.5V
CC
V
= +3.3V
CC
V
CC
= +2.7V
SDA = SCL = THR[3:1] = V
GAIN[3:1] = OPEN
INP[3:1] = INN[3:1] = GND
SDA = SCL = THR[3:1] = V
GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN
INP[3:1] = INN[3:1] = GND
CC
CC
0
1
2
3
4
5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-20
0
20
40
60
80
V
OUT
(V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE COEFFICIENT
vs. SETTING (SOURCE)
TEMPERATURE COEFFICIENT
vs. SETTING (SINK)
VOLTCO (SINK)
250
225
200
175
150
300
250
200
150
100
50
650
550
450
350
250
150
50
40kΩ LOAD ON FS[3:0].
= +5.5V
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE RANGE
RANGE FOR THE 50μA TO 200μA
CURRENT SINK RANGE
V
CC
+25°C TO -40°C
+25°C TO +85°C
+25°C TO -40°C
+25°C TO +85°C
-50
SDA = SCL = THR[3:1] = V
GAIN[3:1] = OPEN
CC
0
-150
-250
INP[3:1] = INN[3:1] = GND
-50
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
0
25
50
75
100
125
0
25
50
75
100
125
V
OUT
(V)
SETTING (DEC)
SETTING (DEC)
INTEGRAL LINEARITY
DIFFERENTIAL LINEARITY
1.0
0.8
1.0
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE AND SINK RANGE
RANGE FOR THE 50μA TO 200μA
CURRENT SOURCE AND SINK RANGE
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
25
50
75
100
125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
_______________________________________________________________________________________
5
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
Pin Description
PIN
NAME
SDA
FUNCTION
2
1
Serial Data Input/Output. I C data pin.
2
2
SCL
Serial Clock Input. I C clock input.
3
V
CC
Voltage Supply
DS426
4
OUT0
Current DAC Output
5, 6, 7
OUT1, OUT2, OUT3 Current DAC and Tracking Control Output
8
9
GND
A0
Ground
2
I C Address Input 0
2
10
A1
I C Address Input 1
11, 13, 15
12, 14, 16
INP1, INP2, INP3
INN1, INN2, INN3
Power-Supply Tracking Positive Input
Power-Supply Tracking Negative Input
Threshold Input. Comparator input used to set threshold for tracking
17, 19, 20
18
THR3, THR2, THR1
DNC
enable/disable based on V
/2.
REF
Do Not Connect
Full-Scale Calibration Input. A resistor-to-ground on this input determines full-
scale output current on the associated output.
21–24
FS0, FS1, FS2, FS3
GAIN3, GAIN2,
GAIN1
25, 26, 27
Gain Adjustment Pin. Connect a resistor between this pin and V
.
CC
28
—
N.C.
EP
No Connection
Exposed Pad. No connection.
To calculate the output-current value (I
corresponding DAC value (see Table 2 for correspond-
ing memory addresses), use the following equation:
) based on the
OUT
Detailed Description
2
The DS4426 contains four I C-adjustable current
sources that are each capable of sinking and sourcing
current. Three of the current outputs (OUT[3:1]) also
have power-supply tracking circuitry that allows addi-
tional current to be sourced during power-up.
DACValue(dec)
I
=
× I
FS
OUT
127
On power-up, the DS4426 current DAC outputs are set
to zero current. This is done to prevent the device from
sinking or sourcing an incorrect current before the sys-
tem host controller has a chance to modify its setting.
Note, however, that if power-supply tracking is enabled
(see the Power-Supply Tracking Circuit section), then
the DS4426 can still source current at power-up.
Adjustable Current DACs
Each output (OUT[3:0]) has 127 sink and 127 source
2
settings that are programmed through the I C interface.
The full-scale current ranges (and corresponding step
sizes) of the outputs are determined by external resis-
tors connected to the corresponding FS pins (see
Figure 1). The formula to determine the external resistor
When used in adjustable power-supply applications
(see Figure 8), the DS4426 does not affect the initial
power-up voltage of the supply because it defaults to
providing zero output current on power-up unless
power-supply tracking is enabled. As it sources or
sinks current into the feedback voltage node, it
changes the amount of output voltage required by the
regulator to reach its steady-state operating point.
values (R ) for each output is given by:
FS
V
16 × I
RFS
R
=
×127
FS
FS
where I is the desired full-scale current value, V
is
FS
FS
RFS
the R voltage (see the DC Electrical Characteristics
table), and R is the external resistor value.
FS
6
_______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
Using the external resistors R
to set the output-
FS[3:0]
current range, the DS4426 provides some flexibility for
adjusting the impedances of the feedback network or
the range over which the power supply can be con-
trolled or margined.
2
I C CONTROL
TRACKING
OUT[3:1] ONLY
MSB
LSB
As a source for biasing instrumentation or other circuits,
the DS4426 provides a simple and inexpensive current
127 POSITIONS
EACH FOR SOURCE
AND SINK MODE
2
source with an I C interface for control. The adjustable,
SOURCE
OR
SINK MODE
CURRENT
DAC[3:0]
full-scale range allows the application to get the most
out of its 7-bit sink or source resolution.
Power-Supply Tracking Circuit
FS[3:0]
OUT[3:0]
By making use of the power-supply tracking circuitry,
the DS4426 has the ability to source current on power-
up. This current is additive with the current DAC
source/sink currents and is determined by the value of
R
FS[3:0]
the gain resistor, R , and the supply voltage, V . This
G
CC
current is controlled by the voltages presented to the
corresponding INP and INN pins, and the voltages pre-
sented to the corresponding threshold (THR) pins.
Figure 1. Current DAC Detail
V
CC
Maximum Source Current
The maximum current the DS4426 can source at
power-up using the power-supply tracking circuitry
R
G
GAIN
depends on the value of the supply voltage, V , and
CC
INP
INN
+
-
the gain resistor, R , connected from the correspond-
G
G
VI
ing GAIN pin to V . The maximum current (I
) that
CC
MAX
SLAVE
FEEDBACK
NODE
can be sourced to the corresponding OUT pin can be
estimated using the following equation:
OUT
SHUTDOWN
V
− V
OUT
(
)
CC
I
≅
MAX
DAC
R
G
The power-supply tracking circuit can be estimated
with Figure 2.
Figure 2. Gain Stage
Inputs for Power-Supply Tracking:
INP and INN
I
AT V = +5.0V
CC
Each pair of power-supply tracking inputs, INP and
I
MAX
INN, determines if and how much of the I
current is
MAX
sourced when the power-supply tracking circuit is
enabled. When the difference between the voltage pre-
sented to INP (V
) and INN (V
) is more than
INN
INP
approximately +0.3V, then the maximum source cur-
rent, as determined by the value I , is sourced into
G
VI
MAX
the OUT pin connection. When the difference between
and V is less than approximately -0.2V, then no
V
INP
INN
current is sourced into the corresponding OUT pin. The
change in current from no current to I
can be esti-
VI
MAX
mated by the power-supply tracking gain, G (see the
Power-Supply Tracking Characteristics table).
V
-0.2
+0.3
(V - V
INP
)
INN
Figure 3 shows the typical current behavior of the
power-supply tracking circuit with respect to the volt-
age difference seen at the INP and INN inputs.
Figure 3. INP and INN Differential Inputs
_______________________________________________________________________________________
7
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
V
V
MASTER
DS426
V
SLAVE
DS4426 TRACKING DISABLED
V
THRESHOLD
GAIN
ERROR
TRACKING RANGE: DS4426 OVERRIDES SLAVE'S FEEDBACK LOOP
t
Figure 4. Enabling Power-Supply Tracking Using the THR Input
THR Inputs for Enabling
Power-Supply Tracking
Loop Bandwidth Consideration
Power-supply tracking is used to override each slave
DC-DC’s feedback loop during power-up and power-
down. Power-supply tracking is capable of slewing at a
much faster rate than most DC-DC converters. Care
must be exercised when selecting the loop bandwidth
of the master DC-DC, slave DC-DC, and power-supply
tracking control loop such that oscillations and over-
shoot are minimized.
Comparators are used to individually enable/disable
power-supply tracking based on the voltage presented
to the corresponding THR pin relative to a fixed internal
reference (V
/2 = +0.62V). Figure 4 shows a typical
REF
startup and shutdown plot based on the voltage pre-
sented to the THR pin. Tracking can be disabled by
connecting the corresponding THR pin to a voltage
greater than V
/2. Below this threshold, the tracking
REF
While the slave DC-DC supplies are tracking the master
DC-DC supply, there are three time constants of concern:
circuit is active.
1) Master BW. The master DC-DC control loop band-
width, power-up ramp rate, and power-down ramp
rate.
Power-Supply Tracking in DC-DC
Power Applications
The DS4426 provides several options for power-supply
tracking control of DC-DC power supplies. In many
cases, it is desirable to prevent certain DC-DC supplies
from exceeding the voltage of other supplies. This is
often the case with the voltages applied to a digital
core and I/O. Each DS4426 supports one master with
three slave DC-DCs. See Figure 5 for more information.
2) Slave BW. The slave DC-DC supplies control loop
bandwidths.
3) Tracking BW. The DS4426 tracking circuit band-
width.
To ensure stable operation and minimize peaking, the
bandwidths should follow the following rule:
Master BW and Slave BW < (Tracking BW/10)
8
_______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
5.0V
V
CC
V
CC
VOUT
MASTER
0.1μF
10kΩ
10kΩ
10kΩ
DC-DC
CONVERTER
R
R
F0
SDA
SCL
A0
2
I C
2
I C CONTROL
FB
INTERFACE
A1
E0
R
FS0
FS0
V
REF
REF
1.24V
OUT0
x3
R
FS[3:1]
FS[3:1]
INP[3:1]
INN[3:1]
5.0V
OUT[3:1]
R
B[3:1]
R
G[3:1]
VOUT
SLAVE
DC-DC
CONVERTER
GAIN[3:1]
V
R
A[3:1]
R
R
F[3:1]
/2
REF
DS4426
FB
COMP
10kΩ
THR[3:1]
E[3:1]
R
THR[3:1]
R
D[3:1]
R
C[3:1]
Figure 5. Typical DC-DC Power-Supply Tracking Application
changing the ratio of R /R . If oscillations occur,
Ratiometric Tracking
The DS4426 can maintain a defined ratio between a
slave voltage and the master voltage where:
L
G
increasing R reduces gain and increases the system’s
G
phase margin. If the slave DC-DC has a compensation
pin, the RC network connected to this pin can also be
adjusted to improve phase margin. This pin is often
labeled COMP or ITH. A larger compensation time con-
stant (increased R and/or increased C) often increases
the stability of the system during tracking; however, this
also modifies the DC-DC's transient response. In order
to prevent modification of the slave DC-DC’s transient
K
SM
= V
/V
.
SLAVE MASTER
In Figure 5, this ratio is given by the following:
K
= [R
/(R
+ R
D[3:1]
)]/[R /(R
D[3:1] C[3:1]
SM
B[3:1] A[3:1]
B[3:1]
)].
+ R
Nonratiometric tracking is the special case where K = 1.
SM
response after power-supply tracking is complete, R
G
Power-Supply Tracking Loop Gain Stability
Slave DC-DC output tracking is controlled by the
DS4426 sourcing current into the slave DC-DC's feed-
back loop. This changes the stability of the loop during
tracking. The amount of gain used can be adjusted by
should first be modified before adjusting the compen-
sation network. The higher the gain, the less the gain
error. Reducing the gain increases the gain error during
tracking. See Figure 4 for more information.
_______________________________________________________________________________________
9
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
Table 1. Slave Addresses
Table 2. Memory Addresses
A1
A0
SLAVE ADDRESS (HEX)
MEMORY ADDRESS (HEX)
CURRENT SOURCE
GND
GND
GND
90h
92h
94h
96h
F8h
F9h
FAh
FBh
OUT0
OUT1
OUT2
OUT3
V
CC
V
V
GND
CC
CC
V
CC
DS426
Inputs for Tracking in DC-DC Power
Applications
Memory Organization
The DS4426’s current sources are controlled by writing
to memory addresses listed in Table 2.
When enabling/disabling the power-supply tracking, a
resistor-divider connected to the THR input sets the dis-
The format of each of the output control registers is
given by:
able threshold (see V
in Figure 4). The top
THRESHOLD
of the resistor-divider must be connected to the master
DC-DC voltage for correct operation. Below this thresh-
old, the tracking circuit is active.
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
Power-Supply Sequencing
The DS4426 can be used to perform power-supply
sequencing. This is a subset of power-supply tracking
with modifications to the external resistor network. The
basic concept is that the DS4426 sources maximum
current into the slave power supply's feedback node
until a voltage in the system has risen above a specific
voltage level. By sourcing the maximum current into the
feedback node, the power supply's output is held off.
Maximum sourcing current is achieved with two steps:
S
D
D
D
D
D
D
D
0
6
5
4
3
2
1
where:
POWER-ON
DEFAULT
BIT NAME
DESCRIPTION
Determines if DAC sources or
sinks current. For sink, S = 0.
For source, S = 1.
Sign
Bit
S
0b
1) Apply the maximum allowed input voltage across
7-bit data word controlling DAC
output. Setting 0000000b
outputs zero current regardless
of the state of the sign bit.
INP and INN. Connect INP to V
- 1.4V using a
CC
D
Data
0000000b
X
voltage-divider to ground. Connect INN to ground.
2) Set the gain to the maximum allowed (R /R = 5).
L
G
The slave power supply is allowed to turn on once the
voltage on THR is greater than V /2. Use a resistor-
For example:
REF
divider connected to the rising system voltage to scale
the trip point to V /2.
R
= 80kΩ and register 0xF8h is written to a value of
FS0
0xAAh. Use the following formula to calculate the out-
put current:
REF
2
I C Slave Address
I
FS
= (1.0V/80kΩ) x (127/16) = 99.22µA
2
The DS4426 responds to one of four I C slave address-
es determined by the state of the input on the two
address inputs. The two input states are connected to
The MSB of the output register is 1, so the output is
sourcing the value corresponding to position 2Ah (42
decimal). The magnitude of the output current is equal
to the following:
V
CC
or connected to ground.
99.22µA x (42/127) = 32.8125µA
10 ______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
2
master generates all SCL clock pulses, including
I C Serial Interface Description
when it is reading bits from the slave.
2
I C Definitions
Acknowledgement (ACK and NACK): An
Acknowledgement (ACK) or Not Acknowledge
(NACK) is always the ninth bit transmitted during a
byte transfer. The device receiving data (the master
during a read or the slave during a write operation)
performs an ACK by transmitting a zero during the
ninth bit. A device performs a NACK by transmitting
a 1 during the ninth bit. Timing for the ACK and
NACK is identical to all other bit writes (Figure 6). An
ACK is the acknowledgment that the device is prop-
erly receiving data. A NACK is used to terminate a
read sequence or as an indication that the device is
not receiving data.
The following terminology is commonly used to
describe I C data transfers:
2
2
I C Slave Address: The slave address of the
DS4426 is determined by the state of the A0 and A1
pins (see Table 1).
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive
data at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states. When the bus is
idle it often initiates a low-power mode for slave
devices.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgement
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write def-
inition, and the acknowledgement is read using the
bit-read definition.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 3 for applicable timing.
Byte Read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit-read definition, and the master
transmits an ACK using the bit-write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave returns control of SDA to the master.
STOP Condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition. See
Figure 3 for applicable timing.
Repeated START Condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
See Figure 6 for applicable timing.
2
Slave Address Byte: Each slave on the I C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
DS4426’s slave address is determined by the state
of the A0 and A1 pins (see Table 1). When the R/W
bit is 0 (such as in 90h), the master is indicating it
will write data to the slave. If R/W = 1 (91h in this
case), the master is indicating it wants to read from
the slave. If an incorrect slave address is written, the
DS4426 assumes the master is communicating with
Bit Write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL,
plus the setup-and-hold time requirements (Figure
6). Data is shifted into the device during the rising
edge of the SCL.
2
another I C device and ignores the communication
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (Figure 6) before the next rising edge
of SCL during a bit read. The device shifts out each
bit of data on SDA at the falling edge of the previous
SCL pulse, and the data bit is valid at the rising
edge of the current SCL pulse. Remember that the
until the next START condition is sent.
2
Memory Address: During an I C write operation,
the master must transmit a memory address to iden-
tify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following
the slave address byte.
______________________________________________________________________________________ 11
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
SDA
t
BUF
DS426
t
t
F
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 6. I C Timing Diagram
2
TYPICAL I C WRITE TRANSACTION
MSB
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
0
0
1
0
A1 A0 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
SLAVE
ADDRESS*
READ/
WRITE
REGISTER/MEMORY ADDRESS
DATA
2
EXAMPLE I C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED)
90h
F9h
A) SINGLE-BYTE WRITE
START 1 0 0 1 0 0 0 0
-WRITE REGISTER F9h TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 1 1 1 0 0 1
0 0 0 0 0 0 0 0
STOP
90h
F8h
91h
1 0 0 1 0 0 0 1
DATA
B) SINGLE-BYTE READ
START 1 0 0 1 0 0 0 0
-READ REGISTER F8h
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
MASTER
NACK
1 1 1 1 1 0 0 0
STOP
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
2
Figure 7. I C Communication Examples
2
Reading from a Slave: To read from the slave, the
master generates a START condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a STOP condition.
I C Communication
Writing to a Slave: The master must generate a START
condition, write the slave address byte (R/W = 0), write
the memory address, write the byte of data, and gener-
ate a STOP condition. Remember that the master must
read the slave’s acknowledgement during all byte-write
operations.
12 ______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
I
is chosen to be 100µA (midrange source/sink
OUT0
Applications Information
current for the DS4426). Summing the currents into the
feedback node, we have the following:
Example Calculations for an Adjustable
Power Supply
In this example, the circuit shown in Figure 8 is used to
margin a +2.0V supply by 20ꢀ. The margined power
I
= I
- I
OUT0
R0B R0A
where:
and
supply has a DC-DC converter output voltage, V
, of
OUT
V
R
FB
0B
I
=
+2.0V and a DC-DC converter feedback voltage, V
,
,
FB
0B
R0B
of +0.8V. To determine the relationship of R and R
0A
start with the equation:
R
0B
+ R
V
− V
FB
V
=
× V
OUT
R
FB
OUT
I
=
R0A
R
0A
0B
0A
Substituting V = +0.8V and V
= +2.0V, the rela-
FB
OUT
To create a 20ꢀ margin in the supply voltage, the
tionship between R and R is determined to be:
0A
0B
value of V
place, R
is set to +2.4V. With these values in
OUT
R
0A
= 1.5 x R
is calculated to be 2.67kΩ, and R
is
0A
0B
0B
V
CC
V
OUT
= 2.0V*
OUT
FB
4.7kΩ
4.7kΩ
V
CC
SDA
SCL
DC-DC
CONVERTER
I
I
R
= 4kΩ
R0A
0A
DS4426
OUT0
V
FB
= 0.8V*
R0B
R
0B
= 2.67kΩ
GND
FS0
R
I
OUT0
= 80kΩ
FS0
*V
OUT
AND V VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH V
AND V OF THE DS4426.
OUT REF
FB
Figure 8. Example Typical Application Circuit
______________________________________________________________________________________ 13
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
calculated to be 4.00kΩ. The current DAC in this con-
Functional Diagram
figuration allows the output voltage to be moved linearly
from +1.6V to +2.4V using 127 settings. This corre-
sponds to a resolution of 6.3mV/step.
V
CC
V
CC
V
Decoupling
CC
SDA
SCL
A0
To achieve the best results when using the DS4426,
decouple the power supply with a 0.01µF (or 0.1µF)
capacitor. Use a high-quality, ceramic, surface-mount
capacitor if possible. Surface-mount components mini-
mize lead inductance, which improves performance.
Ceramic capacitors tend to have adequate high-fre-
quency response for decoupling applications.
2
I C CONTROL
DS426
INTERFACE
A1
FS0
V
REF
REF
1.24V
OUT0
FS1
INP1
Package Information
OUT1
For the latest package outline information and land patterns, go
INN1
to www.maxim-ic.com/packages.
GAIN1
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
V
REF
V
REF
V
REF
/2
/2
/2
28 TQFN
T2844+1
21-0139
THR1
INP2
FS2
OUT2
INN2
GAIN2
THR2
INP3
FS3
OUT3
INN3
GAIN3
DS4426
THR3
GND
14 ______________________________________________________________________________________
2
Quad-Channel, I C-Margining IDACs with
Three Channels of Power-Supply Tracking
DS426
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
4/08
Initial release.
—
2
Added OUT[3:0] to the Absolute Maximum Ratings for the following condition:
Voltage Range on A0, A1, FS[3:0], GAIN[3:1], INN[3:1], INP[3:1], and THR[3:1].
1
7/09
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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