DS8500_V01 [MAXIM]
HART Modem;
| 型号： | DS8500_V01 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | HART Modem |
| 文件： | 总7页 (文件大小：474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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DS8500
HART Modem
General Description
Benefits and Features
● Single-Chip, Half-Duplex Modem Overlays 1200bps
FSK Digital Communication on Top of Installed 4mA–
20mA Current Loop Infrastructure
The DS8500 is a single-chip modem with Highway
Addressable Remote Transducer (HART) capabilities.
It has been fully tested and verified and has received a
®
HART Certificate of Registration. The device integrates
● Digital Signal Processing Provides Reliable Input
the modulation and demodulation of the 1200Hz/2200Hz
FSK signal, has very low power consumption, and needs
only a few external components due to the integrated
digital signal processing. The input signal is sampled by
an analog-to-digital converter (ADC), followed by a digi-
tal filter/demodulator. This architecture ensures reliable
signal detection in noisy environments. The output digital-
to-analog converter (DAC) generates a sine wave and
provides a clean signal with phase-continuous switching
between 1200Hz and 2200Hz. Low power is achieved
by disabling the receive circuits during transmit and vice
versa. The DS8500 is ideal for low-power process control
transmitters.
Signal Detection in Noisy Conditions
● Standard Component 3.6864MHz Crystal Reduces
System Cost
● Fully Tested and Verified as a HART-Registered
Modem IC
● Integrated Solution Requires Minimal Power and
Space
• 2.7V to 3.6V Operating Voltage
• 285μA (max) Current Consumption
• Space-Saving, 5mm x 5mm x 0.8mm, 20-Pin
TQFN Package
• Few External Components Required
Applications
Ordering Information
● 4mA–20mA Loop-Powered Transmitters for
Temperature, Pressure, Flow, and Level
Measurement
● HART Multiplexers
● HART Modem Interface Connectivity
PART
TEMP RANGE
PIN-PACKAGE
DS8500-JND+
-40°C to +85°C
20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
TOP VIEW
15
14
13
12
11
DGND 16
MODE 17
DGND 18
D_OUT 19
D_IN 20
10 XCEN
DGND
XTAL2
XTAL1
RTS
9
8
7
6
DS8500
*EP
ꢇ
HART is a registered trademark of the HART Communication
Foundation. Membership in the HART Communication
Foundation does not guarantee a product has been verified or
received a HART Registration Certificate.
1
2
3
4
5
THꢀꢁ ꢂꢃꢁ
ꢄ5mm ꢅ 5mmꢆ
*EXPOSED PAD.
19-7581; Rev 3; 2/20
DS8500
HART Modem
Absolute Maximum Ratings
Voltage Range on All Pins (including AVDD,
DVDD) Relative to Ground...............................-0.5V to +3.6V
Voltage Range on Any Pin Relative to
Operating Temperature Range........................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Soldering Temperature..........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Ground Except AVDD, DVDD...........-0.5V to (V
+ 0.5V)
DVDD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Recommended DC Operating Conditions
(V
= V
= 2.7V to 3.6V, T = -40°C to +85°C.) (Note 1)
DVDD
AVDD A
PARAMETER
SYMBOL
CONDITIONS
MIN
2.7
2.7
0
TYP
MAX
3.6
UNITS
Digital Supply Voltage
Analog Supply Voltage
Ground
V
V
V
DVDD
V
V
= V
DVDD
3.6
AVDD
AVDD
GND
AGND = DGND
Monitors V
0
V
Digital Power-Fail Reset Voltage
Active Current
V
2.59
2.64
2.69
285
0.30 x
V
RST
DVDD
I
V
= V = 2.7V (Note 2)
DVDD
µA
DD
AVDD
Input Low Voltage
V
DGND
0.75 x
V
IL
V
DVDD
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
V
V
IL
DVDD
V
DVDD
V
I
I
= 4mA
DGND
0.8 x
0.4
OL
OL
V
= -4mA
OH
OH
V
DVDD
I/O Pin Capacitance
C
Guaranteed by design (Note 3)
15
45
pF
kΩ
µA
µA
µA
IO
RST Pullup Resistance
Input Leakage Current XTAL, RST
Input Leakage Current All Other Pins
Input Low Current for RST
CLOCK SOURCE
R
I
19
-30
-2
RST
+30
+2
ILRX
I
IL
I
V
= 0.4V
170
IL1
IN
External Clock Frequency
VOLTAGE REFERENCE
Internal Reference Voltage
FSK INPUT
f
-1%
3.6864
1.23
+1%
MHz
V
HFIN
V
(Note 5)
REF
Input Voltage Range at FSK_IN
FSK OUTPUT
0
V
V
REF
Output Voltage at FSK_OUT
V
400
-1%
-1%
500
1200
2200
600
+1%
+1%
mV
P-P
AC-coupled max 30kΩ load
For a mark
OUT
Frequency of FSK_OUT (Note 4)
Hz
For a space
Note 1: Specifications to -40°C are guaranteed by design and are not production tested.
Note 2: Active currents are measured when the device is driven by an external clock XCEN = 1 condition.
Note 3: Guaranteed by design and not production tested.
Note 4: Accuracy is guaranteed based on the external crystal or clock provided.
Note 5: V
voltage is output only in demodulator mode.
REF
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DS8500
HART Modem
Pin Description
PIN
NAME
FUNCTION
1, 2
DVDD
Digital Supply Voltage
Digital Ground
3, 9,
16, 18
DGND
Active-Low Reset, Digital Input/Output. This pin includes an internal pullup resistor and is driven low
as an output when an internal reset condition occurs.
4
5
6
RST
Carrier Detect, Digital Output. A logic-high indicates a valid carrier detection on FSK_IN.
OCD
OCD = 1 when FSK_IN amplitude is greater than 120mV
.
P-P
OCD = 0 when FSK_IN amplitude is less than 80mV
.
P-P
Request to Send, Digital Input. When set high, the device is put into the demodulator mode.
A logic-low puts the device into modulator mode.
RTS
7
8
XTAL1
XTAL2
Crystal Pin or Input for External Clock at 3.6864MHz
Crystal Pin or Output of the Crystal Amplifier
External Clock Enable, Digital Input. When set high, this pin allows the user to drive an external clock
signal through XTAL1. When in this mode, XTAL2 should be left unconnected. An external crystal
must be connected between XTAL1 and XTAL2 when set low.
10
XCEN
11
12
AVDD
Analog Supply Voltage
FSK Out, Analog Output. Output of the modulator. Provides a phase-continuous, FSK-modulated output
signal (1200Hz and 2200Hz output frequencies) to the 4–20mA current loop interface circuit.
FSK_OUT
Reference, Analog Output. The internal voltage reference is provided as an output when in demodulator
mode. This pin must be connected to a 0.1µF capacitor.
13
REF
FSK In, Analog Input. Input for the FSK-modulated HART receive signal from the 4–20mA current loop
interface circuit.
14
15
17
FSK_IN
AGND
MODE
Analog Ground
This pin should be tied high for HART applications. This pin can also be tied low for support of legacy
designs.
19
20
—
D_OUT Digital Data Out, Digital Output. Output from the demodulator.
D_IN
EP
Digital Data In, Digital Input. Input to the modulator.
Exposed Pad. Should be connected to ground (DGND, AGND).
Block Diagram
RST
DVDD DGND AGND
AVDD
V
1.23V
REF
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
CLOCK
GENERATOR
POWER
MONITOR
REF
XCEN
OCD
MODE
D_OUT
Rx
DIGITAL
FILTER
SAMPLE/HOLD
ADC
FSK_IN
DEMODULATOR
RTS
Tx
DAC
FSK_OUT
MODULATOR
D_IN
DS8500
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DS8500
HART Modem
Introduction to HART
Modulator
The modulator performs the FSK modulation of the digital
data at the D_IN input. The FSK-modulated sinusoidal
signal is present at the FSK_OUT output as illustrated in
Figure 1. The modulator is enabled by RTS being a logic-
low. The modulation is done between 1200Hz (mark) or
2200Hz (space) depending on the logic level of the input
signal. The modulator preserves a continuous phase
when switching between frequencies to minimize the
bandwidth of the transmitted signal.
HART is a backward-compatible enhancement to existing
4–20mA instrumentation networks that allows two-way,
half-duplex, digital communication with a microcontroller-
based field device. The digital signal is encoded on top
of the existing instrumentation signal. Communication
is accomplished through a series of commands and
responses dependent on the specific protocol and net-
work topology. The DS8500 does not implement any
portion of the communication protocol; it only handles the
modulation and demodulation of the encoded informa-
tion. Digital data is encoded using frequency-shift keying
(FSK), which is illustrated in Figure 1. A “1” is identified as
a mark symbol and is represented with a center frequency
of 1.2kHz. A “0” is identified as a space symbol and is rep-
resented with a center frequency of 2.2kHz. This allows
a throughput of 1.2kbps, with each symbol occupying an
833μs slot.
Figure 2 illustrates an example waveform of the DS8500
in modulate mode. The data to be modulated is presented
in a UART format (start, 8 data bits, parity, stop bit) at
D_IN. FSK_OUT shows the modulated output.
Demodulator
The demodulator accepts an FSK signal at the FSK_IN
input and reproduces the original modulating signal at
the D_OUT output. The HART signal should be presented
as an 11-bit UART character with a start, data, parity, and
stop bits for proper operation of the demodulator block.
The nominal bit rate of the D_OUT signal is 1200 bits per
second. A simple RC filter is sufficient for anti-aliasing.
Figure 3 illustrates an example waveform of the DS8500
in demodulate mode.
V
Applications Information
Figure 4 shows the typical application circuit. As the
DS8500 integrates a digital filter, only a simple passive
RC filter is required in front of the ADC. R3 and C3 imple-
ment a lowpass filter with a 10kHz cutoff frequency; C2
and R2/R1 implement a highpass filter with a 480Hz cut-
off frequency. The resistor-divider formed by R1 and R2
T
provides an input bias voltage of V
(R1 = R2) when in demodulator mode. V
down in modulator mode in order to save power.
/2 to the ADC input
REF
1.2kHz MARK
"1"
2.2kHz SPACE
"0"
is powered
REF
The output DAC provides a sine-wave signal, and C4
provides the AC-coupled signal output from the DS8500.
The typical value of C4 can be anything greater than 20nF
based on the application.
Figure 1. HART FSK Signal
Functional Description
The DS8500 modem chip consists of a demodulator, car-
rier detect, digital filter, ADC for input signal conversion,
a modulator and DAC for output signal generation, and
receive and transmit state machine blocks to perform
the HART communication. The Block Diagram illustrates
the interface between various blocks of circuitry. The
input HART signal’s noise interference is attenuated by
a one-pole highpass filter that is external to the chip; the
attenuated signal is digitized by the ADC and filtered by
the receive state machine. The transmit state machine
modulates the input to the HART-compliant signal with the
help of the modulator and the DAC.
HART Registration
This IC has been tested and has received a Modem IC
Registration Certificate from the HART Communication
Foundation. The use of this HART-registered IC reduces
the customer cost and effort associated with achieving
HART registration of the end product.
A copy of the DS8500 Registration Certificate (L2-06-
1000-346) is available from the HART Communication
Foundation at www.hartcomm.org.
Technical Support
For technical support, go to http://support.maximinte-
grated.com/micro.
Maxim Integrated
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DS8500
HART Modem
1200bps/833µs
D_IN
STOP
START
8-BIT DATA
PARITY
FSK_OUT
Figure 2. Actual DS8500 Modulator Waveform
FSK_IN
STOP
PARITY
START
8-BIT DATA
D_OUT
1200bps/833µs
ONE UART CHARACTER (START, 8 DATA BITS, PARITY, STOP)
Figure 3. Actual DS8500 Demodulator Waveform
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DS8500
HART Modem
POWER SUPPLY
2.7V TO 3.6V
3.6864MHz
RST
DVDD DGND
AGND
AVDD
MODE
XTAL1
XTAL2
V
1.23V
REF
CRYSTAL
OSCILLATOR
CLOCK
GENERATOR
POWER
MONITOR
3.6864MHz
CRYSTAL
REF
27pF
27pF
C1
C3
R1
C2
XCEN
OCD
R3
FSK_IN
Rx
DIGITAL
FILTER
SAMPLE/HOLD
ADC
HART IN
DEMODULATOR
D_OUT
R2
DS8500
C4
HART AND
4–20mA
OUT
RTS
Tx
DAC
MODULATOR
D_IN
FSK_OUT
MICROCONTROLLER
4–20mA
DAC OUTPUT
Figure 4. Typical Application Circuit
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
20 TQFN
T2055+3
21-0140
90-0008
Maxim Integrated
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DS8500
HART Modem
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
10/08
Initial release.
—
In the Electrical Characteristics table, changed the Frequency of FSK_OUT
parameter units from kHz to Hz.
2
3
1
2/09
Added the EP description to the Pin Description table.
Updated Benefits and Features section, added HART registration information,
clarified alternate function of pin 17
2
3
4/15
2/20
1, 3, 4, 6
Updated Recommended DC Operating Conditions, added Note 5, Pin Description,
and Application Information section
2–4
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
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