MAX1005EEE+ [MAXIM]
Analog Circuit, 1 Func, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX1005EEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog Circuit, 1 Func, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 |
| 文件： | 总8页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1291; Rev 0; 9/97
IF Un d e rs a m p le r
MAX105
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Differential-Input, 5-Bit ADC
The MAX1005 is a combined digitizer and reconstruc-
tion integrated circuit designed to work in systems that
demodulate and modulate communications signals. It
integrates IF undersampling and signal synthesis func-
tions into a single, low-power circuit. Its analog-to-
digital converter (ADC) is used to directly sample or
und e rs a mp le a d ownc onve rte d RF s ig na l, while its
digital-to-analog converter (DAC) recreates the IF sub-
carrier and transmission data. The MAX1005’s ADC is
ideal for undersampling applications, due to the analog
input amplifier’s wide (15MHz) bandwidth. The DAC
has very low glitch energy, which minimizes the trans-
mis s ion of unwa nte d s p urious s ig na ls . An on-c hip
reference provides for low-noise ADC and DAC conver-
sions.
♦ Differential-Output, 7-Bit DAC
♦ 15Msps Min Conversion Rate
♦ 25MHz -1dB Full-Power Bandwidth
♦ 44dB SFDR for ADC
39dB at 10.7MHz SFDR (Imaged) for DAC
♦ Internal Voltage Reference
♦ Parallel Logic Interface
♦ Single-Supply Operation (+2.7V to +5.5V)
♦ 0.1µA Low-Power Shutdown Mode
The MAX1005 provides a high level of signal integrity
from a low power budget. It operates from a single
power supply, or from separate analog and digital sup-
plies with independent voltages ranging from +2.7V to
+5.5V. The MAX1005 can operate with an unregulated
analog supply of 5.5V and a regulated digital supply
down to 2.7V. This flexible power-supply operation
saves additional power in complex digital systems.
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 QSOP
MAX1005CEE
MAX1005EEE
-40°C to +85°C
16 QSOP
The MAX1005 has three operating modes: transmit
(DAC a c tive ), re c e ive (ADC a c tive ), a nd s hutd own
(ADC and DAC inactive). In shutdown mode, the total
supply current drops below 1µA. The device requires
only 2.4µs to wa ke up from s hutd own mod e . The
MAX1005 is ideal for hand-held, as well as base-station
applications. It is available in a tiny 16-pin QSOP pack-
age specified for operation over both the commercial
and extended temperature ranges.
__________________P in Co n fig u ra t io n
TOP VIEW
VCCD
DGND
RXEN
AIO+
1
2
3
4
5
6
7
8
16 CLK
15 D0
14 D1
13 D2
12 D3
11 D4
10 D5
________________________Ap p lic a t io n s
PWT1900
PHS/P
MAX1005
AIO-
Wireless Loops
PCS/N
TXEN
AGND
VCCA
9
D6
QSOP
Functional Diagram appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
IF Un d e rs a m p le r
ABSOLUTE MAXIMUM RATINGS
VCCA to AGND ........................................................-0.3V, +6.0V
VCCD to DGND........................................................-0.3V, +6.0V
VCCA to VCCD ...................................................................±6.3V
Digital I/O Pins (D0–D6, CLK, RXEN, TXEN)
Power Dissipation (T = +70°C)
A
QSOP (derate 5.90mW/°C above 70°C) ......................470mW
Operating Temperature Ranges
MAX1005CEE .....................................................0°C to +70°C
MAX1005EEE...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
to DGND .................................-0.3V to (VCCD + 0.3V) or 6.0V
(whichever is smaller)
Analog I/O Pins (AIO+, AIO-)
to AGND................................(VCCA - 1.5V) to (VCCA + 0.3V)
AGND to DGND........................................................-0.3V, +0.3V
MAX105
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCCA = VCCD = 3.0V, f
= 15MHz, R = ∞, T = T
to T , unless otherwise noted.)
MAX
CLK
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMIT DAC DC ACCURACY (Note 1)
Resolution
N
7
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
±0.2
±0.2
±1
±1
LSB
±1
LSB
Transmit Full-Scale Output Voltage
V
736
28
800
864
mVp-p
OUT
TRANSMIT DAC DYNAMIC PERFORMANCE (T = +25°C) (Note 2)
A
VCCA = VCCD = 3.0V
39
39
Spurious-Free Dynamic Range
SFDR
(Note 3)
dBc
dBc
VCCA = VCCD = 2.7V to 5.5V
Total Harmonic Distortion plus
Noise
THD+N (Note 4)
VCCA = VCCD = 3.0V
-28
2.4
Wakeup Time Exiting Shutdown
Clock Feedthrough
t
0.7
-50
µs
WAKE
PSR
(Note 5)
dBc
CLK
period
DAC Latency
(Notes 6, 7)
0.5
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
Power-Supply Rejection
67
dB
TRANSMIT ADC DC ACCURACY (Note 8)
Resolution
N
5
Bits
LSB
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
±0.2
±0.2
±2
AIO+ = AIO-
Full-Scale Input Range
V
IN
368
400
432
-24
RECEIVE ADC DYNAMIC PERFORMANCE (T = +25°C) (Note 8)
A
VCCA = VCCD = 3.0V
-42
-42
44
Total Harmonic Distortion
Spurious-Free Dynamic Range
Effective Number of Bits
THD
SFDR
ENOB
(Notes 9, 10)
(Note 9)
dB
dB
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
24
VCCA = VCCD = 2.7V to 5.5V
VCCA = VCCD = 3.0V
44
4.5
4.9
4.9
(Note 9)
Bits
VCCA = VCCD = 2.7V to 5.5V
2
_______________________________________________________________________________________
IF Un d e rs a m p le r
MAX105
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
= 15MHz, R = ∞, T = T
to T , unless otherwise noted.)
MAX
CLK
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
15
TYP
MAX
UNITS
MHz
Msps
µs
Input Full-Power Bandwidth
(-1dB)
V
IN
= 90% of full scale
25
Conversion Rate
15
Wakeup Time Exiting Shutdown
Mode
t
0.6
2.4
WAKE
VCC_ (A or D or both) = 3.0V ±100mVp-p at
100kHz
Power-Supply Rejection
PSR
<0.1
LSB
ANALOG INPUT/OUTPUT (AIO+, AIO-) (Note 11)
T
AIO-
= +25°C, differential between AIO+ and
A
Input Resistance
R
1.56
2.00
2.44
kΩ
ppm/°C
pF
IN
Input Resistance Temperature
Coefficient
TCR
-2000
IN
Differential between AIO+ and AIO-
AIO+ or AIO- to GND
4
4
Input Capacitance (Note 6)
POWER REQUIREMENTS
Supply Voltage
C
IN
VCCA,
VCCD
2.7
5.5
14.8
3.8
6.4
5.6
5
V
RXEN = 1, TXEN = 0,
ADC on, DAC off
9.0
2.5
VCCA = VCCD
= 3.0V,
C
Analog Supply Current
ICCA
ICCD
mA
RXEN = 0, TXEN = 1,
ADC off, DAC on
≤ 12.5pF
L
RXEN = 1, TXEN = 0,
ADC on, DAC off
4.0
VCCA = VCCD
= 3.0V,
C
Digital Supply Current
mA
µA
RXEN = 0, TXEN = 1,
ADC off, DAC on
≤ 12.5pF
L
3.0
ICCA + VCCA = VCCD = 3.0V, C ≤ 12.5pF,
L
Shutdown Supply Current
<0.1
ICD
RXEN = TXEN
DIGITAL INPUTS/OUTPUTS (D0–D6, RXEN, TXEN, CLK) (Note 12)
D0–D4, VCCD = 2.7V to 5.5V,
= 200µA
Output High Voltage
Output Low Voltage
V
VCCD - 1.0
VCCD
0.5
V
V
OH
I
SOURCE
V
OL
D0–D4, VCCD = 2.7V to 5.5V, I
= 50µA
0
SINK
D0–D6, CLK
VCCD = 2.7V
0.7VCCD
Input High Voltage
Input Low Voltage
V
V
V
IH
VCCD -
0.5
VCCD +
0.1
to 5.5V
RXEN, TXEN
D0–D6, CLK
RXEN, TXEN
0.3VCCD
0.5
VCCD = 2.7V
to 5.5V
V
IL
-0.1
_______________________________________________________________________________________
3
IF Un d e rs a m p le r
ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCD = 3.0V, f
= 15MHz, R = ∞, T = T
to T , unless otherwise noted.)
MAX
CLK
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
7
UNITS
µA
D0–D6, CLK; VCCD = 2.7V to 5.5V
-1
TXEN = RXEN
RXEN, TXEN;
±1
VCCD = 2.7V
to 3.6V
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
±2
±1
±4
8
Input Current
I
IN
MAX105
TXEN = RXEN
RXEN, TXEN;
VCCD = 3.6V
to 5.5V
TXEN = 0 and RXEN = 1, or
TXEN = 1 and RXEN = 0
Input Capacitance
C
D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)
pF
IN
TIMING CHARACTERISTICS (Data Outputs: R = 1MΩ, C = 15pF, T = T
to T , unless otherwise noted.) (Note 12)
MAX
L
L
A
MIN
DAC Data Setup Time
DAC Data Hold Time
CLK Duty Cycle
t
T
= +25°C (Note 6)
5
5
0.6
0.3
ns
ns
%
DS
A
t
T
A
= +25°C (Note 6)
HOLD
45
55
20
ADC CLK to Output Data Valid
t
C
≤ 12.5pF
L
13
ns
DO
Note 1: TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-
Point Linearity method.
Note 2:
f
IN
= 4.3MHz digital sine wave applied to DAC data inputs; f
= 15MHz. The reference frequency (f ) is defined to be
REF
CLK
10.7MHz (f
- f ). All frequency components present in the DAC output waveform except for f
and f are consid-
REF IN
CLK IN
ered spurious.
Note 3: For DAC SFDR measurements, the amplitude of f
(10.7MHz) is compared to the amplitudes of all frequency compo-
REF
nents of the output waveform except for f (4.3MHz).
IN
Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of
all harmonic and noise components of the output waveform (except for f and f
IN
) to the RMS amplitude of the f
com-
REF
REF
ponent.
Note 5: Clock feedthrough is defined as the difference in amplitude between the f
measured differentially from AIO+ to AIO-.
component and the f
component when
REF
CLK
Note 6: Guaranteed by design. Not production tested.
Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to
propagate through to the DAC switches.
Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-
entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.
Note 9:
f
IN
= 10.7MHz, f
= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (f ) is defined to be 4.3MHz
REF
CLK
(f
- f ). All components except for f
and f are considered spurious.
REF IN
CLK IN
Note 10: Receive ADC THD measurements include the first five harmonics.
Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause
latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are
required, then bypass these pins only to VCCA.
Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are
measured to V
for rising output signals and to V
for falling output signals. The values for V and V
OH(AC) OL(AC)
OH(AC)
OL(AC)
as a function of the VCCD supply are shown in the following table:
VCCD (V)
2.7 to 3.3
3.3 to 5.5
V
(V)
V
(V)
OL(AC)
OH(AC)
VCCD - 1.1
2/3 x VCCD
0.5
0.5
4
_______________________________________________________________________________________
IF Un d e rs a m p le r
MAX105
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(VCCA = VCCD = 3.0V, T = +25°C, unless otherwise noted.)
A
RECEIVE ADC
INTEGRAL NONLINEARITY
RECEIVE ADC
DIFFERENTIAL NONLINEARITY
TRANSMIT DAC
INTEGRAL NONLINEARITY
0.50
0.40
0.50
0.40
0.5
0.4
0.30
0.30
0.3
0.20
0.20
0.2
0.10
0.10
0.1
0.00
0.00
0
-0.10
-0.20
-0.30
-0.40
-0.50
-0.10
-0.20
-0.30
-0.40
-0.50
-0.1
-0.2
-0.3
-0.4
-0.5
-15 -12 -9 -6 -3
0
3
6
9
12 15
-15 -12 -9 -6 -3
0
3
6
9
12 15
-64 -48 -32 -16
0
16 32 48 64
CODE
CODE
CODE
TRANSMIT DAC
DIFFERENTIAL NONLINEARITY
FULL POWER ANALOG
INPUT BANDWIDTH
RECEIVE ADC FFT PLOT
0.5
0.4
30
20
0
-1
-2
-3
-4
-5
-6
-7
f
= 10.7MHz
= 15MHz
256 POINTS
IN
V
IN
= 90% OF FULL SCALE
f
CLK
0.3
10
0.2
0
0.1
-10
-20
-30
-40
-50
-60
-70
0
-0.1
-0.2
-0.3
-0.4
-0.5
-64 -48 -32 -16
0
16 32 48 64
0
1.465 2.930
4.395 5.860
7.325
1
10
100
CODE
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
IF Un d e rs a m p le r
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
VCCD
Digital Supply Voltage, +2.7V to +5.5V
1
2
DGND
Digital Ground. Connect to digital ground plane.
Receive ADC Enable Input. A logic-high level on this input combined with a logic-low level on TXEN enables
the receive ADC and disables the transmit DAC. If RXEN = TXEN, the MAX1005 enters its low-power shut-
down mode.
3
RXEN
MAX105
Positive Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO+ is the positive analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO+ is the positive transmit DAC output pin.
4
5
AIO+
AIO-
Negative Analog Input/Output Pin. If RXEN = 1 and TXEN = 0, then AIO- is the negative analog input to the
receive ADC. If RXEN = 0 and TXEN = 1, then AIO- is the negative transmit DAC output pin.
Transmit DAC Enable Input. A logic-high level on this input combined with a logic-low level on RXEN
enables the transmit DAC and disables the receive ADC. If RXEN = TXEN, the MAX1005 enters its low-
power shutdown mode.
6
TXEN
7
8
AGND
VCCA
D6, D5
Analog Ground. Connect to analog ground plane.
Analog Supply Voltage, +2.7V to +5.5V
9, 10
Two MSBs for DAC input data. D6 is the MSB.
Data Input/Output Pins. If RXEN = 0 and TXEN = 1, then D4–D0 function as the five lower bits of DAC input
data, with D0 as the LSB. If RXEN = 1 and TXEN = 0, then D4–D0 function as the five data outputs for the
ADC, with D4 as the MSB and D0 as the LSB. In low-power shutdown mode (RXEN = TXEN), D0–D4 should
not be externally held high, to prevent excessive input leakage currents.
11–15
16
D4–D0
Clock Input. If the receive ADC is active (RXEN = 1, TXEN = 0), the analog input is sampled on the falling
edge of clock and the data outputs (D4-D0) are updated on the rising edge of CLK. If the transmit DAC is
active (TXEN = 1, RXEN = 0), input data is clocked in on the falling edge of CLK and the DAC output is
updated on the rising edge of CLK. The input clock may continue to run when the MAX1005 is shut down
(TXEN = RXEN).
CLK
Table 1. Transmit DAC Code Table
_______________De t a ile d De s c rip t io n
The MAX1005 is designed to operate with the Maxim
PWT1900 (TAG-6) wireless transceiver chipset consisting
of the MAX2411 RF transceiver, the MAX2511 IF trans-
ceiver, and the MAX1007 power-control/diversity IC. The
MAX1005 integrates all the functions of an IF undersam-
pler into a single low-power integrated circuit. It is also
well suited for other time-division duplex (TDD) communi-
cations systems. This device includes a 7-bit transmit
DAC, a 5-bit receive ADC, two internal bandgap refer-
ences, clock drivers, and all necessary interface and
control logic.
DAC INPUT DATA
ANALOG OUTPUT
011 1111
000 0000
100 0000
+FS
0
-FS
Re c e ive ADC
The 5-bit receive ADC is used to directly sample or
undersample a downconverted RF signal. The ADC
converts an analog input signal to a 5-bit digital output
code in the twos-complement format. Figure 1 shows
the ADC transfer function.
Tra ns m it DAC
The low-side alias frequency (f
- f
= 10.7MHz)
CLK
OUT
Analog input signals are applied differentially between
AIO+ and AIO-, with a full-scale range of ±200mV. An
internal amplifier buffers the input signal and drives the
comparator array, minimizing loading on the external
signal source. The input amplifier has a full-power -1dB
bandwidth of at least 15MHz, making this device ideally
suited for undersampling applications.
generated by the MAX1005’s 7-bit DAC is used to recre-
ate the IF sub-carrier and transmission data in TDD and
other communications systems. The DAC accepts CMOS
input data in the twos-complement format and outputs a
corresponding analog voltage differentially between
AIO+ and AIO-. The full-scale output voltage range is typ-
ically ±400mV. The DAC code table is shown in Table 1.
6
_______________________________________________________________________________________
IF Un d e rs a m p le r
MAX105
SAMPLE
n
SAMPLE
n + 2
SAMPLE
n + 1
01111
01110
ANALOG
INPUT
CLK
00010
00001
00000
D0–D4
n - 1
n
n + 1
11111
11110
11101
t
DO
Figure 3. Receive ADC Timing Diagram
10001
10000
Op e ra t in g Mo d e s
The MAX1005 has three operating modes: transmit,
receive, and shutdown. The operating mode is selected
by the RXEN and TXEN inputs, as shown in Table 2.
COM
- FS
+FS
INPUT VOLTAGE (LSB)
In transmit mode, the DAC is active and the ADC is
inactive. Power consumption is typically 16.5mW with a
3V supply voltage. In receive mode, the ADC is active
and the DAC is inactive. Power consumption in this
mode is typically 39mW with a 3V supply voltage.
Figure 1. Receive ADC Transfer Function
The third mode is shutdown, in which both the DAC
and the ADC are inactive. Select this mode by setting
RXEN = TXEN at any voltage from DGND to VCCD. In
shutdown mode, the CLK input can continue to run
without damaging the device and with no significant
increase in the typical shutdown supply current specifi-
cation of 0.1µA. When exiting shutdown, the MAX1005
is guaranteed to be operational within 2.4µs after TXEN
or RXEN is asserted, as shown in Table 2.
CLK
t
DS
DAC
INPUT
DATA
n - 1
n
n + 1
n + 2
(D0–D6)
t
HOLD
DAC
OUTPUT
n - 1
n
n + 1
To prevent supply-current drain due to leakage cur-
rents from entering the ADC output bits, the ADC out-
puts (D0–D4) should not be held high in low-power
shutdown mode.
Figure 2. Transmit DAC Timing Diagram
Dig it a l In t e rfa c e
The DAC has a 7-bit parallel digital interface. Figure 2
shows the timing diagram for the transmit DAC. Digital
data is latched into the DAC input register on the falling
edge of CLK. On the next rising edge of CLK the data
is transferred to the DAC register and the DAC output
voltage is updated.
Table 2. Operating Mode Selection
RXEN
TXEN
OPERATING MODE
Low-power shutdown: ADC and DAC
disabled
0
0
The ADC is enabled by setting TXEN = 0 and RXEN =
1. Figure 3 shows the ADC timing diagram. Input data
is sampled on the falling edge of CLK, while output
data changes state on the rising edge of CLK. This
minimizes digital feedthrough and noise while the ana-
log input is being sampled. The ADC output data is
applied to the 5-bit parallel output pins (D0–D4), with
the MSB at D4.
0
1
1
0
Transmit mode: DAC active, ADC disabled
Receive mode: ADC active, DAC disabled
Low-power shutdown: ADC and DAC
disabled
1
1
_______________________________________________________________________________________
7
IF Un d e rs a m p le r
P o w e r-S u p p ly Byp a s s in g a n d Gro u n d in g
The MAX1005 has separate analog (VCCA) and digital
(VCCD) power-supply connections, as well as separate
analog and digital ground connections to minimize cou-
pling of noisy digital signals into the circuit’s analog por-
tion. The device will operate with both of these power
supplies connected to any voltage between +2.7V and
+5.5V. This feature allows the digital circuitry to operate
from a regulated logic power supply; this reduces power
consumption and maintains compatibility with external
logic, while allowing the analog circuitry to operate from
an unregulated supply.
________________Fu n c t io n a l Dia g ra m
TXEN
RXEN VCCA AGND VCCD DGND
DAC
BANDGAP
REFERENCE REFERENCE
ADC
BANDGAP
ADC
CLOCK
DRIVER
CLK
MAX105
VCCA
DAC
CLOCK
DRIVER
1k
1k
The analog ground (AGND) and digital ground (DGND)
should be tied together close to the device. At no time
should the voltage between AGND and DGND exceed
±0.3V.
AIO+
AIO-
5-BIT
FLASH ADC
5
7
DIGITAL
INTERFACE
D6–D0
7
The entire board needs good DC bypassing for both
analog and digital supplies. Place the power-supply
bypass capacitors close to where the power is routed
onto board. 10µF electrolytic capacitors with low equiva-
lent-series-resistance (ESR) ratings are recommended.
For best effective bits performance, minimize capacitive
loading at the digital outputs. Keep the digital output
traces as short as possible. Bypass each of the VCC_
s up p ly p ins to its re s p e c tive GND with hig h-q ua lity
ceramic capacitors located as close to the package as
possible.
7-BIT DAC
MAX1005
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2377
SUBSTRATE CONNECTED TO AGND
________________________________________________________P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
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