MAX1030BCTI+T [MAXIM]
ADC, Successive Approximation, 10-Bit, 1 Func, 16 Channel, Serial Access, BICMOS, 5 X 5 MM, TQFN-28;
| 型号： | MAX1030BCTI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 10-Bit, 1 Func, 16 Channel, Serial Access, BICMOS, 5 X 5 MM, TQFN-28 信息通信管理 转换器 |
| 文件： | 总23页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2853; Rev 2; 10/05
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
General Description
Features
The MAX1026/MAX1028/MAX1030 are serial 10-bit ana-
log-to-digital converters (ADCs) with an internal reference
and an internal temperature sensor. These devices fea-
ture on-chip FIFO, scan mode, internal clock mode, inter-
nal averaging, and AutoShutdown™. The maximum
sampling rate is 300ksps using an external clock. The
MAX1030 has 16 input channels, the MAX1028 has 12
input channels, and the MAX1026 has 8 input channels.
All input channels are configurable for single-ended or
differential inputs in unipolar or bipolar mode. All three
devices operate from a +5V supply and contain a 10MHz
SPI™/QSPI™/MICROWIRE™-compatible serial port.
♦ Internal Temperature Sensor (±±1° ꢀAAuraAcy
♦ ±6-Entrc First-In/First-Out (FIFOy
♦ ꢀnalog Multiplexer with True Differential
TraAk/Hold
±6-, ±2-, 8-°hannel Single Ended
8-, 6-, 4-°hannel True Differential
(Unipolar or Bipolary
♦ ꢀAAuraAc: ±± ꢁSB Iꢂꢁ, ±± ꢁSB Dꢂꢁ, ꢂo Missing
°odes Over Temperature
♦ SAan Mode, Internal ꢀveraging, and Internal °loAk
The MAX1030 is available in 28-pin 5mm x 5mm TQFN
with exposed pad and 24-pin QSOP packages. The
MAX1026/MAX1028 are only available in QSOP pack-
ages. All three devices are specified over the extended
-40°C to +85°C temperature range.
♦ ꢁow-Power Single +5V Operation
±.9mꢀ at 300ksps
♦ Internal 4.096V ReferenAe or External Differential
ReferenAe
♦ ±0MHz 3-Wire SPI/QSPI/MI°ROWIRE-°ompatible
InterfaAe
________________________Applications
System Supervision
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
♦ SpaAe-Saving 28-Pin 5mm x 5mm TQFꢂ PaAkage
Ordering Information
TEMP
RꢀꢂGE
PIꢂ-
Pꢀ°KꢀGE
PKG
°ODE
PꢀRT
MꢀX±026ACEE-T
0°C to +70°C
16 QSOP
E16-1
E16-1
Instrumentation
MAX1026AEEE-T
-40°C to +85°C 16 QSOP
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
Ordering Information continued at end of data sheet.
MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations
TOP VIEW
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
20 EOC
19 DOUT
18 DIN
17 CS
AIN0
1
2
3
4
5
6
7
8
16 EOC
15 DOUT
14 DIN
13 CS
AIN1
AIN2
MAX1028
16 SCLK
AIN3
MAX1026
15
14
V
DD
AIN4
12 SCLK
GND
AIN5
11
10 GND
REF+
V
DD
13 REF+
REF-/AIN6
CNVST/AIN7
12 CNVST/AIN11
11 REF-/AIN10
9
AIN9 10
QSOP
QSOP
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
±
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
ꢀBSOꢁUTE MꢀXIMUM RꢀTIꢂGS
DD
V
to GND..............................................................-0.3V to +6V
Operating Temperature Ranges
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (V
AIN0–AIN13, REF-/AIN_, CNVST/AIN_,
REF+ to GND.........................................-0.3V to (V
Maximum Current into Any Pin............................................50mA
+ 0.3V)
MAX10__C__.......................................................0°C to +70°C
MAX10__E__....................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
20-Pin QSOP (derate 9.1mW/°C above +70°C)...........727mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
28-Pin TQFN 5mm x 5mm
(derate 20.8mW/°C above +70°C)..........................1667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢁE°TRI°ꢀꢁ °HꢀRꢀ°TERISTI°S
(V
= +5V 5ꢀ, f
= 300kHz, f
= 4.8MHz (50ꢀ duty cycle), V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PꢀRꢀMETER
D° ꢀ°°URꢀ°Y (ꢂote ±y
Resolution
SYMBOꢁ
°OꢂDITIOꢂS
MIꢂ
TYP
MꢀX
UꢂITS
RES
INL
10
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
1.0
1.0
2.0
2.0
DNL
No missing codes over temperature
(Note 2)
0.5
0.5
Gain Error
Offset Error Temperature
Coefficient
ppm/°C
FSR
2
Gain Temperature Coefficient
0.8
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYꢂꢀMI° SPE°IFI°ꢀTIOꢂS (±0kHz sine wave input, 4.096VP-P, 300ksps, fS°ꢁK = 4.8MHzy
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
70
-82
80
76
1
dB
dBc
dBc
dBc
MHz
kHz
Up to the 5th harmonic
SFDR
IMD
f
= 9.9kHz, f = 10.2kHz
in2
in1
-3dB point
Full-Linear Bandwidth
S / (N + D) > 68dB
25
2
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
EꢁE°TRI°ꢀꢁ °HꢀRꢀ°TERISTI°S (Aontinuedy
(V
= +5V 5ꢀ, f
= 300kHz, f
= 4.8MHz (50ꢀ duty cycle), V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PꢀRꢀMETER
SYMBOꢁ
°OꢂDITIOꢂS
MIꢂ
TYP
MꢀX
UꢂITS
°OꢂVERSIOꢂ RꢀTE
External reference
0.8
65
Power-Up Time
Acquisition Time
Conversion Time
t
µs
µs
µs
PU
Internal reference (Note 3)
t
0.6
ACQ
Internally clocked
3.5
t
CONV
Externally clocked (Note 4)
Externally clocked conversion
Data I/O
2.7
0.1
4.8
10
60
External Clock Frequency
f
MHz
SCLK
SCLK Duty Cycle
Aperture Delay
Aperture Jitter
40
ꢀ
ns
ps
30
<50
ꢀꢂꢀꢁOG IꢂPUT
Unipolar
0
V
REF
Input Voltage Range
V
Bipolar (Note 5)
-V
/ 2
V
REF
/ 2
REF
Input Leakage Current
Input Capacitance
V
= V
0.01
24
1
µA
pF
IN
DD
During acquisition time (Note 6)
IꢂTERꢂꢀꢁ TEMPERꢀTURE SEꢂSOR
Grade A, T = +25°C
0.3
0.5
0.75
0.7
1.2
0.1
1/8
0.3
A
Grade A, T = -20°C to +85°C
1
A
Measurement Error (Note 7)
Grade A, T = T
to T
1.5
°C
A
MIN
MAX
Grade B, T = +25°C
A
Grade B, T = T
A
to T
3.0
MIN
MAX
Temperature Measurement Noise
Temperature Resolution
Power-Supply Rejection
IꢂTERꢂꢀꢁ REFEREꢂ°E
REF Output Voltage
°C
RMS
°C
°C/V
4.024
4.096
8
4.168
V
Grade A
Grade B
REF Temperature Coefficient
TC
ppm/°C
REF
30
Output Resistance
6.5
200
-70
kΩ
REF Output Noise
µV
RMS
REF Power-Supply Rejection
EXTERꢂꢀꢁ REFEREꢂ°E IꢂPUT
REF- Input Voltage Range
REF+ Input Voltage Range
PSRR
dB
V
0
500
+ 50mV
100
mV
V
REF-
V
1.0
V
DD
REF+
V
V
= 4.096V, f
= 4.096V, f
= 300ksps
= 0
40
REF+
REF+
SAMPLE
SAMPLE
REF+ Input Current
I
µA
REF+
0.1
5
_______________________________________________________________________________________
3
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
EꢁE°TRI°ꢀꢁ °HꢀRꢀ°TERISTI°S (Aontinuedy
(V
= +5V 5ꢀ, f
= 300kHz, f
= 4.8MHz (50ꢀ duty cycle), V
= 4.096V, T = T
to T
, unless otherwise noted.
MAX
DD
SAMPLE
SCLK
REF
A
MIN
Typical values are at T = +25°C.)
A
PꢀRꢀMETER
SYMBOꢁ
°OꢂDITIOꢂS
MIꢂ
TYP
MꢀX
UꢂITS
DIGITꢀꢁ IꢂPUTS (S°ꢁK, DIꢂ, CS, CNVST)
Input Voltage Low
V
0.8
V
V
IL
Input Voltage High
V
2.0
IH
Input Hysteresis
V
200
0.01
15
mV
µA
pF
HYST
Input Leakage Current
Input Capacitance
I
V
= 0 or V
DD
1.0
IN
IN
C
IN
DIGITꢀꢁ OUTPUTS (DOUT, EO°y
I
I
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Voltage Low
V
V
OL
SINK
Output Voltage High
V
= 1.5mA
V - 0.5
DD
V
OH
SOURCE
Tri-State Leakage Current
Tri-State Output Capacitance
POWER REQUIREMEꢂTS
Supply Voltage
I
CS = V
CS = V
0.05
15
1
µA
pF
L
DD
DD
C
OUT
V
4.75
5.25
3100
2300
1350
5
V
DD
DD
During temp sense
2400
1950
1000
0.2
f
f
= 300ksps
Internal
reference
SAMPLE
SAMPLE
= 0, REF on
Supply Current (Note 8)
I
µA
Shutdown
During temp sense
1650
1250
0.2
2300
1500
5
External
reference
f
= 300ksps
SAMPLE
Shutdown
Power-Supply Rejection
PSR
V
= 4.75V to 5.25V; full-scale input
0.2
1
mV
DD
ꢂote ±: Tested at V
= +5V, unipolar input mode.
DD
ꢂote 2: Offset nulled.
ꢂote 3: Time for reference to power up and settle to within 1 LSB.
ꢂote 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle.
ꢂote 5: The operational input voltage range for each individual input of a differentially configured pair is from GND to V . The oper-
DD
ational input voltage difference is from -V
/ 2 to +V
/ 2.
REF
REF
ꢂote 6: See Figure 3 (Input Equivalent Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
ꢂote 7: Fast automated test, excludes self-heating effects.
ꢂote 8: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
Temperature measurements always use the internal reference.
4
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
TIMIꢂG °HꢀRꢀ°TERISTI°S (Figure ±y
PꢀRꢀMETER
SYMBOꢁ
°OꢂDITIOꢂS
Externally clocked conversion
Data I/O
MIꢂ
208
100
40
TYP
MꢀX
UꢂITS
SCLK Clock Period
t
ns
CP
SCLK Duty Cycle
t
60
40
40
40
40
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
µs
CH
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS to SCLK Rise Setup
SCLK Rise to CS Hold
t
C
C
C
= 30pF
= 30pF
= 30pF
DOT
LOAD
LOAD
LOAD
t
DOD
t
DOE
t
DS
DH
t
0
t
40
CSS
CSH
t
0
t
CKSEL = 00, CKSEL = 01 (temp sense)
CKSEL = 01 (voltage conversion)
Temp sense
40
1.4
CSW
CNVST Pulse Width
t
t
55
7
TS
RP
CS or CNVST Rise to EOC
Low (Note 9)
Voltage conversion
µs
Reference power-up
65
ꢂote 9: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive. The internal reference is always used for temperature measurements.
Typical Operating Characteristics
(V
= +5V, V
= +4.096V, f
= 4.8MHz, C = 30pF, T = +25°C, unless otherwise noted.)
LOAD A
DD
REF
SCLK
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
SINAD vs. FREQUENCY
vs. OUTPUT CODE
0.4
0.4
100
90
80
70
60
50
40
30
20
10
0
0.3
0.2
0.3
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
0
256
512
768
1024
0
256
512
768
1024
0.1
1
10
100
1000
OUTPUT CODE
OUTPUT CODE
FREQUENCY (kHz)
_______________________________________________________________________________________
5
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Typical Operating Characteristics (continued)
(V
= +5V, V
= +4.096V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
DD
REF
SCLK
LOAD A
SFDR vs. FREQUENCY
SUPPLY CURRENT vs. SAMPLING RATE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
120
100
80
60
40
20
0
1200
1200
1150
1100
1050
1000
1000
800
600
400
200
0.1
1
10
100
1000
1
10
100
1000
4.75
4.85
4.95
5.05
5.15
5.25
FREQUENCY (kHz)
SAMPLING RATE (ksps)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1300
0.6
0.5
0.4
0.3
0.2
0.1
f
= 300ksps
S
1250
1200
1150
1100
1050
1000
0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
4.0500
4.0499
4.0498
4.0497
4.0496
4.0495
4.0494
0.6
0.5
0.4
0.3
0.2
0.1
0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Typical Operating Characteristics (continued)
(V
= +5V, V
= +4.096V, f
= 4.8MHz, C
= 30pF, T = +25°C, unless otherwise noted.)
A
DD
REF
SCLK
LOAD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
OFFSET ERROR
vs. TEMPERATURE
4.051
0.6
0.5
0.4
0.3
0.2
0.1
0.6
0.5
0.4
0.3
0.2
0.1
0
4.050
4.049
4.048
4.047
0
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.5
0
0.5
0
-0.5
-1.0
-0.5
-1.0
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SAMPLING ERROR
vs. SOURCE IMPEDANCE
TEMPERATURE SENSOR ERROR
vs. TEMPERATURE
1
1.00
0.75
0
-1
-2
-3
-4
-5
0.50
0.25
GRADE A
0
-0.25
GRADE B
-0.50
-0.75
-1.00
0
2
4
6
8
10
-40
-15
10
35
60
85
SOURCE IMPEDANCE (kΩ)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Pin Description
MꢀX±030 MꢀX±030
MꢀX±028 MꢀX±026
ꢂꢀME
N.C.
FUꢂ°TIOꢂ
TQFꢂ
QSOP
1, 17, 19,
25
—
—
—
—
—
No Connection. Not internally connected.
Analog Inputs
2–12, 26,
27, 28
1–14
AIN0–13
—
—
—
—
1–10
—
—
AIN0–9
AIN0–5
Analog Inputs
Analog Inputs
1–6
Negative Input for External Differential Reference/Analog Input 14.
See Table 3 for details on programming the setup register.
13
—
—
14
—
—
15
—
—
16
—
—
—
11
—
—
12
—
—
—
7
REF-/AIN14
REF-/AIN10
REF-/AIN6
Negative Input for External Differential Reference/Analog Input 10.
See Table 3 for details on programming the setup register.
Negative Input for External Differential Reference/Analog Input 6.
See Table 3 for details on programming the setup register.
CNVST/
AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3
for details on programming the setup register.
—
—
8
CNVST/
AIN11
Active-Low Conversion Start Input/Analog Input 11. See Table 3
for details on programming the setup register.
CNVST/
AIN7
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
15
16
18
17
18
19
13
14
15
9
REF+
GND
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
10
11
V
Power Input. Bypass to GND with a 0.1µF capacitor.
DD
Serial Clock Input. Clocks data in and out of the serial interface.
(Duty cycle must be 40ꢀ to 60ꢀ.) See Table 3 for details on
programming the clock mode.
20
20
16
12
SCLK
Active-Low Chip-Select Input. When CS is low, the serial interface
is enabled. When CS is high, DOUT is high impedance.
21
22
21
22
17
18
13
14
CS
Serial Data Input. DIN data is latched into the serial interface on
the rising edge of SCLK.
DIN
Serial Data Output. Data is clocked out on the falling edge of
23
24
23
24
19
20
15
16
DOUT
SCLK. High impedance when CS is connected to V
.
DD
EOC
End of Conversion Output. Data is valid after EOC pulls low.
8
_______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
CS
t
CSH
t
t
t
CSH
t
CH
CP
CSS
t
CSS
SCLK
DIN
t
DH
t
DS
t
t
DOT
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
EOC
OSCILLATOR
CONTROL
CNVST
AIN1
AIN2
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
T/H
AIN15
TEMP
SENSE
REF-
REF+
INTERNAL
REFERENCE
MAX1026
MAX1028
MAX1030
Figure 2. Functional Diagram
configurations. Microprocessor (µP) control is made
easy through a 3-wire SPI/QSPI/MICROWIRE-compati-
ble serial interface.
Detailed Description
The MAX1026/MAX1028/MAX1030 are low-power, seri-
al-output, multichannel ADCs with temperature-sensing
capability for temperature-control, process-control, and
monitoring applications. These 10-bit ADCs have inter-
nal track and hold (T/H) circuitry that supports single-
ended and fully differential inputs. Data is converted
from an internal temperature sensor or analog voltage
sources in a variety of channel and data-acquisition
Figure 2 shows a simplified functional diagram of the
MAX1026/MAX1028/MAX1030 internal architecture. The
MAX1026 has eight single-ended analog input chan-
nels or four differential channels. The MAX1028 has 12
single-ended analog input channels or six differential
channels. The MAX1030 has 16 single-ended analog
input channels or eight differential channels.
_______________________________________________________________________________________
9
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Tables 1–7 detail the register descriptions. Bits 5 and 4,
Converter Operation
The MAX1026/MAX1028/MAX1030 ADCs use a fully dif-
ferential, successive-approximation register (SAR) con-
version technique and an on-chip T/H block to convert
temperature and voltage signals into a 10-bit digital
result. Both single-ended and differential configurations
are supported, with a unipolar signal range for single-
ended mode and bipolar or unipolar ranges for differ-
ential mode.
CKSEL1 and CKSEL0, respectively, control the clock
modes in the setup register (see Table 3). Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conver-
sion start and use it to request the programmed inter-
nally timed conversions without tying up the serial bus.
In clock mode 01, use CNVST to request conversions
one channel at a time, controlling the sampling speed
without tying up the serial bus. Request and start inter-
nally timed conversions through the serial interface by
writing to the conversion register in the default clock
mode, 10. Use clock mode 11 with SCLK up to 4.8MHz
for externally timed acquisitions to achieve sampling
rates up to 300ksps. Clock mode 11 disables scanning
and averaging. See Figures 4–7 for timing specifica-
tions and how to begin a conversion.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequen-
cy signals aliasing into the frequency band of interest.
Analog Input Protection
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the
last-requested operation and is waiting for the next
input data byte (for clock modes 00 and 10). For clock
mode 01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or CNVST
goes low. EOC is always high in clock mode 11.
Internal ESD protection diodes clamp all pins to V
DD
and GND, allowing the inputs to swing from (GND -
0.3V) to (V + 0.3V) without damage. However, for
DD
accurate conversions near full scale, the inputs must
not exceed V by more than 50mV or be lower than
DD
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
Single-Ended/Differential Input
The MAX1026/MAX1028/MAX1030 use a fully differen-
tial ADC for all conversions. The analog inputs can be
configured for either differential or single-ended con-
versions by writing to the setup register (see Table 3).
Single-ended conversions are internally referenced to
GND (see Figure 3).
3-Wire Serial Interface
The MAX1026/MAX1028/MAX1030 feature a serial
interface compatible with SPI/QSPI and MICROWIRE
devices. For SPI/QSPI, ensure the CPU serial interface
runs in master mode so it generates the serial clock
signal. Select the SCLK frequency of 10MHz or less,
and set clock polarity (CPOL) and phase (CPHA) in the
µP control registers to the same value. The MAX1026/
MAX1028/MAX1030 operate with SCLK idling high or
low, and thus operate with CPOL = CPHA = 0 or CPOL
= CPHA = 1. Set CS low to latch input data at DIN on
the rising edge of SCLK. Output data at DOUT is
updated on the falling edge of SCLK. Bipolar true-dif-
ferential results and temperature sensor results are
available in two’s complement format, while all others
are in binary.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from
the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
and AIN14/AIN15. AIN0–AIN7 are available on the
MAX1026, MAX1028, and MAX1030. AIN8–AIN11 are
only available on the MAX1028 and MAX1030.
AIN12–AIN15 are only available on the MAX1030. See
Tables 2–5 for more details on configuring the inputs.
For the inputs that can be configured as CNVST or an
analog input, only one can be used at a time. For the
inputs that can be configured as REF- or an analog
input, the REF- configuration excludes the analog input.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. Send a second
byte, immediately following the setup byte, to write to
the unipolar mode or bipolar mode registers (see
Tables 1, 3, 4, and 5). A high-to-low transition on CS ini-
tiates the data input operation. The input data byte and
the subsequent data bytes are clocked from DIN into
the serial interface on the rising edge of SCLK.
±0 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
needed for a signal to be acquired, plus the power-up
time. It is calculated by the following equation:
REF
GND
AIN0-AIN15
(SINGLE ENDED);
AIN0, AIN2,
DAC
t
= 9 x R + R
x 24pF + t
PWR
(
)
AQC
S
IN
AIN4…AIN14
(DIFFERENTIAL)
CIN+
COMPARATOR
+
where R = 1.5kΩ, R is the source impedance of the
IN
S
PWR
input signal, and t
= 1µs, the power-up time of the
HOLD
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
-
GND
(SINGLE ENDED);
AIN1, AIN3,
AIN5…AIN15
(DIFFERENTIAL)
CIN-
t
is never less than 1.4µs, and any source imped-
ACQ
ance below 300Ω does not significantly affect the
HOLD
HOLD
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening t
or by
ACQ
V
DD
/2
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
Figure 3. Equivalent Input Circuit
Internal FIFO
The MAX1026/MAX1028/MAX1030 contain a FIFO
buffer that can hold up to 16 ADC results plus one tem-
perature result. This allows the ADC to handle multiple
internally clocked conversions and a temperature mea-
surement, without tying up the serial bus.
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
appropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0 to
If the FIFO is filled and further conversions are request-
ed without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by 4
leading zeros and the LSB followed by 2 sub-bits. After
each falling edge of CS, the oldest available byte of
data is available at DOUT, MSB first. When the FIFO is
empty, DOUT is zero.
V
. A negative differential analog input in unipolar
REF
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to
V
REF
/ 2. The digital output code is binary in unipo-
lar mode and two’s complement in bipolar mode (see
the transfer function graphs, Figures 8 and 9).
In single-ended mode, the MAX1026/MAX1028/
MAX1030 always operate in unipolar mode. The analog
inputs are internally referenced to GND with a full-scale
The first 2 bytes of data read out after a temperature mea-
surement always contain the temperature result preceded
by 4 leading zeros, MSB first. If another temperature mea-
surement is performed before the first temperature result
is read out, the old measurement is overwritten by the
new result. Temperature results are in degrees Celsius
(two’s complement) at a resolution of 1/8 of a degree. See
the Temperature Measurements section for details on
converting the digital code to a temperature.
input range from 0 to V
.
REF
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX1026/MAX1028/MAX1030s’ input architecture. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode (and AIN0, AIN2,
AIN4…AIN14 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5…AIN15 in differential mode). For
external track-and-hold timing, use clock mode 01.
After the T/H enters hold mode, the difference between
the sampled positive and negative input voltages is
converted. The time required for the T/H to acquire an
input signal is determined by how quickly its input
capacitance is charged. If the input signal’s source
impedance is high, the required acquisition time length-
Internal Clock
The MAX1026/MAX1028/MAX1030 operate from an inter-
nal oscillator, which is accurate within 10ꢀ of the
4.4MHz nominal clock rate. The internal oscillator is
active in clock modes 00, 01, and 10. Read out the data
at clock speeds up to 10MHz. See Figures 4–7 for details
on timing specifications and starting a conversion.
ens. The acquisition time, t
, is the maximum time
ACQ
______________________________________________________________________________________ ±±
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
t
= internal reference wake-up; set to zero if the inter-
RP
Applications Information
nal reference is already powered up or if the external
reference is being used
Register Descriptions
The MAX1026/MAX1028/MAX1030 communicate
between the internal registers and the external circuitry
through the SPI/QSPI-compatible serial interface. Table
1 details the registers and the bit names. Tables 2–7
show the various functions within the conversion regis-
ter, setup register, averaging register, reset register,
unipolar register, and bipolar register.
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by writing
to the conversion register. Table 2 details channel
selection, the four scan modes, and how to request a
temperature measurement. Request a scan by writing
to the conversion register when in clock mode 10 or 11,
or by applying a low pulse to the CNVST pin when in
clock mode 00 or 01.
Conversion Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use.
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
A conversion is not performed if it is requested on a
channel that has been configured as CNVST or REF-.
Do not request conversions on channels 8–15 on the
MAX1026 and channels 12–15 on the MAX1028. Set
CHSEL3:CHSEL0 to the lower channel’s binary value. If
the last two channels are configured as a differential
pair and one of them has been reconfigured as CNVST
or REF-, the pair is ignored.
total conversion time = t
where:
x n
x n + t + t
result TS RP
cnv
avg
t
= t
(max) + t
(max)
conv
cnv
acq
n
n
= samples per result (amount of averaging)
avg
= number of FIFO results requested; determined
result
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel and one result per differential pair
within the requested range, plus one temperature result if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the averaging register (Table 6). Select scan
mode 11 to return only one result from a single channel.
by number of channels being scanned or by NSCAN1,
NSCAN0
t
= time required for temperature measurement; set
TS
to zero if temp measurement is not requested
Table ±. Input Data Bcte (MSB Firsty
REGISTER ꢂꢀME
Conversion
BIT 7
BIT 6
BIT 5
CHSEL2
CKSEL1
1
BIT 4
CHSEL1
CKSEL0
AVGON
1
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
BIT 2
SCAN1
REFSEL0
NAVG0
X
BIT ±
SCAN0
DIFFSEL1
NSCAN1
X
BIT 0
TEMP
1
CHSEL3
Setup
0
0
1
0
DIFFSEL0
NSCAN0
X
Averaging
Reset
0
0
0
Unipolar mode (setup)
Bipolar mode (setup)
UCH0/1
BCH0/1
UCH2/3
BCH1/2
UCH4/5
BCH4/5
UCH6/7
BCH6/7
UCH8/9*
BCH8/9*
UCH10/11* UCH12/13** UCH14/15**
BCH10/11* BCH12/13** BCH14/15**
*Unipolar/bipolar channels 8–15 are only valid on the MAX1028 and MAX1030.
**Unipolar/bipolar channels 12–15 are only valid on the MAX1030.
X = Don’t care.
±2 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Setup Register
Table 2. °onversion Register*
Write a byte to the setup register to configure the clock,
reference, and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode, acquisition and sam-
pling, and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reference use.
Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the
unipolar mode and bipolar mode registers and configure
the analog input channels for differential operation.
BIT
ꢂꢀME
BIT
FUꢂ°TIOꢂ
—
7 (MSB) Set to 1 to select conversion register.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
6
5
4
3
2
1
Analog input channel select.
Analog input channel select.
Analog input channel select.
Analog input channel select.
Scan mode select.
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar/bipolar mode address registers. Set bits 1 and
0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipo-
lar mode register. Set bits 1 and 0 to 11 to write to the
bipolar mode register. In both cases, the setup byte
must be followed immediately by 1 byte of data written
to the unipolar register or bipolar register. Hold CS low
and run 16 SCLK cycles before pulling CS high. If the
last 2 bits of the setup register are 00 or 01, neither the
unipolar mode register nor the bipolar mode register is
written. Any subsequent byte is recognized as a new
input data byte. See Tables 4 and 5 to program the
unipolar and bipolar mode registers.
Scan mode select.
Set to 1 to take a single temperature
TEMP 0 (LSB) measurement. The first conversion result
of a scan contains temperature information.
*See below for bit details.
SEꢁE°TED
°HSEꢁ3 °HSEꢁ2 °HSEꢁ± °HSEꢁ0
°HꢀꢂꢂEꢁ (ꢂy
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
If a channel is configured as both unipolar and bipolar,
the unipolar setting takes precedence. In unipolar
AIN3
AIN4
mode, AIN+ can exceed AIN- by up to V
. The out-
REF
AIN5
put format in unipolar mode is binary. In bipolar mode,
AIN6
either input can exceed the other by up to V
output format in bipolar mode is two's complement.
/ 2. The
REF
AIN7
AIN8
Averaging Register
Write to the averaging register to configure the ADC to
average up to 32 samples for each requested result,
and to independently control the number of results
requested for single-channel scans.
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Table 2 details the four scan modes available in the con-
version register. All four scan modes allow averaging as
long as the AVGON bit, bit 4 in the averaging register, is
set to 1. Select scan mode 10 to scan the same channel
multiple times. Clock mode 11 disables averaging.
S°ꢀꢂ MODE (°HꢀꢂꢂEꢁ ꢂ IS
SEꢁE°TED BY BITS °HSEꢁ3–°HSEꢁ0y
Reset Register
Write to the reset register (as shown in Table 7) to clear
the FIFO or to reset all registers to their default states.
Set the RESET bit to 1 to reset the FIFO. Set the reset
bit to zero to return the MAX1026/MAX1028/MAX1030
to the default power-up state.
S°ꢀꢂ± S°ꢀꢂ0
0
0
0
1
Scans channels 0 through N.
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The averaging
register sets the number of results.
1
1
0
1
No scan. Converts channel N once only.
______________________________________________________________________________________ ±3
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Table 3. Setup Register*
BIT ꢂꢀME
—
BIT
FUꢂ°TIOꢂ
7 (MSB) Set to zero to select setup register.
—
6
Set to 1 to select setup register.
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration. Resets to 1 at power-up.
Clock mode and CNVST configuration.
4
3
Reference mode configuration.
2
1
Reference mode configuration.
Unipolar/bipolar mode register configuration for differential mode.
Unipolar/bipolar mode register configuration for differential mode.
0 (LSB)
*See below for bit details.
°KSEꢁ±
°KSEꢁ0
°OꢂVERSIOꢂ °ꢁO°K
Internal
ꢀ°QUISITIOꢂ/SꢀMPꢁIꢂG
Internally timed
CNVST °OꢂFIGURꢀTIOꢂ
CNVST
0
0
1
1
0
1
0
1
Internal
Externally timed through CNVST
Internally timed
CNVST
Internal
AIN15/11/7
AIN15/11/7
External (4.8MHz max)
Externally timed through SCLK
REFSEꢁ± REFSEꢁ0
VOꢁTꢀGE REFEREꢂ°E
Internal
ꢀutoShutdown
REF- °OꢂFIGURꢀTIOꢂ
AIN14/10/6
Reference off after scan; need
wake-up delay.
0
0
1
1
0
1
0
1
External single ended
Internal
Reference off; no wake-up delay.
AIN14/10/6
Reference always on; no wake-up
delay.
AIN14/10/6
External differential
Reference off; no wake-up delay.
REF-
DIFFSEꢁ± DIFFSEꢁ0
FUꢂ°TIOꢂ
0
0
1
1
0
1
0
1
No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
One byte of data follows the setup byte and is written to the unipolar mode register.
One byte of data follows the setup byte and is written to the bipolar mode register.
±4 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
The reference voltage used for the temperature mea-
surements is derived from the internal reference source
to ensure a resolution of 1/8 of a degree.
Power-Up Default State
The MAX1026/MAX1028/MAX1030 power up with all
blocks in shutdown, including the reference. All registers
power up in state 00000000, except for the setup regis-
ter, which powers up in clock mode 10 (CKSEL1 = 1).
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX1026/MAX1028/MAX1030. The 10-bit conversion
result is output in MSB-first format with 4 leading zeros
and 2 trailing sub-bits. The 12-bit temperature mea-
surement is output with 4 leading zeros. DIN data is
latched into the serial interface on the rising edge of
SCLK. Data on DOUT transitions on the falling edge of
SCLK. Conversions in clock modes 00 and 01 are initiat-
ed by CNVST. Conversions in clock modes 10 and 11
are initiated by writing an input data byte to the conver-
sion register. Data is binary for unipolar mode and two’s
complement for bipolar mode.
Temperature Measurements
The MAX1026/MAX1028/MAX1030 perform tempera-
ture measurements with an internal diode-connected
transistor. The diode bias current changes from 68µA
to 4µA to produce a temperature-dependent bias volt-
age difference. The second conversion result at 4µA is
subtracted from the first at 68µA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the above digital
code minus an offset to adjust from Kelvin to Celsius.
Table 4. Unipolar Mode Register (ꢀddressed Through Setup Registery
BIT ꢂꢀME
UCH0/1
BIT
FUꢂ°TIOꢂ
7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion.
UCH2/3
6
Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion.
UCH4/5
5
Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion.
UCH6/7
4
Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion.
UCH8/9
3
Set to 1 to configure AIN8 and AIN9 for unipolar differential conversion (MAX1028/MAX1030 only).
Set to 1 to configure AIN10 and AIN11 for unipolar differential conversion (MAX1028/MAX1030 only).
Set to 1 to configure AIN12 and AIN13 for unipolar differential conversion (MAX1030 only).
Set to 1 to configure AIN14 and AIN15 for unipolar differential conversion (MAX1030 only).
UCH10/11
UCH12/13
UCH14/15
2
1
0 (LSB)
Table 5. Bipolar Mode Register (ꢀddressed Through Setup Registery
BIT ꢂꢀME
BCH0/1
BIT
FUꢂ°TIOꢂ
7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion.
BCH2/3
6
Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion.
BCH4/5
5
Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion.
BCH6/7
4
Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion.
BCH8/9
3
Set to 1 to configure AIN8 and AIN9 for bipolar differential conversion (MAX1028/MAX1030 only).
Set to 1 to configure AIN10 and AIN11 for bipolar differential conversion (MAX1028/MAX1030 only).
Set to 1 to configure AIN12 and AIN13 for bipolar differential conversion (MAX1030 only).
Set to 1 to configure AIN14 and AIN15 for bipolar differential conversion (MAX1030 only).
BCH10/11
BCH12/13
BCH14/15
2
1
0 (LSB)
______________________________________________________________________________________ ±5
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Table 6. ꢀveraging Register*
BIT ꢂꢀME
—
BIT
FUꢂ°TIOꢂ
7 (MSB) Set to zero to select averaging register.
—
6
Set to zero to select averaging register.
Set to 1 to select averaging register.
—
5
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to 1 to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
3
2
1
Single-channel scan count. (Scan mode 10 only.)
Single-channel scan count. (Scan mode 10 only.)
0 (LSB)
*See below for bit details.
ꢀVGOꢂ
ꢂꢀVG±
ꢂꢀVG0
FUꢂ°TIOꢂ
Performs 1 conversion for each requested result.
0
1
1
1
1
x
0
0
1
1
x
0
1
0
1
Performs 4 conversions and returns the average for each requested result.
Performs 8 conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
ꢂS°ꢀꢂ±
ꢂS°ꢀꢂ0
FUꢂ°TIOꢂ (ꢀPPꢁIES OꢂꢁY IF S°ꢀꢂ MODE ±0 IS SEꢁE°TEDy
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
Table 7. Reset Register
BIT ꢂꢀME
BIT
FUꢂ°TIOꢂ
—
7 (MSB) Set to zero to select reset register.
—
6
Set to zero to select reset register.
Set to zero to select reset register.
Set to 1 to select reset register.
—
5
—
4
RESET
3
Set to zero to reset all registers. Set to 1 to clear the FIFO only.
Reserved. Don’t care.
x
x
x
2
1
Reserved. Don’t care.
0 (LSB)
Reserved. Don’t care.
±6 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
the internal oscillator. See Figure 5 for clock mode 01
timing.
Internally Timed Acquisitions and
Conversions Using CNVST
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If the internal
reference needs to wake up, an additional 65µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement are internally
timed. In this case, hold CNVST low for at least 40ns.
Performing Conversions in Clock Mode 00
In clock mode 00, the wake up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1026/MAX1028/
MAX1030 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature measurement result, if requested, pre-
cedes all other FIFO results.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. If a temperature measure-
ment is programmed, it is performed after the first rising
edge of CNVST following the input data byte written to
the conversion register. The result is available on DOUT
once EOC has been pulled low.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
LSB1
MSB2
MSB1
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. X = DON'T CARE.
Figure 4. Clock Mode 00
______________________________________________________________________________________ ±7
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
CNVST
(CONVERSION2)
(ACQUISITION1)
(ACQUISITION2)
CS
(CONVERSION1)
SCLK
DOUT
EOC
LSB1
MSB1
MSB2
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. X = DON'T CARE.
Figure 5. Clock Mode 01
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DIN
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. X = DON'T CARE.
Figure 6. Clock Mode 10
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX1026/MAX1028/MAX1030 then power up,
scan all requested channels, store the results in the
FIFO, and shut down. After the scan is complete, EOC
is pulled low and the results are available in the FIFO. If
a temperature measurement is requested, the tempera-
ture result precedes all other FIFO results. EOC stays
low until CS is pulled low again.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
±8 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
(CONVERSION BYTE)
DIN
(ACQUISITION2)
(ACQUISITION1)
(CONVERSION1)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. X = DON'T CARE.
Figure 7. Clock Mode 11
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
Output coding is binary, with 1 LSB = V
/ 1024V for
REF
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is
being requested, wait 65µs with CS high after writing the
conversion byte to extend the acquisition and allow the
internal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. For the TQFN package, connect its
exposed pad to GND. Board layout should ensure that
digital and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
neath the MAX1026/MAX1028/MAX1030 package. High-
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
frequency noise in the V
power supply can affect
DD
performance. Bypass the V
supply with a 0.1µF
DD
capacitor to GND, close to the V
pin. Minimize
DD
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
______________________________________________________________________________________ ±9
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
OUTPUT CODE
OUTPUT CODE
V
REF
2
FS
+ V
COM
=
FULL-SCALE
TRANSITION
011 . . . 111
011 . . . 110
11 . . . 111
11 . . . 110
ZS = COM
-V
2
REF
-FS =
11 . . . 101
000 . . . 010
000 . . . 001
000 . . . 000
V
1024
REF
1 LSB =
FS = V + V
REF
COM
111 . . . 111
111 . . . 110
111 . . . 101
ZS = V
COM
V
REF
1 LSB =
1024
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
COM*
0
- FS
+FS - 1 LSB
1
2
3
FS
(COM)
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
*V
≥ V / 2
REF
COM
Figure 8. Unipolar Transfer Function, Full Scale (FSꢀ = ꢁ
Figure 9. Bipolar Transfer Function, Full Scale ( FSꢀ =
ꢁ
REF
/ 2
REF
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1026/MAX1028/MAX1030 is measured using
the end-point method.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
SINAD (dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
the time between the samples.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
ENOB = (SINAD - 1.76) / 6.02
20 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Total Harmonic Distortion
Ordering Information (continued)
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
TEMP
PIꢂ-
PKG
PꢀRT
RꢀꢂGE
Pꢀ°KꢀGE
°ODE
MꢀX±026BCEE-T
MAX1026BEEE-T
MꢀX±028ACEP-T
MAX1028AEEP-T
MAX1028BCEP-T
MAX1028BEEP-T
MꢀX±030ACEG-T
0°C to +70°C
16 QSOP
E16-1
E16-1
E20-1
E20-1
E20-1
E20-1
E24-1
E24-1
E24-1
E24-1
⎛
⎞
⎠
2
2
2
2
-40°C to +85°C 16 QSOP
0°C to +70°C 20 QSOP
-40°C to +85°C 20 QSOP
0°C to +70°C 20 QSOP
-40°C to +85°C 20 QSOP
0°C to +70°C 24 QSOP
THD = 20 x log
V
+ V3 + V4 + V5 / V
⎜
⎝
⎟
(
)
2
1
where V1 is the fundamental amplitude, and V2–V5 are
the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
MAX1030AEEG-T -40°C to +85°C 24 QSOP
MAX1030BCEG-T 0°C to +70°C 24 QSOP
MAX1030BEEG-T -40°C to +85°C 24 QSOP
MAX1030BCTI-T
MAX1030BETI-T
0°C to +70°C
28 TQFN-EP* T2855-6
-40°C to +85°C 28 TQFN-EP* T2855-6
*EP = Exposed paddle (connect to GNDꢀ.
Chip Information
TRANSISTOR COUNT: 30,889
PROCESS: BiCMOS
Pin Configurations (continued)
TOP VIEW
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
24 EOC
23 DOUT
22 DIN
21 CS
21 20 19 18 17 16 15
14
13
DIN 22
DOUT 23
CNVST/AIN15
REF-/AIN14
MAX1030
20 SCLK
12 AIN13
24
25
26
27
28
EOC
N.C.
AIN0
AIN1
AIN2
19
V
DD
AIN12
AIN11
AIN10
AIN9
11
10
9
MAX1030
18 GND
17 REF+
16 CNVST/AIN15
15 REF-/AIN14
14 AIN13
8
AIN9 10
AIN10 11
AIN11 12
1
2
3
4
5
6
7
13 AIN12
TQFꢂ
QSOP
______________________________________________________________________________________ 2±
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-iA.Aom/paAkages.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
E
1
22 ______________________________________________________________________________________
10-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-iA.Aom/paAkages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
AAAAA
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
I
21-0140
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
L
DOWN
BONDS
ALLOWED
YES
NO
exceptions
PKG.
CODES
±0.15
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
T1655-2
T1655-3
**
**
**
**
A1
0
0
0
0
0
A3
b
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-3
T2055-4
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
D
E
NO
**
YES
T2055-5
T2855-3
T2855-4
T2855-5
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
YES
YES
NO
**
**
**
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
YES
YES
T2855-6
T2855-7
**
**
N
ND
NE
16
4
4
20
5
28
7
32
8
8
40
10
10
5
7
T2855-8
3.15 3.25 3.35 3.15 3.25 3.35 0.40
JEDEC
WHHB
WHHC
WHHD-1
WHHD-2
-----
T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35
NO
YES
NO
YES
NO
**
**
**
**
**
**
T3255-3
T3255-4
T3255-5
3.00 3.10 3.20 3.00 3.10 .20
3.00 3.10 3.20 3.00 3.10 .20
3.00 3.10 3.20 3.00 3.10 3.20
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
I
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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