MAX1034_技术文档

19-3574; Rev 0; 5/05

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

General Description

Features

♦ Software-Programmable Input Range for Each

The MAX1034/MAX1035 multirange, low-power, 14-bit,

successive-approximation, analog-to-digital converters

(ADCs) operate from a single +5V supply and achieve

throughput rates up to 115ksps. A separate digital sup-

ply allows digital interfacing with 2.7V to 5.25V systems

using the SPI™-/QSPI™-/MICROWIRE™-compatible

serial interface. Partial power-down mode reduces the

supply current to 1.3mA (typ). Full power-down mode

reduces the power-supply current to 1µA (typ).

Channel

♦ Single-Ended Input Ranges

0 to +V

/2, -V

/2 to 0, 0 to +V

, -V

to

REF

0, ±V

/4, ±V

/2, and ±V

REF

♦ Differential Input Ranges

±V /2, ±V , and ±2 ꢀ V

REF

♦ Eight Single-Ended or Four Differential Analog

The MAX1034 provides eight (single-ended) or four (true

differential) analog input channels. The MAX1035 pro-

vides four (single-ended) or two (true differential) analog

input channels. Each analog input channel is indepen-

dently software programmable for seven single-ended

Inputs (MAX1034)

♦ Four Single-Ended or Two Differential Analog

Inputs (MAX1035)

♦ ±±V ꢁOerOoltage Tolerant Inputs

♦ Internal or Eꢀternal Reference

♦ 115ksps Maꢀimum Sample Rate

♦ Single +5V Power Supply

input ranges (0 to +V

/2, -V

/2 to 0, 0 to +V

,

REF

V

REF

/2, and

REF

-V

to 0,

V

/4,

V

), and three

REF

differential input ranges ( V

/2, V

, 2 x V ).

REF REF

REF

An on-chip +4.096V reference offers a small convenient

ADC solution. The MAX1034/MAX1035 also accept an

external reference voltage between 3.800V and 4.136V.

♦ 20-/24-Pin TSSꢁP Package

The MAX1034 is available in a 24-pin TSSOP package

and the MAX1035 is available in a 20-pin TSSOP pack-

age. Each device is specified for operation from -40°C

to +85°C.

Ordering Information

PIN-

PART

TEMP RANGE

CHANNELS

PACKAGE

Applications

MAX1034EUG*

MAX1035EUP

-40°C to +85°C 24 TSSOP

-40°C to +85°C 20 TSSOP

8

4

Industrial Control Systems

Data-Acquisition Systems

Avionics

*Future product—contact factory for availability.

Pin Configurations

Robotics

TOP VIEW

AV

1

2

3

4

5

6

7

8

9

24 AGND1

23 AGND2

DD1

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

22 AV

DD2

21 AGND3

20 REF

MAX1034

19 REFCAP

18 DV

17 DV

DD

DDO

16 DGND

15 DGNDO

14 DOUT

13 SCLK

CS 10

DIN 11

SSTRB 12

SPI and QSPI are a trademarks of Motorola, Inc.

MICROWIRE is a trademark of National Semiconductor Corp.

TSSꢁP

Pin Configurations continued at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

ABSꢁLUTE MAXIMUM RATINGS

AV

DV

DV , DV

AV

DD1

to AGND1 ....................................................-0.3V to +6V

to AGND2 ....................................................-0.3V to +6V

CH0–CH7 to AGND1...................................................-6V to +6V

REF, REFCAP to AGND1.......................-0.3V to (AV + 0.3V)

DD1

DD2

DD1

Continuous Current (any pin) ........................................... 50mA

to DGND........................................................-0.3V to +6V

to DGNDO ..................................................-0.3V to +6V

DD

DDO

to DV

Continuous Power Dissipation (T = +70°C)

A

......................................................-0.3V to +6V

20-Pin TSSOP (derate 11mW/°C above +70°C) ..........879mW

24-Pin TSSOP (derate 12.2mW/°C above +70°C) .......976mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature .....................................................+150°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

DD

DDO

to AV

........................................-0.3V to +6V

DD DDO

DD1

, DV , DV

DD DDO

to AV

..........................-0.3V to +6V

DD2

DGND, DGNDO, AGND3, AGND2 to AGND1 ......-0.3V to +0.3V

CS, SCLK, DIN, DOUT, SSTRB to

DGNDO............................................-0.3V to (DV

+ 0.3V)

DDO

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= AV

= DV = DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle), external

CLK

DD1

DD2

DD

DDO

clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range ( V ), C

DD1 REF DOUT

REF

= 50pF, C

= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)

SSTRB

A

PARAMETER

SYMBꢁL

CꢁNDITIꢁNS

MIN

TYP

MAX

UNITS

DC ACCURACY (Notes 1, 2)

Resolution

14

Bits

LSB

Integral Nonlinearity

Differential Nonlinearity

INL

0.25

1

DNL

No missing codes

External or internal reference

0.5

2

Transition Noise

LSB

RMS

Unipolar

0

10

20

Single-ended inputs

Bipolar

Unipolar

Bipolar

-1.0

0

Offset Error

mV

Differential inputs

(Note 3)

-2

Channel-to-Channel Gain

Matching

Unipolar or bipolar

0.025

1.0

%FSR

mV

Channel-to-Channel Offset Error

Matching

Unipolar

Bipolar

Unipolar

Bipolar

Unipolar

Bipolar

10

5

Offset Temperature Coefficient

Gain Error

ppm/°C

%FSR

ppm/°C

LSB

0.5

0.3

1.5

1.0

Gain Temperature Coefficient

Unipolar Endpoint Overlap

Negative unipolar full scale to positive

unipolar zero-scale

0

5

2

_______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= AV

= DV = DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle), external

CLK

DD1

DD2

DD

DDO

clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range ( V ), C

DD1 REF DOUT

REF

= 50pF, C

= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)

SSTRB

A

PARAMETER

SYMBꢁL

CꢁNDITIꢁNS MIN

= 5kHz, V = FSR - 0.05dB, f = 130ksps (Notes 1, 2)

SAMPLE

TYP

MAX

UNITS

DYNAMIC SPECIFICATIꢁNS f

IN(SINE-WAVE)

IN

Differential inputs, FSR = 2 x V

84.5

REF

Single-ended inputs, FSR = V

84

Signal-to-Noise Plus Distortion

SINAD

SNR

dB

/ 2

82.5

80.5

84.5

84

REF

/ 4

79

Differential inputs, FSR = 2 x V

REF

Single-ended inputs, FSR = V

REF

Signal-to-Noise Ratio

dB

/ 2

/ 4

82.5

80.5

Total Harmonic Distortion

(Up to the 5th Harmonic)

THD

-98

Spurious-Free Dynamic Range

Aperture Delay

SFDR

92

99

15

dB

ns

t

Figure 21

AD

Aperture Jitter

t

100

105

ps

dB

AJ

Channel-to-Channel Isolation

CꢁNVERSIꢁN RATE

External clock mode, Figure 2

114

84

Byte-Wide Throughput Rate

f

External acquisition mode, Figure 3

Internal clock mode, Figure 4

ksps

SAMPLE

106

ANALꢁG INPUTS (CH0–CH3 MAX1035, CH0–CH7 MAX1034, AGND1)

Small-Signal Bandwidth

Full-Power Bandwidth

All input ranges, V = 100mV

(Note 2)

2

MHz

kHz

IN

P-P

All input ranges, V = 4V

IN

(Note 2)

700

P-P

R[2:1] = 001

R[2:1] = 010

R[2:1] = 011

R[2:1] = 100

R[2:1] = 101

R[2:1] = 110

R[2:1] = 111

-V

/4

/2

+V

/4

REF

0

REF

0

+V

/2

REF

Input Voltage Range (Table 6)

V

-V

REF

/2

CH_

REF

0

-V

REF

0

+V

REF

-V

+V

REF

True-Differential Analog

Common-Mode Voltage Range

V

DIF/SGL = 1

-4.75

+5.50

V

CMDR

Common-Mode Rejection Ratio

Input Current

CMRR

DIF/SGL = 1, input voltage range =

-V < V < +V

V

REF

/4

75

dB

µA

pF

kΩ

I

-1500

+650

CH_

REF

CH_

REF

Input Capacitance

Input Resistance

C

5

6

CH_

R

_______________________________________________________________________________________

3

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= AV

= DV = DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle), external

CLK

DD1

DD2

DD

DDO

clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range ( V ), C

DD1 REF DOUT

REF

= 50pF, C

= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)

SSTRB

A

PARAMETER

SYMBꢁL

CꢁNDITIꢁNS

MIN

TYP

MAX

UNITS

INTERNAL REFERENCE (Bypass REFCAP with 0.1µF to AGND1 and REF with 1.0µF to AGND1)

Reference Output Voltage

V

4.056

4.096

30

4.136

V

REF

Reference Temperature

Coefficient

TC

ppm/°C

REF

REF shorted to AGND1

REF shorted to AV

10

-1

Reference Short-Circuit Current

Reference Load Regulation

I

mA

mV

REFSC

DD

I

= 0 to 0.5mA

0.1

10

REF

EXTERNAL REFERENCE (REFCAP = AV

)

DD

Reference Input Voltage Range

V

3.800

AV

- 0.4

4.136

V

REF

REFCAP Buffer Disable

Threshold

AV

DD1

- 0.1

DD1

V

(Note 4)

= +4.096V, external clock mode,

RCTH

V

REF

external acquisition mode, internal clock

mode, or partial power-down mode

90

0.1

45

40

200

10

Reference Input Current

I

µA

REF

V

= +4.096V, full power-down mode

REF

External clock mode, external acquisition

mode, internal clock mode, or partial

power-down mode

20

Reference Input Resistance

R

kΩ

REF

Full power-down mode

DIGITAL INPUTS (DIN, SCLK, CS)

0.7 x

Input High Voltage

V

IH

DV

DDO

0.3 x

Input Low Voltage

V

IL

DV

DDO

Input Hysteresis

V

0.2

10

V

HYST

Input Leakage Current

Input Capacitance

I

IN

V

= 0 to DV

DDO

-10

+10

µA

pF

IN

C

IN

DIGITAL ꢁUTPUTS (DꢁUT, SSTRB)

DV

= 4.75V, I

= 10mA

0.4

DDO

SINK

Output Low Voltage

V

OL

= 2.7V, I

= 5mA

SINK

DV

- 0.4

DDO

Output High Voltage

V

I

= 0.5mA

V

OH

SOURCE

DOUT Tri-State Leakage Current

I

CS = DV

-10

+10

µA

DDO

PꢁWER REQUIREMENTS (AV

Analog Supply Voltage

and AGND1, AV

and AGND2, DV

and DGND, DV

and DGNDꢁ)

DDꢁ

DD1

DD2

DD

AV

4.75

5.25

V

DD1

Digital Supply Voltage

DV

DD

4

_______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= AV

= DV = DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle), external

CLK

DD1

DD2

DD

DDO

clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range ( V ), C

DD1 REF DOUT

REF

= 50pF, C

= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)

SSTRB

A

PARAMETER

SYMBꢁL

CꢁNDITIꢁNS

MIN

4.75

2.70

TYP

MAX

5.25

UNITS

Preamplifier Supply Voltage

Digital I/O Supply Voltage

AV

DV

V

DD2

DDO

External clock mode,

external acquisition

mode, or internal

clock mode

Internal reference

External reference

3

3.5

3

AV

Supply Current

I

mA

DD1

AVDD1

2.5

0.9

17.5

0.2

External clock mode, external acquisition

mode, or internal clock mode

DV

AV

DV

Supply Current

I

2

mA

DD

DVDD

External clock mode, external acquisition

mode, or internal clock mode

Supply Current

I

25

1

DD2

DDO

AVDD2

External clock mode, external acquisition

mode, or internal clock mode

I

DVDDO

PSRR

Partial power-down mode

Full power-down mode

All analog input ranges

1.3

1

mA

µA

Total Supply Current

Power-Supply Rejection Ratio

0.125

LSB

TIMING CHARACTERISTICS (Figures 15 and 1±)

External clock mode

External acquisition mode

Internal clock mode

272

228

100

109

92

62

83

SCLK Period

t

µs

ns

CP

External clock mode

External acquisition mode

Internal clock mode

SCLK High Pulse Width (Note 5)

SCLK Low Pulse Width (Note 5)

t

CH

40

External clock mode

External acquisition mode

Internal clock mode

109

92

t

CL

40

DIN to SCLK Setup

40

ns

DS

DH

DO

DIN to SCLK Hold

t

0

SCLK Fall to DOUT Valid

CS Fall to DOUT Enable

CS Rise to DOUT Disable

CS Fall to SCLK Rise Setup

CS High Minimum Pulse Width

SCLK Fall to CS Rise Hold

SSTRB Rise to CS Fall Setup

DOUT Rise/Fall Time

t

40

t

DV

t

TR

t

40

0

CSS

t

CSPW

t

CSH

40

C = 50pF

L

10

SSTRB Rise/Fall Time

C = 50pF

L

_______________________________________________________________________________________

5

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

ELECTRICAL CHARACTERISTICS (continued)

(AV

= AV

= DV = DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle), external

CLK

DD1

DD2

DD

DDO

clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range ( V ), C

DD1 REF DOUT

REF

= 50pF, C

= 50pF, T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)

SSTRB

A

Note 1: Parameter tested at AV

= AV

= DV

= 5V.

DDO

DD1

DD2

DD

Note 2: See definitions in the Parameter Definitions section at the end of the data sheet.

Note 3: Guaranteed by correlation with single-ended measurements.

Note 4: To ensure external reference operation, V

must exceed (AV - 0.1V). To ensure internal reference operation, V

DD1 REFCAP

REFCAP

must be below (AV

- 0.4V). Bypassing REFCAP with a 0.1µF or larger capacitor to AGND1 sets V ≈ 4.096V. The tran-

DD1

REFCAP

sition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold

minimum and maximum values (Figures 17 and 18).

Note 5: The SCLK duty cycle can vary between 40% and 60%, as long as the t and t

timing requirements are met.

CL

CH

Typical Operating Characteristics

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

ANALOG SUPPLY CURRENT

vs. ANALOG SUPPLY VOLTAGE

PREAMPLIFIER SUPPLY CURRENT

vs. PREAMPLIFIER SUPPLY VOLTAGE

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

2.60

2.55

2.50

2.45

2.40

2.35

2.30

24

23

22

21

20

19

18

17

16

15

0.90

EXTERNAL CLOCK MODE

0.85

T

= +85°C

A

T

= +85°C

A

T

A

= +85°C

0.80

0.75

0.70

0.65

T = +25°C

A

T

= +25°C

= -40°C

T

= +25°C

= -40°C

T

A

= -40°C

T

A

T

A

4.75

4.85

4.95

AV

5.05

(V)

5.15

5.25

4.75

4.85

4.95

AV

5.05

(V)

5.15

5.25

4.75

4.85

4.95

5.05

5.15

5.25

DV (V)

DD

DD1

DD2

±

_______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Typical Operating Characteristics (continued)

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

DIGITAL I/O SUPPLY CURRENT

ANALOG SUPPLY CURRENT

vs. DIGITAL I/O SUPPLY VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

0.12

0.10

0.55

0.53

0.51

0.49

0.47

0.45

EXTERNAL CLOCK MODE

PARTIAL POWER-DOWN MODE

T

= +85°C

= +25°C

A

T

= +85°C

A

T

A

= +25°C

T

A

T

A

= -40°C

T

A

= -40°C

4.75

4.85

4.95

DV

5.05

(V)

5.15

5.25

4.75

4.85

4.95

5.05

(V)

5.15

5.25

AV

DDO

DD1

PREAMPLIFIER SUPPLY CURRENT

vs. PREAMPLIFIER SUPPLY VOLTAGE

DIGITAL SUPPLY CURRENT

vs. DIGITAL SUPPLY VOLTAGE

0.20

0.18

0.16

0.14

0.12

0.10

0.136

0.134

0.132

0.130

0.128

0.126

0.124

0.122

0.120

PARTIAL POWER-DOWN MODE

= +85°C

T

A

= +85°C

T

A

T

A

= +25°C

T

A

= -40°C

T

A

= -40°C

T

= +25°C

A

4.75

4.85

4.95

AV

5.05

(V)

5.15

5.25

4.75

4.85

4.95

5.05

5.15

5.25

DV (V)

DD2

DD

_______________________________________________________________________________________

7

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Typical Operating Characteristics (continued)

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

PREAMPLIFIER SUPPLY CURRENT

vs. CONVERSION RATE

ANALOG SUPPLY CURRENT

vs. CONVERSION RATE

25

20

15

10

5

3.0

f

= 7.5MHz (NOTE 6)

CLK

EXTERNAL CLOCK MODE

2.5

2.0

1.5

1.0

0.5

0

EXTERNAL CLOCK MODE

FULL POWER-DOWN MODE,

PARTIAL POWER-DOWN MODE

PARTIAL

POWER-DOWN MODE

FULL

POWER-DOWN MODE

0

50

100

150

200

0

50

100

150

200

CONVERSION RATE (ksps)

DIGITAL SUPPLY CURRENT

vs. CONVERSION RATE

DIGITAL I/O SUPPLY CURRENT

vs. CONVERSION RATE

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0.6

0.5

0.4

0.3

0.2

0.1

0

f

= 7.5MHz (NOTE 6)

f

= 7.5MHz (NOTE 6)

CLK

EXTERNAL CLOCK MODE

EXTERNAL CLOCK MODE,

PARTIAL POWER-DOWN MODE

FULL POWER-DOWN MODE

FULL POWER-DOWN MODE,

PARTIAL POWER-DOWN MODE

0

50

100

150

200

0

50

100

150

200

CONVERSION RATE (ksps)

Note ±: For partial power-down and full power-down modes, external clock mode was used for a burst of continuous samples.

Partial power-down or full power-down modes were entered thereafter. By using this method, the conversion rate was found

by averaging the number of conversions over the time starting from the first conversion to the end of the partial power-down

or full power-down modes.

8

_______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Typical Operating Characteristics (continued)

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

EXTERNAL REFERENCE INPUT CURRENT

vs. EXTERNAL REFERENCE INPUT VOLTAGE

GAIN DRIFT

vs. TEMPERATURE

OFFSET DRIFT

vs. TEMPERATURE

0.10

0.08

0.06

0.04

0.02

0

1.0

0.16

ALL MODES

0.8

0.6

V

REF

BIPOLAR RANGE

+V /4 BIPOLAR RANGE

REF

0.15

0.4

0.2

0

+V /2 BIPOLAR

REF

0.14

0.13

0.12

-0.02

-0.04

-0.06

-0.08

-0.10

-0.2

-0.4

V

REF

/4 BIPOLAR

V

REF

BIPOLAR

-0.6

-0.8

-1.0

3.80 3.85 3.90 3.95 4.00 4.05 4.10 4.15

EXTERNAL REFERENCE VOLTAGE (V)

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

CHANNEL-TO-CHANNEL ISOLATION

vs. INPUT FREQUENCY

COMMON-MODE REJECTION RATIO

vs. FREQUENCY

1.0

0.5

0

-20

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

f

= 115ksps

BIPOLAR RANGE

f

= 115ksps

BIPOLAR RANGE

SAMPLE

f

= 115ksps

BIPOLAR RANGE

SAMPLE

V

REF

V

REF

V

REF

CH0 TO CH2

-40

-60

-80

-0.5

-1.0

-100

-120

0

4096

8192

12,288

16,383

1

10

100

1000

10,000

1

10

100

FREQUENCY (kHz)

1000

10,000

DIGITAL OUTPUT CODE

FREQUENCY (kHz)

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

FFT AT 5kHz

1.0

0.5

0

-20

f

= 115ksps

= 5kHz

BIPOLAR RANGE

f

= 115ksps

BIPOLAR RANGE

SAMPLE

f

V

REF

IN(SINE WAVE)

V

REF

-40

-60

-80

-100

-120

-0.5

-1.0

-140

0

4096

8192

12,288

16,383

10

20

30

40

50

DIGITAL OUTPUT CODE

FREQUENCY (kHz)

_______________________________________________________________________________________

9

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Typical Operating Characteristics (continued)

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

SNR, SINAD, ENOB

vs. ANALOG INPUT FREQUENCY

SNR, SINAD, ENOB vs. SAMPLE RATE

MAX1034/35 toc20

MAX1034/35 toc21

16

15

14

13

12

11

10

9

100

90

80

70

60

50

40

30

20

10

0

14

13

12

11

10

9

100

80

60

40

20

0

ENOB

SNR, SINAD

SNR

SINAD

ENOB

8

f

= 115ksps

BIPOLAR RANGE

f

= 5kHz

SAMPLE

IN(SINE WAVE)

7

V

REF

V

REF

BIPOLAR RANGE

6

1

10

100

1000

0.1

1

10

SAMPLE RATE (ksps)

100

1000

FREQUENCY (kHz)

-SFDR, THD vs. ANALOG INPUT

FREQUENCY

-SFDR, THD vs. SAMPLE RATE

0

-20

0

f

= 115ksps

f

= 5kHz

SAMPLE

IN(SINE WAVE)

V

BIPOLAR RANGE

V

BIPOLAR RANGE

REF

-20

-40

-60

-80

THD

-100

-120

-100

-120

-SFDR

1

10

100

1000

0.1

1

10

SAMPLE RATE (ksps)

100

1000

FREQUENCY (kHz)

ANALOG INPUT CURRENT

vs. ANALOG INPUT VOLTAGE

1.5

1.0

0.5

0

ALL MODES

-0.5

-1.0

-1.5

-6

-4

-2

0

2

4

6

ANALOG INPUT VOLTAGE (V)

10 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Typical Operating Characteristics (continued)

(AV

= AV

= DV

= 5V, AGND1 = DGND = DGNDO = AGND2 = AGND3 = 0, f

= 3.5MHz (50% duty cycle),

DD1

DD2

DD

DDO

CLK

external clock mode, V

= 4.096V (external reference operation), REFCAP = AV

, maximum single-ended bipolar input range

REF

DD1

( V

), C

= 50pF, C

= 50pF, unless otherwise noted.)

REF

DOUT

SSTRB

REFERENCE VOLTAGE vs. TIME

FULL-POWER BANDWIDTH

SMALL-SIGNAL BANDWIDTH

MAX1034/35 toc27

0

-10

-20

-30

-40

-50

-60

0

-5

-10

-15

-20

-25

-30

1V/div

0V

1

10

100

1000

10,000

1

10

100

1000

10,000

4ms/div

FREQUENCY (kHz)

NOISE HISTOGRAM

(CODE EDGE)

NOISE HISTOGRAM

(CODE CENTER)

40,000

70,000

60,000

65,534 SAMPLES

35,000

30,000

25,000

20,000

15,000

10,000

5000

50,000

40,000

30,000

20,000

10,000

0

8190 8191 8192 8193 8194 8195

CODE

8190

8191

8192

8193

8194

CODE

______________________________________________________________________________________ 11

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Pin Description

NAME

FUNCTIꢁN

MAX1034 MAX1035

Analog Supply Voltage 1. Connect AV

to a +4.75V to +5.25V power-supply voltage.

DD1

1

2

AV

DD1

Bypass AV

to AGND1 with a 0.1µF capacitor.

DD1

2

3

4

5

6

7

8

9

3

4

CH0

Analog Input Channel 0

Analog Input Channel 1

Analog Input Channel 2

Analog Input Channel 3

Analog Input Channel 4

Analog Input Channel 5

Analog Input Channel 6

Analog Input Channel 7

CH1

CH2

CH3

CH4

CH5

CH6

CH7

5

6

—

Active-Low Chip-Select Input. When CS is low, data is clocked into the device from DIN on

the rising edge of SCLK. With CS low, data is clocked out of DOUT on the falling edge of

SCLK. When CS is high, activity on SCLK and DIN is ignored and DOUT is high impedance.

10

11

7

8

CS

Serial Data Input. When CS is low, data is clocked in on the rising edge of SCLK. When CS is

high, transitions on DIN are ignored.

DIN

Serial-Strobe Output. When using the internal clock, SSTRB rising edge transitions indicate

that data is ready to be read from the device. When operating in external clock mode, SSTRB

is always low. SSTRB does not tri-state, regardless of the state of CS, and therefore requires

a dedicated I/O line.

12

9

SSTRB

Serial Clock Input. When CS is low, transitions on SCLK clock data into DIN and out of DOUT.

When CS is high, transitions on SCLK are ignored.

13

14

10

11

SCLK

DOUT

Serial Data Output. When CS is low, data is clocked out of DOUT with each falling SCLK

transition. When CS is high, DOUT is high impedance.

15

16

12

13

DGNDO

DGND

Digital I/O Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

Digital Ground. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

Digital I/O Supply Voltage Input. Connect DV

to a +2.7V to +5.25V power-supply voltage.

DDO

17

18

14

15

DV

DDO

Bypass DV

to DGNDO with a 0.1µF capacitor.

DDO

Digital-Supply Voltage Input. Connect DV

to a +4.75V to +5.25V power-supply voltage.

DD

DV

DD

Bypass DV

to DGND with a 0.1µF capacitor.

DD

Bandgap-Voltage Bypass Node. For external reference operation, connect REFCAP to AV

For internal reference operation, bypass REFCAP with a 0.01µF capacitor to AGND1

.

DD

19

20

16

17

REFCAP

REF

(V

REFCAP

≈ 4.096V).

Reference-Buffer Output/ADC Reference Input. For external reference operation, apply an

external reference voltage from 3.800V to 4.136V to REF. For internal reference operation,

bypassing REF with a 1µF capacitor to AGND1 sets V

= 4.096V 1%.

REF

12 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Pin Description (continued)

NAME

FUNCTIꢁN

MAX1034 MAX1035

Analog Signal Ground 3. AGND3 is the ADC negative reference potential. Connect AGND3 to

AGND1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

21

22

18

19

AGND3

Analog Supply Voltage 2. Connect AV

to a +4.75V to +5.25V power-supply voltage.

DD2

AV

DD2

Bypass AV

to AGND2 with a 0.1µF capacitor.

DD2

Analog Ground 2. This ground carries approximately five times more current than AGND1.

DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

23

24

20

1

AGND2

AGND1

Analog Ground 1. DGND, DGNDO, AGND3, AGND2, and AGND1 must be connected together.

5.0V

0.1µF

AV

DD2

AV

DD1

DV

DD

3.3V

CHO

CH1

CH2

CH3

CH4

CH5

CH6

CH7

REF

DV

V

DD

4–20mA

PLC

DDO

0.1µF

MC68HCXX

ACCELERATION

PRESSURE

µC

SCLK

CS

SCK

I/O

TEMPERATURE

WHEATESTONE

MAX1034

DIN

MOSI

I/O

SSTRB

DOUT

AGND1

REFCAP

AGND2

MISO

1µF

V

SS

AGND3 DGND DGNDO

0.1µF

Figure 1. Typical Application Circuit

single-ended conversions, the valid analog input voltage

range spans from -V below ground to +V above

Detailed Description

REF

The MAX1034/MAX1035 multirange, low-power, 14-bit

successive-approximation ADCs operate from a single

+5V supply and have a separate digital supply allowing

digital interface with 2.7V to 5.25V systems. These 14-bit

ADCs have internal track-and-hold (T/H) circuitry that

supports single-ended and fully differential inputs. For

ground. The maximum allowable differential input volt-

age spans from -2 x V to +2 x V . Data can be

REF

converted in a variety of software-programmable chan-

nel and data-acquisition configurations. Microprocessor

(µP) control is made easy through an SPI-/QSPI-/

MICROWIRE-compatible serial interface.

______________________________________________________________________________________ 13

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

The MAX1034 has eight single-ended analog input

channels or four differential channels (see the Block

Diagram at the end of the data sheet). The MAX1035

has four single-ended analog input channels or two dif-

ferential channels. Each analog input channel is inde-

pendently software programmable for seven

AGND3, DGND, and DGNDO together as close to the

device as possible. Bypass each supply to the corre-

sponding ground using a 0.1µF capacitor (Table 1). If

significant low-frequency noise is present, add a 10µF

capacitor in parallel with the 0.1µF bypass capacitor.

Converter Operation

The MAX1034/MAX1035 ADCs feature a fully differen-

tial, successive-approximation register (SAR) conver-

sion technique and an on-chip T/H block to convert

voltage signals into a 14-bit digital result. Both single-

ended and differential configurations are supported

with programmable unipolar and bipolar signal ranges.

single-ended input ranges (0 to +V

/2,

REF

-V

/2 to 0, 0 to +V

REF

, -V

to 0,

V /4,

REF

V

REF

/2,

REF

and V

REF

) and three differential input ranges ( V

REF

V

, and 2 x V

). Additionally, all analog input

REF

channels are fault tolerant to 6V. A fault condition on

an idle channel does not affect the conversion result of

other channels.

Track-and-Hold Circuitry

The MAX1034/MAX1035 feature a switched-capacitor

T/H architecture that allows the analog input signal to be

stored as charge on sampling capacitors. See Figures 2,

3, and 4 for T/H timing and the sampling instants for

each operating mode. The MAX1034/MAX1035 analog

input circuitry buffers the input signal from the sampling

capacitors, resulting in a constant analog input current

with varying input voltage (Figure 5).

Power Supplies

To maintain a low-noise environment, the MAX1034 and

MAX1035 provide separate power supplies for each

section of circuitry. Table 1 shows the four separate

power supplies. Achieve optimal performance using

separate AV

, AV

, DV , and DV

supplies.

DDO

DD1

DD2

DD

DD1

Alternatively, connect AV

, AV

, and DV

DD2 DD

together as close to the device as possible for a conve-

nient power connection. Connect AGND1, AGND2,

Table 1. MAX1034/MAX1035 Power Supplies and Bypassing

PꢁWER

SUPPLY/GRꢁUND

SUPPLY VꢁLTAGE

RANGE (V)

TYPICAL SUPPLY

CURRENT (mA)

CIRCUIT SECTIꢁN

BYPASSING

DV

/DGNDO

/AGND2

/AGND1

2.7 to 5.25

4.75 to 5.25

0.2

17.5

3.0

Digital I/O

0.1µF to DGNDO

0.1µF to AGND2

0.1µF to AGND1

DDO

AV

Analog Circuitry

DD2

DD1

Digital Control Logic and

Memory

DV /DGND

4.75 to 5.25

0.9

0.1µF to DGND

DD

Table 2. Analog Input Configuration Byte

BIT

NUMBER

NAME

DESCRIPTIꢁN

7

6

5

4

START

C2

Start Bit. The first logic 1 after CS goes low defines the beginning of the analog input configuration byte.

Channel-Select Bits. SEL[2:0] select the analog input channel to be configured (Tables 4 and 5).

C1

C0

Differential or Single-Ended Configuration Bit. DIF/SGL = 0 configures the selected analog input channel

for single-ended operation. DIF/SGL = 1 configures the channel for differential operation. In single-ended

3

DIF/SGL mode, input voltages are measured between the selected input channel and AGND1, as shown in

Table 4. In differential mode, the input voltages are measured between two input channels, as shown in

Table 5. Be aware that changing DIF/SGL adjusts the FSR, as shown in Table 6.

2

1

0

R2

Input-Range-Select Bits. R[2:0] select the input voltage range, as shown in Table 6 and Figure 7.

R1

R0

14 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

CS

SCLK

BYTE 1

BYTE 2

BYTE 3

BYTE 4

SSTRB

DIN

S

C2 C1 C0

0

f ≈ f / 32

SAMPLE SCLK

SAMPLING INSTANT

t

ACQ

ANALOG INPUT

TRACK AND HOLD*

HOLD

TRACK

HOLD

HIGH

IMPEDANCE

HIGH

IMPEDANCE

B13 B12 B11 B10 B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

X

DOUT

*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.

Figure 2. External Clock-Mode Conversion (Mode 0)

the analog configuration byte for the positive channel.

For example, to configure CH2 and CH3 for a dif-

ferential conversion, set the CH2 analog configuration

byte for a differential conversion with the range

(1010 1100). To initiate a conversion for the CH2 and

CH3 differential pair, issue the command 1010 0000.

Analog Input Circuitry

The analog inputs can be individually configured for

either differential or single-ended conversions by writing

the associated analog input configuration byte (Table 2).

The analog input signal source must be capable of dri-

ving the ADC’s 6kΩ input resistance (Figure 6).

V

REF

V

REF

Figure 6 shows the simplified analog input circuit. The

analog inputs are 6V fault tolerant and are protected

by back-to-back diodes. The summing junction voltage,

SJ

voltage:

Analog Input Bandwidth

The MAX1034/MAX1035 input-tracking circuitry has a

1.5MHz small-signal bandwidth. The 1.5MHz input

bandwidth makes it possible to digitize high-speed

transient events. Harmonic distortion increases when

digitizing signal frequencies above 15kHz as shown in

the THD, -SFDR vs. Analog Input Frequency plot in the

Typical Operating Characteristics.

V

, is a function of the channel’s input common-mode





R1

R1 + R2

R1

R1 + R2









V

=

× 2.375V + 1+

× V

CM

















SJ









Analog Input Range and Fault Tolerance

Figure 7 illustrates the software-selectable single-

ended analog input voltage range that produces a valid

digital output. Each analog input channel can be inde-

pendently programmed to one of seven single-ended

input ranges by setting the R[2:0] control bits with

DIF/SGL = 0.

As a result, the analog input impedance is relatively

constant over the input voltage as shown in Figure 5.

Single-ended conversions are internally referenced to

AGND1 (Tables 3 and 4). In differential mode, IN+ and

IN- are selected according to Tables 3 and 5. When con-

figuring differential channels, the differential pair follows

______________________________________________________________________________________ 15

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

CS

SSTRB

SCLK

BYTE 1

BYTE 2

BYTE 3

BYTE 4

DIN

S

C2 C1 C0

0

HIGH

IMPEDANCE

B13 B12 B11 B10 B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

X

DOUT

f

≈ f

SAMPLE SCLK

/ 32 + f

/ 17

INTCLK

SAMPLING INSTANT

t

ACQ

ANALOG INPUT

TRACK AND HOLD*

HOLD

TRACK

HOLD

100ns to 400ns

INTCLK**

f

≈ 4.5MHz

INTCLK

*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.

**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.

Figure 3. External Acquisition-Mode Conversion (Mode 1)

Figure 8 illustrates the software-selectable differential

analog input voltage range that produces a valid digital

output. Each analog input differential pair can be inde-

pendently programmed to one of three differential input

ranges by setting the R[2:0] control bits with DIF/SGL = 1.

Any voltage beyond FSR, but within the 6V fault-

tolerant range, applied to an analog input results in a

full-scale output voltage for that channel.

Clamping diodes with breakdown thresholds in excess

of 6V protect the MAX1034/MAX1035 analog inputs

during ESD and other transient events (Figure 6). The

clamping diodes do not conduct during normal device

operation, nor do they limit the current during such

transients. When operating in an environment with the

potential for high-energy voltage and/or current tran-

sients, protect the MAX1034/MAX1035 externally.

Regardless of the specified input voltage range and

whether the channel is selected, each analog input is

6V fault tolerant. The analog input fault protection is

active whether the device is unpowered or powered.

1± ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

CS

SSTRB

SCLK

BYTE 1

BYTE 2

BYTE 3

DIN

S

C2 C1 C0

0

HIGH IMPEDANCE

B13 B12 B11 B10 B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

X

DOUT

f

≈ f

/ 24 + f / 28

INTCLK

SAMPLE SCLK

SAMPLING INSTANT

t

ACQ

ANALOG INPUT

TRACK AND HOLD*

HOLD

TRACK

HOLD

100ns to 400ns

INTCLK**

f

≈ 4.5MHz

INTCLK

*TRACK AND HOLD TIMING IS CONTROLLED BY INTCLK, AND IS NOT ACCESSIBLE TO THE USER.

**INTCLK IS AN INTERNAL SIGNAL AND IS NOT ACCESSIBLE TO THE USER.

Figure 4. Internal Clock-Mode Conversion (Mode 2)

R2

MAX1034

MAX1035

R1

1.5

1.0

0.5

0

*R

SOURCE

IN_+

ANALOG

SIGNAL

SOURCE

V

SJ

R2

-0.5

-1.0

-1.5

*R

R1

V

SOURCE

IN_+

ANALOG

SIGNAL

SOURCE

SJ

-6

-4

-2

0

2

4

6

ANALOG INPUT VOLTAGE (V)

*MINIMIZE R

TO AVOID GAIN ERROR AND DISTORTION.

SOURCE

Figure 5. Analog Input Current vs. Input Voltage

Figure 6. Simplified Analog Input Circuit

______________________________________________________________________________________ 17

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Table 3. Input Data Word Formats

DATA BIT

ꢁPERATIꢁN

D7

(START)

D±

C2

M2

D5

C1

M1

D4

C0

M0

D3

D2

0

D1

0

D0

0

ConOersion-Start Byte

(Tables 4 and 5)

1

0

DIF/SGL

1

Analog-Input Configuration Byte

R2

0

R1

0

R0

0

(Table 2)

Mode-Control Byte

(Table 7)

Table 4. Channel Selection in Single-Ended Mode (DIF/SGL = 0)

CHANNEL-SELECT BIT

CHANNEL

C2

0

C1

0

C0

0

CH0

CH1

CH2

CH3

CH4

CH5

CH±

CH7

AGND1

+

-

0

1

+

0

1

0

+

0

1

+

1

0

+

1

0

1

+

1

0

+

1

+

Table 5. Channel Selection in True-Differential Mode (DIF/SGL = 1)

CHANNEL-SELECT BIT

CHANNEL

CH4

C2

0

C1

0

C0

0

CH0

CH1

CH2

CH3

CH5

CH±

CH7

AGND1

+

-

0

1

RESERVED

0

1

0

+

-

0

1

RESERVED

+

1

0

-

1

0

1

RESERVED

1

0

+

-

1

RESERVED

tions, each individual analog input must be limited to

6V with respect to AGND1.

Differential Common-Mode Range

The MAX1034/MAX1035 differential common-mode

range (V ) must remain within -4.75V to +5.5V to

obtain valid conversion results. The differential com-

mon-mode range is defined as:

CMDR

The range-select bits R[2:0] in the analog input configu-

ration bytes determine the full-scale range for the corre-

sponding channel (Tables 2 and 6). Figures 9, 10, and

11 show the valid analog input voltage ranges for

the MAX1034/MAX1035 when operating with FSR =

CH_+ + CH_−

(

)

(

)

V

=

CMDR

V

/ 2, FSR = V

, and FSR = 2 x V

, respectively.

2

REF

The shaded area contains the valid common-mode

voltage ranges that support the entire FSR.

In addition to the common-mode input voltage limita-

18 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

+V

REF

+3/4 V

+3/2 V

REF

+V /2

REF

+V

REF

+V /4

REF

+V /2

REF

0

-V /4

REF

-V /2

REF

-V /2

REF

-V

REF

-3/4 V

REF

-3/2 V

REF

-V

-2 x V

REF

INPUT RANGE SELECTION BITS, R[2:0]

EACH INPUT IS FAULT TOLERANT TO 6V.

INPUT RANGE SELECTION BITS, R[2:0]

EACH INPUT IS FAULT TOLERANT TO 6V.

Figure 7. Single-Ended Input Voltage Ranges

Figure 8. Differential Input Voltage Ranges

Digital Interface

Chip Select (CS)

The MAX1034/MAX1035 feature a serial interface that is

compatible with SPI/QSPI and MICROWIRE devices.

DIN, DOUT, SCLK, CS, and SSTRB facilitate bidirection-

al communication between the MAX1034/MAX1035 and

the master at SCLK rates up to 10MHz (internal clock

mode, mode 2), 3.67MHz (external clock mode, mode

0), or 4.39MHz (external acquisition mode, mode 1).

The master, typically a microcontroller, should use the

CPOL = 0, CPHA = 0, SPI transfer format, as shown in

the timing diagrams of Figures 2, 3, and 4.

CS enables communication with the MAX1034/MAX1035.

When CS is low, data is clocked into the device from DIN

on the rising edge of SCLK and data is clocked out of

DOUT on the falling edge of SCLK. When CS is high,

activity on SCLK and DIN is ignored and DOUT is high

impedance allowing DOUT to be shared with other

peripherals. SSTRB is never high impedance and there-

fore cannot be shared with other peripherals.

Serial-Strobe Output (SSTRB)

As shown in Figures 3 and 4, the SSTRB transitions high

to indicate that the ADC has completed a conversion

and results are ready to be read by the master. SSTRB

remains low in the external clock mode (Figure 2) and

consequently may be left unconnected. SSTRB is driven

high or low regardless of the state of CS, therefore

SSTRB cannot be shared with other peripherals.

The digital interface is used to:

• Select single-ended or true-differential input channel

configurations

• Select the unipolar or bipolar input range

• Select the mode of operation:

External clock (mode 0)

External acquisition (mode 1)

Internal clock (mode 2)

Reset (mode 4)

Partial power-down (mode 6)

Full power-down (mode 7)

• Initiate conversions and read results

______________________________________________________________________________________ 19

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Table ±. Range-Select Bits

DIF/SGL

R2

R1

R0

MꢁDE

No Range Change*

TRANSFER FUNCTIꢁN

0

—

Single-Ended

Bipolar - V

REF

Full-Scale Range (FSR) = V

/4 to +V

/4

0

1

0

1

0

1

0

1

0

1

0

Figure 12

Figure 13

Figure 14

Figure 12

Figure 13

Figure 14

REF

/ 2

REF

Single-Ended

Unipolar -V

/2 to 0

REF

FSR = V

/ 2

REF

Single-Ended

Unipolar 0 to +V

/2

REF

FSR = V

/ 2

REF

Single-Ended

Bipolar -V

REF

/2 to +V

/2

REF

FSR = V

REF

Single-Ended

Unipolar -V

to 0

REF

FSR = V

Single-Ended

Unipolar 0 to +V

REF

FSR = V

REF

DEFAULT SETTING

Single-Ended

0

1

Figure 12

Bipolar -V

to +V

REF

FSR = 2 x V

REF

1

0

1

No Range Change**

—

Differential

Bipolar -V

/2 to +V

/2

Figure 12

REF

FSR = V

REF

1

0

1

0

1

Reserved

—

Differential

Bipolar -V

1

0

to +V

Figure 12

REF

FSR = 2 x V

REF

1

0

1

0

Reserved

—

Differential

Bipolar -2 x V

to +2 x V

REF

1

Figure 12

REF

FSR = 4 x V

REF

*Conversion-Start Byte (see Table 3).

**Mode-Control Byte (see Table 3).

20 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

INPUT COMMON-MODE VOLTAGE RANGE

vs. OUTPUT VOLTAGE (FSR = V

INPUT COMMON-MODE VOLTAGE RANGE

vs. OUTPUT VOLTAGE (FSR = 2 x V

)

REF

6

4

6

4

2

0

-2

-4

-6

-2

-4

-6

V

= 4.096V

6

V

= 4.096V

6

REF

4

REF

4

-8 -6 -4 -2

0

2

8

-8 -6 -4 -2

0

2

8

INPUT VOLTAGE (V)

Figure 9. Common-Mode Voltage vs. Input Voltage (FSR = V

)

REF

Figure 10. Common-Mode Voltage vs. Input Voltage (FSR = 2 x

V

)

REF

INPUT COMMON-MODE VOLTAGE RANGE

Output Data Format

vs. OUTPUT VOLTAGE (FSR = 4 x V

)

REF

Output data is clocked out of DOUT in offset binary for-

mat on the falling edge of SCLK, MSB first (B13). For

output binary codes, see the Transfer Function section

and Figures 12, 13, and 14.

6

4

2

Configuring Analog Inputs

Each analog input has two configurable parameters:

0

• Single-ended or true-differential input

• Input voltage range

-2

-4

-6

These parameters are configured using the analog input

configuration byte as shown in Table 2. Each analog

input has a dedicated register to store its input configura-

tion information. The timing diagram of Figure 15 shows

how to write to the analog input configuration registers.

Figure 16 shows DOUT and SSTRB timing.

V

= 4.096V

6

REF

4

-8 -6 -4 -2

0

2

8

INPUT VOLTAGE (V)

Figure 11. Common-Mode Voltage vs. Input Voltage (FSR = 4 x

V

)

REF

Transfer Function

An ADC’s transfer function defines the relationship

between the analog input voltage and the digital output

code. Figures 12, 13, and 14 show the MAX1034/

MAX1035 transfer functions. The transfer function is

determined by the following characteristics:

Start Bit

Communication with the MAX1034/MAX1035 is accom-

plished using the three input data word formats shown

in Table 3. Each input data word begins with a start bit.

The start bit is defined as the first high bit clocked into

DIN with CS low when any of the following are true:

• Analog input voltage range

• Single-ended or differential configuration

• Reference voltage

• Data conversion is not in process and all data from

the previous conversion has clocked out of DOUT.

• The device is configured for operation in external

clock mode (mode 0) and previous conversion-result

bits B13–B1 have clocked out of DOUT.

The axes of an ADC transfer function are typically in least

significant bits (LSBs). For the MAX1034/MAX1035, an

LSB is calculated using the following equation:

• The device is configured for operation in external

acquisition mode (mode 1) and previous conversion-

result bits B13–B5 have clocked out of DOUT.

FSR × V

REF

1 LSB =

N

2

× 4.096V

• The device is configured for operation in internal

clock mode (mode 2) and previous conversion-

result bits B13–B2 have clocked out of DOUT.

where N is the number of bits (N = 14) and FSR is the

full-scale range (see Figures 7 and 8).

______________________________________________________________________________________ 21

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

FSR

3FFF

3FFE

3FFD

3FFF

3FFE

3FFD

2001

2000

1FFF

2001

2000

1FFF

0003

FSR x V

REF

16,384 x 4.096V

0002

1 LSB =

0002

0001

0000

FSR x V

REF

16,384 x 4.096V

1 LSB =

0001

0000

0

1

2

3

8,192

INPUT VOLTAGE (LSB [DECIMAL])

16,381 16,383

(AGND1)

-8,192 -8,190

-1

0

+1

+8,189 +8,191

AGND1 (DIF/SGL = 0)

0V (DIF/SGL = 1)

Figure 13. Ideal Unipolar Transfer Function, Single-Ended

Input, -FSR to 0

INPUT VOLTAGE (LSB [DECIMAL])

Figure 12. Ideal Bipolar Transfer Function, Single-Ended or

Differential Input

Selecting the Conversion Method

The conversion method is selected using the mode-

control byte (see the Mode Control section), and the con-

version is initiated using a conversion-start command

(Table 3, and Figures 2, 3, and 4). The MAX1034/

MAX1035 convert analog signals to digital data using one

of three methods:

FSR

3FFF

3FFE

3FFD

•

External Clock Mode, Mode 0 (Figure 2)

• Highest maximum throughput (see the Electrical

Characteristics table)

2001

2000

1FFF

• User controls the sample instant

• CS remains low during the conversion

• User supplies SCLK throughout the ADC con-

version and reads data at DOUT

0003

FSR x V

REF

16,384 x 4.096V

0002

0001

0000

1 LSB =

•

External Acquisition Mode, Mode 1 (Figure 3)

• Lowest maximum throughput (see the Electrical

Characteristics table)

0

1

2

3

8,192

INPUT VOLTAGE (LSB [DECIMAL])

16,381 16,383

• User controls the sample instant

(AGND1)

• User supplies two bytes of SCLK, then drives

CS high to relieve processor load while the

ADC converts

Figure 14. Ideal Unipolar Transfer Function, Single-Ended

Input, 0 to +FSR

Mode Control

• After SSTRB transitions high, the user supplies

two bytes of SCLK and reads data at DOUT

The MAX1034/MAX1035 contain one byte-wide mode-

control register. The timing diagram of Figure 15 shows

how to use the mode-control byte, and the mode-con-

trol byte format is shown in Table 7. The mode-control

byte is used to select the conversion method and to

control the power modes of the MAX1034/MAX1035.

•

Internal Clock Mode, Mode 2 (Figure 4)

• High maximum throughput (see the Electrical

Characteristics table)

• The internal clock controls the sampling instant

22 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

t

CSPW

t

CSS

CS

t

CL

t

CSH

CH

SCLK

DIN

1

8

1

8

t

CP

t

DS

t

DH

START

SEL2

SEL1

SEL0

DIF/SGL

R2

R1

R0

START

M2

M1

M0

1

0

ANALOG INPUT CONFIGURATION BYTE

MODE CONTROL BYTE

t

DV

t

TR

HIGH

IMPEDANCE

HIGH

IMPEDANCE

HIGH

IMPEDANCE

DOUT

Figure 15. Analog Input Configuration Byte and Mode-Control Byte Timing

• User supplies one byte of SCLK, then drives CS

high to relieve processor load while the ADC

converts

SSTRB

• After SSTRB transitions high, the user supplies

two bytes of SCLK and reads data at DOUT

t

SSCS

CS

SCLK

DOUT

External Clock Mode (Mode 0)

The MAX1034/MAX1035’s fastest maximum throughput

rate is achieved operating in external clock mode.

SCLK controls both the acquisition and conversion of

the analog signal, facilitating precise control over when

the analog signal is captured. The analog input sam-

pling instant is at the falling edge of the 14th SCLK

(Figure 2).

t

CSS

t

DO

HIGH

IMPEDANCE

MSB

NꢁTE: SSTRB AND CS REMAIN LOW IN EXTERNAL CLOCK MODE (MODE 0).

Since SCLK drives the conversion in external clock

mode, the SCLK frequency should remain constant

while the conversion is clocked. The minimum SCLK

frequency prevents droop in the internal sampling

capacitor voltages during conversion.

Figure 16. DOUT and SSTRB Timing

External Acquisition Mode (Mode 1)

SSTRB remains low in the external clock mode, and as a

result may be left unconnected if the MAX1034/

MAX1035 will always be used in the external clock mode.

The slowest maximum throughput rate is achieved with

the external acquisition method. SCLK controls the

acquisition of the analog signal in external acquisition

mode, facilitating precise control over when the analog

Table 7. Mode-Control Byte

BIT NUMBER

BIT NAME

DESCRIPTIꢁN

7

6

5

4

3

2

1

0

START

Start Bit. The first logic 1 after CS goes low defines the beginning of the mode-control byte.

M2

M1

M0

1

Mode-Control Bits. M[2:0] select the mode of operation as shown in Table 8.

Bit 3 must be a logic 1 for the mode-control byte.

Bit 2 must be a logic 0 for the mode-control byte.

Bit 1 must be a logic 0 for the mode-control byte.

Bit 0 must be a logic 0 for the mode-control byte.

0

______________________________________________________________________________________ 23

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Table 8. Mode-Control Bits M[2:0]

M2

0

M1

0

M0

0

MꢁDE

External Clock (DEFAULT)

External Acquisition

Internal Clock

0

1

0

1

0

1

Reserved

1

0

Reset

1

0

1

Reserved

1

0

Partial Power-Down

Full Power-Down

1

signal is captured. The internal clock controls the con-

version of the analog input voltage. The analog input

sampling instant is at the falling edge of the 16th SCLK

(Figure 3).

Partial Power-Down Mode (Mode 6)

As shown in Table 8, when M[2:0] = 110, the device

enters partial power-down mode. In partial power-

down, all analog portions of the device are powered

down except for the reference voltage generator and

bias supplies.

For the external acquisition mode, CS must remain low

for the first 15 clock cycles and then rise on or after the

falling edge of the 16th clock cycle as shown in Figure 3.

For optimal performance, idle DIN and SCLK during the

conversion. With careful board layout, transitions at DIN

and SCLK during the conversion have a minimal impact

on the conversion result.

To exit partial power-down, change the mode by issu-

ing one of the following mode-control bytes (see the

Mode Control section):

• External-Clock-Mode Control Byte

• External-Acquisition-Mode Control Byte

• Internal-Clock-Mode Control Byte

• Reset Byte

After the conversion is complete, SSTRB asserts high

and CS can be brought low to read the conversion

result. SSTRB returns low on the rising SCLK edge of

the subsequent start bit.

• Full Power-Down-Mode Control Byte

Internal Clock Mode (Mode 2)

In internal clock mode, the internal clock controls both

acquisition and conversion of the analog signal. The inter-

nal clock starts approximately 100ns to 400ns after the

falling edge of the eighth SCLK and has a rate of about

4.5MHz. The analog input sampling instant occurs at the

falling edge of the 11th internal clock signal (Figure 4).

This prevents the MAX1034/MAX1035 from inadvertent-

ly exiting partial power-down mode because of a CS

glitch in a noisy digital environment.

Full Power-Down Mode (Mode 7)

When M[2:0] = 111, the device enters full power-down

mode and the total supply current falls to 1µA (typ). In

full power-down, all analog portions of the device are

powered down. When using the internal reference,

upon exiting full power-down mode, allow 10ms for the

internal reference voltage to stabilize prior to initiating a

conversion.

For the internal clock mode, CS must remain low for the

first seven SCLK cycles and then rise on or after the

falling edge of the eighth SCLK cycle. After the conver-

sion is complete, SSTRB asserts high and CS can be

brought low to read the conversion result. SSTRB returns

low on the rising SCLK edge of the subsequent start bit.

To exit full power-down, change the mode by issuing

one of the following mode-control bytes (see the Mode

Control section):

Reset (Mode 4)

As shown in Table 8, set M[2:0] = 100 to reset the

MAX1034/MAX1035 to its default conditions. The

default conditions are full power operation with each

• External-Clock-Mode Control Byte

• External-Acquisition-Mode Control Byte

channel configured for

V

, bipolar, single-ended

REF

conversions using external clock mode (mode 0).

24 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

• Internal-Clock-Mode Control Byte

Internal Reference

The MAX1034/MAX1035 contain an internal 4.096V

bandgap reference. This bandgap reference is connect-

ed to REFCAP through a nominal 5kΩ resistor (Figure 17).

The voltage at REFCAP is buffered creating 4.096V at

REF. When using the internal reference, bypass

REFCAP with a 0.1µF or greater capacitor to AGND1 and

bypass REF with a 1.0µF or greater capacitor to AGND1.

• Reset Byte

• Partial Power-Down-Mode-Control Byte

This prevents the MAX1034/MAX1035 from inadvertent-

ly exiting full power-down mode because of a CS glitch

in a noisy digital environment.

Power-On Reset

The MAX1034/MAX1035 power up in normal operation

configured for external clock mode with all circuitry

active (Tables 7 and 8). Each analog input channel

(CH0–CH7) is set for single-ended conversions with a

External Reference

For external reference operation, disable the internal

reference and reference buffer by connecting REFCAP

to AV

. With AV

connected to REFCAP, REF

DD1

V

bipolar input range (Table 6).

becomes a high-impedance input and accepts an

external reference voltage. The MAX1034/MAX1035

external reference current varies depending on the

applied reference voltage and the operating mode (see

the External Reference Input Current vs. External

Reference Input Voltage in the Typical Operating

Characteristics).

REF

Allow the power supplies to stabilize after power-up. Do

not initiate any conversions until the power supplies

have stabilized. Additionally, allow 10ms for the internal

reference to stabilize when C

= 1.0µF and C

REFCAP

REF

= 0.1µF. Larger reference capacitors require longer

stabilization times.

Applications Information

Internal or External Reference

The MAX1034/MAX1035 operate with either an internal or

external reference. The reference voltage impacts the

ADC’s FSR (Figures 12, 13, and 14). An external refer-

ence is recommended if more accuracy is required than

the internal reference provides, and/or multiple converters

require the same reference voltage.

Noise Reduction

Additional samples can be taken and averaged (over-

sampling) to remove the effect of transition noise on

conversion results. The square root of the number of

samples determines the improvement in performance.

For example, with 2/3 LSB

(4 LSB ) transition

P-P

RMS

noise, 16 (4²= 16) samples must be taken to reduce

the noise to 1 LSB

.

P-P

Interface with 4–20mA Signals

Figure 19 illustrates a simple interface between the

MAX1034/MAX1035 and a 4–20mA signal. 4–20mA sig-

naling can be used as a binary switch (4mA represents

a logic-low signal, 20mA represents a logic-high sig-

nal), or for precision communication where currents

between 4mA and 20mA represent intermediate analog

data. For binary switch applications, connect the

4–20mA signal to the MAX1034/MAX1035 with a resis-

tor to ground. For example, a 200Ω resistor converts

the 4–20mA signal to a 0.8V to 4V signal. Adjust the

resistor value so the parallel combination of the resistor

and the MAX1034/MAX1035 source impedance is

200Ω. In this application, select the single-ended 0 to

4.096V

REF

SAR

ADC

REF

1.0µF

0.1µF

1x

REFCAP

MAX1034

MAX1035

5kΩ

4.096V

V

RCTH

BANDGAP

REFERENCE

AGND1

V

range (R[2:0] = 011, Table 6). For applications

REF

that require precision measurements of continuous

analog currents between 4mA and 20mA, use a buffer

to prevent the MAX1034/MAX1035 input from diverting

current from the 4–20mA signal.

Figure 17. Internal Reference Operation

______________________________________________________________________________________ 25

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

V+

1.0µF

IN

4.096V

REF

SAR

ADC

OUT

REF

1.0µF

MAX6341

AV

DD1

1x

GND

REFCAP

MAX1034

MAX1035

5kΩ

4.096V

V

RCTH

BANDGAP

REFERENCE

AGND1

Figure 18. External Reference Operation

Bridge Application

Layout, Grounding, and Bypassing

The MAX1034/MAX1035 convert 1kHz signals more

accurately than a similar sigma-delta converter that

might be considered in bridge applications. The input

impedance of the MAX1034, in combination with the cur-

rent-limiting resistors, can affect the gain of the

MAX1034. In many applications this error is acceptable,

but for applications that cannot tolerate this error, the

MAX1034 inputs can be buffered (Figure 20). Connect

the bridge to a low-offset differential amplifier and then

the true-differential inputs of the MAX1034/MAX1035.

Larger excitation voltages take advantage of more of the

Careful PC board layout is essential for best system per-

formance. Boards should have separate analog and digi-

tal ground planes and ensure that digital and analog

signals are separated from each other. Do not run analog

and digital (especially clock) lines parallel to one another,

or digital lines underneath the device package.

Figure 1 shows the recommended system ground con-

nections. Establish an analog ground point at AGND1

and a digital ground point at DGND. Connect all analog

grounds to the star analog ground. Connect the digital

grounds to the star digital ground. Connect the digital

ground plane to the analog ground plane at one point.

For lowest noise operation, make the ground return to

the star ground’s power-supply low impedance and as

short as possible.

V

REF

/2 differential input voltage range. Select an input

voltage range that matches the amplifier output. Be

aware of the amplifier offset and offset-drift errors when

selecting an appropriate amplifier.

Dynamically Adjusting the Input Range

Software control of each channel’s analog input range

and the unipolar endpoint overlap specification make it

possible for the user to change the input range for a

channel dynamically and improve performance in some

applications. Changing the input range results in a

small LSB step-size over a wider output voltage range.

High-frequency noise in the AV

power supply

DD1

degrades the ADC’s high-speed comparator perfor-

mance. Bypass AV to AGND1 with a 0.1µF ceramic

DD1

surface-mount capacitor. Make bypass capacitor con-

nections as short as possible.

Parameter Definitions

For example, by switching between a -V

/2 to 0

REF

Integral Nonlinearity (INL)

INL is the deviation of the values on an actual transfer

function from a straight line. This straight line is either a

best straight-line fit or a line drawn between the end-

points of the transfer function once offset and gain

errors have been nullified. The MAX1034/MAX1035 INL

is measured using the endpoint method.

range and a 0 to V

/2 range, an LSB is:

REF

V

/2 × V

REF

16,384 × 4.096

but the input voltage range effectively spans from

-V /2 to +V /2 (FSR = V ).

REF

2± ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

4–20mA INPUT

CH0

µC

200Ω

MAX1034

4–20mA INPUT

CH8

200Ω

Figure 19. 4–20mA Application

LOW-OFFSET

DIFFERENTIAL

AMPLIFIER

CH0

CH1

µP

MAX1034

MAX1035

REF

BRIDGE

Figure 20. Bridge Application

Differential Nonlinearity (DNL)

DNL is the difference between an actual step width and

the ideal value of 1 LSB. A DNL error specification of

greater than -1 LSB guarantees no missing codes and

a monotonic transfer function.

Channel-to-Channel Isolation

Channel-to-channel isolation indicates how well each

analog input is isolated from the others. The channel-to-

channel isolation for these devices is measured by

applying a near full-scale magnitude 5kHz sine wave to

the selected analog input channel while applying an

equal magnitude sine wave of a different frequency to

all unselected channels. An FFT of the selected chan-

nel output is used to determine the ratio of the magni-

tudes of the signal applied to the unselected channels

and the 5kHz signal applied to the selected analog

input channel. This ratio is reported, in dB, as channel-

to-channel isolation.

Transition Noise

Transition noise is the amount of noise that appears at a

code transition on the ADC transfer function. Conversions

performed with the analog input right at the code transi-

tion can result in code flickering in the LSBs.

______________________________________________________________________________________ 27

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Full-Power Bandwidth

Unipolar Offset Error

A 95% of full-scale sine wave is applied to the ADC,

and the input frequency is then swept up to the point

where the amplitude of the digitized conversion result

has decreased by -3dB.

-FSR to 0V

When a zero-scale analog input voltage is applied to

the converter inputs, the digital output is all ones

(0x3FFF). Ideally, the transition from 0x3FFF to 0x3FFE

occurs at AGND1 - 0.5 LSB. Unipolar offset error is the

amount of deviation between the measured zero-scale

transition point and the ideal zero-scale transition point,

with all untested channels grounded.

Common-Mode Rejection Ratio (CMRR)

CMRR is the ability of a device to reject a signal that is

“common” to or applied to both input terminals. The

common-mode signal can be either an AC or a DC sig-

nal or a combination of the two. CMR is expressed in

decibels. Common-mode rejection ratio is the ratio of

the differential signal gain to the common-mode signal

gain. CMRR applies only to differential operation.

0V to +FSR

When a zero-scale analog input voltage is applied to

the converter inputs, the digital output is all zeros

(0x0000). Ideally, the transition from 0x0000 to 0x0001

occurs at AGND1 + 0.5 LSB. Unipolar offset error is the

amount of deviation between the measured zero-scale

transition point and the ideal zero-scale transition point,

with all untested channels grounded.

Power-Supply Rejection Ratio (PSRR)

PSRR is the ratio of the output-voltage shift to the

power-supply-voltage shift for a fixed input voltage. For

the MAX1034/MAX1035, AV

can vary from 4.75V to

DD1

5.25V. PSRR is expressed in decibels and is calculated

using the following equation:

Bipolar Offset Error

When a zero-scale analog input voltage is applied to

the converter inputs, the digital output is a one followed

by all zeros (0x2000). Ideally, the transition from

0x1FFF to 0x2000 occurs at (2^N-1- 0.5) LSB. Bipolar off-

set error is the amount of deviation between the mea-

sured midscale transition point and the ideal midscale

transition point, with untested channels grounded.





5.25V − 4.75V

PSRR[dB] = 20 × log





V

(5.25V) − V

(4.75V)





OUT

For the MAX1034/MAX1035, PSRR is tested in bipolar

operation with the analog inputs grounded.

Gain Error

When a positive full-scale voltage is applied to the con-

verter inputs, the digital output is all ones (0x3FFF). The

transition from 0x3FFE to 0x3FFF occurs at 1.5 LSB

below full scale. Gain error is the amount of deviation

between the measured full-scale transition point and

the ideal full-scale transition point with the offset error

removed and all untested channels grounded.

Aperture Jitter

Aperture jitter, t , is the statistical distribution of the

AJ

variation in the sampling instant (Figure 21).

Aperture Delay

Aperture delay, t , is the time from the falling edge of

AD

SCLK to the sampling instant (Figure 21).

Signal-to-Noise Ratio (SNR)

SNR is computed by taking the ratio of the RMS signal

to the RMS noise. RMS noise includes all spectral com-

ponents to the Nyquist frequency excluding the funda-

mental, the first five harmonics, and the DC offset.

Unipolar Endpoint Overlap

Unipolar endpoint overlap is the change in offset when

switching between complementary input voltage

ranges. For example, the difference between the volt-

age that results in a 0x3FFF output in the -V

/2 to 0V

REF

input voltage range and the voltage that results in a

0x0000 output in the 0 to +V /2 input voltage range

is the unipolar endpoint overlap. The unipolar endpoint

overlap is positive for the MAX1034/MAX1035, prevent-

ing loss of signal or a dead zone when switching

between adjacent analog input voltage ranges.

Signal-to-Noise Plus Distortion (SINAD)

SINAD is computed by taking the ratio of the RMS sig-

nal to the RMS noise plus distortion. RMS noise plus

distortion includes all spectral components to the

Nyquist frequency excluding the fundamental and the

DC offset.

REF

Small-Signal Bandwidth





Signal

Noise

A 100mV

sine wave is applied to the ADC, and the

RMS

P-P

SINAD(dB) = 20 × log





input frequency is then swept up to the point where the

amplitude of the digitized conversion result has

decreased by -3dB.





RMS

28 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Effective Number of Bits (ENOB)

SCLK

(MODE 0)

ENOB indicates the global accuracy of an ADC at a

14

15

13

specific input frequency and sampling rate. With an

input range equal to the ADC’s full-scale range, calcu-

late the ENOB as follows:

SCLK

(MODE 1)

16

11

15

10

SINAD − 1.76





ENOB =









INTCLK

(MODE 2)

6.02

12

Total Harmonic Distortion (THD)

For the MAX1034/MAX1035, THD is the ratio of the

RMS sum of the input signal’s first four harmonic com-

ponents to the fundamental itself. This is expressed as:

t

AJ

t

AD

SAMPLE INSTANT

HOLD

ANALOG INPUT

TRACK AND HOLD













TRACK

2

V

+ V

5

2

3

4

THD = 20 × log

V

Figure 21. Aperture Diagram

1

where V is the fundamental amplitude, and V through

1

2

V

are the amplitudes of the 2nd- through 5th-order

harmonic components.

5

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio of RMS amplitude of the fundamental

(maximum signal component) to the RMS value of the

next-largest spectral component.

______________________________________________________________________________________ 29

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Block Diagram

DV

DDO

CS

DIN

CONTROL LOGIC AND REGISTERS

SERIAL I/O

SSTRB

DOUT

SCLK

DGNDO

CH0

CH1

AV

DD2

CLOCK

DV

DD

ANALOG

INPUT MUX

AND

MULTIRANGE

CIRCUITRY

CH2

CH3

CH4

CH5

CH6

CH7

AGND1

SAR

ADC

IN

OUT

FIFO

PGA

DGND

AV

REF

DD1

AGND2

AGND3

5kΩ

4.096V

BANDGAP

REFERENCE

1x

AV

AGND2

DD2

MAX1034

REFCAP

REF

Pin Configurations (continued)

Chip Information

TRANSISTOR COUNT: 28,210

PROCESS: BiCMOS

TOP VIEW

AGND1

AV

1

2

3

4

5

6

7

8

9

20 AGND2

19 AV

DD1

DD2

CH0

CH1

CH2

CH3

CS

18 AGND3

17 REF

MAX1035

16 REFCAP

15 DV

DD

14

DV

DDO

DIN

13 DGND

12 DGNDO

11 DOUT

SSTRB

SCLK 10

TSSꢁP

30 ______________________________________________________________________________________

8-/4-Channel, ±± Multirange Inputs,

REF

Serial 14-Bit ADCs

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maꢀim-ic.com/packages.)

PACKAGE OUTLINE, TSSOP 4.40mm BODY

1

21-0066

G

1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX1034
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	8-/4-Channel, 【VREF Multirange Inputs, Serial 14-Bit ADCs 8 / 4通道，【 VREF多量程输入，串行14位ADC
文件：	总31页 (文件大小：833K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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