MAX1066CCUP_技术文档

19-2466; Rev 0; 4/02

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

General Description

Features

The MAX1065/MAX1066 14-bit, low-power successive

approximation analog-to-digital converters (ADCs) fea-

ture automatic power-down, a factory-trimmed internal

clock, and a high-speed, 14-bit-wide (MAX1065) or

byte-wide (MAX1066) parallel interface. The devices

operate from a single 4.75V to 5.25V analog supply and

a 2.7V to 5.25V digital supply.

ꢀ 14-Bit-Wide (MAX1065) and Byte-Wide (MAX1066)

Parallel Interface

ꢀ High Speed: 165ksps Sample Rate

ꢀ Accurate: 1ꢀSB ꢁDꢀ (maꢂ)ꢃ 1ꢀSB IDꢀ (maꢂ)

ꢀ 4.096Vꢃ 35ppm/°C Internal Reference

ꢀ Eꢂternal Reference Range 3.8V to 5.25V

ꢀ Single 4.75V to 5.25V Analog Supply Voltage

ꢀ 2.7V to 5.25V ꢁigital Supply Voltage

The MAX1065/MAX1066 use an internal 4.096V refer-

ence or an external reference. The MAX1065/MAX1066

consume only 1.8mA at a sampling rate of 165ksps with

external reference and 2.7mA with internal reference.

AutoShutdown™ reduces supply current to 0.1mA at

10ksps.

ꢀ ꢀow Supply Current

1.8mA (Eꢂternal Reference)

2.7mA (Internal Reference)

0.1mA AutoShutdown Mode (10kspsꢃ Eꢂternal

Reference)

The MAX1065/MAX1066 are ideal for high-performance,

battery-powered, data-acquisition applications.

Excellent dynamic performance and low-power con-

sumption in a small package make the MAX1065/

MAX1066 the best choice for circuits with demanding

power consumption and space requirements.

ꢀ Small Footprint

28-Pin TSSOP Package (14-Bit Wide)

20-Pin TSSOP Package (Byte Wide)

The 14-bit-wide MAX1065 is available in a 28-pin TSSOP

package, and the byte-wide MAX1066 is available in a

20-pin TSSOP package. Both devices are available in

either the 0°C to +70°C commercial, or the -40°C to

+85°C extended temperature range.

Applications

Ordering Information

Temperature

Cable/Harness Tester

PIN-

PACKAGE

PART

TEMP RANGE

INL

Sensor/Monitor

Accelerometer

Measurements

Industrial Process

Control

MAX1065ACUI

MAX1065BCUI

MAX1065CCUI

MAX1065AEUI

MAX1065BEUI

MAX1065CEUI

MAX1066ACUP

MAX1066BCUP

MAX1066CCUP

MAX1066AEUP

MAX1066BEUP

MAX1066CEUP

0°C to 70°C

28 TSSOP

20 TSSOP

1

2

3

1

2

3

1

2

3

1

2

3

Digital Signal Processing

I/O Boards

0°C to 70°C

Data-Acquisition

Systems

-40°C to +85°C

0°C to 70°C

Typical Operating Circuit

5V ANALOG

5V DIGITAL

0°C to 70°C

0.1µF

-40°C to +85°C

µP DATA

BUS

AV

DD

DV

DD

D0–D13

ANALOG INPUT

AIN

R/C

CS

EOC

REF

MAX1065

Pin Configurations appear at end of data sheet.

RESET

REFADJ

AGND DGND

0.1µF

1µF

AutoShutdown is a registered trademark of Maxim Integrated

Products, Inc.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

ABSOLUTE MAXIMUM RATINGS

AV

DV

to AGND .........................................................-0.3V to +6V

to DGND.........................................................-0.3V to +6V

Continuous Power Dissipation (T = +70°C)

DD

A

20-Pin TSSOP (derate 10.9mW/°C above +70°C) .......879mW

28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW

Operating Temperature Ranges

AGND to DGND.....................................................-0.3V to +0.3V

AIN, REF, REFADJ to AGND....................-0.3V to (AV + 0.3V)

DD

MAX106_ _CU_...................................................0°C to +70°C

MAX106_ _EU_................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +150°C

Junction Temperature......................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

CS, HBEN, R/C, RESET to DGND ............................-0.3V to +6V

Digital Output (D13–D0, EOC)

to DGND ..................................................-0.3V to (DV

+ 0.3V)

DD

Maximum Continuous Current Into Any Pin ........................50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(AV

= DV

= 5V, external reference = 4.096V, C

= 1µF, C

= 0.1µF, T = T

to T

, unless otherwise noted.

MAX

DD

REF

REFADJ

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

DC ACCURACY

Resolution

SYMBOL

N

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

14

1

2

3

1

MAX106_A

MAX106_B

MAX106_C

Relative Accuracy (Note 1)

INL

LSB

Differential Nonlinearity

Transition Noise

DNL

No missing codes over temperature

LSB

RMS noise, includes quantization

noise

LSB

RMS

0.32

Offset Error

Gain Error

Offset Drift

Gain Drift

0.2

0.002

0.6

1

mV

(Note 2)

0.02

%FSR

ppm/°C

0.2

DYNAMIC PERFORMANCE (f

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

Total Harmonic Distortion

Spurious-Free Dynamic Range

Full-Power Bandwidth

Full-Linear Bandwidth

CONVERSION RATE

Sample Rate

= 1kHz, V = 4.096V , 165ksps)

IN(SINE-WAVE)

SINAD

SNR

IN

P-P

81

82

84

-99

102

4

dB

THD

-86

dB

SFDR

87

dB

-3dB point

MHz

kHz

SINAD > 81dB

20

f

165

ksps

ns

SAMPLE

Aperture Delay

40

Aperture Jitter

100

ps

ANALOG INPUT

Input Range

V

0

V

AIN

REF

Input Capacitance

C

40

pF

AIN

2

_______________________________________________________________________________________

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= 5V, external reference = 4.096V, C

= 1µF, C

= 0.1µF, T = T

to T

, unless otherwise noted.

MAX

DD

REF

REFADJ

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

INTERNAL REFERENCE

REF Output Voltage

V

4.056

4.096

35

4.136

V

ppm/°C

mA

REF

REF Output Tempco

TC

REF

REF Short-Circuit Current

Capacitive Bypass at REFADJ

Capacitive Bypass at REF

REFADJ Input Leakage Current

EXTERNAL REFERENCE

I

10

REFSC

C

0.1

1

µF

REFADJ

C

µF

REF

REFADJ

I

20

µA

REFADJ Buffer Disable

Threshold

AV

0.4

-

AV

0.1

-

DD

To power-down the internal reference

Internal reference disabled

V

REF Input Voltage Range

3.8

AV

DD

V

= 4.096V, f

= 165ksps

SAMPLE

62

120

REF

REF Input Current

I

µA

REF

Shutdown mode

0.1

DIGITAL INPUTS/OUTPUTS (CS, R/C, EOC, D0–D13, RESET, HBEN)

0.7 x

Input High Voltage

Input Low Voltage

V

IH

DV

DD

V

0.3 x

V

IL

DV

DD

Input Leakage Current

Input Hysteresis

I

V

= 0 or DV

DD

0.1

15

1

µA

V

IN

IH

V

HYST

Input Capacitance

C

pF

IN

I

= 0.5mA,

= 2.7V to 5.25V,

= 5.25V

SOURCE

D

-

VDD

0.4

DV

AV

Output High Voltage

V

DD

OH

I

= 1.6mA,

SINK

DV

AV

= 2.7V to 5.25V,

Output Low Voltage

V

0.4

10

DD

OL

= 5.25V

DD

Three-State Leakage Current

I

D0–D13

0.1

15

µA

pF

OZ

Three-State Output

Capacitance

C

OZ

POWER REQUIREMENTS

Analog Supply Voltage

Digital Supply Voltage

AV

DV

4.75

2.7

5.25

V

DD

AV

DD

165ksps

100ksps

10ksps

1ksps

2.7

2.0

1.0

1.8

1.1

0.1

0.01

3.2

Internal reference

External reference

Analog Supply Current

I

mA

AVDD

165ksps

100ksps

10ksps

1ksps

2.3

_______________________________________________________________________________________

3

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

ELECTRICAL CHARACTERISTICS (continued)

(AV

= DV

= 5V, external reference = 4.096V, C

= 1µF, C

= 0.1µF, T = T

to T

, unless otherwise noted.

MAX

DD

REF

REFADJ

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

165ksps

MIN

TYP

MAX

UNITS

0.5

0.3

0.7

100ksps

10ksps

1ksps

Digital Supply Current

I

D0–D13 = all zeros

mA

DVDD

SHDN

0.03

0.003

0.05

0.5

I

5

mA

µA

AVDD

DVDD

Full power-down

I

Shutdown Supply Current

(Note 3)

REF and REF

buffer enabled

(standby mode)

I

1.0

0.5

1.2

5

mA

µA

AVDD

DVDD

I

Power-Supply Rejection Ratio

(Note 4)

PSRR

AV

= 5V, 5%, full-scale input

68

dB

DD

TIMING CHARACTERISTICS (Figures 1 and 2)

(AV

= 4.75V to 5.25V, DV

= 2.7V to AV , external reference = 4.096V, C

= 1µF, C

= 0.1µF, C

C

= 20pF,

DD

REF

REFADJ

13–D0, EOC

D

T

A

= T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

µs

Acquisition Time

Conversion Time

CS Pulse Width High

t

1.1

ACQ

t

4.7

CONV

t

(Note 5)

40

60

0

ns

CSH

V

= 4.75V to 5.25V

DVDD

CS Pulse Width Low

t

ns

CSL

= 2.7V to 4.74V

R/C to CS Fall Setup Time

R/C to CS Fall Hold Time

t

ns

DS

V

= 4.75V to 5.25V

= 2.7V to 5.25V

= 4.75V to 5.25V

= 2.7V to 4.74V

40

60

DVDD

t

ns

DH

40

80

CS to Output Data Valid

t

ns

DO

HBEN Transition To

Output Data Valid

(MAX1066 only)

V

= 4.75V to 5.25V

= 2.7V to 4.74V

40

80

DVDD

t

DO1

EOC Fall To CS Fall

t

0

ns

DV

V

= 4.75V to 5.25V

= 2.7V to 4.74V

= 4.75V to 5.25V

= 2.7V to 4.74V

40

80

40

80

DVDD

CS Rise To EOC Rise

t

EOC

Bus Relinquish Time

(Note 5)

t

ns

BR

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 2: Offset nulled.

Note 3: Maximum specification is limited by automated test equipment.

Note 4: Defined as the change in positive full scale caused by a 5% variation in the nominal supply.

Note 5: To ensure best performance, finish reading the data and wait t before starting a new acquisition.

BR

4

_______________________________________________________________________________________

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Typical Operating Characteristics

(AV

= DV

= 5V, external reference = 4.096V, C

= 1µF, C

= 0.1µF, T = +25°C, unless otherwise noted.)

REFADJ

A

DD

REF

I

+ I

SUPPLY CURRENT

AVDD DVDD

DNL vs. OUTPUT CODE

INL vs. OUTPUT CODE

vs. SAMPLE RATE

1.0

0.8

2.0

1.5

10

1

0.6

1.0

0.4

0.5

0.2

0.1

0

-0.2

-0.4

-0.6

-0.8

-1.0

0.01

0.001

0.0001

-0.5

-1.0

-1.5

-2.0

0

4096

8192

12288

16384

0

4096

8192

12288

16384

0.01

0.1

1

10

100

1000

OUTPUT CODE

CONVERSION RATE (ksps)

I

+ I

SHUTDOWN CURRENT

INTERNAL REFERENCE

vs. TEMPERATURE

I

+ I

SUPPLY CURRENT

AVDD DVDD

vs. TEMPERATURE

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.136

4.126

4.116

4.106

4.096

4.086

4.076

4.066

4.056

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

SAMPLE RATE = 165ksps

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

TEMPERATURE (°C)

SINAD vs. FREQUENCY

GAIN ERROR vs. TEMPERATURE

OFFSET ERROR vs. TEMPERATURE

1000

800

600

400

200

0

0.020

0.015

0.010

0.005

0

100

90

80

70

60

50

40

30

20

10

0

-200

-400

-600

-800

0

-0.005

-0.010

-0.015

-0.020

SAMPLE RATE = 165ksps

10

FREQUENCY (kHz)

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

0.1

1

100

TEMPERATURE (°C)

_______________________________________________________________________________________

5

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Typical Operating Characteristics (continued)

(AV

= DV

= 5V, external reference = 4.096V, C

= 1µF, C

= 0.1µF, T = +25°C, unless otherwise noted.)

REFADJ

A

DD

REF

SPURIOUS-FREE DYNAMIC RANGE

vs. FREQUENCY

TOTAL HARMONIC DISTORTION

vs. FREQUENCY

FFT AT 1kHz

0

-20

110

100

90

80

70

60

50

40

30

20

10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

SAMPLE RATE = 165ksps

-40

-60

-80

-100

-120

-140

-100

-110

SAMPLE RATE = 165ksps

0

20

40

60

80

0.1

1.0

10

100

0.1

1

10

100

FREQUENCY (kHz)

Pin Description

NAME

FUNCTION

MAX1065 MAX1066 MAX1065 MAX1066

1

2

3

4

5

6

7

8

1

2

D6

D7

D4/D12

D5/D13

D6/0

D7/0

—

Three-State Digital Data Output

Three-State Digital Data Output. D13 is the MSB.

Three-State Digital Data Output

3

D8

4

D9

Three-State Digital Data Output

—

D10

D11

D12

D13

Three-State Digital Data Output

—

Three-State Digital Data Output

—

Three-State Digital Data Output

—

Three-State Digital Data Output (MSB)

Read/Convert Input. Power up and put the MAX1065/MAX1066 in acquisition

mode by holding R/C low during the first falling edge of CS. During the

second falling edge of CS the level on R/C determines whether the reference

and reference buffer power down or remain on after conversion. Set R/C high

during the second falling edge of CS to power down the reference and buffer,

or set R/C low to leave the reference and buffer powered up. Set R/C high

during the third falling edge of CS to put valid data on the bus.

9

5

R/C

10

11

12

13

6

7

8

9

EOC

End Of Conversion. EOC drives low when conversion is complete.

Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.

Analog Ground. Primary analog ground (star ground).

Analog Input

AV

DD

AGND

AIN

Analog Ground. Connect Pin 14 to Pin 12 (MAX1065). Connect Pin 10 to Pin 8

(MAX1066).

14

10

AGND

6

_______________________________________________________________________________________

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Pin Description (continued)

NAME

FUNCTION

MAX1065 MAX1066 MAX1065 MAX1066

Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for

15

11

REFADJ

internal reference mode. Connect REFADJ to AV

reference mode.

to select external

DD

Reference Input/Output. Bypass REF with a 1µF capacitor to AGND for internal

reference mode. External reference input when in external reference mode.

16

17

12

REF

—

RESET

Reset Input. Logic high resets the device.

High Byte-Enable Input. Used to multiplex the 14-bit conversion result.

1: Most significant byte available on the data bus.

—

13

HBEN

0: Least significant byte available on the data bus.

Convert Start. The first falling edge of CS powers up the device and enables

acquire mode when R/C is low. The second falling edge of CS starts

conversion. The third falling edge of CS loads the result onto the bus when R/C

is high.

18

14

CS

19

20

15

16

DGND

Digital Ground

DV

Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.

DD

No Connection. Do Not Connect (MAX1065).

Three-State Digital Data Output (MAX1066).

21

22

17

18

N.C.

D0/D8

D1/D9

No Connection. Do Not Connect (MAX1065).

Three-State Digital Data Output (MAX1066).

23

24

25

26

27

28

19

20

—

D0

D1

D2

D3

D4

D5

D2/D10

D3/D11

—

Three-State Digital Data Output

—

Functional Diagram

AV

AGND DV

DGND

REFADJ

HBEN*

DD

5kΩ

REFERENCE

14 OR 8*

D0–D13

OUTPUT

REGISTERS

OR

D0/D8–D5/D13*

REF

AIN

CAPACITIVE

DAC

MAX1065

MAX1066

AGND

SUCCESSIVE-

APPROXIMATION

REGISTER AND

CONTROL LOGIC

RESET**

CLOCK

EOC

CS

R/C

*BYTE WIDE (MAX1066 ONLY)

**16-BIT WIDE (MAX1065 ONLY)

_______________________________________________________________________________________

7

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Analog Input

The equivalent input circuit is shown in Figure 4. A

Detailed Description

switched capacitor digital-to-analog converter (DAC)

provides an inherent track-and-hold function. The sin-

gle-ended input is connected between AIN and AGND.

Converter Operation

The MAX1065/MAX1066 use a successive-approximation

(SAR) conversion technique with an inherent track-and-

hold (T/H) stage to convert an analog input into a 14-bit

digital output. Parallel outputs provide a high-speed inter-

face to most microprocessors (µPs). The Functional

Diagram shows a simplified internal architecture of the

MAX1065/MAX1066. Figure 3 shows a typical application

circuit for the MAX1066.

Input Bandwidth

The ADC’s input-tracking circuitry has a 4MHz small-

signal bandwidth, so it is possible to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid aliasing of

unwanted high-frequency signals into the frequency

band of interest, use antialias filtering.

DV

DD

Internal protection diodes, which clamp the analog

1mA

input to AV

and/or AGND, allow the input to swing

DD

D0–D13

from AGND - 0.3V to AV

the device.

+ 0.3V, without damaging

DD

C

LOAD

= 20pF

C

= 20pF

1mA

LOAD

If the analog input exceeds 300mV beyond the sup-

plies, limit the input current to 10mA.

DGND

Track and Hold (T/H)

In track mode, the analog signal is acquired on the

internal hold capacitor. In hold mode, the T/H switches

open and the capacitive DAC samples the analog input.

a) HIGH-Z TO V

OH,

b) HIGH-Z TO V

OL,

V

TO V AND

OL

OH

OH,

TO HIGH-Z

V

OH

V

OL

TO V AND

OL,

TO HIGH-Z

Figure 1. Load Circuits for D0–D13 Enable Time, CS to D0–D13

Delay Time and Bus Relinquish Time

t

CSH

CSL

CS

R/C

t

ACQ

REF POWER-

DOWN BIT

t

DS

t

DV

DH

t

EOC

t

BR

t

DO

CONV

HI–Z

HI-Z

D0–D13

DATA VALID

HBEN*

t

BR

t

DO1

HIGH/LOW

BYTE VALID

HIGH/LOW

BYTE VALID

D7/D13–D0/D8*

*HBEN AND BYTE-WIDE DATA BUS AVAILABLE ON MAX1066 ONLY.

Figure 2. MAX1065/MAX1066 Timing Diagram

_______________________________________________________________________________________

8

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

During the acquisition, the analog input (AIN) charges

capacitor C . The acquisition ends on the second

Internal Clock

The MAX1065/MAX1066 generate an internal conver-

sion clock. This frees the microprocessor from the bur-

den of running the SAR conversion clock. Total

conversion time after entering hold mode (second

falling edge of CS) to end-of-conversion (EOC) falling is

4.7µs (max).

DAC

falling edge of CS. At this instant, the T/H switches

open. The retained charge on C

sample of the input.

represents a

DAC

In hold mode, the capacitive DAC adjusts during the

remainder of the conversion time to restore node ZERO

to zero within the limits of 14-bit resolution. At the end of

the conversion, force CS low to put valid data on the bus.

Applications Information

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is

high, the acquisition time lengthens and more time

must be allowed between conversions. The acquisition

Starting a Conversion

CS and R/C control acquisition and conversion in the

MAX1065/MAX1066 (Figure 2). The first falling edge of

CS powers up the device and puts it into acquisition

mode if R/C is low. The convert start is ignored if R/C is

high. When powering up from shutdown, the MAX1065/

time (t

) is the maximum time the device takes to

ACQ

acquire the signal. Use the following formula to calcu-

late acquisition time:

MAX1066 needs at least 10ms (C

= 0.1µF, C

REF

REFADJ

= 1µF) for the internal reference to wake up and settle

before starting the conversion. The ADC may wake up

from shutdown to an unknown state. Put the ADC in a

known state by completing one “dummy” conversion.

The MAX1065/ MAX1066 will be in a known state, ready

for actual data acquisition, after the completion of the

dummy conversion. A dummy conversion consists of one

full conversion cycle.

t

= 11(R + R ) x 35pF

S IN

ACQ

where R = 800Ω, R = the input signal’s source

IN

S

ACQ

impedance, and t

is never less than 1.1µs. A

source impedance less than 1kΩ does not significantly

affect the ADC’s performance.

To improve the input-signal bandwidth under AC condi-

tions, drive AIN with a wideband buffer (>4MHz) that can

drive the ADC’s input capacitance and settle quickly.

The MAX1065 provides an alternative reset function to

reset the device (see RESET section).

Power-Down Modes

Select standby mode or shutdown mode with the R/C

bit during the second falling edge of CS (see Selecting

Standby or Shutdown Mode section). The MAX1065/

MAX1066 automatically enter either standby mode, ref-

erence and buffer on, or shutdown, reference and

buffer off, after each conversion depending on the sta-

tus of R/C during the second falling edge of CS.

Selecting Standby or Shutdown Mode

The MAX1065/MAX1066 have a selectable standby or

low-power shutdown mode. In standby mode, the

ADC’s internal reference and reference buffer do not

power down between conversions, eliminating the need

to wait for the reference to power up before performing

the next conversion. Shutdown mode powers down the

reference and reference buffer after completing a con-

version. Supply current is greatly reduced when in

shutdown mode. The reference and reference buffer

5V ANALOG

5V DIGITAL

0.1µF

require a minimum of 10ms (C

= 0.1µF, C

=

REF

REFADJ

1µF) to power up and settle from shutdown.

µP DATA

BUS

AV

DD

DV

DD

D0–D7 OR

D8–D13

The state of R/C at the second falling edge of CS

selects which power-down mode the MAX1065/

MAX1066 enters upon conversion completion. Holding

R/C low causes the MAX1065/MAX1066 to enter stand-

by mode. The reference and buffer are left on after the

conversion completes. R/C high causes the

MAX1065/MAX1066 to enter shutdown mode and shut

down the reference and buffer after conversion

(Figures 5 and 6).

ANALOG INPUT

AIN

R/C

CS

EOC

REF

MAX1066

HIGH

BYTE

REFADJ

HBEN

AGND DGND

LOW

BYTE

0.1µF

1µF

When using an external reference, set the REF power-

down bit high for lowest current operation.

Figure 3. Typical Application Circuit for MAX1066

_______________________________________________________________________________________

9

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Internal and External Reference

REF

Internal Reference

TRACK

The internal reference of the MAX1065/MAX1066 is

CAPACITIVE DAC

AIN

internally buffered to provide 4.096V (typ) output at

ZERO

C

SWITCH

3pF

REF. Bypass REF to AGND and REFADJ to AGND with

1µF and 0.1µF respectively. Fine adjustments can be

made to the internal reference voltage by sinking or

sourcing current at REFADJ. The input impedance at

REFADJ is nominally 5kΩ. The internal reference volt-

age is adjustable to 1.5% with the circuit of Figure 7.

C

DAC

= 32pF

HOLD

R

HOLD

IN

800Ω

AGND

TRACK

AUTO-ZERO

RAIL

External Reference

An external reference can be placed at either the input

(REFADJ) or the output (REF) of the MAX1065/

MAX1066’s internal buffer amplifier. When connecting

an external reference to REFADJ, the input impedance

is typically 5kΩ. Using the buffered REFADJ input

makes buffering the external reference unnecessary;

however, the internal buffer output must be bypassed

at REF with a 1µF capacitor.

Figure 4. Equivalent Input Circuit

Standby Mode

While in standby mode, the supply current is reduced

to less than 1mA (typ). The next falling edge of CS with

R/C low causes the MAX1065/MAX1066 to exit standby

mode and begin acquisition. The reference and refer-

ence buffer remain active to allow quick turn-on time.

Standby mode allows significant power savings while

running at the maximum sample rate.

Connect REFADJ to AV

to disable the internal buffer.

DD

Directly drive REF using an external reference. During

conversion, the external reference must be able to

drive 100µA of DC load current and have an output

impedance of 10Ω or less. REFADJ’s impedance is typ-

ically 5kΩ. The DC input impedance of REF is 40kΩ

minimum.

Shutdown Mode

In shutdown mode, the reference and reference buffer

are shut down between conversions. Shutdown mode

reduces supply current to 0.5µA (typ) immediately after

the conversion. The falling edge of CS with R/C low

causes the reference and buffer to wake up and enter

acquisition mode. To achieve 14-bit accuracy, allow

For optimal performance, buffer the reference through

an op amp and bypass REF with a 1µF capacitor.

Consider the MAX1065/MAX1066’s equivalent input

noise (80µV

) when choosing a reference.

RMS

10ms (C

= 0.1µF, C

= 1µF) for the internal

REF

REFADJ

reference to wake up. Increase wakeup time propor-

tionally when using larger values of C

and C

.

REFADJ

REF

DATA

OUT

DATA

OUT

ACQUISITION

CONVERSION

ACQUISITION

CONVERSION

CS

R/C

REF POWER-

DOWN BIT

CS

REF POWER-

DOWN BIT

R/C

EOC

REF

AND

BUFFER

REF

AND

BUFFER

Figure 5. Selecting Standby Mode

Figure 6. Selecting Shutdown Mode

10 ______________________________________________________________________________________

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

OUTPUT CODE

5V

FULL-SCALE

TRANSITION

11...111

11...110

11...101

MAX1065

MAX1066

68kΩ

100kΩ

REFADJ

0.22µF

150kΩ

FS = V

REF

V

REF

1LSB =

16384

00...011

00...010

00...001

00...000

Figure 7. MAX1065/MAX1066 Reference Adjust Circuit

0

1

2

3

FS

FS - 3/2LSB

Reading the Conversion Result

EOC is provided to flag the microprocessor when a con-

version is complete. The falling edge of EOC signals

that the data is valid and ready to be output to the bus.

INPUT VOLTAGE (LSB)

Figure 8. MAX1065/MAX1066 Transfer Function

the required output voltage change before the beginning

of the acquisition time. At the beginning of acquisition, the

internal sampling capacitor array connects to AIN (the

amplifier output) causing some output disturbance.

Ensure that the sampled voltage has settled to within the

required limits before the end of the acquisition time. If

the frequency of interest is low, AIN can be bypassed

with a large enough capacitor to charge the internal sam-

pling capacitor with very little ripple. However, for AC use,

AIN must be driven by a wideband buffer (at least

10MHz), which must be stable with the ADC’s capacitive

load (in parallel with any AIN bypass capacitor used) and

also settle quickly. An example of this circuit using the

MAX4434 is given in Figure 9.

D0–D13 are the parallel outputs of the MAX1065/

MAX1066. These three-state outputs allow for direct

connection to a microcontroller I/O bus. The outputs

remain high-impedance during acquisition and conver-

sion. Data is loaded onto the bus with the third falling

edge of CS with R/C high after t ns. Bringing CS high

DO

forces the output bus back to high-impedance. The

MAX1065/MAX1066 then waits for the next falling edge

of CS to start the next conversion cycle (Figure 2).

The MAX1065 loads the conversion result onto a 14-bit-

wide data bus while the MAX1066 has a byte-wide out-

put format. HBEN toggles the output between the

most/least significant byte. The least significant byte is

loaded onto the output bus when HBEN is low and the

most significant byte is on the bus when HBEN is high

(Figure 2).

RESET

Toggle RESET with CS high. The next falling edge of

CS will begin acquisition. This reset is an alternative to

the dummy conversion explained in the Starting a

Conversion section.

MAX1065/

MAX1066

Transfer Function

Figure 8 shows the MAX1065/MAX1066 output transfer

function. The output is coded in standard binary.

AIN

10Ω

ANALOG

INPUT

MAX4434

40pF

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multiplexed,

the input channel should be switched immediately after

acquisition, rather than near the end of or after a conver-

sion. This allows more time for the input buffer amplifier to

respond to a large step-change in input signal. The input

amplifier must have a high enough slew rate to complete

Figure 9. MAX1065/MAX1066 Fast Settling Input Buffer

______________________________________________________________________________________ 11

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

In reality, there are other noise sources besides quanti-

zation noise: thermal noise, reference noise, clock jitter,

etc. SNR is computed by taking the ratio of the RMS

signal to the RMS noise, which includes all spectral

components minus the fundamental, the first five har-

monics, and the DC offset.

Layout, Grounding, and Bypassing

For best performance, use printed circuit boards. Do not

run analog and digital lines parallel to each other, and do

not lay out digital signal paths underneath the ADC pack-

age. Use separate analog and digital ground planes with

only one point connecting the two ground systems (ana-

log and digital) as close to the device as possible.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to the

RMS equivalent of all the other ADC output signals.

Route digital signals far away from sensitive analog and

reference inputs. If digital lines must cross analog lines,

do so at right angles to minimize coupling digital noise

onto the analog lines. If the analog and digital sections

share the same supply, then isolate the digital and ana-

log supply by connecting them with a low-value (10Ω)

resistor or ferrite bead.













Signal

(Noise + Distortion)

RMS

SINAD(dB) = 20 × log

RMS

The ADC is sensitive to high-frequency noise on the AV

DD

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the effective number

of bits as follows:

supply. Bypass AV

to AGND with a 0.1µF capacitor in

DD

parallel with a 1µF to 10µF low-ESR capacitor and the

smallest capacitor closest to the device. Keep capacitor

leads short to minimize stray inductance.

Definitions

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nullified. The

static linearity parameters for the MAX1065/MAX1066

are measured using the end-point method.

−

SINAD 1.76

=

ENOB

6.02

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1LSB. A

DNL error specification of 1LSB guarantees no missing

codes and a monotonic transfer function.













2

V

+ V + V + V

3 4 5









2

THD = 20 × log

V

1









Aperture Jitter and Delay

Aperture jitter is the sample-to-sample variation in the

time between samples. Aperture delay is the time

between the rising edge of the sampling clock and the

instant when the actual sample is taken.

where V is the fundamental amplitude and V through

V are the 2nd- through 5th-order harmonics.

1

2

5

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of the

RMS amplitude of the fundamental (maximum signal

component) to the RMS value of the next largest fre-

quency component.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of the

full-scale analog input (RMS value) to the RMS quanti-

zation error (residual error). The ideal, theoretical mini-

mum analog-to-digital noise is caused by quantization

noise error only and results directly from the ADC’s res-

olution (N-bits):

Chip Information

TRANSISTOR COUNT: 15,140

PROCESS: BiCMOS

SNR = (6.02 x N + 1.76)dB

where N = 14 bits.

12 ______________________________________________________________________________________

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Pin Configurations

TOP VIEW

D4/D12

D5/D13

D6/0

1

2

3

4

5

6

7

8

9

20 D3/D11

19 D2/D10

18 D1/D9

17 D0/D8

D6

D7

1

2

3

4

5

6

7

8

9

28 D5

27 D4

26 D3

25 D2

24 D1

23 D0

22 N.C.

21 N.C.

D8

D7/0

D9

MAX1066

R/C

16 DV

DD

D10

D11

D12

D13

R/C

MAX1065

EOC

15 DGND

14

AV

DD

CS

AGND

AIN

13 HBEN

12 REF

20 DV

DD

AGND 10

11 REFADJ

EOC 10

AV 11

19 DGND

18 CS

DD

TSSOP

AGND 12

AIN 13

17 RESET

16 REF

AGND 14

15 REFADJ

TSSOP

______________________________________________________________________________________ 13

Low-Power, 14-Bit Analog-to-Digital Converters

with Parallel Interface

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1066CCUP
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Low-Power, 14-Bit Analog-to-Digital Converters with Parallel Interface 低功耗， 14位模数转换，并行接口转换器转换器
文件：	总14页 (文件大小：322K)
中文：	中文翻译
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