MAX108CHC-D [MAXIM]
ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, Bipolar, PBGA192, 25 X 25 MM, ESBGA-192;
| 型号： | MAX108CHC-D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, Bipolar, PBGA192, 25 X 25 MM, ESBGA-192 转换器 |
| 文件： | 总31页 (文件大小：1259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1492; Rev 1; 10/01
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
General Description
Features
The MAX108 PECL-compatible, 1.5Gsps, 8-bit analog-
to-digital converter (ADC) allows accurate digitizing of
analog signals with bandwidths to 2.2GHz. Fabricated
on Maxim’s proprietary advanced GST-2 bipolar
process, the MAX108 integrates a high-performance
track/hold (T/H) amplifier and a quantizer on a single
monolithic die.
ꢀ 1.5Gsps Conversion Rate
ꢀ 2.2GHz Full-Power Analog Input Bandwidth
ꢀ 7.5 Effective Bits at f = 750MHz (Nyquist
IN
Frequency)
ꢀ
0.25ꢀLB INꢀ and ꢁNꢀ
ꢀ 50Ω ꢁifferential Analog Inputs
250ꢂm Input Lignal Range
The innovative design of the internal T/H, which has an
exceptionally wide 2.2GHz full-power input bandwidth,
results in high performance (typically 7.5 effective bits)
at the Nyquist frequency. A fully differential comparator
design and decoding circuitry reduce out-of-sequence
code errors (thermometer bubbles or sparkle codes)
and provide excellent metastable performance. Unlike
other ADCs that can have errors resulting in false full-
or zero-scale outputs, the MAX108 limits the error mag-
nitude to 1LSB.
ꢀ
ꢀ On-Chip, +2.5m Precision Bandgap moltage
Reference
ꢀ ꢀatched, ꢁifferential PECꢀ ꢁigital Outputs
ꢀ Lelectable 8:16 ꢁeꢂultiplexer
ꢀ Internal ꢁeꢂux Reset Input with Reset Output
ꢀ 192-Contact ELBGA Package
The analog input is designed for either differential or
single-ended use with a 250mꢀ input voltage range.
Dual, differential, positive-referenced emitter-coupled
logic (PECL)-compatible output data paths ensure easy
interfacing and include an 8:16 demultiplexer feature
that reduces output data rates to one-half the sampling
clock rate. The PECL outputs can be operated from any
supply between +3ꢀ to +5ꢀ for compatibility with +3.3ꢀ
or +5ꢀ referenced systems. Control inputs are provided
for interleaving additional MAX108 devices to increase
the effective system sampling rate.
ꢀ Pin Coꢂpatible with MAX104 (1Gsps) and
MAX106 (600Msps)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX108CHC
0°C to +70°C
192 ESBGA
192-Contact ESBGA
Ball Assignment Matrix
The MAX108 is packaged in a 25mm x 25mm, 192-con-
tact Enhanced Super Ball-Grid Array (ESBGA™) and is
specified over the commercial (0°C to +70°C) tempera-
ture range. For pin-compatible, lower speed versions of
the MAX108, see the MAX104 (1Gsps) and the MAX106
(600Msps) data sheets.
TOP VIEW
Applications
Digital RF/IF Signal Processing
Direct RF Downconversion
High-Speed Data Acquisition
Digital Oscilloscopes
MAX108
High-Energy Physics
Radar/ECM Systems
ATE Systems
Typical Operating Circuit appears at end of data sheet.
ELBGA
PCB land pattern appears at end of data sheet.
ESBGA is a trademark of Amkor/Anam.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
ABLOꢀUTE MAXIMUM RATINGL
ꢀ
CC
ꢀ
CC
ꢀ
CC
ꢀ
CC
A to GNDA .........................................................-0.3ꢀ to +6ꢀ
D to GNDD.........................................................-0.3ꢀ to +6ꢀ
I to GNDI............................................................-0.3ꢀ to +6ꢀ
RSTIN+, RSTIN- ......................................-0.3ꢀ to (ꢀ O + 0.3ꢀ)
CC
ꢀOSADJ Adjust Input ................................-0.3ꢀ to (ꢀ I + 0.3ꢀ)
CC
CLK+ to CLK- ꢀoltage Difference.......................................... 3ꢀ
O to GNDD........................................-0.3ꢀ to (ꢀ D + 0.3ꢀ)
CLK+, CLK-.....................................(ꢀ - 0.3ꢀ) to (GNDD + 1ꢀ)
CC
EE
AUXEN1, AUXEN2 to GND .....................-0.3ꢀ to (ꢀ D + 0.3ꢀ)
CLKCOM.........................................(ꢀ - 0.3ꢀ) to (GNDD + 1ꢀ)
EE
ꢀIN+ to ꢀIN- ꢀoltage Difference............................................ 2ꢀ
ꢀIN+, ꢀIN- to GNDI................................................................ 2ꢀ
CC
ꢀ
to GNDI..............................................................-6ꢀ to +0.3ꢀ
Between GNDs......................................................-0.3ꢀ to +0.3ꢀ
EE
ꢀ
ꢀ
A to ꢀ D .......................................................-0.3ꢀ to +0.3ꢀ
Continuous Power Dissipation (T = +70°C)
192-Contact ESBGA (derate 61mW/°C above +70°C)....4.88W
(with heatsink and 200 LFM airflow,
CC
CC
CC
A
A to ꢀ I.........................................................-0.3ꢀ to +0.3ꢀ
CC
PECL Digital Output Current...............................................50mA
REFIN to GNDR ........................................-0.3ꢀ to (ꢀ I + 0.3ꢀ)
derate 106mW/°C above +70°C).....................................8.48W
Operating Temperature Range
MAX108CHC.........................................................0°C to +70°C
Operating Junction Temperature.....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
CC
REFOUT Current ................................................+100µA to -5mA
ICONST, IPTAT to GNDI .......................................-0.3ꢀ to +1.0ꢀ
TTL/CMOS Control Inputs
(DEMUXEN, DIꢀSELECT) ......................-0.3ꢀ to (ꢀ D + 0.3ꢀ)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ꢁC EꢀECTRICAꢀ CHARACTERILTICL
(ꢀ A = ꢀ I = ꢀ D = +5.0ꢀ 5ꢁ, ꢀ = -5.0ꢀ 5ꢁ, ꢀ O = +3.0ꢀ to ꢀ D, REFIN connected to REFOUT, T = T
to T
,
MAX
CC
CC
CC
EE
CC
CC
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
ACCURACY
LYMBOꢀ
CONꢁITIONL
MIN
TYP
MAX
UNITL
Resolution
RES
INL
8
Bits
LSB
Integral Nonlinearity (Note 1)
Differential Nonlinearity (Note 1)
Missing Codes
T
T
= +25°C
-0.5
-0.5
0.25
0.25
0.5
0.5
A
DNL
= +25°C
LSB
A
No missing codes guaranteed
None
Codes
ANAꢀOG INPUTL
Full-Scale Input Range
Common-Mode Input Range
Input Resistance
ꢀ
Note 1
475
49
500
0.8
50
525
51
mꢀp-p
FSR
ꢀ
Signal + offset w.r.t. GNDI
ꢀ
CM
R
ꢀIN+ and ꢀIN- to GNDI, T = +25°C
A
Ω
IN
Input Resistance Temperature
Coefficient
TC
150
ppm/°C
R
mOL AꢁJULT CONTROꢀ INPUT
Input Resistance (Note 2)
R
ꢀOS
14
4
25
kΩ
Input ꢀ Adjust Range
OS
ꢀOSADJ = 0 to 2.5ꢀ
5.5
LSB
REFERENCE INPUT ANꢁ OUTPUT
Reference Output ꢀoltage
REFOUT Driving REFIN input only
2.475
4
2.50
5
2.525
5
ꢀ
Reference Output Load
Regulation
∆REFOUT 0 < I < 2.5mA
mꢀ
kΩ
SOURCE
Reference Input Resistance
R
REF
Referenced to GNDR
2
_______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
ꢁC EꢀECTRICAꢀ CHARACTERILTICL (continued)
(ꢀ A = ꢀ I = ꢀ D = +5.0ꢀ 5ꢁ, ꢀ = -5.0ꢀ 5ꢁ, ꢀ O = +3.0ꢀ to ꢀ D, REFIN connected to REFOUT, T = T
to T
,
MAX
CC
CC
CC
EE
CC
CC
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
CꢀOCK INPUTL (Note 3)
Clock Input Resistance
LYMBOꢀ
CONꢁITIONL
MIN
TYP
MAX
UNITL
R
CLK+ and CLK- to CLKCOM, T = +25°C
48
50
52
Ω
CLK
A
Input Resistance Temperature
Coefficient
TC
150
ppm/°C
R
TTꢀ/CMOL CONTROꢀ INPUTL (ꢁEMUXEN, ꢁImLEꢀECT)
High-Level Input ꢀoltage
Low-Level Input ꢀoltage
ꢀ
2.0
ꢀ
ꢀ
IH
ꢀ
0.8
50
1
IL
High-Level Input Current
I
IH
ꢀ
ꢀ
= 2.4ꢀ
= 0
µA
µA
IH
Low-Level Input Current
I
IL
-1
IL
ꢁEMUX RELET INPUT (Note 4)
Digital Input High ꢀoltage
Digital Input Low ꢀoltage
ꢀ
-1.165
ꢀ
ꢀ
IH
ꢀ
-1.475
IL
PECꢀ ꢁIGITAꢀ OUTPUTL (Note 5)
Digital Output High ꢀoltage
Digital Output Low ꢀoltage
POWER REQUIREMENTL
Positive Analog Supply Current
Positive Input Supply Current
Negative Input Supply Current
Digital Supply Current
ꢀ
-1.025
-1.810
-0.880
-1.620
ꢀ
ꢀ
OH
ꢀ
OL
I
A
480
108
-210
205
75
780
150
mA
mA
mA
mA
mA
W
CC
I
I
CC
I
EE
-290
I
D
O
340
115
CC
CC
Output Supply Current (Note 6)
Power Dissipation (Note 6)
I
P
DISS
5.25
Common-Mode Rejection Ratio
(Note 7)
CMRR
PSRR+
PSRR-
ꢀIN+ = ꢀIN- = 0.1ꢀ
(Note 9)
40
40
40
68
73
68
dB
dB
dB
Positive Power-Supply Rejection
Ratio (Note 8)
Negative Power-Supply
Rejection Ratio (Note 8)
(Note 10)
_______________________________________________________________________________________
3
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
AC EꢀECTRICAꢀ CHARACTERILTICL
(ꢀ A = ꢀ I = ꢀ D = +5.0ꢀ, ꢀ = -5.0ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, f at -1dBFS, T = +25°C,
CC
CC
CC
EE
CC
S
IN
A
unless otherwise noted.)
PARAMETER
LYMBOꢀ
CONꢁITIONL
MIN
TYP
MAX
UNITL
ANAꢀOG INPUT
Analog Input Full-Power
Bandwidth
BW
2.2
GHz
-3dB
Analog Input ꢀSWR
ꢀSWR
f
= 500MHz
1.1:1
0
ꢀ/ꢀ
IN
Transfer Curve Offset
ꢀ
OS
ꢀOSADJ control input open
-2
+2
LSB
ꢁYNAMIC LPECIFICATIONL
Differential
7.07
7.07
7.51
7.53
7.71
7.71
44.8
44.9
46.8
46.9
47.4
47.4
-44.5
-44.2
-52.1
-52.8
-60.2
-61.3
44.6
45.5
54.0
54.1
61.6
61.7
43.3
43.4
46.0
46.1
47.2
47.2
ENOB
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 1500MHz
= 750MHz
= 250MHz
= 1500MHz
= 750MHz
= 250MHz
= 1500MHz
= 750MHz
= 250MHz
= 1500MHz
= 750MHz
= 250MHz
= 1500MHz
= 750MHz
= 250MHz
1500
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Single-ended
Differential
Effective Number of Bits
(Note 11)
ENOB
ENOB
Bits
dB
dB
dB
750
Single-ended
Differential
7.3
250
Single-ended
Differential
SNR
1500
Single-ended
Differential
Signal-to-Noise Ratio
(No Harmonics)
SNR
SNR
750
Single-ended
Differential
44.8
250
Single-ended
Differential
THD
1500
Single-ended
Differential
Total Harmonic Distortion
(Note 12)
THD
THD
750
Single-ended
Differential
-55.5
250
Single-ended
Differential
SFDR
1500
Single-ended
Differential
Spurious-Free Dynamic Range
SFDR
SFDR
SINAD
750
250
1500
Single-ended
Differential
55.0
44.7
Single-ended
Differential
Single-ended
Differential
Signal-to-Noise Ratio and
Distortion
SINAD
SINAD
dB
dB
750
250
Single-ended
Differential
f
f
IN
Single-ended
= 247MHz, f
= 253MHz,
at -7dB below full-scale
IN1
IN2
Two-Tone Intermodulation
IMD
-66.8
4
_______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
AC EꢀECTRICAꢀ CHARACTERILTICL (continued)
(ꢀ A = ꢀ I = ꢀ D = +5.0ꢀ, ꢀ = -5.0ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, f at -1dBFS, T = +25°C,
CC
CC
CC
EE
CC
S
IN
A
unless otherwise noted.)
PARAMETER
LYMBOꢀ
CONꢁITIONL
MIN
TYP
MAX
UNITL
TIMING CHARACTERILTICL
Maximum Sample Rate
Clock Pulse Width Low
Clock Pulse Width High
Aperture Delay
f
1.5
0.3
0.3
Gsps
ns
MAX
t
Figure 17
PWL
t
Figure 17
Figure 4
Figure 4
5
ns
PWH
t
100
ps
AD
Aperture Jitter
t
AJ
<0.5
ps
Reset Input Data Setup Time
(Note 13)
t
Figure 15
Figure 15
Figure 17
Figure 17
0
0
ps
ps
ns
ps
SU
Reset Input Data Hold Time
(Note 13)
t
HD
CLK to DREADY Propagation
Delay
t
2.2
PD1
PD2
DREADY to DATA Propagation
Delay (Note 14)
t
-50
150
350
DATA Rise Time
DATA Fall Time
t
20ꢁ to 80ꢁ, C = 3pF
420
360
220
180
7.5
ps
ps
ps
ps
RDATA
L
t
20ꢁ to 80ꢁ, C = 3pF
L
FDATA
DREADY Rise Time
DREADY Fall Time
t
20ꢁ to 80ꢁ, C = 3pF
L
RDREADY
t
20ꢁ to 80ꢁ, C = 3pF
L
FDREADY
DIꢀ1, DIꢀ2 modes
DIꢀ4 mode
Primary Port Pipeline
Delay
Clock
Cycles
t
Figures 6, 7, 8
Figures 6, 7, 8
PDP
7.5
DIꢀ1, DIꢀ2 modes
DIꢀ4 mode
8.5
Auxiliary Port Pipeline
Delay
Clock
Cycles
t
PDA
9.5
Note 1: Static linearity parameters are computed from a “best-fit” straight line through the code transition points. The full-scale
range (FSR) is defined as 256 times the slope of the line.
Note 2: The offset control input is a self-biased voltage divider from the internal +2.5ꢀ reference voltage. The nominal open-circuit
voltage is +1.25ꢀ. It may be driven from an external potentiometer connected between REFOUT and GNDI.
Note 3: The clock input’s termination voltage can be operated between -2.0ꢀ and GNDI. Observe the absolute maximum ratings
on the CLK+ and CLK- inputs.
Note 4: Input logic levels are measured with respect to the ꢀ O power-supply voltage.
CC
Note 5: All PECL digital outputs are loaded with 50Ω to ꢀ O - 2.0ꢀ. Measurements are made with respect to the ꢀ O power-
CC
CC
supply voltage.
Note 6: The current in the ꢀ O power supply does not include the current in the digital output’s emitter followers, which is a func-
CC
tion of the load resistance and the ꢀ termination voltage.
TT
Note 7: Common-mode rejection ratio (CMRR) is defined as the ratio of the change in the transfer-curve offset voltage to the
change in the common-mode voltage, expressed in dB.
Note 8: Power-supply rejection ratio (PSRR) is defined as the ratio of the change in the transfer-curve offset voltage to the change
in power-supply voltage, expressed in dB.
Note 9: Measured with the positive supplies tied to the same potential; ꢀ A = ꢀ D = ꢀ I. ꢀ varies from +4.75ꢀ to +5.25ꢀ.
CC
CC
CC
CC
Note 10: ꢀ varies from -5.25ꢀ to -4.75ꢀ.
EE
_______________________________________________________________________________________
5
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Note 11: Effective number of bits (ENOB) are computed from a curve fit referenced to the theoretical full-scale range.
Note 12: Total harmonic distortion (THD) is computed from the first five harmonics.
Note 13: Guaranteed by design with a reset pulse width one clock period long or greater.
Note 14: Guaranteed by design. The DREADY to DATA propagation delay is measured from the 50ꢁ point on the rising edge of the
DREADY signal (when the output data changes) to the 50ꢁ point on a data output bit. This places the falling edge of the
DREADY signal in the middle of the data output valid window, within the differences between the DREADY and DATA rise
and fall times, which gives maximum setup and hold time for latching external data latches.
Typical Operating Characteristics
(ꢀ A = ꢀ I = ꢀ D = +5ꢀ, ꢀ = -5ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, T = +25°C, unless otherwise
CC
CC
CC
EE
CC
S
A
noted.)
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
EFFECTIVE NUMBER OF BITS
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
8.00
7.75
7.50
7.25
7.00
6.75
6.50
6.25
8.00
7.75
7.50
7.25
7.00
6.75
6.50
6.25
55
50
45
40
35
30
-12dB FS
-12dB FS
-1dB FS
-6dB FS
-1dB FS
-6dB FS
-1dB FS
-6dB FS
-12dB FS
10
100
1000 2000
ANALOG INPUT FREQUENCY (MHz)
10
100
1000 2000
ANALOG INPUT FREQUENCY (MHz)
10
100
1000
10,000
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
50
46
42
38
34
55
50
45
40
35
30
50
46
42
38
34
-1dB FS
-1dB FS
-1dB FS
-6dB FS
-6dB FS
-6dB FS
-12dB FS
-12dB FS
-12dB FS
30
30
10
100
1000 2000
10
100
1000 2000
10
100
1000
10,000
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Typical Operating Characteristics (continued)
(ꢀ A = ꢀ I = ꢀ D = +5ꢀ, ꢀ = -5ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, T = +25°C, unless otherwise
CC
CC
CC
EE
CC
S
A
noted.)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(DIFFERENTIAL ANALOG INPUT DRIVE)
EFFECTIVE NUMBER OF BITS
vs. CLOCK FREQUENCY
(f = 250MHz, 1dB FS)
IN
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(SINGLE-ENDED ANALOG INPUT DRIVE)
70
65
60
55
50
45
40
8.00
7.75
7.50
7.25
7.00
6.75
6.50
70
65
60
55
50
45
40
-6dB FS
-1dB FS
-12dB FS
-6dB FS
-1dB FS
-12dB FS
35
35
10
100
1000 2000
100
1000
1500
10
100
1000 2000
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
CLOCK FREQUENCY (MHz )
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
vs. CLOCK POWER
(f = 250MHz, -1dB FS)
IN
vs. V I = V A = V D
EFFECTIVE NUMBER OF BITS vs. V
CC
CC
CC
EE
(f = 250MHz, -1dB FS)
IN
(f = 250MHz, -1dB FS)
IN
8.00
7.75
7.50
7.25
7.00
6.75
6.50
8.00
7.75
7.50
7.25
7.00
6.75
6.50
8.00
7.75
7.50
7.25
7.00
6.75
6.50
DIFFERENTIAL CLOCK DRIVE
SINGLE-ENDED CLOCK DRIVE
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10
4.5
4.7
4.9
5.1
(V)
5.3
5.5
-5.5
-5.3
-5.1
-4.9
(V)
-4.7
-4.5
CLOCK POWER (dBm) PER SIDE
V
V
EE
CC
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK POWER
SPURIOUS-FREE DYNAMIC RANGE
vs. V I = V A = V
SPURIOUS-FREE DYNAMIC RANGE vs. V
D
CC
EE
CC
CC
(f = 250MHz, -1dB FS)
IN
(f = 250MHz, -1dB FS)
IN
(f = 250MHz, -1dB FS)
IN
67
66
65
64
63
62
61
60
59
58
57
67
66
65
64
63
62
61
60
59
58
57
67
65
63
61
59
57
55
53
51
49
47
SINGLE-ENDED CLOCK DRIVE
DIFFERENTIAL CLOCK DRIVE
-12 -10 -8 -6 -4 -2
0
2
4
6
8 10
-5.5
-5.3
-5.1
-4.9
(V)
-4.7
-4.5
4.5
4.7
4.9
5.1
(V)
5.3
5.5
CLOCK POWER (dBm) PER SIDE
V
V
EE
CC
_______________________________________________________________________________________
7
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Typical Operating Characteristics (continued)
(ꢀ A = ꢀ I = ꢀ D = +5ꢀ, ꢀ = -5ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, T = +25°C, unless otherwise
CC
CC
CC
EE
CC
S
A
noted.)
TOTAL HARMONIC DISTORTION
vs. V I = V A = V
FFT PLOT
(f = 250.9460449MHz,
RECORD LENGTH 16,384)
TOTAL HARMONIC DISTORTION vs. V
EE
D
CC
CC
CC
IN
(f = 250MHz, -1dB FS)
IN
(f = 250MHz, -1dB FS)
IN
-54
-55
-56
-57
-58
-59
-60
-61
-62
-63
-64
-54
-55
-56
-57
-58
-59
-60
-61
-62
-63
0
-25.6
ENOB = 7.73
SINAD = 48.3dB
SNR = 47.3dB
THD = -59.9dB
SFDR = 61.5dB
-51.2
FUNDAMENTAL
H2
H3
-76.8
-102.4
-128.0
-64
4.5
-5.5
-5.3
-5.1
-4.9
(V)
-4.7
-4.5
4.7
4.9
5.1
(V)
5.3
5.5
0
150
300
450
600
750
V
EE
V
ANALOG INPUT FREQUENCY (MHz)
CC
FFT PLOT
(f = 747.1618562MHz,
RECORD LENGTH 16,384)
FFT PLOT
(f = 1503.021240MHz,
-3dB FS, RECORD LENGTH 16,384)
FFT PLOT
(f = 1503.021240MHz,
-1dB FS, RECORD LENGTH 16,384)
IN
IN
IN
0
-25.6
0
-25.6
0
-25.6
ENOB = 7.61
ENOB = 7.60
ENOB = 7.12
FUNDAMENTAL
SINAD = 47.6dB
SNR = 46.7dB
THD = -56.5dB
SFDR = 59.4dB
SINAD = 47.5dB
SNR = 42.0dB
THD = -51.3dB
SFDR = 51.3dB
SINAD = 44.6dB
FUNDAMENTAL
SNR = 44.7dB
THD = -44.4dB
SFDR = 44.4dB
H3
H3
FUNDAMENTAL
H3
-51.2
-51.2
-51.2
H2
H2
H2
-76.8
-76.8
-76.8
-102.4
-128.0
-102.4
-128.0
-102.4
-128.0
0
150
300
450
600
750
0
150
300
450
600
750
0
150
300
450
600
750
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
(LOW-FREQUENCY SERVO-LOOP DATA)
ANALOG INPUT BANDWIDTH
-6dB BELOW FULL SCALE
ANALOG INPUT BANDWIDTH
FULL POWER
0.5
0.4
-5
0
0.3
-6
-7
-1
-2
-3
-4
-5
0.2
0.1
0
-8
-0.1
-0.2
-0.3
-0.4
-0.5
-9
SMALL-SIGNAL BANDWIDTH = 2.4GHz
FULL-POWER BANDWIDTH = 2.2GHz
-10
0
32 64 96 128 160 192 224 256
OUTPUT CODE
500
1500 2500
500
1500 2500
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
8
_______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Typical Operating Characteristics (continued)
(ꢀ A = ꢀ I = ꢀ D = +5ꢀ, ꢀ = -5ꢀ, ꢀ O = +3.3ꢀ, REFIN connected to REFOUT, f = 1.5Gsps, T = +25°C, unless otherwise
CC
CC
CC
EE
CC
S
A
noted.)
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
(LOW-FREQUENCY SERVO-LOOP DATA)
DREADY RISE/FALL TIME,
DATA-OUTPUT RISE/FALL TIME
0.5
0.4
0.3
0.2
DREADY
200mV/div
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
DATA
200mV/div
0
32 64 96 128 160 192 224 256
OUTPUT CODE
500ps/div
TWO-TONE INTERMODULATION FFT PLOT
(f = 247.1008301MHz, f = 253.3264160MHz,
IN1
IN2
7dB BELOW FULL SCALE, RECORD LENGTH 16,384)
VSWR vs. ANALOG INPUT FREQUENCY
1.5
1.4
1.3
1.2
1.1
1.0
0
f
1
IN
-25.6
-51.2
f
2
IN
-76.8
-102.4
-128.0
0
150
300
450
600
750
0
500
1000
1500
2000
2500
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Pin Description
CONTACT
NAME
FUNCTION
A1–A4, A6, A7, B1, B2, C1, C2, D1–D3,
G1, H1, J2, J3, K1–K3, L2, L3, M1, N1,
T2, T3, U1, ꢀ1, ꢀ2, W1–W4
Analog Ground. For T/H amplifier, clock distribution, bandgap
reference, and reference amplifier.
GNDI
Analog Supply ꢀoltage, +5ꢀ. Supplies T/H amplifier, clock distri-
bution, bandgap reference, and reference amplifier.
A5, B5, C5, H2, H3, M2, M3, U5, ꢀ5, W5
ꢀ
CC
I
A8, B8, C8, U6, ꢀ6, W6
A9, B9, C9, U7, ꢀ7, W7
A10, E17, F2, P3, R17, R18
GNDA
Analog Ground. For comparator array.
ꢀ
CC
A
Analog Supply ꢀoltage, +5ꢀ. Supplies analog comparator array.
Test Point. ꢁo not connect.
TESTPOINT (T.P.)
A11, B11, B16, B17, C11, C16, U9, U17,
ꢀ9, ꢀ17, ꢀ18, W9
GNDD
Digital Ground
_______________________________________________________________________________________
9
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Pin Description (continued)
CONTACT
NAME
FUNCTION
A12–A19, B19, C19, D19, E19, F19,
G19, H19, J19, K19, L19, M19, N19,
P19, T19, U19, ꢀ19, W10–W19
ꢀ
CC
O
PECL Supply ꢀoltage, +3ꢀ to +5ꢀ
B3, B4, C3, C4, E3, F3, G2, G3, N2, N3,
U2–U4, ꢀ3, ꢀ4
Analog Supply ꢀoltage, -5ꢀ. Supplies T/H amplifier, clock distribu-
tion, bandgap reference, and reference amplifier.
ꢀ
EE
B6, B7
GNDR
Reference Ground. Must be connected to GNDI.
B10, B18, C10, C17, C18, T17, T18, U8,
U18, ꢀ8, W8
ꢀ
CC
D
Digital Supply ꢀoltage, +5ꢀ
B12
B13
B14
B15
C6
P0+
A0+
Primary Output Data Bit 0 (LSB)
Auxiliary Output Data Bit 0 (LSB)
Primary Output Data Bit 1
P1+
A1+
Auxiliary Output Data Bit 1
REFIN
REFOUT
P0-
Reference Input
C7
Reference Output
C12
C13
C14
C15
Complementary Primary Output Data Bit 0 (LSB)
Complementary Auxiliary Output Data Bit 0 (LSB)
Complementary Primary Output Data Bit 1
Complementary Auxiliary Output Data Bit 1
A0-
P1-
A1-
TTL/CMOS Demux Divide Selection Input
1: Decimation DIꢀ4 mode
D17
DIꢀSELECT
0: Demultiplexed DIꢀ2 mode
Connect to ꢀ O to power the auxiliary port, or connect to GNDD
CC
to power down.
D18
E1
AUXEN2
ICONST
IPTAT
Die Temperature Measurement Test Point. See Die Temperature
Measurement section.
Die Temperature Measurement Test Point. See Die Temperature
Measurement section.
E2
TTL/CMOS Demux Enable Control
1: Enable Demux
E18
DEMUXEN
0: Disable Demux
F1
ꢀOSADJ
P2-
Offset Adjust Input
F17
F18
G17
G18
H17
H18
Complementary Primary Output Data Bit 2
Primary Output Data Bit 2
P2+
A2-
Complementary Auxiliary Output Data Bit 2
Auxiliary Output Data Bit 2
A2+
P3-
Complementary Primary Output Data Bit 3
Primary Output Data Bit 3
P3+
10 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Pin Description (continued)
CONTACT
NAME
FUNCTION
Differential Input ꢀoltage (-)
J1
J17
J18
K17
K18
L1
ꢀIN-
A3-
Complementary Auxiliary Output Data Bit 3
Auxiliary Output Data Bit 3
A3+
DREADY-
DREADY+
ꢀIN+
Complementary Data-Ready Clock
Data-Ready Clock
Differential Input ꢀoltage (+)
L17
L18
M17
M18
N17
N18
P1
P4-
Complementary Primary Output Data Bit 4
Primary Output Data Bit 4
P4+
A4-
Complementary Auxiliary Output Data Bit 4
Auxiliary Output Data Bit 4
A4+
P5-
Complementary Primary Output Data Bit 5
Primary Output Data Bit 5
P5+
CLK-
Complementary Sampling Clock Input
This contact ꢂust be connected to GNDI.
Complementary Auxiliary Output Data Bit 5
Auxiliary Output Data Bit 5
P2
TESTPOINT (T.P.)
A5-
P17
P18
R1–R3
A5+
CLKCOM
50Ω Clock Termination Return
Connect to ꢀ O to power the auxiliary port, or connect to
CC
GNDD to power down.
R19
AUXEN1
T1
CLK+
RSTIN-
RSTOUT-
OR-
Sampling Clock Input
U10
U11
U12
U13
U14
U15
U16
ꢀ10
ꢀ11
ꢀ12
ꢀ13
ꢀ14
ꢀ15
ꢀ16
Complementary PECL Demux Reset Input
Complementary PECL Reset Output
Complementary PECL Overrange Bit
Complementary Auxiliary Output Data Bit 7 (MSB)
Complementary Primary Output Data Bit 7 (MSB)
Complementary Auxiliary Output Data Bit 6
Complementary Primary Output Data Bit 6
PECL Demux Reset Input
A7-
P7-
A6-
P6-
RSTIN+
RSTOUT+
OR+
PECL Reset Output
PECL Overrange Bit
A7+
Auxiliary Output Data Bit 7 (MSB)
Primary Output Data Bit 7 (MSB)
Auxiliary Output Data Bit 6
P7+
A6+
P6+
Primary Output Data Bit 6
______________________________________________________________________________________ 11
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
REF REF
OUT IN
REFERENCE
AMPLIFIER
BANDGAP
REFERENCE
+2.5V
DIFFERENTIAL
PECL OUTPUTS
GNDR
MAX108
VOSADJ
BIAS CURRENTS
OVERRANGE
BIT
OR
2
GNDI
50Ω
50Ω
AUXILIARY
DATA PORT
T/H AMPLIFIER
VIN+
VIN-
2
A0–A7
P0–P7
8-BIT
FLASH ADC
16
16
16
PRIMARY
DATA PORT
GNDI
DATA
DREADY
READY CLOCK
2
CLK+
CLKCOM
CLK-
LOGIC
CLOCK
DRIVER
50Ω
50Ω
DEMUX
CLOCK
DRIVER
ADC
CLOCK
DRIVER
T/H
CLOCK
DRIVER
DELAYED
RESET
DEMUX
CLOCK
GENERATOR
RSTIN+
RSTIN-
RESET
PIPELINE
RESET
INPUT DUAL LATCH
DEMUX
RESET OUTPUT
RSTOUT
2
DIVSELECT
DEMUXEN
Figure 1. Simplified Functional Diagram
has internal reset capability that allows multiple
MAX108s to be time-interleaved to achieve higher
effective sampling rates.
_______________Detailed Description
The MAX108 is an 8-bit, 1.5Gsps flash analog-to-digital
converter (ADC) with on-chip T/H amplifier and differ-
ential PECL-compatible outputs. The ADC (Figure 1)
employs a fully differential 8-bit quantizer and a unique
encoding scheme to limit metastable states, with no
error exceeding 1LSB max.
When clocked at 1.5Gsps, the MAX108 provides a typi-
cal ENOB of 7.5 bits at an analog input frequency of
750MHz. The analog input of the MAX108 is designed
for differential or single-ended use with a 250mꢀ full-
scale input range. In addition, this fast ADC features an
on-chip +2.5ꢀ precision bandgap reference. If desired,
an external reference can also be used.
An integrated 8:16 output demultiplexer simplifies inter-
facing to the part by reducing the output data rate to
one-half the sampling clock rate. This demultiplexer
12 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Principle of Operation
The MAX108’s flash or parallel architecture provides
OVERRANGE +
255
255
254
the fastest multibit conversion of all common integrated
ADC designs. The key to this high-speed flash archi-
tecture is the use of an innovative, high-performance
comparator design. The flash converter and down-
stream logic translate the comparator outputs into a
parallel 8-bit output code and pass this binary code on
to the optional 8:16 demultiplexer, where primary and
auxiliary ports output PECL-compatible data at up to
750Msps per port (depending on how the demultiplex-
er section is set on the MAX108).
129
128
127
126
3
2
1
0
The ideal transfer function appears in Figure 2.
0
On-Chip Track/Hold Amplifier
As with all ADCs, if the input waveform is changing
rapidly during conversion, ENOB and signal-to-noise
ratio (SNR) specifications will degrade. The MAX108’s
on-chip, wide-bandwidth (2.2GHz) T/H amplifier
reduces this effect and increases the ENOB perfor-
mance significantly, allowing precise capture of fast
analog data at high conversion rates.
ANALOG INPUT
Figure 2. Transfer Function
ALL INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
AMPLIFIER
INPUT
SAMPLING
BRIDGE
BUFFER
AMPLIFIER
The T/H amplifier buffers the input signal and allows a
full-scale signal input range of 250mꢀ. The T/H ampli-
fier’s differential 50Ω input termination simplifies inter-
facing to the MAX108 with controlled impedance lines.
Figure 3 shows a simplified diagram of the T/H amplifier
stage internal to the MAX108.
VIN+
VIN-
TO
COMPARATORS
50Ω
50Ω
50Ω
C
HOLD
GNDI
GNDI
Aperture width, delay, and jitter (or uncertainty) are
parameters that affect the dynamic performance of
high-speed converters. Aperture jitter, in particular,
directly influences SNR and limits the maximum slew
rate (dꢀ/dt) that can be digitized without contributing
significant errors. The MAX108’s innovative T/H amplifier
design limits aperture jitter typically to less than 0.5ps.
CLK+
CLK-
CLOCK
SPLITTER
TO
COMPARATORS
50Ω
CLKCOM
Figure 3. Internal Structure of the 2.2GHz T/H Amplifier
Aperture Width
Aperture width (t ) is the time the T/H circuit requires
AW
CLK
CLK
(Figure 4) to disconnect the hold capacitor from the
input circuit (for instance, to turn off the sampling
bridge and put the T/H unit in hold mode).
t
AW
ANALOG
INPUT
Aperture Jitter
t
AD
Aperture jitter (t ) is the sample-to-sample variation
AJ
t
AJ
(Figure 4) in the time between the samples.
SAMPLED
DATA (T/H)
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 4).
HOLD
TRACK
TRACK
T/H
APERTURE DELAY (t
)
AW
)
AD
APERTURE WIDTH (t
)
Internal Reference
The MAX108 features an on-chip +2.5ꢀ precision
bandgap reference that can be used by connecting
APERTURE JITTER (t
AJ
Figure 4. T/H Aperture Timing
______________________________________________________________________________________ 13
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
REFOUT to REFIN. This connects the reference output
to the positive input of the reference buffer. The buffer’s
negative input is internally connected to GNDR. GNDR
must be connected to GNDI on the user’s application
board. If required, REFOUT can source up to 2.5mA to
supply external devices.
V
O
CC
500Ω
500Ω
A_+/P_+
A_-/P_-
An adjustable external reference can be used to adjust
the ADC’s full-scale range. To use an external refer-
ence supply, connect a high-precision reference to the
REFIN pin and leave the REFOUT pin floating. In this
configuration, REFOUT ꢂust not be simultaneously
connected, to avoid conflicts between the two refer-
ences. REFIN has a typical input resistance of 5kΩ and
accepts input voltages of +2.5ꢀ 200mꢀ. For best per-
formance, Maxim recommends using the MAX108’s
internal reference.
DIFF.
PAIR
GNDD
1.8mA
GNDD
GNDD
Digital Outputs
The MAX108 provides data in offset binary format to
differential PECL outputs. A simplified circuit schematic
of the PECL output cell is shown in Figure 5. All PECL
Figure 5. Simplified PECL Output Structure
following sections on Demultiplexed DIV2 Mode, Non-
Demultiplexed DIV1 Mode, and Decimation DIV4
Mode) controlled by two TTL/CMOS-compatible inputs:
DEMUXEN and DIꢀSELECT.
outputs are powered from ꢀ O, which may be operat-
CC
ed from any voltage between +3.0ꢀ to ꢀ D for flexible
CC
interfacing with either +3.3ꢀ or +5ꢀ systems. The nomi-
nal ꢀ O supply voltage is +3.3ꢀ.
CC
DEMUXEN enables or disables operation of the internal
1:2 demultiplexer. A logic high on DEMUXEN activates
the internal demultiplexer, and a logic low deactivates
it. With the internal demultiplexer enabled, DIꢀSELECT
controls the selection of the operational mode. DIꢀSE-
LECT low selects demultiplexed DIꢀ2 mode, and DIꢀ-
SELECT high selects decimation DIꢀ4 mode (Table 2).
All PECL outputs on the MAX108 are open-emitter
types and must be terminated at the far end of each
transmission line with 50Ω to ꢀ O - 2ꢀ. Table 1 lists all
CC
MAX108 PECL outputs and their functions.
Demultiplexer Operation
The MAX108 features an internal demultiplexer that
provides for three different modes of operation (see the
Table 1. PECꢀ Output Functions
PECꢀ OUTPUT LIGNAꢀL
FUNCTIONAꢀ ꢁELCRIPTION
Primary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
P0+ to P7+, P0- to P7-
A0+ to A7+, A0- to A7-
Auxiliary-Port Differential Outputs from LSB to MSB. A “+” indicates the true outputs; a “-”
denotes the complementary outputs.
Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch
the output data from the primary to the auxiliary output ports. Data changes on the rising
edge of the DREADY clock.
DREADY+, DREADY-
OR+, OR-
Overrange True and Complementary Outputs
Reset Output True and Complementary Outputs
RSTOUT+, RSTOUT-
14 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Non-Demultiplexed DIV1 Mode
The MAX108 may be operated at up to 750Msps in
non-demultiplexed DIꢀ1 mode (Table 2). In this mode,
the internal demultiplexer is disabled and sampled
data is presented to the primary port only, with the
data repeated at the auxiliary port but delayed by one
clock cycle (Figure 6). Since the auxiliary output port
contains the same data stream as the primary output
port, the auxiliary port can be shut down to save
power by connecting AUXEN1 and AUXEN2 to digital
ground (GNDD). This powers down the internal bias
cells and causes both outputs (true and complemen-
tary) of the auxiliary port to pull up to a logic-high
level. To save additional power, the external 50Ω ter-
mination resistors connected to the PECL termination
power supply (ꢀ O - 2ꢀ) may be removed from all
CC
auxiliary output ports.
Demultiplexed DIV2 Mode
The MAX108 features an internally selectable DIꢀ2
mode (Table 2) that reduces the output data rate to
one-half of the sample clock rate. The demultiplexed
outputs are presented in dual 8-bit format with two con-
secutive samples appearing in the primary and auxil-
iary output ports on the rising edge of the data-ready
clock (Figure 7). The auxiliary data port contains the
previous sample, and the primary output contains the
most recent data sample. AUXEN1 and AUXEN2 must
be connected to ꢀ O to power up the auxiliary port
CC
PECL output drives.
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4 n+5 n+6 n+7 n+8
CLK-
CLK
n
n+1
n+2
n+3
n+9
n+10
n+11
n+12
n+13
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
n
n+1
n+2
n+2
n+3
n+3
n+4
n+4
n+5
DATA PORT
PRIMARY
DATA PORT
n+1
NOTE: THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA.
GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TO SAVE POWER.
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
CLK-
CLK
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
n-1
n
n+1
n+2
n+3
n+4
DATA PORT
PRIMARY
DATA PORT
NOTE: THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES.
BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 7. Demuxed DIV2-Mode Timing Diagram
______________________________________________________________________________________ 15
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Decimation DIV4 Mode
The MAX108 also offers a special decimated, demulti-
plexed output (Figure 8) that discards every other input
sample and outputs data at one-quarter the input sam-
pling rate for system debugging at slower output data
rates. With an input clock of 1.5GHz, the effective output
data rate will be reduced to 375MHz per output port in
the DIꢀ4 mode (Table 2). Since every other sample is
discarded, the effective sampling rate is 750Msps.
the OR bit will flag an overrange condition if either the
primary or auxiliary port contains an overranged sam-
ple (Table 2). In non-demultiplexed DIꢀ1 mode, the OR
port will flag an overrange condition only when the pri-
mary output port contains an overranged sample.
Applications Information
Single-Ended Analog Inputs
The MAX108 T/H amplifier is designed to work at full
speed for both single-ended and differential analog
inputs (Figure 9). Inputs ꢀIN+ and ꢀIN- feature on-chip,
laser-trimmed 50Ω termination resistors to provide
excellent voltage standing-wave ratio (ꢀSWR) perfor-
mance.
Overrange Operation
A single differential PECL overrange output bit (OR+,
OR-) is provided for both primary and auxiliary demulti-
plexed outputs. The operation of the overrange bit
depends on the status of the internal demultiplexer. In
demultiplexed DIꢀ2 mode and decimation DIꢀ4 mode,
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4 n+5 n+6 n+7 n+8
CLK-
CLK
n
n+1
n+2
n+3
n+9
n+10
n+11
n+12
n+13
CLK+
DREADY+
DREADY
DREADY-
AUXILIARY
n-2
n
n+2
DATA PORT
PRIMARY
DATA PORT
n+4
NOTE: THE LATENCY TO THE PRIMARY PORT REMAINS 7.5 CLOCK CYCLES, WHILE THE LATENCY OF THE AUXILIARY PORT INCREASES TO 9.5 CLOCK CYCLES.
THIS EFFECTIVELY DISCARDS EVERY OTHER SAMPLE AND REDUCES THE OUTPUT DATA RATE TO 1/4 THE SAMPLE CLOCK RATE.
Figure 8. Decimation DIV4-Mode Timing Diagram
Table 2. ꢁeꢂultiplexer Operation
ꢁEMUXEN
ꢁImLEꢀECT
ꢁEMUX MOꢁE
OmERRANGE BIT OPERATION
DIꢀ1
750Msps (max)
Flags overrange data appearing in primary
port only.
Low
X
DIꢀ2
750Msps/port
High
High
Low
Flags overrange data appearing in either
the primary or auxiliary port.
DIꢀ4
375Msps/port
High
X = Don’t care
16 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
ANALOG INPUTS ARE ESD PROTECTED
(NOT SHOWN IN THIS SIMPLIFIED DRAWING).
V
IN+
+2.8V
+250mV
500mV
P-P
FS ANALOG
VIN+
500mV
0V
INPUT RANGE
50Ω
V
IN-
-250mV
GNDI
t
V
= 250mV
IN
50Ω
VIN-
Figure 10a. Single-Ended Analog Input Signals
V
EE
Figure 9. Simplified Analog Input Structure (Single-Ended/
Differential)
V
IN+
V
+125mV
IN-
250mV
FS ANALOG
In a typical single-ended configuration, the analog
input signal (Figure 10a) enters the T/H amplifier stage
at the in-phase input (ꢀIN+), while the inverted phase
input (ꢀIN-) is reverse-terminated to GNDI with an
external 50Ω resistor. Single-ended operation allows for
an input amplitude of 250mꢀ. Table 3 shows a selec-
tion of input voltages and their corresponding output
codes for single-ended operation.
250mV
-250mV
0V
INPUT RANGE
-125mV
t
Figure 10b. Differential Analog Input Signals
Differential Analog Inputs
To obtain a full-scale digital output with differential input
drive (Figure 10b), 250mꢀp-p must be applied between
ꢀIN+ and ꢀIN- (ꢀIN+ = +125mꢀ, and ꢀIN- = -125mꢀ).
Midscale digital output codes (01111111 or 10000000)
occur when there is no voltage difference between
ꢀIN+ and ꢀIN-. For a zero-scale digital output code, the
in-phase (ꢀIN+) input must see -125mꢀ and the invert-
ed input (ꢀIN-) must see +125mꢀ. A differential input
drive is recommended for best performance. Table 4
represents a selection of differential input voltages and
their corresponding output codes.
Table 3. Ideal Input moltage and Output Code Results for Lingle-Ended Operation
mIN+
mIN-
0ꢀ
OmERRANGE BIT
OUTPUT COꢁE
11111111 (full scale)
11111111
+250mꢀ
1
0
+250mꢀ - 1LSB
0ꢀ
01111111
toggles
0ꢀ
0ꢀ
0
10000000
-250mꢀ + 1LSB
-250mꢀ
0ꢀ
0ꢀ
0
0
0000001
00000000 (zero scale)
______________________________________________________________________________________ 17
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 4. Ideal Input moltage and Output Code Results for ꢁifferential Operation
mIN+
mIN-
-125mꢀ
OmERRANGE BIT
OUTPUT COꢁE
11111111 (full scale)
11111111
+125mꢀ
1
0
+125mꢀ - 0.5LSB
-125mꢀ + 0.5LSB
01111111
toggles
0ꢀ
0ꢀ
0
10000000
-125mꢀ + 0.5LSB
-125mꢀ
+125mꢀ - 0.5LSB
+125mꢀ
0
0
00000001
00000000 (zero scale)
Offset Adjust
The MAX108 provides a control input (ꢀOSADJ) to com-
pensate for system offsets. The offset adjust input is a
self-biased voltage divider from the internal +2.5ꢀ preci-
sion reference. The nominal open-circuit voltage is one-
half the reference voltage. With an input resistance of
typically 25kΩ, this pin may be driven by an external
10kΩ potentiometer (Figure 11) connected between
REFOUT and GNDI to correct for offset errors. This con-
trol provides a typical 5.5LSB offset adjustment range.
REFOUT
MAX108
POT
10kΩ
VOSADJ
GNDI
Clock Operation
The MAX108 clock inputs are designed for either sin-
gle-ended or differential operation (Figure 12) with flexi-
ble input drive requirements. Each clock input is
terminated with an on-chip, laser-trimmed 50Ω resistor
to CLKCOM (clock-termination return). The CLKCOM
termination voltage can be connected anywhere
between ground and -2ꢀ for compatibility with standard
ECL drive levels.
Figure 11. Offset Adjust with External 10kΩ Potentiometer
CLK+
50Ω
50Ω
+0.8V
The clock inputs are internally buffered with a preampli-
fier to ensure proper operation of the data converter,
even with small-amplitude sine-wave sources. The
MAX108 was designed for single-ended, low-phase-
noise sine-wave clock signals with as little as 100mꢀ
amplitude (-10dBm). This eliminates the need for an
external ECL clock buffer and its added jitter.
CLKCOM
CLK-
GNDI
Single-Ended Clock Inputs (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase-noise sine-wave source into a single
clock input (Figure 13a, Table 5). For proper DC bal-
ance, the undriven clock input should be externally
50Ω reverse-terminated to GNDI.
CLOCK INPUTS ARE
ESD PROTECTED
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
The dynamic performance of the data converter is
essentially unaffected by clock-drive power levels from
-10dBm (100mꢀ clock signal amplitude) to +10dBm
(1ꢀ clock signal amplitude). The MAX108 dynamic per-
V
EE
Figure 12. Simplified Clock Input Structure (Single-Ended/
Differential)
18 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
formance specifications are determined by a single-
Single-Ended Clock Inputs (ECL Drive)
Configure the MAX108 for single-ended ECL clock
drive by connecting the clock inputs as shown in Figure
ended clock drive of +4dBm (500mꢀ clock signal
amplitude). To avoid saturation of the input amplifier
stage, limit the clock power level to a maximum of
+10dBm.
13c (Table 5). A well-bypassed ꢀ
supply (-1.3ꢀ) is
BB
essential to avoid coupling noise into the undriven
clock input, which would degrade dynamic perfor-
mance.
Differential Clock Inputs (Sine-Wave Drive)
The advantages of differential clock drive (Figure 13b,
Table 5) can be obtained by using an appropriate
balun or transformer to convert single-ended sine-wave
sources into differential drives. The precision on-chip,
laser-trimmed 50Ω clock-termination resistors ensure
excellent amplitude matching. See Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
Differential Clock Inputs (ECL Drive)
Drive the MAX108 from a standard differential (Figure
13d, Table 5) ECL clock source by setting the clock ter-
mination voltage at CLKCOM to -2ꢀ. Bypass the clock-
termination return (CLKCOM) as close to the ADC as
possible with a 0.01µF capacitor connected to GNDI.
CLK+
CLK+
+0.5V
CLK-
+0.5V
CLK- = 0V
-0.5V
-0.5V
t
t
NOTE: CLKCOM = 0V
NOTE: CLKCOM = 0V
Figure 13b. Differential Clock Input Signals
Figure 13a. Single-Ended Clock Input Signals
CLK+
CLK+
-0.8V
CLK-
-0.8V
CLK- = -1.3V
-1.8V
t
-1.8V
t
NOTE: CLKCOM = -2V
NOTE: CLKCOM = -2V
Figure 13d. Differential ECL Clock Drive
Figure 13c. Single-Ended ECL Clock Drive
______________________________________________________________________________________ 19
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 5. ꢁC-Coupled Clock ꢁrive Options
CꢀOCK ꢁRImE
Single-Ended Sine Wave
Differential Sine Wave
Single-Ended ECL
CꢀK+
CꢀK-
External 50Ω to GNDI
-10dBm to +4dBm
-1.3ꢀ
CꢀKCOM
GNDI
GNDI
-2ꢀ
REFERENCE
Figure 13a
-10dBm to +4dBm
-10dBm to +4dBm
ECL Drive
Figure 13b
Figure 13c
Differential ECL
ECL Drive
-2ꢀ
Figure 13d
ECL Drive
AC-Coupling Clock Inputs
The clock inputs CLK+ and CLK- can be driven with
PECL logic if the clock inputs are AC-coupled. Under
this condition, connect CLKCOM to GNDI. Single-
ended ECL/PECL/sine-wave drive is also possible if the
undriven clock input is reverse-terminated to GNDI
through a 50Ω resistor in series with a capacitor whose
value is identical to that used to couple the driven
input.
V
O
CC
50kΩ
50kΩ
RSTIN+
Demux Reset Operation
The MAX108 features an internal 1:2 demultiplexer that
reduces the data rate of the output digital data to one-
half the sample clock rate. Demux reset is necessary
when interleaving multiple MAX108s and/or synchroniz-
ing external demultiplexers. The simplified block dia-
gram of Figure 1 shows that the demux reset signal path
consists of four main circuit blocks. From input to out-
put, they are the reset input dual latch, the reset
pipeline, the demux clock generator, and the reset out-
put. The signals associated with the demux reset opera-
tion and the control of this section are listed in Table 6.
RSTIN-
20µA
RESET INPUTS ARE
ESD PROTECTED
GNDD
(NOT SHOWN IN THIS
SIMPLIFIED DRAWING).
Reset Input Dual Latch
The reset input dual-latch circuit block accepts differ-
ential PECL reset inputs referenced to the same ꢀ
O
CC
Figure 14. Simplified Reset Input Structure
power supply that powers the MAX108 PECL outputs.
For applications that do not require a synchronizing
reset, the reset inputs can be left open. In this case,
they will self-bias to a proper level with internal 50kΩ
resistors and 20µA current source. This combination
creates a -1ꢀ difference between RSTIN+ and RSTIN-
to disable the internal reset circuitry. When driven with
RSTIN+
50%
50%
RSTIN-
PECL logic levels terminated with 50Ω to (ꢀ O - 2ꢀ),
CC
the internal biasing network can easily be overdriven.
Figure 14 shows a simplified schematic of the reset
input structure.
t
t
HD
SU
CLK+
CLK-
To properly latch the reset input data, the setup time
50%
(t ) and the data-hold time (t ) must be met with
SU
HD
respect to the rising edge of the sample clock. The tim-
ing diagram of Figure 15 shows the timing relationship
of the reset input and sampling clock.
Figure 15. Reset Input Timing Definitions
20 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 6. ꢁeꢂux Operating and Reset Control Lignals
LIGNAꢀ NAME
TYPE
FUNCTION
CLK+, CLK-
Sampling clock inputs
Master ADC timing signal. The ADC samples on the rising edge of CLK+.
Data-Ready PECL Output. Output data changes on the rising edge of
DREADY+.
DREADY+, DREADY-
Differential PECL outputs
RSTIN+, RSTIN-
Differential PECL inputs
Differential PECL outputs
Demux reset input signals. Resets the internal demux when asserted.
Reset outputs for resetting additional external demux devices.
RSTOUT+, RSTOUT-
Reset Pipeline
The phase relationship between the sampling clock at
the CLK+/CLK- inputs and the data-ready clock at the
Dready+/Dready- outputs will be random at device
power-up. As with all divide-by-two circuits, two possi-
ble phase relationships exist between these clocks.
The difference between the phases is simply the inver-
sion of the DIꢀ2-Dready clock. The timing diagram in
Figure 16 shows this relationship.
The next section in the reset signal path is the reset
pipeline. This block adds clock cycles of latency to the
reset signal to match the latency of the converted ana-
log data through the ADC. In this way, when reset data
arrives at the RSTOUT+/RSTOUT- PECL output it will be
time-aligned with the analog data present in the prima-
ry and auxiliary ports at the time the reset input was
deasserted at RSTIN+/RSTIN-.
Reset all MAX108 devices to a known DREADY phase
after initial power-up for applications such as interleav-
ing, where two or more MAX108 devices are used to
achieve higher effective sampling rates. This synchro-
nization is necessary to set the order of output samples
between the devices. Resetting the converters accom-
plishes this synchronization. The reset signal is used to
force the internal counter in the demux clock-generator
block to a known phase state.
Demux Clock Generator
The demux clock generator creates the DIꢀ1, DIꢀ2, or
DIꢀ4 clocks required for the different modes of demux
and non-demultiplexed operation. The TTL/CMOS con-
trol inputs DEMUXEN and DIꢀSELECT control the
demuxed mode selection, as described in Table 2. The
timing diagrams in Figures 16 and 17 show the output
timing and data alignment in DIꢀ1, DIꢀ2, and DIꢀ4
modes, respectively.
t
t
PWL
PWH
CLK+
CLK+
50%
CLK-
CLK-
t
PD1
t
PD1
DREADY +
DREADY -
DREADY-
"PHASE 1"
50%
t
PD2
DREADY+
DREADY +
t
t
FDREADY
RDREADY
AUXILIARY PORT DATA
PRIMARY PORT DATA
80%
80%
"PHASE 2"
DREADY -
20%
20%
Figure 17. Output Timing for All Modes (DIV1, DIV2, DIV4)
Figure 16. CLK and DREADY Timing in Demuxed DIV2 Mode
Showing Two Possible DREADY Phases
______________________________________________________________________________________ 21
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Reset Output
Finally, the reset signal is presented in differential PECL
format to the last block of the reset signal path.
RSTOUT+/RSTOUT- output the time-aligned reset sig-
nal, used for resetting additional external demuxes in
applications that need further output data-rate reduc-
tion. Many demux devices require their reset signal to
be asserted for several clock cycles while they are
clocked. To accomplish this, the MAX108 DREADY
clock will continue to toggle while RSTOUT is asserted.
port. The reduced latency of RSTOUT serves to mark
the start of synchronized data in the primary and auxil-
iary ports. When the RSTOUT signal returns to a zero,
the DREADY clock phase is reset.
Since there are two possible phases of the DREADY
clock with respect to the input clock, there are two pos-
sible timing diagrams to consider. The first timing dia-
gram (Figure 18) shows the RSTOUT timing and data
alignment of the auxiliary and primary output ports
when the DREADY clock phase is already reset. For
this example, the RSTIN pulse is two clock cycles long.
Under this condition, the DREADY clock continues
uninterrupted, as does the data stream in the auxiliary
and primary ports.
When a single MAX108 device is used, no synchroniz-
ing reset is required because the order of the samples
in the output ports is unchanged, regardless of the
phase of the DREADY clock. In DIꢀ2 mode, the data in
the auxiliary port is delayed by 8.5 clock cycles, while
the data in the primary port is delayed by 7.5 clock
cycles. The older data is always in the auxiliary port,
regardless of the phase of the DREADY clock.
The second timing diagram (Figure 19) shows the
results when the DREADY phase is opposite from the
reset phase. In this case, the DREADY clock “swallows”
a clock cycle of the sample clock, resynchronizing to
the reset phase. Note that the data stream in the auxil-
iary and primary ports has reversed. Before reset was
The reset output signal, RSTOUT, is delayed by one
fewer clock cycles (6.5 clock cycles) than the primary
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4 n+5 n+6 n+7 n+8
CLK-
CLK
CLK+
n
n+1
n+2
n+3
n+9
n+10
n+11
n+12
n+13
t
SU
t
HD
RSTIN-
RESET
INPUT
RSTIN+
DREADY-
DREADY+
DREADY
AUXILIARY
DATA PORT
n-1
n
n+1
n+2
n+3
n+4
PRIMARY
DATA PORT
RSTOUT-
RSTOUT+
RESET OUT
DATA PORT
NOTE: THE LATENCY TO THE RESET OUTPUT IS 6.5 CLOCK CYCLES. THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND
THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. ALL DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 18. Reset Output Timing in Demuxed DIV2 Mode (DREADY Aligned)
22 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
ADC SAMPLE NUMBER
n+1 n+2
ADC SAMPLES ON THE RISING EDGE OF CLK+
n+4 n+5 n+6 n+7 n+8
CLK-
CLK
CLK+
n
n+3
n+9
n+10
n+11
n+12
n+13
t
SU
t
HD
RSTIN-
RESET
INPUT
RSTIN+
CLOCK PULSE “SWALLOWED”
DREADY+
DREADY-
DREADY
OUT-OF-SEQUENCE SAMPLE
n
AUXILIARY
DATA PORT
n-2
n-1
n+2
n+4
PRIMARY
DATA PORT
n+1
RSTOUT-
RSTOUT+
RESET OUT
DATA PORT
NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY “SWALLOWING” ONE INPUT CLOCK CYCLE.
THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.
Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)
asserted, the auxiliary port contained “even” samples
while the primary port contained “odd” samples. After
the RSTOUT is deasserted (which marks the start of the
DREADY clock’s reset phase), note that the order of the
samples in the ports has been reversed. The auxiliary
port also contains an out-of-sequence sample. This is a
consequence of the “swallowed” clock cycle that was
needed to resynchronize DREADY to the reset phase.
Also note that the older sample data is always in the
auxiliary port, regardless of the DREADY phase.
no reset output will occur at all. In effect, the RSTOUT
signal will be “swallowed” with the clock pulse. The
best method to ensure complete system reset is to
assert RSTIN for the appropriate number of DREADY
clock cycles required to complete reset of the external
demuxes.
Die Temperature Measurement
For applications that require monitoring of the die tem-
perature, it is possible to determine the die temperature
of the MAX108 under normal operating conditions by
These examples illustrate the combinations that result
with a reset input signal of two clock cycles. It is also
possible to reset the internal MAX108 demux success-
fully with a reset pulse of only one clock cycle, provid-
ed that the setup time and hold-time requirements are
met with respect to the sample clock. However, this is
not recommended when additional external demuxes
are used.
observing the currents I
and I
, at contacts
PTAT
CONST
ICONST and IPTAT. I
and I
are two 100µA
PTAT
CONST
(nominal) currents that are designed to be equal at
+27°C. These currents are derived from the MAX108’s
internal precision +2.5ꢀ bandgap reference. I
designed to be temperature independent, while I
is
is
CONST
PTAT
directly proportional to the absolute temperature. These
currents are derived from PNP current sources refer-
enced from ꢀ I and driven into two series diodes con-
CC
nected to GNDI. The contacts ICONST and IPTAT may
be left open because internal catch diodes prevent sat-
uration of the current sources. The simplest method of
determining the die temperature is to measure each
Note that many external demuxes require their reset
signals to be asserted while they are clocked, and may
require more than one clock cycle of reset. More impor-
tantly, if the phase of the DREADY clock is such that a
clock pulse will be “swallowed” to resynchronize, then
______________________________________________________________________________________ 23
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
current with an ammeter (which shuts off the internal
catch diodes) referenced to GNDI. The die temperature
in °C is then calculated by the expression:
To calibrate the circuit, first connect pins 2 and 3 on
JU1 to zero the input of the PTAT path. With the
MAX108 powered up, adjust potentiometer R3 until the
voltage at the ꢀ
output is -2.728ꢀ. Connecting
TEMP
pins 1 and 2 on JU1 restores normal operation to the
I
PTAT
T
= 300 ×
− 273
DIE
circuit after the calibration is complete. The voltage at
I
CONST
the ꢀ
node will then be proportional to the actual
TEMP
MAX108 die temperature according to the equation:
Another method of determining the die temperature
uses the operational amplifier circuit shown in Figure
20. The circuit produces a voltage that is proportional
to the die temperature. A possible application for this
signal is speed control for a cooling fan to maintain
constant MAX108 die temperature. The circuit operates
T
DIE
(°C) = 100 x ꢀ
TEMP
The overall accuracy of the die temperature measure-
ment using the operational-amplifier scaling circuitry is
limited mainly by the accuracy and matching of the
resistors in the circuit.
by converting the I
and I
currents to volt-
PTAT
CONST
ages ꢀ
and ꢀ
, with appropriate scaling to
CONST
PTAT
Thermal Management
Depending on the application environment for the
ESBGA-packaged MAX108, the customer may have to
apply an external heatsink to the package after board
assembly. Existing open-tooled heatsinks are available
from standard heatsink suppliers (see Heatsink
Manufacturers). The heatsinks are available with preap-
plied adhesive for easy package mounting.
account for their equal values at +27°C. This voltage
difference is then amplified by two amplifiers in an
instrumentation-amplifier configuration with adjustable
gain. The nominal value of the circuit gain is 4.5092ꢀ/ꢀ.
The gain of the instrumentation amplifier is given by the
expression:
ꢀ
TEMP
A
=
ꢀ
ꢀ
− ꢀ
PTAT
CONST
R1
R1
A
= 1 +
+ 2 ×
ꢀ
R2
R3
5kΩ
3.32kΩ
10-TURN
6.65kΩ
R2
15kΩ
R1
7.5kΩ
R2
15kΩ
I
PTAT
JU1
1
3
12.1kΩ
12.1kΩ
2
R1
7.5kΩ
V
1/4 MAX479
PTAT
1/4 MAX479
6.65kΩ
I
CONST
V
TEMP
V
CONST
1/4 MAX479
1/4 MAX479
6.05kΩ
Figure 20. Die Temperature Acquisition Circuit with the MAX479
24 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Table 7. Therꢂal Perforꢂance for
MAX108 With or Without Heatsink
THERMAL RESISTANCE vs. AIRFLOW
18
16
14
12
10
8
MAX108 θ (°C/W)
JA
AIRFꢀOW
(linear ft/ꢂin)
WITHOUT
WITH HEATLINK
HEATLINK
WITHOUT
HEATSINK
0
16.5
12.5
9.4
8.3
7.4
200
400
800
14.3
13
12.5
WITH HEATSINK
Thermal Performance
6
The MAX108 has been modeled to determine the ther-
mal resistance from junction to ambient. Table 7 lists
the ADC’s thermal performance parameters:
0
100 200 300 400 500 600 700 800
AIRFLOW (linear ft./min.)
Figure 21. MAX108 Thermal Performance
Ambient Temperature:
Heatsink Dimensions:
PC Board Size and Layout:
T = +70°C
A
25mm x 25mm x 10mm
Maxim strongly recommends using a multilayer printed
circuit board (PCB) with separate ground and power-
supply planes. Since the MAX108 has separate analog
and digital ground connections (GNDA, GNDI, GNDR,
and GNDD, respectively), the PCB should feature sep-
arate analog and digital ground sections connected at
only one point (star ground at the power supply). Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane. Keep digital signals far away from the sensitive
analog inputs, reference inputs, and clock inputs. High-
speed signals, including clocks, analog inputs, and
digital outputs, should be routed on 50Ω microstrip
lines, such as those employed on the MAX108 evalua-
tion kit.
4 in. x 4 in.
2 Signal Layers
2 Power Layers
Heatsink Manufacturers
Aavid Engineering and IERC provide open-tooled, low-
profile heatsinks, fitting the 25mm x 25mm ESBGA
package.
Aavid Engineering, Inc.
Phone: 714-556-2665
Heatsink Catalog No.: 335224B00032
Heatsink Dimensions: 25mm x 25mm x 10mm
International Electronic Research Corporation (IERC)
Phone: 818-842-7277
Heatsink Catalog No.: BDN09-3CB/A01
Heatsink Dimensions: 23.1mm x 23.1mm x 9mm
The MAX108 has separate analog and digital power-
supply inputs: ꢀ
(-5ꢀ analog and substrate supply)
EE
and ꢀ I (+5ꢀ) to power the T/H amplifier, clock distri-
CC
bution, bandgap reference, and reference amplifier;
ꢀ
ꢀ
A (+5ꢀ) to supply the ADC’s comparator array;
CC
CC
Bypassing/Layout/Power Supply
Grounding and power-supply decoupling strongly influ-
ence the MAX108’s performance. At a 1.5GHz clock
frequency and 8-bit resolution, unwanted digital
crosstalk may couple through the input, reference,
power-supply, and ground connections and adversely
influence the dynamic performance of the ADC.
Therefore, closely follow the grounding and power-sup-
ply decoupling guidelines (Figure 22).
O (+3ꢀ to ꢀ D) to establish power for all PECL-
CC
based circuit sections; and ꢀ D (+5ꢀ) to supply all
CC
logic circuits of the data converter.
The MAX108 ꢀ
open while the part is being powered up. To avoid this
condition, add a high-speed Schottky diode (such as a
Motorola 1N5817) between ꢀ and GNDI. This diode
EE
prevents the device substrate from forward biasing,
which could cause latchup.
supply contacts ꢂust not be left
EE
______________________________________________________________________________________ 25
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
All supplies should be decoupled with large tantalum or
electrolytic capacitors at the point they enter the PCB.
For best performance, bypass all power supplies to the
appropriate ground with a 10µF tantalum capacitor to
filter power-supply noise, in parallel with a 0.1µF
capacitor and a high-quality 47pF ceramic chip capaci-
tor located very close to the MAX108 device to filter
very high-frequency noise.
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX108 are mea-
sured using the best-straight-line fit method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Static Parameter Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
V
O
CC
NOTE:
10µF
10nF
10nF
47pF
47pF
47pF
47pF
LOCATE ALL 47pF CAPACITORS AS CLOSE
AS POSSIBLE TO THE MAX108 DEVICE.
GNDD
V
CC
I
10µF
10nF
10nF
47pF
47pF
47pF
47pF
GNDI
V
EE
V
A
CC
10µF
1N5817
10nF
10nF
47pF
47pF
47pF
47pF
GNDI
10µF
10nF
10nF
47pF
47pF
GNDA
V
V
V
V
V
A = +4.75V TO +5.25V
D = +4.75V TO +5.25V
I = +4.75V TO +5.25V
CC
CC
CC
CC
EE
V
D
CC
O = +3.0V TO V
D
CC
= -4.75V TO -5.25V
10µF
10nF
10nF
47pF
47pF
47pF
47pF
GNDD
Figure 22. MAX108 Bypassing and Grounding
26 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Bit Error Rates
Errors resulting from metastable states may occur when
the analog input voltage (at the time the sample is
taken) falls close to the decision point of any one of the
input comparators. Here, the magnitude of the error
depends on the location of the comparator in the com-
parator network. If it is the comparator for the MSB, the
error will reach full scale. The MAX108’s unique encod-
ing scheme solves this problem by limiting the magni-
tude of these errors to 1LSB.
Effective Number of Bits
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is calculated from a curve fit referenced to the theoreti-
cal full-scale range.
Signal-to-Noise Plus Distortion
Signal-to-Noise plus distortion (SINAD) is calculated
from the ENOB as follows:
SINAD = (6.02 x ENOB) + 1.76
Dynamic Parameter Definitions
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first four harmonics of the input signal to the
fundamental itself. This is expressed as:
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
2
2
2
2
THD = 20 × log
ꢀ
+ ꢀ + ꢀ + ꢀ
/ ꢀ
1
2
3
4
5
SNR
= (6.02 x N + 1.76)dB
(MAX)
where ꢀ is the fundamental amplitude, and ꢀ through
5
harmonics.
1
2
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is calculated by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
ꢀ
are the amplitudes of the 2nd- through 5th-order
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio,
expressed in decibels, of the RMS amplitude of the fun-
damental (maximum signal component) to the RMS
value of the next largest spurious component, excluding
DC offset.
Intermodulation Distortion
The two-tone intermodulation distortion (IMD) is the
ratio, expressed in decibels, of either input tone to the
worst 3rd-order (or higher) intermodulation products.
The input tone levels are at -7dB full scale.
Chip Information
TRANSISTOR COUNT: 20,486
SUBSTRATE CONNECTED TO ꢀ
EE
______________________________________________________________________________________ 27
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Typical Operating Circuit
Z = 50Ω
0
50Ω
ALL PECL OUTPUTS
MUST BE TERMINATED
LIKE THIS.
+5V ANALOG
-5V ANALOG +5V DIGITAL
+3.3V DIGITAL
V
O - 2V
CC
V
V
A
V
I
V D AUXEN1 V O AUXEN2
CC CC
EE
CC
CC
DIVSELECT
2
2
OR+/OR-
DEMUXEN
VOSADJ
+5V DIGITAL
P7+/P7-
2
2
2
2
2
2
2
2
2
P6+/P6-
P5+/P5-
2
2
2
DIFFERENTIAL
ANALOG
VIN+
VIN-
Z = 50Ω
0
PRIMARY
PECL
P4+/P4-
P3+/P3-
INPUT
Z = 50Ω
0
500mVp-p FS
OUTPUTS
P2+/P2-
P1+/P1-
MAX108
SAMPLE
CLOCK
1.5GHz
+4dBm
CLK+
CLK-
Z = 50Ω
0
P0+/P0-
A7+/A7-
2
2
2
2
2
50Ω
A6+/A6-
A5+/A5-
GNDI
GNDI
CLKCOM
AUXILARY
PECL
OUTPUTS
A4+/A4-
A3+/A3-
A2+/A2-
A1+/A1-
RSTIN+
RSTIN-
A0+/A0-
DREADY+/DREADY-
RSTOUT+/RSTOUT-
GNDA GNDR GNDI GNDD REFOUT REFIN
28 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
192-Contact ESBGA PCB Land Pattern
TOP VIEW
MAX108 192 Ball ESBGA
Printed Circuit Board (PCB) Land Pattern
MAX108
+5V Track/Hold Analog VCCI
+5V Comparator Analog VCCA
+5V Logic Digital VCCD
-5V Track/Hold Analog VEE
+3.3V PECL Supply VCCO
T/H Ground GNDI
Comparator Ground GNDA
Logic Ground GNDD
______________________________________________________________________________________ 29
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
30 ______________________________________________________________________________________
±±5, 1.±Gsps, 8-Bit ADC with
On-Chip 2.2GHz Track/Hold Amplifier
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 31
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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