MAX1101 [MAXIM]
Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA; 单芯片， 8位CCD数字化仪带夹具和6位PGA
| 型号： | MAX1101 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Chip, 8-Bit CCD Digitizer with Clamp and 6-Bit PGA |
| 文件： | 总12页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1166; Rev 0; 12/96
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX1101 is a highly integrated IC designed pri-
marily for digitizing the output of a linear CCD array. It
provides the components required for all necessary
analog functions, including clamp circuitry for black-
level correction or correlated double sampling (CDS), a
three-input multiplexer (mux), and an 8-bit analog-to-
digital converter (ADC).
♦ 1.0 Million Pixels/sec Conversion Rate
♦ Built-In Clamp Circuitry for Black-Level
Correction or Correlated Double Sampling
♦ 64-Step PGA, Programmable from Gain = -2 to -10
♦ Auxiliary Mux Inputs for Added Versatility
♦ Compatible with a Large Range of CCDs
♦ 8-Bit ADC Included
The MAX1101 operates with a sample rate up to 1MHz
and with a wide range of linear CCDs. The logic inter-
face is serial, and a single input sets the bidirectional
data line as either data in or data out, thus minimizing
the I/O pins required for communication.
♦ Space-Saving, 24-Pin SO Package
Packaged in a 24-pin SO, the MAX1101 is available in
the commercial (0°C to +70°C) temperature range.
________________________Ap p lic a t io n s
______________Ord e rin g In fo rm a t io n
Scanners
PART
TEMP. RANGE
PIN-PACKAGE
MAX1101CWG
0°C to +70°C
24 Wide SO
Fax Machines
Digital Copiers
CCD Imaging
Pin Configuration appears on last page.
___________________________________________________Typ ic a l Op e ra t in g Circ u it
1
24
GND
GND
C
EXT
0.047µF
0.1µF
+5V DC (SUPPLY)
23
22
2
3
MAX1101
CCDIN
GND
V
DD
CLAMP
CCD
ARRAY
4
5
21
20
AIN1
GND
VIDSAMP
LOAD
µP/µC/
STATE LOGIC
6
7
19
18
17
DATA
SCLK
MODE
GND
AIN2
GND
16
15
14
V
DD
11
12
REFGND
REF-
REFBIAS
REF+
+5V DC (REFERENCE)
0.1µF
0.1µF
13
1
2
AUXILIARY
ANALOG INPUTS
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
ABSOLUTE MAXIMUM RATINGS
V
to GND............................................................-0.3V to +12V
Operating Temperature Range ...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
All Pins to GND...........................................-0.3V to (V + 0.3V)
Current into Every Pin (except V ).................................±20mA
DD
DD
Current into V ...............................................................±50mA
DD
Continuous Power Dissipation (T = +70°C)
A
SO (derate 11.76mW/°C above +70°C)......................941mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX01
ELECTRICAL CHARACTERISTICS
(V
= V
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C
= 47nF, T = T
to T
,
DD
REFBIAS
EXT
A
MIN
MAX
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
ANALOG-TO-DIGITAL CONVERTER
Resolution
N
DNL
INL
8
Bits
Differential Nonlinearity
Integral Nonlinearity
No-missing-codes guaranteed
Best straight-line fit
±0.5
±1
±1
LSB
LSB
±1.5
±2.5
Total Unadjusted Error
Zero-Scale Drift
TUE
LSB
TCVOS
TCFS
125
0.016
1.2
%µV/°C
%FS/°C
MHz
kHz
Full-Scale Drift
Maximum Sample Rate
Minimum Sample Rate
Input Full-Power Bandwidth
Aperture Delay
f
s
0.67
1
(Note 1)
V
IN
= 2.5Vp-p
1
MHz
ns
t
10
AP
ANALOG INPUT—CCD INTERFACE
G
G
= -2
1.25
0.25
-2
PGA
PGA
Maximum Peak CCD
Differential Signal Range
V
(V
=
- V
WHITE
V
V
WHITE
) / G
REF+
REF- PGA
= -10
Minimum PGA Gain Setting
Maximum PGA Gain Setting
Gain Adjust Resolution
Gain Adjust Step Size
PGA Gain Error
-1.9
-2.1
V/V
V/V
-9.375 -9.875 -10.375
64
0.125
±5
Steps
V/V
% Gain
Ω
Black Sample Switch On-Resistance
Input Leakage (Note 2)
R
60
1
150
50
ON(BSS)
I
Including black sample switch off-leakage
= V (Figure 4)
nA
L(CCDIN)
CCD Interface Offset Voltage
V
V
VIDEO
0
4
8
LSB
OS(CCD)
RESET
ANALOG INPUT—AUXILIARY INPUTS
Input Voltage Range
Input Capacitance (Note 1)
On-Resistance
V
V
REF-
V
V
pF
Ω
IN
REF+
C
Channel on
Channel off
45
IN(ON)
C
10
IN(OFF)
R
ON
120
2
_______________________________________________________________________________________
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= +4.75V to +5.25V, REFGND = 0V, REF- bypassed to REFGND with 0.1µF, C
= 47nF, T = T
to T
,
DD
REFBIAS
EXT
A
MIN
MAX
unless otherwise noted.)
PARAMETER
REFERENCE VOLTAGE INPUT
Positive Reference Voltage
Negative Reference Voltage
POWER SUPPLIES
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
V
REF+
Internally generated, V
REFBIAS
Internally generated, V
REFBIAS
= 5V
= 5V
2.94
0.49
3.00
0.50
3.06
0.51
V
V
V
REF-
Positive Supply-Voltage Range
PSRR, PGA and ADC
V
4.75
48
5
5.25
40
V
DD
PSRR
4.75V ≤ V ≤ 5.25V
60
20
dB
mA
DD
Supply Current
I
DD
DIGITAL INPUTS/OUTPUTS
Digital Input Voltage High
Digital Input Voltage Low
Digital Input Leakage Current
Digital Output Voltage High
Digital Output Voltage Low
Digital Output Leakage Current
V
3.5
-10
V
V
IH
V
IL
1.5
10
I
IL
µA
V
V
OH
I
= 4mA
V
- 0.5
SOURCE
DD
V
OL
I
= 4mA
0.5
10
V
SINK
I
OL
Output in high-impedance mode
-10
µA
DIGITAL TIMING SPECIFICATIONS (t , t ≤ 10ns, C ≤ 50pF, unless otherwise noted)
f
r
L
SCLK Frequency
f
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK
SCLK Pulse Width
t
50
500
50
SPW
VIDSAMP Pulse Width
VIDSAMP to CLAMP Separation
LOAD Pulse Width
t
VS
VB
LD
t
t
50
VIDSAMP Fall to SCLK Rise Time
VIDSAMP Fall to DATA
VIDSAMP to Reset Separation
Reset to CLAMP Separation
SCLK Rise to DATA
t
MODE = 1
MODE = 1
(Note 2)
50
VLS
VLD
t
60
60
t
50
50
VR
RB
SD
t
t
(Note 2)
DATA Set-Up Time
t
20
20
50
50
50
300
20
20
DSU
DATA Hold Time
t
DH
LOAD Fall to SCLK Rise Time
SCLK Rise to LOAD Rise Time
MODE Setup Time
t
MODE = 0
LS
SL
t
MODE = 0
t
Same as bus-relinquish time
MSU
CLAMP Pulse Width
t
BS
BC
CLAMP Fall to Video Update
Digital Quiet Time (Note 3)
t
(Note 1)
t
± around VIDSAMP falling edge
Q
Note 1: Due to leakage in the PGA and ADC, operation at sample rates below 1ksps is not recommended, as
performance may degrade, particularly at high temperatures.
Note 2: Production test equipment settling time prohibits leakage measurements below 1nA.
Lab equipment has shown the MAX1101 switch input leakage below 1pA at T = +25°C, and below 50pA at T = +70°C.
A
A
Note 3: Not a test parameter. Recommended for optimal performance.
_______________________________________________________________________________________
3
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1, 3, 5, 7,
10, 16, 24
GND
Ground
2
CCDIN
AIN1
CCD Input. Connect CCD through a series 0.047µF capacitor (C
Auxiliary Analog Input Channel 1
).
EXT
4
6
AIN2
Auxiliary Analog Input Channel 2
MAX01
8, 9, 10
11
I.C.
Internally Connected. Do not connect to this pin.
Reference Ground. Ground reference for all analog signals.
REFGND
Lower Limit of Reference Span. Sets the zero-code voltage. Range is GND ≤ REF- ≤ REF+.
Nominally 0.5V.
12
13
REF-
REF+
Upper Limit of Reference Span. Sets the full-scale input. Voltage range is REF- ≤ REF+ ≤ V
.
DD
Nominally 3.0V.
14
REFBIAS
Reference Power Supply. Connect to external +5.0V to set V
to +3.0V and V
to +0.5V.
REF+
REF-
Power Supply, +5V. Bypass to ground very close to the device and connect the two pins together,
close to the MAX1101.
15, 23
17
V
DD
Control Input. Set high, DATA is an output of the ADC. Set low, DATA enables programming of the
PGA and mux.
MODE
18
19
20
21
22
SCLK
DATA
Serial Clock Input
Data Input or Output, as controlled by MODE
LOAD
Control Input. Loads serial shift-register data to PGA and multiplexer registers when MODE = 0.
Control Input. Samples the video level and initiates the ADC conversion.
Control Input. Samples black level. Can be used for correlated double sampling.
VIDSAMP
CLAMP
_______________De t a ile d De s c rip t io n
REFBIAS
Ove rvie w
AIN2
AIN1
2
1
The MAX1101 directly processes the pixel stream from
a monochrome CCD, and removes black level, offset,
REF+
MUX
ADC
a nd nois e e rrors throug h a n inte rna l c la mp c irc uit,
which can be used as a correlated double sampler
(CDS). It uses a 6-bit, programmable-gain amplifier
(PGA) to adjust gain. A three-input multiplexer (mux)
selects either the PGA output or two unassigned inputs
(AIN1, AIN2). The processed analog signal is digitized
by an 8-bit, half-flash analog-to-digital converter (ADC),
and output serially through the DATA pin.
8
CLAMP
CIRCUIT
PGA
GAIN
REF-
CCDIN
CLAMP
0
2
6
REFGND
VIDSAMP
REGISTER
8
Digital data is input and output through the bidirectional
serial pin (DATA) synchronously with the external serial
clock (SCLK). When MODE = 0, the mux channels and
the PGA gain can be programmed via DATA. With MODE
= 1 (high), ADC serial data is output through this pin.
REGISTER
6
REGISTER
2
DATA
SCLK
LOAD
MODE
SERIAL
PORT
Figure 1. MAX1101 Functional Diagram
_______________________________________________________________________________________
4
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
REF+
REF+
REF+
REF-
REF-
S1
S2
CF
C
F
CLAMP
S1
C
I
S1P
C
I
S2
FROM
CCD
V
= V - ±V
0S
OUT REF
TO
ADC
C
EXT
0.047µF
REF-
REF-
Figure 3a. PGA Connection with VIDSAMP = Low
VIDSAMP
C
F
S1*
OFF
ON
C
I
V
+
REF
- V
(FROM DC
*
S2
OFF
VIDEO
ON
RESTORE)
S1P*
OFF
ON
REF-
* INTERNALLY GENERATED SIGNALS
Figure 3b. PGA Connection with VIDSAMP = High
Figure 2. PGA Functional Diagram
VIDSAMP controls the sampling of the video signal
and offset nulling of the PGA. To null out the offset,
VIDSAMP causes switches S1 and S1P to close, plac-
ing the amplifier in a unity-gain configuration, as shown
in Figure 3a. This configuration causes the amplifier’s
offset voltage to be stored on CF. In the next portion of
the cycle, when VIDSAMP returns low, the S1 switches
are opened and S2 is closed (Figure 3b). This is the
standard inverting op-amp configuration. The only dif-
ference is that capacitors are used to set the gain, and
the amplifier’s offset voltage has been stored on these
capacitors and is thus canceled. The amplifier’s output
P ro g ra m m a b le -Ga in Am p lifie r
The PGA amplifies the differential video signal from the
CCD (at CCDIN). Gain is settable with the 6-bit con-
trol word from -2 to -10 in 64 steps, in increments of
-0.125. The PGA also provides for periodic DC restora-
tion of the capacitively coupled input.
As shown in Figure 2, the switched-capacitor amplifier’s
gain is set by the ratio C /C . The input is sampled on
I
F
the C capacitors, which is a set of equal capacitors.
I
The 6-bit gain control word determines the number
of c a p a c itors us e d . Thus the PGA g a in is s e t from
-2 to -10.
is [C /C ] x V
+ V . The CDS function is shown
F
I
VIDEO
REF-
A voltage equal to V
is applied to the PGA’s nonin-
REF-
in Figure 4.
verting input. This offsets the PGA output to be within
the range of the ADC (V to V ).
ADC
REF+
REF-
The ADC uses a recycling half-flash conversion tech-
nique in which a 4-bit flash ADC section achieves an
8-bit result in two steps (Figure 5). Using 15 compara-
tors , the fla s h ADC c omp a re s the unknown inp ut
voltage to the reference ladder (using REF+ and REF-)
and provides the upper four data bits.
Cla m p Circ u it
As shown in Figure 2, the CCD output is connected to
the MAX1101 inp ut (CCDIN) throug h a n e xte rna l
c a p a c itor, whic h re move s the p ote ntia lly la rg e DC
c ommon-mod e volta g e s from the inp ut s ig na l.
Whenever CLAMP is high, the CLAMP switch is closed
An internal digital-to-analog converter (DAC) uses the
four most significant bits (MSBs) to generate the analog
result from the first flash conversion and a residue volt-
age that is the difference between the unknown voltage
a nd C
is c ha rg e d to V
. It c a n b e a c tua te d
EXT
REF+
either once per pixel (sampling reset level) or less fre-
quently (such as for restoring optical black level once
per line), as required by the application.
_______________________________________________________________________________________
5
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
CCD OUTPUT
LEVELS VARY
DUE TO CCD
RESET NOISE
CCD OUTPUT
CLAMP PULSE
(CLAMP)
MAX01
VOLTAGE OF
RESET SECTION
IS SET TO V
BY CLAMP
REF+
V
VIDEO
CLAMP OUTPUT
SAMPLE-AND-HOLD PULSE
(VIDSAMP)
Figure 4. Correlated Double Sampler (CDS)
and the DAC output. The residue is then compared
again with the flash comparators to obtain the lower
four data bits.
REF+
REF-
Single-shot timers control the timing of the two conver-
s ion s te p s . Onc e b oth MSBs a nd LSBs ha ve b e e n
determined, the comparators return to input-acquisi-
tion/auto-zero mode.
4-BIT
FLASH
ADC
FROM
MUX
REF+ a n d REF-
The REF+ and REF- pins set the ADC’s full-scale range.
The optimum input range is +0.5V to +3.0V. Figure 6
shows a matched resistive ladder that generates the
reference voltages. Four pins are available: REF+,
REF-, REFBIAS, and REFGND. If 5.00V is applied to
REFBIAS while REFGND is grounded, then 3.00V and
0.50V are generated at REF+ and REF-, respectively.
OUTPUT
REGISTER
DATA
OUT
4-BIT
DAC
VREF+
16
4-BIT
FLASH
ADC
(4LSB)
For increased accuracy or power-supply immunity,
REF+ can be connected to an external +3.00V refer-
ence. If this is done, the accuracy must be better than
±5%. REFBIAS should be left open in this case.
Figure 5. ADC Functional Diagram
Mu lt ip le x e r
The mux selects either the output of the PGA or one of
two othe r inputs to the ADC. The mux switc hing is
break-before-make to prevent transient shorts between
channels. The first two bits of the input control byte
select the mux input channel (Table 1).
S e ria l-In t e rfa c e Lo g ic
The serial interface inputs and outputs data in 8-bit
word s . The inte rfa c e is c ontrolle d b y four s ig na ls :
MODE, LOAD, DATA, and SCLK.
6
_______________________________________________________________________________________
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
MODE
MODE controls the direction of data transfer. When
MODE = 0, data is being shifted into the MAX1101 at
the DATA pin either for the mux or the PGA. When
MODE = 1, the ADC outp ut is s hifte d out from the
MAX1101 at the DATA pin. Data is shifted in and out of
the MAX1101 at the rising edge of SCLK.
Data Output
Data is clocked in and out of the device with the rising
edge of SCLK. The first bit (the MSB, D7) immediately
follows the falling edge of VIDSAMP (Figures 7 and 8).
The first rising edge of SCLK clocks out the next bit,
D6. Data is loaded into the shift register at the falling
edge of VIDSAMP. Following the output of D0, DATA
output is unspecified for additional SCLK pulses.
LOAD
LOAD is normally low and used only when MODE = 0.
Once all eight bits have been clocked in, bring LOAD
high to update the MAX1101 registers.
Eight-bit-wide storage and output registers hold data
from the ADC and delay the data output. The timing dia-
g ra m in Fig ure 9 s hows the d a ta la te nc y of two
VIDSAMP cycles. New data is available after the second
falling edge of VIDSAMP.
DATA
DATA is a bidirectional I/O pin. MODE controls the
direction of data transfer. When MODE = 1, DATA is
configured as an output from the shift register. Data is
clocked out of the shift register by SCLK’s rising edge.
When MODE = 0, DATA is configured as an input to the
shift register, shifted in by the rising edge of SCLK. In
this mode, the DATA output driver is disabled, putting
DATA into a high-impedance state and allowing it to be
driven externally.
Data Input
During data input, the first two bits (A0, A1) are the
address, selecting either the mux or PGA. The next six
bits set the input channel or PGA gain (Table 1).
CLAMP and VIDSAMP
The last two digital inputs are VIDSAMP and CLAMP.
VIDSAMP controls the overall cycle timing, with one
VIDSAMP cycle corresponding to one CCD pixel. The
input is sampled into the ADC by the falling edge of
VIDSAMP. CLAMP controls the black sample switch,
REFBIAS
which sets a reference DC voltage level (V
capacitively coupled CCDIN input. The sample switch
is on when CLAMP is high.
) at the
REF+
800Ω
REF+
1kΩ
Control and Interface Logic
The control and interface logic consists of a serial I/O
port, which shifts data into and out of the MAX1101, and
two registers for storing the mux channel and the PGA
gain data.
REF-
200Ω
REFGND
Figure 6. Reference Resistor String
Table 1. Control-Byte Format
D5
MSB
D0
LSB
FUNCTION
A0
A1
D4
D3
D2
D1
Address Analog Input Mux
0
0
1
0
0
0
0
0
0
0
0
1
X
0
0
0
1
1
1
1
—
—
X
0
—
—
X
0
—
—
X
0
—
—
X
X
X
X
0
—
—
X
X
X
X
0
—
—
X
X
X
X
0
Address CCD PGA
No Operation
Select CCD input
Select AIN1
0
1
0
Select AIN2
1
0
0
Set PGA Gain to -2
Set PGA Gain to -2.125
Set PGA Gain to -9.750
Set PGA Gain to -9.875
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
X = Don’t Care
_______________________________________________________________________________________
7
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MODE
t
t
t
SPW
MSU
SPW
SCLK
LOAD
t
LS
t
SL
t
LD
t
t
DH
DSU
MAX01
DATA
A0
A1
D5
D4
D3
D2
D1
D0
Figure 7. MODE = 0 Timing
RESET FEEDTHROUGH
PRECHARGE LEVEL
CCD OUT
t
VR
VIDEO LEVEL
t
t
VS
CPW
VIDSAMP
CLAMP
t
BC
t
RB
t
Q
t
VB
t
VB
t
BS
t
VLS
SCLK
DATA
t
t
SD
VLD
D7
D6
D5
D4
D3
D2
D1
D0
DATA OUTPUT AFTER D0 IS UNSPECIFIED
Figure 8. MODE = 1 Timing
LOAD controls the loading of data into the internal stor-
age registers during data input. Once all eight input bits
have been clocked into the shift register, a rising edge on
LOAD clocks the data into the appropriate storage regis-
ter (mux or PGA), decoded from the first two input bits.
Input Buffers and Output Drivers
The DATA driver is capable of driving 50pF load capaci-
tance while meeting the output delay specifications
given in the Electrical Characteristics. The gates of the P-
channel and N-channel drivers are driven separately. If
MODE is low, both drivers are off and the output is high
impedance.
The logic is divided into four blocks: the two storage reg-
isters, the serial I/O port, and a power-on reset genera-
tor. The registers are reset by the power-on reset to
place them in a predictable state (input channel = CCD,
PGA gain = -2) on power-up. The power-on reset typical-
ly has a 2.1µs pulse width.
The VIDSAMP, CLAMP, SCLK, and LOAD inputs are
buffered and have hysteresis to reject noise with slow-
slewing signal edges.
__________Ap p lic a t io n s In fo rm a t io n
The serial I/O port consists of a shift register, an 8-bit
storage register, decode logic to clock input data into
the appropriate storage register, and an output driver.
The 8-bit storage register takes input data from the
ADC.
MAX1 1 0 1 Tim in g
Figure 7 shows the timing configuration when MODE =
0 and data is loaded into the MAX1101. Figure 8 shows
timing when MODE = 1 and the CCD signal is digitized.
Figure 9 is an expansion of Figure 8, illustrating the
two-VIDSAMP-cycle data latency. Figure 10 shows the
relationship of CLAMP to VIDSAMP when MODE = 1.
8
_______________________________________________________________________________________
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
CCD (OUT)
VIDEO N
VIDEO N+1
VIDEO N+2
VIDEO N+3
VIDSAMP
CLAMP
PGA
AUTO-ZERO
SAMPLE N
SAMPLE N
AUTO-ZERO
SAMPLE N+1
SAMPLE N+1
AUTO-ZERO
SAMPLE N+2
SAMPLE N+2
AUTO-ZERO
SAMPLE N+3
SAMPLE N+3
MSB N-1
LSB N-1
MSB N
LSB N
MSB N+1
LSB N+1
MSB N+2
LSB N+2
ADC
DATA N-2
DATA N-3
DATA N-1
DATA N-2
DATA N
DATA N+1
DATA N
ADC REG
DATA N-1
SHIFT REG
SCLK
DATA
D7 D6 D5 D4 D3 D2 D1 D0
DATA N-3
D7 D6 D5 D4 D3 D2 D1 D0
DATA N-2
D7 D6 D5 D4 D3 D2 D1 D0
DATA N-1
D7 D6 D5 D4 D3 D2 D1 D0
DATA N
D7
Figure 9. MODE = 1 Timing Showing Data Latency
BLACK CELL
BLACK CELL
CCD (OUT)
VIDEO N
VIDSAMP
CLAMP
(ONCE PER LINE)
CLAMP
(ONCE PER CELL)
Figure 10. MODE = 1 Timing Showing Relationship of CLAMP to VIDSAMP
Analog Inputs (AIN_)
The transfer function for auxiliary inputs is shown in
Figure 11. Again, coding is binary and full-scale range
. An offset has not been added to
these channels; however, code transitions occur at the
1/2LSB point, as shown in Figure 12.
In p u t /Ou t p u t Tra n s fe r Fu n c t io n
CCD Input
Figure 11 shows the MAX1101 transfer function for
CCDIN. Coding is binary, with a -4LSB offset added to
ensure that offsets within the MAX1101, which can be
positive or negative, do not cause the ADC to be out of
range. Full-scale input range at CCDIN is:
is V
to V
REF-
REF+
Im p le m e n t in g Co rre la t e d
Do u b le S a m p lin g (CDS ) o r
(V
REF+
- V
) / G
REF-
PGA
Bla c k -Le ve l Co m p e n s a t io n
whe re G
amplifier.
is the g a in of the p rogra mma ble ga in
PGA
The CLAMP circuit in the MAX1101 can be used to either
accomplish CDS or to compensate for the CCD black
level. To accomplish CDS, CLAMP is activated once per
_______________________________________________________________________________________
9
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
pixel during the CCD output waveform’s reset phase. To
compensate for the CCD black level, CLAMP is activated
during the black-pixel portion of the linear array, as
DIGITAL
OUTPUT
11. . .111
shown in Figure 10. Each of these modes requires a dif-
11. . .110
ferent value of C
tion.
, as described in the following sec-
EXT
11. . .101
Choosing C
for CDS
EXT
100. . .000
In CDS applications, C
= 4nF. This value is the best
EXT
MAX01
compromise to minimize errors due to the CLAMP switch
resistance/C time constant and switch charge injec-
00. . .111
00. . .110
EXT
tion. The following equation represents the error due to
incomplete charging of C during integration time:
EXT
00. . .101
00. . .100
00. . .011
ε = ∆V
x e-t/RC
RESET
where ∆V
= the maximum change in reset level
RESET
00. . .010
00. . .001
from one pixel to the next, t = CLAMP pulse width, and
R = CLAMP switch resistance (150Ωmax). At a sample
ra te of 670kHz, with t = 750ns e c , a 4nF c a p a c itor
removes at least 70% of the change in reset voltage
level. Typically, R = 60Ω, which corresponds to a 96%
cancellation of the change in reset level.
V
VIDEO
00. . .000
-1
256
1
256
3
256
124
256
249
256
251
256
-3
256
V
FS
V
FS
V
FS
V
FS
V
FS
V
FS
V
FS
-4
256
-2
256
2
256
250
V
FS
V
FS
V
FS
V
FS
256
The offset due to switch charge injection is represented
by 13pC / 4nF = 3mV. Note that this error will behave
like any DC offset; that is, it will be constant from pixel
to pixel.
V
- V
REF+ REF-
V
FS
=
G
V
PGA
= VOLTAGE DIFFERENCE BETWEEN THE
VIDEO
VIDEO LEVEL AND THE PRE-CHARGE (RESET) LEVEL.
Figure 11. Transfer Function for CCDIN
Choosing C
in Black-Level Compensation
EXT
In activating CLAMP once per line to compensate for the
CCD black level, the recommended value of C
governed by the following equations:
is
EXT
DIGITAL
OUTPUT
C
C
≥ 12nF
and
≤ N x t x 760pF/µsec
111. . . . 111
111. . . . 110
111. . . . 101
EXT
EXT
where N is the number of light-shielded cells, and t is
the width of the CLAMP pulse in µsec.
100. . . 000
The second equation ensures that the time constant
formed by R x C
is small enough that the black level
EXT
000. . . 011
000. . . 010
000. . . 001
000. . . 000
is c a p ture d to within 0.5mV d uring the d a rk p ixe l
phase. For example, in an array with 27 dark pixels at a
670kHz sample rate, with t = 750nsec, the second
equation becomes C
than 12nF can be used; however, offset increases due
to switch charge injection, as explained in the section
≤ 15nF. Capacitors smaller
EXT
V
AIN_
1
256
3
256
253
256
255
256
V
FS
V
FS
V
FS
V
FS
254
256
2
256
4
V
Choosing C
for CDS.
EXT
V
FS
V
FS
FS
V
REF-
256
V
FS
= V - V
REF+ REF-
Figure 12. Transfer Function for AIN
10 ______________________________________________________________________________________
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
MAX01
__________________P in Co n fig u ra t io n
100.00
10.00
1.00
TOP VIEW
GND
CCDIN
GND
AIN1
GND
AIN2
GND
I.C.
1
2
3
4
5
6
7
8
24 GND
V
DD
23
22 BLKSAMP
21 VIDSAMP
20 LOAD
0.10
MAX1101
19 DATA
18 SCLK
0.01
3
4
5
6
7
8
9
10
17 MODE
NUMBER OF TIME CONSTANTS
I.C.
9
16 GND
V
15
I.C. 10
REFGND 11
REF- 12
DD
Figure 13. Black Level Error vs. C
Maximum PGA Gain (1mV/bit)
Time Constant at
EXT
14 REFBIAS
13 REF+
Byp a s s in g a n d La yo u t Co n s id e ra t io n s
Solder the MAX1101 to a multilayer board (two or more
layers) where the layer immediately beneath the device
is a ground plane.
SO
Connect the V pins together at the MAX1101. Connect
DD
all ground pins together at the device.
___________________Ch ip In fo rm a t io n
Bypass V
to ground with at least a 0.1µF ceramic
DD
capacitor. If larger capacitors are used, tantalum is
satisfactory.
TRANSISTOR COUNT: 3430
______________________________________________________________________________________ 11
S in g le -Ch ip , 8 -Bit CCD Dig it ize r
w it h Cla m p a n d 6 -Bit P GA
________________________________________________________P a c k a g e In fo rm a t io n
MAX01
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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