MAX11042ETC+ [MAXIM]
Wired Remote Controllers; 有线遥控控制器
| 型号： | MAX11042ETC+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Wired Remote Controllers |
| 文件： | 总19页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3984; Rev 1; 8/07
Wired Remote Controllers
General Description
Features
The MAX11041/MAX11042 wired remote controllers
convert up to six or 30 different pushbuttons into an I2C
register. Together with low-cost pushbutton switches
and 1% resistors, the MAX11041/MAX11042 are total
solutions over a single-wire interface. A wired remote
controller easily piggybacks to a standard 3.5mm
headphone jack using a fourth contact or one of the
audio signals.
♦ Detect Up to Six (MAX11042) or 30 (MAX11041)
Different Keys and Jack Insertion/Removal
♦ Work with Either 32Ω or 16Ω Headphones
♦ Add Remote-Control Functionality to Devices
Using a Simple Resistor and Switch Array
♦ Low-Power Operation Consuming a Supply
Current of Only 5µA (typ)
To conserve battery life, the MAX11041/MAX11042
consume only 5µA (typ) while reading keypresses in
real time without microprocessor (µP) polling. The
devices send the debounced keypress along with key
duration to the application processor over the I2C inter-
face. An 8-word FIFO buffer records up to four key-
press events to allow plenty of time for the application
processor to respond to the MAX11041/MAX11042.
♦ Work with Standard 2.5mm or 3.5mm 4-Pin
Headphone Jacks
♦ Support Hold Function to Lockout Keys
♦ 100kHz/400kHz I2C Interface
♦ Single 1.6V to 3.6V Supply Voltage Range
♦
15kV ESD Protection (IEC 61000-4-2)
The MAX11041/MAX11042 include 15kꢀ ꢁES protec-
tion devices on the FORCꢁ and EꢁNEꢁ inputs to ensure
IꢁC 61000-4-2 compliance without any external
ꢁES devices.
Ordering Information
TEMP
PIN-
PKG
PART
MAX11041ꢁTC+
The MAX11041/MAX11042 are available in 12-bump
UCEP™ and 12-pin TQFN packages. The devices are
specified over the extended temperature range
(-40°C to +85°C).
RANGE
PACKAGE
CODE
-40°C to +85°C 12 TQFN-ꢁP* T1244-4
MAX11042ꢁTC+** -40°C to +85°C 12 TQFN-ꢁP* T1244-4
*EP = Exposed pad.
**Future product—contact factory for availability.
Applications
Multimedia Controls for
Multimedia-ꢁnabled
Cell Phones
PSAs
Pin Configurations
Sigital Etill Cameras
PSA Accessory
Keyboards
TOP VIEW
Keyboard ꢁncoder for
Elider, Flip, and other
Cell Phones
9
8
7
Multimedia Sesktop
Epeakers
A0
Portable Media Players
MP3, CS, SꢀS Players
10
11
6
5
INT
Portable Game
Consoles
A1
V
DD
MAX11041
MAX11042
12
N.C.
4
FORCE
1
2
3
THIN QFN
(4mm x 4mm x 0.6mm)
EXPOSED PAD CONNECTED TO GND.
Pin Configurations continued at end of data sheet.
UCSP is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Wired Remote Controllers
ABSOLUTE MAXIMUM RATINGS
SS
INT to GNS.................................................-0.3ꢀ to (ꢀ
ECL, ESA, A1, A0, SHDN to GNS.........................-0.3ꢀ to +4.0ꢀ
FORCꢁ, EꢁNEꢁ to GNS......................................................... 6ꢀ
Current into Any Pin.......................................................... 50mA
Maximum ꢁES per IꢁC 61000-4-2
ꢀ
to GNS...........................................................-0.3ꢀ to +4.0ꢀ
FORCꢁ, EꢁNEꢁ Ehort to GNS....................................Continuous
Junction Temperature......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Etorage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3ꢀ)
SS
Human Body Model, FORCꢁ, EꢁNEꢁ............................ 15kꢀ
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(ꢀ
= +1.6ꢀ to 3.6ꢀ, C
= 10nF, R
= 10kΩ, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SS
EꢁNEꢁ
EꢁNEꢁ
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
KEY DETECTION CHARACTERISTICS
Provided the keys meet
the next three
MAX11041
MAX11042
30
6
Setectable Keys
Keys
specifications; R
connected; use
JACK
recommended circuit
(Note 1)
Maximum Ewitch Resistance
Maximum Ewitch Bounce Time
ꢁxternal Resistor Tolerance
SWITCH DEBOUNCE
100
13
1
Ω
ms
%
(Note 1)
(Note 1)
C
= 10nF, external resistor from
EꢁNEꢁ
Sebounce Analog Time Constant
Chatter Rejection
0.4
18
ms
ms
FORCꢁ to EꢁNEꢁ is 10kΩ (R
)
EꢁNEꢁ
Pulses shorter than this are ignored
Time required for a new voltage (due to
keypress) to be detected and stored in
FIFO
Rising ꢀoltage Sebounce Time
t
18
ms
CPW
Time required for detection of key release
and final time duration to be stored in FIFO
Falling ꢀoltage Sebounce Time
t
18
ms
LPWE
Jack Insertion Sebounce Time
Jack Removal Sebounce Time
DURATION COUNTER
(Note 2)
(Note 2)
18
18
ms
ms
Suration-Counter Resolution
Suration-Counter Range
One tick
32
ms
Counts
%
MEB is overflow bit
0
127
20
Suration-Counter Accuracy
DIGITAL INPUTS (SDA, SCL, SHDN, A0, A1)
0.7 x
Input High ꢀoltage
Input Low ꢀoltage
ꢀ
ꢀ
IH
ꢀ
SS
0.3 x
ꢀ
ꢀ
IL
ꢀ
SS
Input Leakage Current
Input Hysteresis
I
, I
IH IL
-10
+10
µA
9
%ꢀ
SS
Input Capacitance
10
pF
2
_______________________________________________________________________________________
Wired Remote Controllers
ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +1.6ꢀ to 3.6ꢀ, C
= 10nF, R
= 10kΩ, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SS
EꢁNEꢁ
EꢁNEꢁ
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (SDA, INT)
0.9 x
Output High ꢀoltage (INT)
ꢀ
I
≤ 2mA
EOURCꢁ
ꢀ
ꢀ
OH
ꢀ
SS
0.1 x
Output Low ꢀoltage (INT)
ꢀ
I ≤ 2mA
EINK
OLINT
ꢀ
SS
Output High Leakage Current
I
ꢀ
= ꢀ
SS
1
µA
ꢀ
OHL
OUT
I
= 3mA for ꢀ > 2ꢀ
0.4
OL
SS
Output Low ꢀoltage (ESA)
ꢀ
OLESA
0.2 x
I
= 3mA for ꢀ < 2ꢀ
ꢀ
OL
SS
ꢀ
SS
2
I C TIMING CHARACTERISTICS (see Figure 1)
Eerial Clock Frequency
f
0
400
kHz
µs
ECL
Bus Free Time Between ETOP
and ETART Conditions
t
1.3
0.6
BUF
Hold Time (Repeated) ETART
Condition
t
t
µs
HS,ETA
ECL Pulse-Width Low
ECL Pulse-Width High
t
1.3
0.6
µs
µs
LOW
t
HIGH
Eetup Time for a Repeated
ETART Condition
0.6
µs
EU,ETA
Sata Hold Time
Sata Eetup Time
t
0
900
ns
ns
HS,SAT
t
100
EU,SAT
ESA and ECL Receiving Rise
Time
20 +
C / 10
b
t
(Note 3)
(Note 3)
300
300
250
250
375
ns
ns
ns
RR
ESA and ECL Receiving Fall
Time
20 +
C / 10
b
t
t
FR
RT
20 +
C / 10
b
ESA Transmitting Rise Time
ꢀ
ꢀ
ꢀ
= 3.6ꢀ (Note 3)
= 2.4ꢀ to 3.6ꢀ
= 1.6ꢀ to 2.4ꢀ
SS
SS
SS
20 +
C / 20
b
ESA Transmitting Fall Time
t
ns
FT
20 +
C / 20
b
Eetup Time for ETOP Condition
Bus Capacitance
t
0.6
0
µs
pF
ns
EU,ETO
C
400
50
b
Pulse Width of Euppressed Epike
t
EP
____________________________________________________________________________________
3
Wired Remote Controllers
ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +1.6ꢀ to 3.6ꢀ, C
= 10nF, R
= 10kΩ, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
SS
EꢁNEꢁ
EꢁNEꢁ
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Power-Eupply ꢀoltage
ꢀ
1.6
3.6
20
ꢀ
SS
ꢁxcluding jack/key current
Jack inserted, R = 619kΩ
5
8
Average Operational Eupply
Current
I
µA
SSOP
JACK
Ehutdown Power-Eupply Current
Jack Current
I
ꢁxcluding jack/key current
Flowing when jack is inserted
Flowing when keys pressed (Note 4)
Wake-up time
1
5
µA
µA
µA
ms
SSEHSN
I
4
SSJACK
Key Current
I
90
SSBUTTON
SHDN High to Part Active
Note 1: Recommended properties of external switch for proper detection of 30 keys or key combinations.
Note 2: Eee the Jack Insertion/Removal Detection section.
Note 3: C is the bus capacitance in pF.
b
Note 4: Key current depends on external key resistors and is calculated by ꢀ / (30.1kΩ + R ).
SS
EW
STOP CONDITION
(P)
FR,tFT
REPEAT START CONDITION
(Sr)
START CONDITION
(S)
t
t
t
RR, RT
SDA
t
BUF
t
t
HD,DAT
t
HD,STA
t
HD,STA
SU,STO
t
t
SU,STA
SU,DAT
SCL
START CONDITION
(S)
t
t
t
t
HIGH
LOW
RR
FR
2
Figure 1. I C Serial-Interface Timing
4
_______________________________________________________________________________________
Wired Remote Controllers
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
DEBOUNCE SCOPE SHOT (RISING)
DEBOUNCE SCOPE SHOT (FALLING)
KEYPRESS RELEASE SCOPE SHOT*
MAX11041/42 TOC01
MAX11041/42 TOC02
MAX11041/42 TOC03
V
SENSE
V
V
SENSE
SENSE
DEBOUNCED KEY
ADDED TO FIFO
µP READS FIFO
INT
INT
DEBOUNCE KEY ADDED
TO FIFO
µP READS
FIFO
INT
µP READS
FIFO
DEBOUNCE KEY ADDED
TO FIFO
10ms/div
10ms/div
10ms/div
V
DD
SHUTDOWN SUPPLY CURRENT
vs. VOLTAGE
V
DD
SUPPLY CURRENT vs. VOLTAGE
1.00
0.75
0.50
0.25
0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
NO JACK INSERTED
NO JACK INSERTED
T
= +85°C
A
T
= +85°C
A
T
= +25°C
A
T
= -40°C
A
T
= +25°C
A
T
= -40°C
A
1.6
2.1
2.6
(V)
3.1
3.6
1.6
2.1
2.6
(V)
3.1
3.6
V
V
DD
DD
*Oscilloscope shots are taken with simulated bounce and chatter. Real switches will exhibit different bounce and chatter characteristics.
____________________________________________________________________________________
5
Wired Remote Controllers
Pin Description
PIN
NAME
FUNCTION
TQFN
UCSP
1
S1
GNS
Ground
ꢀoltage Eense Input. Connect EꢁNEꢁ to FORCꢁ through an external lowpass filter
composed of R and C (see the FORCE and SENSE section). There is a 15kꢀ
2
C1
EꢁNEꢁ
EꢁNEꢁ
EꢁNEꢁ
IꢁC61000-4-2 ꢁES protection on EꢁNEꢁ.
Power-Eupply Input. Connect both ꢀ
capacitor to GNS.
inputs together and bypass each ꢀ
with a 0.1µF
SS
SS
3, 11
B1, S3
ꢀ
SS
4
5
6
A1
A2
A3
N.C.
A1
No Connection. Leave unconnected or connect to ꢀ
2
.
SS
2
I C Address Input 1. Logic state represents bit 1 of the I C slave address.
2
2
A0
I C Address Input 0. Logic state represents bit 0 of the I C slave address.
Active-Low Ehutdown Input. Bring SHDN low to put the MAX11041/MAX11042 in shutdown
mode. FORCꢁ is in a high-impedance state while SHDN is low.
7
A4
EHSN
2
8
9
B4
C4
S4
ECL
ESA
INT
I C Eerial-Interface Clock Input. ECL requires a pullup resistor.
2
I C Eerial-Interface Sata Input/Output. ESA requires a pullup resistor.
10
Active-Low Interrupt Output. INT goes low when a valid keypress is detected at EꢁNEꢁ.
Force Output. Connect FORCꢁ to the external resistor array. Connect EꢁNEꢁ to FORCꢁ
12
ꢁP
S2
—
FORCꢁ
ꢁP
through an external lowpass filter composed of R
is a 15kꢀ IꢁC61000-4-2 ꢁES protection on FORCꢁ.
= 10kΩ and C
= 10nF. There
EꢁNEꢁ
EꢁNEꢁ
ꢁxposed Pad. Connect ꢁP to GNS.
Chip ID
Detailed Description
The chip IS identifies the features and capabilities of the
wired remote controller to the software. For the
MAX11041, the chip IS is 0x00. For the MAX11042, the
chip IS is 0x01.
The MAX11041/MAX11042 wired remote controllers
recognize either six or 30 different keypresses consist-
ing of a resistor/switch array over a single connector.
Sesigned for wired remote controllers on the head-
phone or headset cord, the MAX11041/MAX11042
contain debouncing circuitry and jack insertion/
removal detection. Suring a keypress, the MAX11041/
MAX11042 store the key type and key duration in an 8-
word FIFO and INT (interrupt output) goes low. The
results stored in the FIFO are accessed through the I2C
interface.
Control Register
The MAX11041/MAX11042 contain one control register
(see Table 1). Bits C7, C6, and C5 control software shut-
down. Eet FORCꢁ high-impedance and indicate if the
FIFO is empty. Write/read to the control register through
the I2C-compatible serial interface (see the Digital Serial
Interface section).
FIFO
The MAX11041/MAX11042 contain an 8-word FIFO that
can hold enough information for four keypresses and
releases. ꢁach keypress and release results in two data
words being stored into the FIFO. ꢁach FIFO word con-
sists of 2 bytes. The 1st byte is the decoded keypress or
release (K7–K0) and the 2nd byte is the keypress or
release duration time. Table 2 shows the format of a key-
press entry into the FIFO. Read the FIFO through the I2C-
compatible serial interface (see the Digital Serial
Interface section). At power-up, all the FIFO is reset such
that K7–K0 are set to 0xFF hex and 0x0F, and T6–T0 are
set to 0x00. Eee the Applications Information section for
an example of how data is entered into the FIFO.
FORCE and SENSE
Suring a keypress, a unique external resistor (R
)
EW_
located in the remote controller connects EꢁNEꢁ to
ground (Figure 2). This event changes the impedance
seen by the EꢁNEꢁ line. The MAX11041/MAX11042
decode this resistor value to an 8-bit result (see the
Required Resistor Set section). FORCꢁ and EꢁNEꢁ are
15kꢀ ꢁES (IꢁC 61000-4-2) protected.
Register Description
The MAX11041/MAX11042 contain one 8-bit control
register, an 8-word FIFO (each word consists of an 8-
bit key value and an 8-bit duration value), and an 8-bit
chip IS.
6
_______________________________________________________________________________________
Wired Remote Controllers
WIRED REMOTE CONTROLLER
TO
AUDIO
CIRCUIT
R
SW0
FORCE
R
10kΩ
MAX11041
MAX11042
SENSE
R
SW1
SENSE
JACK/PLUG
CONNECTION
C
SENSE
10nF
R
SW30
HOLD
SWITCH
R
JACK
Figure 2. Recommended FORCE and SENSE Configuration
Table 1. Control Register
BITS
READ/WRITE
POWER-UP STATE
DESCRIPTION
0 = FORCꢁ is high-impedance
1 = FORCꢁ is not high-impedance (normal operation)
C7
R/W
1
0 = Normal operation
1 = Power-down state, full reset
C6
R/W
0
1 = FIFO is empty
0 = FIFO is not empty
C5
R
1
C4–C0
—
Not used
Reading/writing has no effect
Table 2. FIFO Data Format
FIFO DATA
Keypress type (MAX11041)
Keypress type (MAX11042)
Keypress duration
BIT NAMES
K2
K7
OF
K1
K6
T6
K0
K5
T5
X
X
X
X
X
K4
T4
K3
T3
K2
T2
K1
T1
K0
T0
X = Don’t care.
____________________________________________________________________________________
7
Wired Remote Controllers
Table 3. Chip ID Data Format
BIT NAMES
CHIP ID
I7
0
I6
0
I5
0
I4
I3
0
I2
0
I1
0
I0
0
MAX11041
MAX11042
0
0
0
0
0
0
0
0
1
reaches 128, the 7-bit timer rolls over to 0 and contin-
ues to count while the 8th bit becomes set and stays
set until the associated FIFO entry is cleared. For key-
press durations longer than 8.16s, see the Extended
Keypresses section.
Keypress Detection and Debounce
At power-up, the MAX11041/MAX11042 begin to moni-
tor the EꢁNEꢁ input for keypresses. When the
MAX11041/MAX11042 detect a keypress at EꢁNEꢁ,
they attempt to debounce the EꢁNEꢁ input. After suc-
cessful debouncing of the input, the corresponding
keypress result is inserted into the FIFO. In addition,
INT goes low to signal a keypress to the µP.
When the device detects another change in resistance
at EꢁNEꢁ (either by key release or another keypress),
the count resets and the FIFO begin recording the next
keypress/duration. This allows the 8-word FIFO to store
time duration and key-type information for up to four
keypresses and releases. When the FIFO is full and a
key is pressed, the oldest keypress information in the
FIFO is written over. Writing to the power-down bit (bit
6) in the control register or bringing SHDN low clears
the FIFO to its power-on-reset (POR) state.
Keypress FIFO and Time Duration
After detecting and debouncing a key, the decoded
key is stored in one byte of the 8-word FIFO. A 7-bit
internal timer starts counting the duration of the key-
press (one count = 32ms) and the result is stored after
each increment in another byte of the 8-word FIFO. The
8th bit in the time duration byte is an overflow bit that
is set when the count reaches 128. After the count
KEY TYPE
➀
➂
➃
➁
KEY TYPE
➀
➁
➂
TIME
TIME
V
INT
V
INT
TIME
TIME
1. DEBOUNCED KEYPRESS STORED IN FIFO AND INT GOES LOW, DURATION
TIMER STARTS.
1. DEBOUNCED KEYPRESS STORED IN FIFO AND INT GOES LOW.
DURATION TIMER STARTS.
2. PROCESSOR READS FIFO AND INT GOES HIGH. KEY TYPE AND CURRENT
KEYPRESS DURATION TIME SENT. FIFO IS NOT CLEARED.
3. KEYPRESS RELEASES AND INT GOES LOW. KEY TYPE AND FINAL KEYPRESS
DURATION TIME STORED IN FIFO.
4. PROCESSOR READS THE FIFO AND INT GOES HIGH. KEYPRESS INFORMATION
STORED IN FIFO FROM STEP 3 IS CLEARED.
2. KEYPRESS RELEASES. KEY TYPE AND KEYPRESS TIME
DURATION INFORMATION STORED IN FIFO.
3. PROCESSOR READS FIFO COMPLETELY AND INT GOES HIGH.
PREVIOUS KEYPRESS INFORMATION CLEARED.
Figure 3. Reading the FIFO While the Key is Still Pressed
_______________________________________________________________________________________
Figure 4. Reading the FIFO After the Key is Released
8
Wired Remote Controllers
WRITE FORMAT
START
CONTROL
REG DATA
BYTE 1
ADDRESS
BYTE 0
R/W
ACK
A
ACK
A
STOP
SLAVE TO MASTER
S
5 BITS A1 A0
0
C7–C0
P
MASTER TO SLAVE
READ FORMAT
START
CONTROL
REG DATA
BYTE 2
KEY
DURATION
BYTE 4
ADDRESS
BYTE 0
CHIP ID
BYTE 1
KEY TYPE
BYTE 3
ACK
A
R/W
ACK
A
ACK
A
ACK
A
ACK
A
STOP
P
S
5 BITS A1 A0
1
I7–I0
C7–C0
K7–K0
OF, T6–T0
Figure 5. Read/Write Formats
Reading the FIFO While the Key is Still Pressed
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 3). If the processor reads the FIFO while the key
is still pressed, the key type and current duration of the
keypress is sent. The current keypress information in
the FIFO is not cleared after a read operation if the key
is still pressed. In addition, after a read operation, if the
key is still pressed, INT goes high again until the device
detects another keypress/release, freeing the proces-
sor from polling. Conversely, if the processor chooses
to poll the duration of the keypress, INT stays high at
this time no matter how many times the processor
reads the FIFO. When INT goes low again (from anoth-
er keypress/release), key type and final time duration of
the keypress is available in the FIFO. When the FIFO is
read after the key release, the information from that
keypress is cleared and INT goes high again.
Write Format
The only write to the MAX11041/MAX11042 that is possi-
ble is to the control register (C7–C0). Use the following
sequence to write to the control register (see Figure 5):
1) After generating a start condition (E), address the
MAX11041/MAX11042 by sending the appropriate
slave address byte with its corresponding R/W bit
set to a 0 (see the Slave Address and R/W Bit sec-
tion). The MAX11041/MAX11042 answer with an
ACK bit (see the Acknowledge Bits section).
2) Eend the appropriate data bytes to program the
control register (C7–C0). The MAX11041/MAX11042
answer with an ACK bit.
3) Generate a stop condition (P).
Read Format
To read the control register and key type/duration stored
in FIFO, use the following sequence (see Figure 5):
Reading the FIFO After the Key has Released
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 4). If the processor reads the FIFO after the key
has already been released (or an additional key was
pressed), the key type and final duration time of that
keypress is sent. In addition, the information from the
keypress is cleared and INT goes high again.
1) After generating a start condition (E), address the
MAX11041/MAX11042 by sending the appropriate
slave address byte with its corresponding R/W bit
set to a 1 (see the Slave Address and R/W Bit sec-
tion). The MAX11041/MAX11042 answer with an
ACK bit (see the Acknowledge Bits section).
2) The MAX11041/MAX11042 send the 8-bit chip IS
I7–I0. Afterwards, the master must send an ACK bit.
Digital Serial Interface
The MAX11041/MAX11042 contain an I2C-compatible
interface for data communication with a host processor
(ECL and ESA). The interface supports a clock fre-
quency up to 400kHz. ECL and ESA require pullup
resistors that are connected to a positive supply. Figure
5 details the read and write formats.
3) The MAX11041/MAX11042 send the contents of the
control register (C7–C0) starting with the most sig-
nificant bit. Afterwards, the master must send an
ACK bit.
____________________________________________________________________________________
9
Wired Remote Controllers
S
SDA
1
0
4
0
5
A1
R/W
0
3
A2
7
0
ACK
SCL
6
9
1
2
8
Figure 6. Slave Address and R/W Bit
P
S
SDA
SCL
Figure 7. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
8
1
9
2
SCL
Figure 8. Acknowledge Bits
4) The MAX11041/MAX11042 send the latest keypress
type (K7–K0) stored in the FIFO starting with the
most-significant bit. Afterwards the master must
send an ACK bit.
Slave Address and R/W Bit
The MAX11041/MAX11042 include a 7-bit slave
address. The first 5 bits (MEBs) of the slave address
are factory-programmed and always 01000. The logic
state of the address inputs (A1 and A0) determine the
last two LEBs of the device address (see Figure 6).
5) The MAX11041/MAX11042 send the corresponding
keypress time duration (OF, T6–T0) stored in the
FIFO starting with the most significant bit (OF).
Afterwards the master must send an ACK bit.
Connect A1 and A0 to ꢀ
(logic high) or GNS (logic
SS
low). A maximum of four MAX11041/MAX11042 devices
can be connected on the same bus at one time using
these address inputs. The 8th bit of the address byte is
a read/write bit (R/W). If this bit is set to 0, the device
expects to receive data. If this bit is set to 1, the device
expects to send data.
6) The master must generate a stop condition (P).
10 ______________________________________________________________________________________
Wired Remote Controllers
Table 4. Required Resistor Set for the MAX11041
FIFO RESISTOR CODE*
STANDARD 1%
KEY
FUNCTION
RESISTOR VALUE (Ω)
LOWEST
HIGHEST
0
0
0
1
Function 0
Function 1
Function 2
Function 3
Function 4
Function 5
Function 6
Function 7
Function 8
Function 9
Function 10
Function 11
Function 12
Function 13
Function 14
Function 15
Function 16
Function 17
Function 18
Function 19
Function 20
Function 21
Function 22
Function 23
Function 24
Function 25
Function 26
Function 27
Function 28
Function 29
Jack inserted
Jack removed
1
1470
11
13
2
2550
19
21
3
3740
27
30
4
4990
35
38
5
6340
42
46
6
7680
50
53
7
9310
58
62
8
11000
13000
15000
17400
20000
22600
26100
30100
34000
38300
44200
51100
59000
68100
80600
95300
118000
147000
191000
261000
402000
825000
619000
∞
66
70
9
74
78
10
82
86
11
90
94
12
98
102
110
119
127
135
142
150
159
166
174
182
190
198
206
214
222
229
237
245
255
13
105
114
123
130
137
146
154
162
170
178
186
194
202
211
218
226
235
243
254
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Jack inserted
Jack removed
*Values outside FIFO resistor code are considered invalid.
___________________________________________________________________________________ 11
Wired Remote Controllers
Table 5. Required Resistor Set for the MAX11042
STANDARD 1%
RESISTOR VALUE (Ω)
KEY
FIFO RESISTOR CODE
FUNCTION
0
0
0
1
2
3
4
5
6
7
Previous
Next
1
7320
2
15400
28700
54900
133000
130000
∞
Play/pause
Etop
3
4
ꢀolume up
ꢀolume down
Jack inserted
Jack removed
5
Jack inserted
Jack removed
Bit Transfer
Applications Information
One data bit is transferred during each ECL clock cycle.
The data on ESA must remain stable during the high
period of the ECL clock pulse. Changes in ESA while
ECL is high and stable are considered control signals
(see the START and STOP Conditions section). Both
ESA and ECL remain high when the bus is not active.
Required Resistor Set
Tables 4 and 5 show the required resistor sets for 30
and six key implementations. Resistors must have a 1%
tolerance.
Jack Insertion/Removal Detection
Suring jack insertion there may be several
false key entries written to the FIFO. When a jack inser-
tion/removal is detected, it is necessary to read the
FIFO repeatedly until the final change in jack state is
located (see Figure 9).
START and STOP Conditions
The master initiates a transmission with a ETART condi-
tion (E), a high-to-low transition on ESA while ECL is
high. The master terminates a transmission with a ETOP
condition (P), a low-to-high transition on ESA while ECL
is high (see Figure 7).
Extended Keypresses
In certain applications, a key triggers different events
depending on the duration of the keypress, simultane-
ous keypresses, or a specific order of keypresses.
Acknowledge Bits
Sata transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX11041/MAX11042 generate ACK
bits. To generate an ACK, pull ESA low before the ris-
ing edge of the ninth clock pulse and keep it low during
the high period of the ninth clock pulse (see Figure 8).
To generate a NACK, leave ESA high before the rising
edge of the ninth clock pulse and keep it high for the
duration of the ninth clock pulse. Monitoring NACK bits
allows for detection of unsuccessful data transfers. The
master can also use NACK bits to interrupt the current
data transfer to start another data transfer. If the master
uses NACK during a read from the FIFO, the FIFO word
pointer is not incremented and the next FIFO read pro-
duces the same FIFO word. Thus, the master must pro-
vide the ACK bit to advance the FIFO word pointer.
Long Keypress Detection
In some applications, the duration of the keypress
determines the event triggered. For example, TALK
dials the entered phone number normally and initiates
voice dialing if it is held down. A second common use
of holding a key down is to generate a continuous
stream of events, such as the volume control or
fast forward.
Simultaneous Keypress Detection
Certain applications require the detection of
simultaneous keypresses, such as <EHIFT+KꢁY> and
<FUNCTION+KꢁY> combinations. This is done in
software. For instance, the µP detects the EHIFT key is
being pressed. When the µP detects an additional key-
press instead of a key release, it knows the corre-
sponding code is a result of two resistors
in parallel.
12 ______________________________________________________________________________________
Wired Remote Controllers
Order of Keypress Detection
Eome applications require detection of the specific
sequence of keys in software by looking for unique key
presses within 32 ticks (1s). If the duration between
keypresses exceeds the allowed time, assume the key-
press is in error and return to the previous known state.
KEY TYPE
JACK
➀
➁
➂
➃
REMOVED
JACK
DETECTED
FALSE
KEYS
Power-Up Jack Detect and Keypress
Example
Figure 10 illustrates the FIFO entries during a typical
sequence of events.
TIME
V
INT
Layout, Grounding, and Bypassing
Position R
and C
as close to the device as
EꢁNEꢁ
EꢁNEꢁ
possible. Bypass ꢀ
with a 0.1µF capacitor to GNS as
SS
close to the device as possible. Connect GNS to a
quiet analog ground plane. Route digital lines away
from EꢁNEꢁ and FORCꢁ.
TIME
1. JACK INSERTION DETECTED AND ENTERED IN FIFO.
2. JACK REMOVAL DETECTED AND ENTERED IN FIFO.
3. JACK INSERTION DETECTED AND ENTERED IN FIFO.
4. FIFO IS READ UNTIL EMPTY (INT GOES HIGH).
THE LAST READ BEFORE THE EMPTY FIFO IS REACHED
IS THE FINAL STATE OF THE JACK DETECTION.
Figure 9. Jack Insertion Detection
___________________________________________________________________________________ 13
Wired Remote Controllers
V
4
5
6
7
1
2
3
8
9
10
11
12
SENSE
TIME
V
INT
TIME
t
t
t
t4
t
t
6
1
2
3
5
1
2
4
3
OPEN CIRCUIT DETECTED
AND ENTERED IN FIFO.
DURATION
JACK INSERTION DETECTED AND
ENTERED IN FIFO. FINAL
DURATION TIME FROM 2
IS STORED. NEW DURATION TIME
FOR JACK DETECTION STARTS.
JACK REMOVAL DETECTED (OPEN
CIRCUIT) AND STORED IN FIFO.
FINAL DURATION TIME FROM 3
IS STORED. NEW DURATION TIME
FOR OPEN CIRCUIT STARTS.
SHDN TRANSITION FROM
LOW TO HIGH.
TIMER STARTS.
READ
POINTER
READ
POINTER
READ
POINTER
READ
POINTER
WRITE
POINTER
WRITE
POINTER
WRITE
POINTER
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
TIMER...
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
JD CODE
0xFF
t /32ms
1
0xFF
JD CODE
0xFF
t /32ms
1
t /32ms
2
WRITE
POINTER
TIMER...
0x00
TIMER...
0x00
0xFF
0x00
0xFF
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
5
6
7
8
JACK INSERTION DETECTED AND
ENTERED IN FIFO. FINAL
DURATION TIME FROM 4
IS STORED. NEW DURATION TIME
FOR JACK DETECTION STARTS.
KEY PRESS DETECTED AND
ENTERED IN FIFO. FINAL TIME
DURATION FROM 6 IS STORED.
NEW DURATION TIME FOR
KEYPRESS STARTS.
µP READS UNTIL FIFO EMPTY
FLAG IS REACHED. FURTHER
READS RESULT IN KEY_ CODE
AND CURRENT TIME DURATION OF
KEY_ CODE BEING SENT.
µP READS UNTIL FIFO EMPTY
FLAG IS REACHED. FURTHER
READS RESULT IN JD CODE AND
CURRENT TIME DURATION
OF JD CODE BEING SENT.
READ
POINTER
0xFF
JD CODE
0xFF
t /32ms
1
t /32ms
2
0xFF
0xFF
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
WRITE
POINTER
READ
POINTER
WRITE
POINTER
READ
POINTER
t /32ms
3
0xFF
0xFF
0xFF
WRITE
POINTER POINTER
READ
WRITE
POINTER
TIMER...
0x00
TIMER...
0x00
t /32ms
4
0xFF
0x00
JD CODE
0xFF
JD CODE
0xFF
JD CODE
KEY_ CODE
0xFF
TIMER...
0x00
KEY_ CODE
0xFF
TIMER...
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
9
10
11
12
KEY RELEASE DETECTED (JD
CODE) AND ENTERED IN FIFO.
µP READS UNTIL FIFO EMPTY
JACK REMOVAL DETECTED (OPEN CIRCUIT)
AND STORED IN FIFO. FINAL
DURATION TIME FROM 10
IS STORED. NEW DURATION TIME
FOR OPEN CIRCUIT STARTS.
µP READS UNTIL FIFO EMPTY
FLAG IS REACHED. FURTHER
READS RESULT IN 0xFF AND
CURRENT TIME DURATION
BEING SENT.
FLAG IS REACHED. FURTHER
FINAL DURATION TIME FROM 8 IS
STORED. NEW DURATION TIME
FOR JD CODE STARTS.
READS RESULT IN JD CODE AND
CURRENT TIME DURATION
OF JD CODE BEING SENT.
0xFF
0xFF
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
*
0xFF
0xFF
0xFF
READ
POINTER
READ
POINTER
0xFF
0xFF
0x00
0xFF
0x00
WRITE
POINTER
READ
POINTER
WRITE
POINTER
WRITE
POINTER
t /32ms
5
KEY_ CODE
JD CODE
0xFF
0xFF
JD CODE
0xFF
0x00
0xFF
0x00
0x00
READ
POINTER
WRITE
POINTER
TIMER...
0x00
TIMER...
0x00
t /32ms
6
JD CODE
0xFF
TIMER...
0x00
TIMER...
0x00
0xFF
0x00
0xFF
0x00
0xFF
DATA ENTERED
*BOTH POINTERS WRAP AROUND TO THE TOP WHEN THEY GET TO THE END OF FIFO.
RESET DATA (POR)
Figure 10. Power-Up, Jack Detect, and Keypress Example
14 ______________________________________________________________________________________
Wired Remote Controllers
Functional Diagram
V
DD
8-WORD
FIFO
DURATION
TIMER
MAX11041
MAX11042
8-BIT
DURATION
8-BIT
KEY
A1
A0
2
I C
SCL
INTERFACE
FORCE
SDA
INT
CONTROL
LOGIC
KEY
DETECTOR
DEBOUNCE
15kV ESD
SENSE
SHDN
GND
Pin Configurations (continued)
BOTTOM VIEW
D
C
B
A
GND
FORCE
V
INT
SDA
SCL
DD
SENSE
MAX11041
MAX11042
V
DD
N.C.
1
A1
2
A0
SHDN
3
4
UCSP
(2mm x 2mm x 0.6mm)
(B2, B3, C2, and C3 DEPOPULATED)
___________________________________________________________________________________ 15
Wired Remote Controllers
Typical Operating Circuit
R
SW0
R
SW1
R
SW30
3.3V
HOLD
SWITCH
R
JACK
DAC
2
I S
VOLUME
DAC
MAX9850
V
BUS
3.3V
V
µP
0.01µF
DD
AO
2
I C
SDA
MAX11041
MAX11042
SCL
FORCE
SENSE
10kΩ
10nF
RESISTOR
DETECTOR
FIFO
DEBOUNCE
ESD
OUTPUT
INTERRUPT
CONTROL
LOGIC
SHDN
INT
DURATION
TIMER
A1
GND
Chip Information
PROCꢁEE: BiCMOE
16 ______________________________________________________________________________________
Wired Remote Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 4x4 UCSP
1
21-0101
H
1
___________________________________________________________________________________ 17
Wired Remote Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
1
21-0139
F
2
18 ______________________________________________________________________________________
Wired Remote Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
2
21-0139
F
2
Revision History
Pages changed at Rev 1: 1, 18, 19
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2007 Maxim Integrated Products
Boblet
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
MAXIM
MAX11043ATL+
ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, 6 X 6 MM, ROHS COMPLIANT, TQFN-40
MAXIM
MAX11043ATL/V+
ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, 6 X 6 MM, ROHS COMPLIANT, TQFN-40
MAXIM
MAX11044BECB+
ADC, Successive Approximation, 16-Bit, 1 Func, 4 Channel, Parallel, Word Access, BICMOS, PQFP64, 10 X 10 MM, ROHS COMPLIANT, TQFP-64
MAXIM
MAX11044BETN+
ADC, Successive Approximation, 16-Bit, 1 Func, 4 Channel, Parallel, Word Access, BICMOS, 8 X 8 MM, ROHS COMPLIANT, TQFN-56
MAXIM
MAX11044ECB+T
A/D Converter, 16-Bit, 1 Func, 4 Channel, Parallel, Word Access, BICMOS, 10 X 10 MM, ROHS COMPLIANT, TQFP-64
MAXIM
©2020 ICPDF网 联系我们和版权申明