MAX11043ATL+ [MAXIM]
ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, 6 X 6 MM, ROHS COMPLIANT, TQFN-40;
| 型号： | MAX11043ATL+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Delta-Sigma, 16-Bit, 1 Func, 4 Channel, Serial Access, BICMOS, 6 X 6 MM, ROHS COMPLIANT, TQFN-40 信息通信管理 转换器 |
| 文件： | 总33页 (文件大小：861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
General Description
Features
o 4 Single-Ended or Differential Channels of
The MAX11043 features 4 single-ended or differential
channels of simultaneous-sampling ADCs with 16-bit
resolution. The MAX11043 contains a versatile filter
block and programmable-gain amplifier (PGA) per
channel. The filter consists of seven cascaded 2nd-
order filter sections for each channel, allowing the con-
struction of a 14th-order filter. The filter coefficients are
user-programmable. Configure each 2nd-order filter as
lowpass (LP), highpass (HP), or bandpass (BP) with
optional rectification. Gain and phase mismatch of the
analog signal path is better than -50dB.
Simultaneous-Sampling, 16-Bit ADCs
1ꢀ ꢁSB ꢂIꢁ, 1 ꢁSB DIꢁ, Io Missing Codes
o
o 93dB SFDR at 1ꢀꢀkHz ꢂnput
o PGA with Gain of 1, 2, 4, 8, 16, 32, or 64 for
Each Channel
o EQ Function Automatically Boosts
High-Frequency, ꢁow-Amplitude Signals
o Seven-Stage ꢂnternal Programmable Biquad
Filters per Channel
o High Throughput, 4ꢀꢀksps per Channel for 4
The ADC can digitize signals up to 200kHz. A 40MHz
serial interface provides communication to and from the
device. The SPI interface provides throughput of
1600ksps; 4 channels at 400ksps per channel or 2
channels at 800ksps per channel. A software-selec-
table scan mode allows reading the ADC results while
simultaneously updating the DAC. Other features of the
MAX11043 include an internal (+2.5V) or external
(+2.0V to +2.8V) reference, power-saving modes, and
a PGA with gains of 1 to 64. The PGA includes an
equalizer (EQ) function that automatically boosts low-
amplitude, high-frequency signals for applications such
as CW-chirp radar.
Channels
o Dual-Stage DAC
Two 8-Bit Coarse Reference DACs
12-Bit Fine DAC
o +2.5V ꢂnternal Reference or +2.ꢀV to +2.8V
External Reference
o Single +3.3V Operation
o Shutdown and Power-Saving Modes
o 4ꢀ-Pin, 6mm x 6mm TQFI Package
o -4ꢀ°C to +125°C Operating Temperature
Ordering Information
The MAX11043 includes two 8-bit coarse DACs that set
the high and low references for a second-stage 12-bit
fine DAC, typically used for VCO control. Use software
controls to write to the DAC or step the DAC up and
down under hardware control in programmable steps.
The device operates from a +3.0V to +3.6V supply. The
MAX11043 is available in a 40-pin, 6mm x 6mm TQFN
package and operates over the extended -40°C to
+125°C temperature range.
PART
TEMP RAIGE
-40°C to +125°C
-40°C to +125°C
PꢂI-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
MAX11043ATL+
MAX11043ATL/V+
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
*EP = Exposed pad.
Pin Configuration
TOP VIEW
Applications
30 29 28 27 26 25 24 23 22 21
20
31
32
33
OSCOUT
AINDN
AINDP
AGND
Automotive Radar Systems
Data Acquisition Systems
Industrial Controls
19 OSCIN
18 EOC
17 I.C.
REFBP 34
16
SCLK
15 DIN
14
35
36
37
38
39
40
I.C.
AINCN
AINCP
REFC
Power-Grid Monitoring
MAX11043
DOUT
13 CS
12
*EP
+
CONVRUN
11 DACSTEP
REFB
AINBP
1
2
3
4
5
6
7
8
9
10
TQFI
*CONNECT EP TO AGND.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-4250; Rev 3; 11/12
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
ABSOꢁUTE MAXꢂMUM RATꢂIGS
AVDD to AGND ....................................................-0.3V to +4.0V
DVDD to DGND.....................................................-0.3V to +4.0V
DVREG to DGND...................................................-0.3V to +3.0V
AGND to DGND.....................................................-0.3V to +0.3V
Analog I/O, REFDACH, REFDACL, REFA, REFB, REFC, REFD,
Continuous Power Dissipation (T = +70°C)
A
TQFN Multilayer Board
(derate 37mW/°C above +70°C)................................2963mW
TQFN Single-Layer Board
(derate 26.3mW/°C above +70°C)..........................2105.3mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
AOUT, REFDAC, REFBP to AGND.....-0.3V to (V
UP/DWN, CONVRUN, SHDN, DACSTEP, EOC, Digital I/O,
OSCIN, OSCOUT to DGND....................-0.3V to (V
Maximum Current into Any Pin except AVDD, DVDD, DVREG,
+ 0.3V)
AVDD
+ 0.3V)
DVDD
AGND, DGND............................................................... 50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= 38.4MHz, f
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
REFBP
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
SꢂGMA-DEꢁTA ADC
Resolution
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
N
16
-16
-1
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
OE
2
Guaranteed monotonic
+1
-35
+35
Offset-Error Drift
30
50
µV/°C
%
Gain Error
GE
Trimmed with 150Ω/330pF anti-alias filter
-1
+1
Gain Temperature Coefficient
Channel Gain-Error Matching
Channel Offset Matching
ppm/°C
%
Complete analog signal path
Complete analog signal path
-0.25
-60
+0.25
+60
mV
DYIAMꢂC PERFORMAICE (PGA Disabled, PGA Gain = 1 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
1.2
85
V
P-P
Input-Referred Noise Spectral
Density
100kHz
nV/√Hz
Second Harmonic to
Fundamental
-80
-93
dB
Third Harmonic to Fundamental
Spurious-Free Dynamic Range
-80
77
-110
93
dB
dB
SFDR
Unused channels are shorted and
unconnected
Channel-to-Channel Isolation
Channel Phase Matching
85
108
dB
Between all channels, including complete
analog signal path
-0.05
+0.05 Degrees
Maxim Integrated
2
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= 38.4MHz, f
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
REFBP
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
DYIAMꢂC PERFORMAICE (PGA Enabled, PGA Gain = 8 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
100kHz
150
20
mV
P-P
Input-Referred Noise Spectral
Density
nV/√Hz
Second Harmonic to
Fundamental
-92
dB
Third Harmonic to Fundamental
Spurious-Free Dynamic Range
-94
92
dB
dB
SFDR
Unused channels are shorted and
unconnected
Channel-to-Channel Isolation
Channel Phase Matching
110
dB
Between all channels, including complete
analog signal path
-0.05
+0.05 Degrees
DYIAMꢂC PERFORMAICE (PGA Enabled, PGA Gain = 16 x (25kHz -1dB Full-Scale Signal))
Maximum Full-Scale Input
ADC modulator gain = 1
75
15
mV
P-P
Input-Referred Noise Spectral
Density
100kHz
nV/√Hz
Second Harmonic to
Fundamental
-99
dB
Third Harmonic to Fundamental
Spurious-Free Dynamic Range
-93
93
dB
dB
SFDR
Unused channels are shorted and
unconnected
Channel-to-Channel Isolation
Channel Phase Matching
106
dB
Between all channels, including complete
analog signal path
-0.075
+0.075 Degrees
DYIAMꢂC PERFORMAICE (EQ Mode (5kHz -1dB Full-Scale Signal, COIFꢂG_ Register Bit 3 = 1))
Maximum Full-Scale Input
ADC modulator gain = 1 (Note 2)
800
6
mV
P-P
Input-Referred Noise Spectral
Density
100kHz
nV/√Hz
Second Harmonic to
Fundamental
-80
-90
dB
Third Harmonic to Fundamental
Spurious-Free Dynamic Range
-77
77
-98
89
dB
dB
SFDR
Input referred (Note 3)
Maxim Integrated
3
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= 38.4MHz, f
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
REFBP
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
Unused channels are shorted and
unconnected
Channel-to-Channel Isolation
80
104
dB
Between all channels, including complete
analog signal path
Channel Phase Matching
DYIAMꢂC PERFORMAICE (All Modes)
Conversion Rate
-0.12
+0.12 Degrees
All 4 channels
400
ksps
800
2 channels only
Minimum Throughput
5
ksps
dB
Power-Supply Rejection Ratio
DCPSRR
50
AIAꢁOG ꢂIPUTS (AꢂIAP/AꢂIAI, AꢂIBP/AꢂIBI, AꢂICP/AꢂICI, AꢂIDP/AꢂIDI)
Absolute Voltage Any Input
Input Impedance (Note 5)
(Note 4)
0
25
100
7
V
V
AVDD
DIFF = 1
DIFF = 0
Direct input to ADC,
gain = 1
Direct input to ADC, gain = 2
Direct input to ADC, gain = 4 or 8
PGA gain = 16
kΩ
pF
7
5.5
Input Capacitance
EQ mode only
50
EQ FꢂꢁTER (Analog and Digital)
Unity-Gain Frequency
Lower Transition Frequency
Upper Transition Frequency
ꢁP FꢂꢁTER
Default
5
kHz
kHz
kHz
Default, from 40dB/decade to 0dB/decade
Default, from 0dB/decade to -80dB/decade
190
205
-3dB Corner Frequency
REFEREICE ꢂIPUT
REF_ Input Voltage Range
Input Current
Default
205
2.5
kHz
V
2
2
2.8
150
2.8
700
1.4
V
µA
V
REF_
REFBP Input Voltage Range
Input Current
V
2.5
REFBP
µA
V
REFDAC Input Voltage Range
Input Resistance
V
1
1.25
REFDAC
17
kΩ
4
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= V
= +2.5V (external reference), V
= V
= 38.4MHz, f
= +1.25V (external reference), V
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
= C
= C
= C
= C
= 1µF, f
= 38.4MHz (external clock applied to
REFBP
REFA
REFB
REFC
REFD
REFDAC
EXCLK
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
REFDAC_ Input Voltage Range
Input Resistance
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
0
TYP
MAX
UIꢂTS
V
V
1.4
REFDAC_
150
kΩ
ꢂITERIAꢁ REFEREICE
Reference Voltage
V
2.45
2.5
2.55
V
REFBP
Reference Temperature
Coefficient
100
ppm/°C
CRYSTAꢁ OSCꢂꢁꢁATOR (Max ESR 1ꢀꢀΩ, 22pF ꢁoad Capacitors to DGID)
Maximum Crystal Operating
Epson Electronics MA-505 (16MHz)
Frequency
16
4
MHz
MHz
External Clock Input Frequency
External clock applied to OSCIN
Range
40
Stability
Excluding crystal
25
10
ppm
ms
Startup Time
Epson Electronics MA-505 (16MHz)
0.3 x
OSCIN Input Low Voltage
OSCIN Input High Voltage
When driven with external clock source
When driven with external clock source
V
V
DVDD
0.7 x
V
V
DVDD
OSCIN Leakage Current
-5
+5
µA
DꢂGꢂTAꢁ ꢂIPUTS
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
V
DVDD
0.3 x
V
IL
V
DVDD
Input Hysterisis
15
15
mV
µA
pF
Input Leakage Current
Input Capacitance
DꢂGꢂTAꢁ OUTPUTS
I
V
= 0V or V
DVDD
-1
+1
IN
IN
C
IN
V
- 0.6
DVDD
Output-Voltage High
V
I
I
= 0.8mA
V
OH
SOURCE
Output-Voltage Low
V
= 1.6mA
SINK
0.4
+1
V
OL
Three-State Leakage Current
Three-State Output Capacitance
VOꢁTAGE REGUꢁATOR
Regulated Digital Supply Voltage
POWER REQUꢂREMEITS
Analog Supply Voltage
DOUT only
DOUT only
-1
µA
pF
15
DV
Internal use only
2.5
V
REG
3.0
3.0
3.6
3.6
V
V
Digital Supply Voltage
Maxim Integrated
5
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= 38.4MHz, f
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
REFBP
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
Analog Supply Current
Digital Supply Current
Shutdown Current
SYMBOꢁ
COIDꢂTꢂOIS
PGA disabled
PGA enabled
MꢂI
TYP
MAX
80
140
40
5
UIꢂTS
mA
60
120
26
I
All channels selected
AVDD
I
mA
DVDD
I
AVDD
DVDD
mA
I
5
STATꢂC ACCURACY—FꢂIE DAC (C = 2ꢀꢀpF, R = 1ꢀkΩ)
ꢁ
ꢁ
Resolution
12
-5
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
+5
+1
DNL
Guaranteed monotonic
-1
-70
+70
Offset-Error Temperature
Coefficient
50
20
µV/°C
Gain Error
-2
0
%
Gain-Error Temperature
Coefficient
ppm of
FS/°C
DYIAMꢂC PERFORMAICE—FꢂIE DAC (C = 2ꢀꢀpF, R = 1ꢀkΩ)
ꢁ
ꢁ
Output Noise
f = 0.1Hz to 1MHz
200
12
3
µV
RMS
DAC Glitch Impulse
Major carry transition
25% to 75% FS
1% FS
nV•s
Voltage-Output Settling Time
µs
1.5
0.6
Voltage-Output Slew Rate
V/µs
STATꢂC ACCURACY—REFDACH AID REFDACꢁ
Resolution
8
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
-0.5
-0.2
-30
+0.5
+0.2
+30
DNL
Offset-Error Temperature
Coefficient
50
µV/°C
LSB
Gain Error
-5
+5
20
Gain-Error Temperature
Coefficient
ppm of
FS/°C
FꢁASH MEMORY
Programming Endurance
Data Retention
10,000
15
Cycles
Years
T
A
= +85°C
6
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
EꢁECTRꢂCAꢁ CHARACTERꢂSTꢂCS (continued)
(V
= +3.0V to +3.6V, V
= +3.0V, C
= 10µF, V
= V = 0V, common-mode input voltage = V /2, V
AVDD REFBP
DGND
DVREG
AVDD
DVDD
AGND
= V
0V, C
= V
= V
= V
= +2.5V (external reference), V
= V
= 38.4MHz, f
= +1.25V (external reference), V
=
REFA
REFB
REFC
REFD
REFDAC
SCLK
REFDACH
REFDACL
= C
= C
= C
= C
= C
= 1µF, f
= 38.4MHz (external clock applied to
REFBP
REFA
REFB
REFC
REFD
REFDAC
EXCLK
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T = T
to T , unless otherwise noted
MAX
A
MIN
(Note 1). Typical values are at T = +25°C.)
A
PARAMETER
SPꢂ ꢂITERFACE
SYMBOꢁ
COIDꢂTꢂOIS
MꢂI
TYP
MAX
UIꢂTS
SCLK Clock Period
t
25
10
10
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
CH
t
CL
SCLK Rise to DOUT Transition
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Setup Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
CS Pulse-Width High
t
C
= 20pF
15
DOT
LOAD
t
10
5
CSS
CSH
t
t
10
0
DS
t
DH
t
10
CSPWH
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t
C
C
= 20pF
= 20pF
20
DOD
LOAD
LOAD
t
1
DOE
t
10
RDS
Iote 1: Devices 100% production tested at T = +125°C. Guaranteed by design and characterization to T = -40°C.
A
A
Iote 2: Full scale in analog EQ mode decreases with increasing frequency at a rate of 20dB/decade from 8kHz. If digital EQ is also
used, full scale decreases with increasing frequency at 40dB/decade from 5kHz.
Iote 3: SFDR in the EQ mode is normalized to the input by subtracting the analog EQ gain at each frequency (20dB/decade) from
the FFT results.
Iote 4: The absolute input voltage range is 0 to AVDD. For optimal performance, use a common-mode voltage of AVDD/2.
Iote 5: Switched capacitor input impedance is proportional to 1/fC. Where f is the sampling frequency and C is the input capacitance.
Typical Operating Characteristics
(V
= +3.3V, V
= +3.0V, f
= f
= 19.2MHz, V
, V = +2.5V, common-mode input voltage = V
REF_
/2,
AVDD
AVDD
DVDD
SCLK
EXCLK
REFBP
T
A
= +25°C, unless otherwise noted.)
400ksps FFT
LP MODE
800ksps FFT
LP MODE
INL vs. CODE
5
0
-20
0
LP MODE
GAIN = 1
f
= 50kHz
IN
f
= 50kHz
4
3
IN
GAIN = 1
-20
-40
GAIN = 1
2
1
-40
-60
0
-60
-80
-1
-2
-3
-4
-5
-80
-100
-120
-140
-100
-120
0
0
16384
32768
49152
65536
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
0
50 100 150 200 250 300 350 400
FREQUENCY (kHz)
CODE (LSB)
Maxim Integrated
7
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Typical Operating Characteristics (continued)
(V
= +3.3V, V
= +3.0V, f
= f
= 19.2MHz, V
, V = +2.5V, common-mode input voltage = V
REF_
/2,
AVDD
AVDD
DVDD
SCLK
EXCLK
REFBP
T
A
= +25°C, unless otherwise noted.)
400ksps FFT
EQ MODE
800ksps FFT
EQ MODE
SINAD vs. INPUT AMPLITUDE
80
70
60
50
40
30
20
10
0
0
0
-20
f
= 100kHz
= 1.4mV
IN
f
= 5kHz
= 560mV
IN
V
INP-P
V
INP-P
-20
-40
-40
-60
50kHz
-60
-80
1kHz
-80
10kHz
-100
-120
-140
-100
-120
-10
-20
-90 -80 -70 -60 -50 -40 -30 -20 -10
INPUT AMPLITUDE (dBFS)
0
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
0
200
400
FREQUENCY (kHz)
FINE DAC INL
vs. CODE
FINE DAC SETTLING
25% TO 75% FS STEP
FINE DAC DNL
vs. CODE
MAX11043 toc09
5
4
1.0
0.8
3
0.6
2
0.4
500mV/div
1
0.2
0
0
-1
-2
-3
-4
-5
-0.2
-0.4
-0.6
-0.8
-1.0
0V
0
1024
2048
3072
4096
0
1024
2048
3072
4096
CODE (LSB)
CODE (LSB)
FINE DAC SETTLING
75% TO 25% FS STEP
FINE DAC SETTLING
1% STEP-UP
MAX11043 toc10
MAX11043 toc11
20mV/div
1200mV
500mV/div
0V
1µs/div
8
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Typical Operating Characteristics (continued)
(V
= +3.3V, V
= +3.0V, f
= f
= 19.2MHz, V
, V = +2.5V, common-mode input voltage = V
REF_
/2,
AVDD
AVDD
DVDD
SCLK
EXCLK
REFBP
T
A
= +25°C, unless otherwise noted.)
COARSE DAC DNL
vs. CODE
FINE DAC SETTLING
1% STEP-DOWN
FINE DAC NOISE FLOOR
MAX11043 toc13
MAX11043 toc12
1.0
0.8
0dBm
CODES 3 TO 255
0.6
20mV/div
1200mV
0.4
DACH
0.2
0
20dBm/div
-0.2
-0.4
-0.6
-0.8
-1.0
DACL
0
20 40 60 80 100 120 140 160 180 200
FREQUENCY (kHz)
0
64
128
CODE (LSB)
192
256
1µs/div
COARSE DAC INL
vs. CODE
COARSE DAC SETTLING TIME,
COARSE DAC SETTLING TIME,
NEGATIVE STEP
POSITIVE STEP
MAX11043 toc16
MAX11043 toc17
0.5
0.4
CODES 3 TO 255
0.3
0.2
200mV/div
200mV/div
0.1
DACH
0
-0.1
-0.2
-0.3
-0.4
-0.5
DACL
0
64
128
192
256
2ms/div
2ms/div
CODE (LSB)
POWER-ON RESET
vs. TEMPERATURE
DVREG VOLTAGE vs. TEMPERATURE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.369
2.368
2.367
2.366
2.365
2.364
2.363
2.362
ANALOG SUPPLY
DIGITAL SUPPLY
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Maxim Integrated
9
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Pin Description
PꢂI
IAME
AINBN
REFA
FUICTꢂOI
1
Channel B Analog Negative Input
2
3
Channel A Reference Bypass. Bypass REFA with a nominal 1µF capacitor to AGND.
Channel A Analog Negative Input
AINAN
AINAP
AVDD
4
Channel A Analog Positive Input
5, 26
6, 24, 33
7, 23
8, 22
9
Analog Supply. Bypass each AVDD with a nominal 1µF capacitor to AGND.
Analog Ground. Connect AGND inputs together.
AGND
DGND
DVDD
Digital Ground. Connect DGND inputs together.
Digital Supply. Bypass each DVDD with a nominal 1µF capacitor to DGND.
Regulated Digital Core Supply. Bypass DVREG to DGND with a 10µF capacitor.
DAC Step Direction Select. Drive high to step up, drive low to step down when DACSTEP is toggled.
DVREG
UP/DWN
10
DAC Step Input. Drive high to move the DAC output in the direction of UP/DWN on the next rising
edge of the system clock.
11
12
DACSTEP
CONVRUN
Convert Run. Drive high to start continuous conversions on all 4 channels. The device is idle when
CONVRUN is low.
13
14
CS
DOUT
DIN
Active-Low Serial-Interface Chip Select
Serial-Interface Data Out. Data transitions on the rising edge of SCLK.
Serial-Interface Data In. Data is sampled on the rising edge of SCLK.
Serial-Interface Clock
15
16
SCLK
I.C.
17, 35
18
Internally Connected. Connect to either AGND or DGND.
Active-Low End-of-Conversion Indicator. EOC asserts low to indicate that new data is ready.
Crystal Oscillator/External Clock Input
EOC
19
OSCIN
OSCOUT
SHDN
AOUT
20
Crystal-Oscillator Output. Leave unconnected when using external clock.
Active-High Shutdown Input. Drive high to shut down the MAX11043.
Buffered 12-Bit Fine DAC Output
21
25
27
REFDACL Fine DAC Low Reference Bypass. Bypass REFDACL with a nominal 1µF capacitor to AGND.
REFDACH Fine DAC High Reference Bypass. Bypass REFDACH with a nominal 1µF capacitor to AGND.
28
29
REFDAC
REFD
Coarse DAC Reference Bypass. Bypass REFDAC with a nominal 1µF capacitor to AGND.
Channel D Reference Bypass. Bypass REFD with a nominal 1µF capacitor to AGND.
Channel D Analog Negative Input
30
31
AINDN
AINDP
REFBP
AINCN
AINCP
REFC
32
Channel D Analog Positive Input
34
Main Reference Bypass. Bypass REFBP with a nominal 1µF capacitor to AGND.
Channel C Analog Negative Input
36
37
Channel C Analog Positive Input
38
Channel C Reference Bypass. Bypass REFC with a nominal 1µF capacitor to AGND.
Channel B Reference Bypass. Bypass REFB with a nominal 1µF capacitor to AGND.
Channel B Analog Positive Input
39
REFB
40
AINBP
Exposed Pad. Connect EP to a ground plane on the PCB to enhance thermal dissipation. Internally
connected to AGND. Not intended as an electrical connection point.
—
EP
10
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Functional Diagram
AVDD DVDD
AINAP
UP/DWN
PGA
EQ
PROGRAMMABLE
DIGITAL FILTER
SIGMA-DELTA
ADC
DACSTEP
CONVRUN
EOC
AINAN
SERIAL
INTERFACE
SHDN
REFA
SCLK
DOUT
AINBP
DIN
PGA
EQ
PROGRAMMABLE
DIGITAL FILTER
SIGMA-DELTA
ADC
AINBN
FLASH
REFB
MAX11043
AINCP
PGA
EQ
PROGRAMMABLE
DIGITAL FILTER
SIGMA-DELTA
ADC
POR
AINCN
DIGITAL SUPPLY
REFC
INTERNAL
REGULATOR
+2.5V
DVREG
AINDP
PROGRAMMABLE
DIGITAL FILTER
SIGMA-DELTA
ADC
PGA
EQ
AINDN
REFD
CLOCK
OSCOUT
OSCIN
CRYSTAL
OSCILLATOR
AND CLOCK
BUFFER
R
R
8-BIT
DAC
12-BIT DAC
+2.5V
VOLTAGE
REFERENCE
2x
AGND DGND
AOUT
REFBP
REFDAC
REFDACL REFDACH
Maxim Integrated
11
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
MAX11043 Signal Path
Detailed Description
Each of the 4 ADC channels features a PGA and filter
The MAX11043 features 4 single-ended or differential
block that feeds the signal to the sigma-delta modula-
channels of simultaneous-sampling ADCs with 16-bit
tor. The PGA can either be bypassed, which provides a
resolution. The MAX11043 contains a versatile filter
gain of 1, set to a gain of 8, a gain of 16, or set to ana-
block and PGA per channel. The filter consists of seven
log EQ mode. For more amplification, set the ADC mod-
cascaded 2nd-order filter sections for each channel
ulator gain to one, two, or four. After the modulator, the
allowing the construction of a 14th-order filter. The filter
result passes through the sinc 5 filter and decimator.
coefficients are user-programmable. Configure each
Seven biquad programmable digital filters isolate the
2nd-order filter as a LP filter, HP filter, or BP filter with
band of interest. Read the result using the 40MHz SPI
optional rectification. Gain and phase mismatch of the
interface. See Figure 1.
analog signal path is better than -50dB.
Analog-to-Digital Converter
The MAX11043 features a quad sigma-delta ADC archi-
tecture with 4 differential input channels. For single-
ended operation, connect the N input to the
common-mode voltage or bypass to AGND with a 10µF
capacitor. All inputs feature a programmable bias gen-
erator; see the CONFIG_ Register (0Ch–0Fh) section.
All four ADCs convert simultaneously with a maximum
modulator sampling rate of 9.6Msps; decimated by 12
or 24 for output rates of 800ksps and 400ksps, respec-
tively. The SPI bus limits the maximum output data rate
to 40Mbps.
The ADCs can digitize signals up to 200kHz. A 40MHz
serial interface provides communication to and from the
device. The SPI interface provides throughput of
1600ksps; 4 channels at 400ksps per channel or 2
channels at 800ksps per channel. A software-selec-
table scan mode allows reading the ADC results while
simultaneously updating the DAC. Other features of the
MAX11043 include an internal (+2.5V) or external
(+2.0V to +2.8V) reference, power-saving modes, and
a PGA with gains of 1 to 64. The PGA includes an EQ
function that automatically boosts low-amplitude, high-
frequency signals for applications such as CW-chirp
radar.
Sinc 5 Filter
The sinc 5 filter removes high-frequency noise from the
output of the sigma-delta modulator and sets the upper
frequency response of the ADC. It also decimates the
modulator data by a factor of 12, providing a maximum
of 800ksps to the programmable filters when the modu-
lator is operating at 9.6Msps. Figure 2 shows the fre-
quency characteristics of the sinc 5 filter with the
The MAX11043 includes two 8-bit coarse DACs that set
the high and low references for a second-stage 12-bit
fine DAC, typically used for VCO control. Use software
controls to set the DAC, or step the DAC up and down
using hardware control in programmable steps.
CHAN X FINE GAIN
RANGE: -4 TO +4
TOTAL
DECIMATION
DECSEL
DECIMATE
0
1
2
1
24
12
RESOLUTION = 16 BITS
FINE
GAIN
ADJUST
MODULATOR
WITH GAINS OF
1, 2, OR 4
SINC 5 FILTER AND
DECIMATE BY 12
BIQUAD
FILTER 1
BIQUAD
FILTER 7
DECIMATE
BY 1 OR 2
PGA AND
FILTER
IN
SPI
7 BIQUAD FILTERS IN SERIES
PGA AND FILTER MODES
BYPASS
PDPGA PGAG EQ
GAIN
MODG1 MODG0
BIQUAD MODES FILT
RAM
1
0
0
0
X
0
1
X
X
0
0
1
1
2
4
4
0
0
1
1
0
1
0
1
LP FILTER
1
0
X
POR VALUES
POR VALUES
USER VALUES
LP FILTER AND GAIN 8X
LP FILTER AND GAIN 16X
EQUALIZER
EQUALIZER
USER DEFINED
Figure 1. Signal Path
12
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
modulator running at 9.6Msps. Operating the modulator
at a lower sample rate causes a proportional reduction
in the frequency response of the sinc 5 filter. The total
attenuation of the MAX11043 is the sum of the analog
filtering, the sinc 5 filter, and the seven stages of pro-
grammable filters.
EOC asserts low when new data is available. Initiate a
data read prior to the next rising edge of EOC or the
result is overwritten. EOC asserts high upon read com-
pletion of all active channels. Use ConfigA, ConfigB,
ConfigC, and ConfigD registers to read single channel
data. Concatenated data is available in the ADCAB,
ADCCD, and ADCABCD registers. Use concatenated
registers to ensure simultaneous results are read. See
the Register Functions section for more details.
Equalizer (EQ)
The EQ matches the frequency/gain characteristics of
CW-chirp radar systems where the distance to the tar-
get is proportional to the measured frequency. Distant
targets not only have a higher frequency, they have a
weaker signal. Hence, higher frequencies need more
amplification than lower frequencies. The EQ provides
gain proportional to frequencies up to 190kHz, at which
point the gain rolls off at 80dB/decade.
A software-selectable scan mode automatically sends
the result from selected channels following the CS
falling edge and allows other registers to be simultane-
ously updated. To enable scan mode, set SCHAN_ bits
high. See the Configuration Register (08h) section for a
detailed description. The ADC output is presented in
two’s complement format (Figure 3).
The EQ consists of an analog section in the PGA and a
digital EQ created from the biquad filters. The analog
EQ (PGA) provides 20dB/decade of gain and the
default digital EQ provides an additional 20dB/decade
of gain. Together they provide 40dB/decade of gain up
to 190kHz with a gain of 0dB at 5kHz.
Digital Filter
Seven cascaded, individually configurable, 2nd-order
filter elements make up the digital filter. Figure 4 shows
the structure of a single filter section. Configure these
elements as LP, BP, HP, or all pass (AP) filters with
optional rectification. Filter configuration is transferred
from the flash to coefficient RAM (C-RAM) on power-up.
Store custom filters permanently in the flash or write
directly to C-RAM each time on power-up. Two sepa-
rate sets of programmable coefficients exist for each
filter. Dual coefficient sets allow rapid filter reconfigura-
tion. These filter coefficients are programmed to LP and
EQ modes at the factory. Multiple flash memory pages
exist so that custom filters can be created while pre-
serving factory-programmed filter coefficients.
Variations in the manufacturing process affect the gain
and phase of the analog filter. Compensation for these
variations include adjustments to the digital filter during
the manufacture of the MAX11043. Use the analog and
digital EQs together for optimal performance.
Conversion and ADC Reading
Drive CONVRUN high to initiate a continuous conver-
sion on all 4 channels. Keep CONVRUN high for the
entire conversion process. Do not pulse CONVRUN.
SINC 5 FILTER AT 9.6Msps
0
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
-20
-40
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
-60
-80
-100
-120
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
0
400
800
1200
1600
2000
-FS
-1
0
+1
+FS
FREQUENCY (kHz)
INPUT VOLTAGE (LSB)
Figure 2. Sinc 5 Filter Frequency Response
Maxim Integrated
Figure 3. Two’s Complement Transfer Function
13
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Filter coefficients A1 and B1 are always 1. B3 is limited
to -1, 0, and 1.
Fine Gain A/B/C/D Registers at the input of each filter
set. Fine gain adjustment has a resolution of 16 bits and
a gain range of -4 to +4. Set the RECT bit to rectify the
filter output.
Filter coefficients A2, A3, and B2 are stored as 16-bit
two’s complement values in the range of -4 to +4. Filter
coefficients A2 and A3 are stored as -A2 and -A3.
Figures 5–8 show the response to a step input of the
default filters used for ADC trimming.
Gain is limited to the following values 24, 22, 20, 2-2, 2-4,
2-6, 2-8, and 2-10. For better gain resolution, adjust the
RECT
G
SINC 5 FILTER OUTPUT
OUT
ABS
+
+
1/A1
B1
B2
+
IN
2500
2000
1500
1000
500
0
-1
Z
X
-A2
+
-1
Z
Y
0
2
4
6
8
10
-A3
B3
SAMPLE
Figure 5. Sinc 5 Filter Response to a Step Input
Figure 4. Single Programmable 2nd-Order Filter Section
Table 1. Default Filter Coefficients
DEFAUꢁT ꢁOWPASS FꢂꢁTER COEFFꢂCꢂEITS
STAGE
B1
1
B2
B3
A1
1
A2
A3
GAꢂI
+0
-2
1
2
3
4
5
6
7
+ 2.0 (typ)
+1.9509
+1.6139
+1.1488
+0.7415
+0.4651
+0.3296
+1.0000
+1.0000
+1.0000
+1.0000
+1.0000
+1.0000
+1.0000
+0.468 (typ)
+0.6874
+0.5936
+0.4395
+0.2715
+0.1310
+0.0493
+0.607 (typ)
+0.1317
+0.2015
+0.3258
+0.4851
+0.6685
+0.8788
1
1
1
1
-2
1
1
+0
+0
+0
+0
1
1
1
1
1
1
DEFAUꢁT EQUAꢁꢂZER COEFFꢂCꢂEITS
STAGE
B1
1
B2
B3
A1
1
A2
A3
GAꢂI
+0
+0
-2
1
2
3
4
5
6
7
+ 2.0 (typ)
+1.9401
+1.5458
+1.0518
+0.6785
-1.0000
+0.4902
+1.0000
+1.0000
+1.0000
+1.0000
+1.0000
+0.0000
+1.0000
+0.468 (typ)
+0.6886
+0.5803
+0.4139
+0.2563
+0.0039
+0.1649
+0.607 (typ)
+0.1359
+0.2275
+0.3887
+0.5966
-0.0000
1
1
1
1
1
1
+0
+0
+4
+2
1
1
1
1
1
1
+0.8489
14
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Programmable Gain Amplifier
Each ADC channel features an input buffer with input
impedance of at least 5kΩ and programmable gain of
eight or 16. When set to a gain of one, the signal
bypasses the PGA to reduce noise.
the step size. The UP/DWN input sets the direction of
the step. Drive UP/DWN high to step up, drive low to
step down.
The coarse 8-bit, dual tap DAC generates the high and
low reference values for the fine DAC. Obtain the
coarse DAC reference from the main reference or by
driving the REFDAC input externally. The main refer-
ence, REFBP, is divided by two before the coarse DAC.
When driving REFDAC, REFDACH, or REFDACL direct-
ly, ensure the voltage to the fine DAC does not exceed
AVDD/2 to prevent the output amplifier from saturating.
The PGA features an optional 20dB/decade analog EQ
mode, with a gain of 0dB near 8kHz and attenuation
above 190kHz to reduce out-of-band noise. Using the
digital EQ filter adds another 20dB/decade of gain and
sets the 0dB frequency to 5kHz. Control the EQ and
PGA gain from their respective CONFIG_ registers. For
additional filtering and equalization, use the integrated
digital filters.
LP FILTER OUTPUT
Digital-to-Analog Converter
The MAX11043 features a 12-bit fine DAC with high and
low reference inputs set by the 8-bit, dual tap coarse DAC
or driven externally. The output buffer of the fine DAC has
a gain of two and can drive 10kΩ and 200pF in parallel.
Bypass the REFDACH and REFDACL with a 1µF capaci-
tor when using the coarse DAC to set the reference
values, or power down the buffers and drive REFDACH
and REFDACL with external references. Alternatively
drive one of the fine DAC references using the coarse
DAC and the other using an external reference.
2500
2000
1500
1000
500
0
The fine DAC register contains the current value of the
output. The output value changes by writing to this reg-
ister or by the rising edge of the DACSTEP input. The
DAC register updates on the next rising edge of the
system clock following the rising edge of the DACSTEP
input. The programmable DACSTEP register contains
0
20
40
60
80
100
SAMPLE
Figure 7. LP Filter Response to a Step Input
STAGE 1 FILTER OUTPUT
EQ FILTER OUTPUT
3500
35,000
30,000
25,000
20,000
15,000
10,000
5000
3000
2500
2000
1500
1000
500
0
-5000
-10,000
-15,000
-20,000
0
-500
0
10
20
30
40
50
0
20
40
60
80
100
SAMPLE
SAMPLE
Figure 6. EQ Filter Response to a Step Input
Maxim Integrated
Figure 8. Stage 1 Default Filter Response to a Step Input
15
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
The system clock, used for all internal timing, is derived
from the clock divider setting and the input clock.
Reference (REFBP)
The MAX11043 features an internal 2.5V bandgap ref-
erence. Bypass REFBP with a 1µF capacitor or power
down the buffer amplifier and drive REFBP with an
external reference. In internal reference mode, REFBP
provides the main reference voltage for the MAX11043.
For optimal performance, derive the SPI clock and sys-
tem clock from the same source.
Power Saving
The MAX11043 features an active-high power-down
input, as well as an SPI-controlled power-down bit that
places the MAX11043 in low-power mode. In addition,
the MAX11043 features an independent, SPI-controlled,
power-down for each ADC channel, the DAC, and the
oscillator. See the Configuration Register (08h) section
for more details.
Refer to www.maximintegrated.com/references for a
list of available precision references.
In addition to the integrated main reference, there are
seven separate references derived from REFBP, one for
each ADC channel, one for the coarse DAC, and two
(one high and one low) for the fine DAC. When using
the main reference, bypass each of the references with
a 1µF capacitor or set the appropriate bits (7–0), in the
reference (10h) register, to power down the references
and drive externally. Use external references capable
of driving a 700µA or total load.
Serial Communication
The SPI-compatible interface allows synchronous serial
data transfers up to 40Mbps. The bandwidth is divided
between the DACs and the ADC. Maximum conversion
throughput depends on which read commands are
used. The highest conversion rates are obtained by
using the scan mode. The second highest rate is
obtained by reading concatenated registers. The slow-
est method is to read the results individually.
Clock Sources
The MAX11043 features an internal 16MHz oscillator
that supports either an external crystal or ceramic res-
onator. For highest performance, set bit 15 in the con-
figuration register to 1 and use an external clock (EX
clock) source, up to 40MHz, to drive OSCIN. A pro-
grammable clock divider divides the EX clock by 2, 3,
4, or 6 to generate the ADC sample clock. The system
clock, used for all digital timing, is twice the ADC sam-
ple clock. Ensure that the minimum EX clock high or
low time is greater than 25ns when using the divide-by-
2 or divide-by-3 mode.
Configure the SPI master for SCLK to idle low (SCLK is
low when CS is asserted). The data at DIN is latched on
the rising edge of SCLK. Data at DOUT transitions
immediately after the rising edge of SCLK.
All SPI transactions start with a command byte. The
command byte selects the address of the register and
the mode of operation (read/write).
SPꢂ Command Byte
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
START
ADR4
ADR3
ADR2
ADR1
ADR0
R/W
0
START<7>: Start bit. This bit must be 0 for normal
operation.
R/W<1>: Read/write bit. 1 = read from device. 0 = write
to device.
ADR_<6:2>: Device register address bits. See the reg-
ister map in Table 2.
16
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
t
CP
t
t
DS
CSH
t
CSS
t
CH
t
DH
CS
t
CL
SCLK
DIN
START
HIGH IMPEDANCE
ADR 4 ADR 3 ADR 2 ADR 1 ADR 0
0
R/W = 0
D7
D6
D5
D4
D3
D2
D1
D0
X
HIGH IMPEDANCE
DOUT
Figure 9. SPI 8-Bit Write Operation
t
CSS
t
t
t
DOD
DOT
CP
t
DS
t
DOE
t
CH
t
t
CL
DH
CS
SCLK
DIN
START
HIGH IMPEDANCE
X
X
X
X
ADR 3 ADR 2 ADR 1 ADR 0 R/W = 1
0
ADR 4
X
X
X
X
X
HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
DOUT
Figure 10. SPI 8-Bit Read Operation
Maxim Integrated
17
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Register Map
Table 2. SPꢂ Register Map
ADDRESS
00h
REGꢂSTER IAME
ADCA
FUICTꢂOI
ADC channel A result register
BꢂTS
16/24
16/24
16/24
16/24
32/48
32/48
64/96
8
01h
ADCB
ADC channel B result register
ADC channel C result register
ADC channel D result register
ADC channels A and B results register
ADC channels C and D results register
ADC channels A, B, C, and D results register
Status register
02h
ADCC
03h
ADCD
04h
ADCAB
ADCCD
ADCABCD
Status
05h
06h
07h
08h
Configuration
DAC
Configures the device
16
09h
Fine DAC value
16
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
DACSTEP
DACH/DACL
ConfigA
ConfigB
ConfigC
ConfigD
Reference/Delay
AGain
Step size for DAC increment/decrement function
High and low coarse DAC values
ADC channel A configuration
ADC channel B configuration
ADC channel C configuration
ADC channel D configuration
Sets the operation state of the reference and buffers
Channel A fine gain
16
8 + 8
16
16
16
16
10h
16
11h
16
12h
BGain
Channel B fine gain
16
13h
CGain
Channel C fine gain
16
14h
DGain
Channel D fine gain
16
Selects the filter coefficient to read or write. This autoincrements
each time the coefficient data register is accessed.
15h
Filter coefficient address
8
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Filter coefficient data out
Filter coefficient data in
Flash mode
Coefficient RAMs output data
32
32
8
Filter coefficient data
Flash mode selection register
Flash addr
Flash address register
16
16
16
—
—
—
—
Flash data in
Flash data out
Reserved
Flash data in register
Flash data out register
—
—
—
—
Reserved
Reserved
Reserved
18
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
ADCAB, ADCCD, and ADCABCD
Result Registers (ꢀ4h–ꢀ6h)
Registers ADCAB, ADCCD, and ADCABCD contain
concatenated ADC results ensuring simultaneous
results are read. This reduces the risk of reading sam-
ples delayed by one cycle from channel to channel.
Register Functions
ADCA, ADCB, ADCC, and ADCD
Result Registers (ꢀꢀh–ꢀ3h)
The ADC channel A, B, C, and D result registers pro-
vide the result data from the 4 ADC channels. EOC
asserts low when new data is available. Initiate a data
read prior to the next rising edge of EOC or the result is
overwritten. Set bit 5 of the configuration register 08h
high to read the data out in 24-bit resolution or set bit 5
low to read the data out in 16-bit resolution.
Set bit 5 of the configuration register 08h high to read
the data out in 24-bit resolution or set bit 5 low to read
the data out in 16-bit resolution.
Status Register (ꢀ7h)
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
X
X
Flash Busy
BOOT
OFLGA
OFLGB
OFLGC
OFLGD
The status register contains the channel overflow flags
and POR bits.
BOOT<4>: Power-on reset flag.
OFꢁG_<3:ꢀ>: Channel overflow flag, one per channel.
X<7:6>: Don’t-care bits.
Flash Busy<5>: Do not start a new flash operation until
this is 0.
Configuration Register (ꢀ8h)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
EXTCLK
CLKDIV1
CLKDIV0
PD
PDA
PDB
PDC
PDD
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
PDDAC
PDOSC
24BIT
SCHANA
SCHANB
SCHANC
SCHAND
DECSEL
EXTCꢁK<15>: External clock select.
PD_<11:8>: ADC power-down for each channel (A, B,
C, and D).
1 = logic-level clock supplied on OSCIN.
1 = powers down analog signal path.
0 = normal operation (default).
0 = crystal or resonator connected between OSCIN
and OSCOUT (default).
CꢁKDꢂV1:CꢁKDꢂVꢀ<14:13>: Clock divider ratio (EX
PDDAC< 7>: DAC power-down.
1 = fine DAC buffer powered down.
0 = normal operation (default).
clock : ADC sample clock).
00 = 1:2 clock divider.
01 = 1:3 clock divider.
PDOSC<6>: Oscillator power-down.
10 = 1:4 clock divider.
1 = oscillator powered down (disconnects EX clock in
EX clock mode).
11 = 1:6 clock divider (default).
PD<12>: Power-down analog circuitry (reference and
0 = normal operation (default).
SPI interface remains active).
24BꢂT<5>: ADC output data format.
1 = ADC data output as 24 bits.
0 = ADC data output as 16 bits (default).
1 = low-power mode.
0 = normal operation (default).
Use the 24-bit ADC output in conjunction with external
digital filtering to improve signal-to-noise ratio.
Maxim Integrated
19
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
SCHAI_<4:1>: Automatic ADC result output for each
after the falling edge of EOC. EOC goes high after the
last bit of the selected channels clocks out or one clock
cycle before the next result is ready. Insufficient SCLK
pulses result in truncated data. Extra clock pulses give
an undefined output. In scan mode, keep DIN high or
write data to the MAX11043 as usual. In scan mode,
the MAX11043 ignores requests for data reads.
channel (A, B, C, and D).
1 = ADC channel data is output on DOUT each time a
new result is valid in the sequence, A, B, C, and D.
0 = ADC data is not presented automatically for this
channel (default).
When SCHAN_ = 1, the selected ADC channel data is
automatically presented on DOUT each time EOC
asserts low in the sequence A, B, C, and D with the
unselected channels omitted. The data transitions on
the rising edge of SCLK. Force CS low to initiate trans-
mission. CS can go high between results. The MSB of
the first selected ADC channel outputs immediately
DECSEꢁ<ꢀ>: Decimate select.
1 = decimate by 12.
0 = decimate by 24 (default).
Set DECSEL high to decimate the ADC result by 12,
doubling the number of samples. The SPI interface is
limited to 40Mbps.
Fine DAC Register (ꢀ9h)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
X
X
X
X
DAC11
DAC10
DAC9
DAC8
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
X<15:12>: Don’t-care bits.
value, this register updates to the new value on the
next rising edge of the system clock following the rising
edge of DACSTEP. The power-on default is 0.
DAC_<11:ꢀ>: Contains current fine DAC output value.
When using the DACSTEP input to change the DAC
DACSTEP Register (ꢀAh)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
X
X
X
X
DACSTEP11
DACSTEP10
DACSTEP9
DACSTEP8
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
DACSTEP7
DACSTEP6
DACSTEP5
DACSTEP4
DACSTEP3
DACSTEP2
DACSTEP1
DACSTEP0
X<15:12>: Don’t-care bits.
the fine DAC register updates on the next rising edge
of the system clock following the rising edge of the
DACSTEP input. The power-on default is 0.
DACSTEP11:DACSTEPꢀ<11:ꢀ>: Provides the size of
the DAC step. The value is positive only and the
UP/DWN input is used to set the direction. The value in
Coarse DACH/DACꢁ Register (ꢀBh)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
DACH7
DACH6
DACH5
DACH4
DACH3
DACH2
DACH1
DACH0
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
DACL7
DACL6
DACL5
DACL4
DACL3
DACL2
DACL1
DACL0
DACH7:DACHꢀ<15:8>: High coarse DAC value.
DACꢁ7:DACꢁꢀ<7:ꢀ>: Low coarse DAC value.
Coarse DAC sets high and low references for the fine
DAC. The power-on default is 0.
20
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
COIFꢂG_ Register (ꢀCh–ꢀFh)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
X
X
X
BDAC3
BDAC2
BDAC1
BDAC0
DIFF
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
EQ
MODG1
MODG0
PDPGA
FILT
PGAG
ENBIASP
ENBIASN
This register sets the input gain of each ADC channel
and selects one of the default filters or EQ function.
EQ<7>: EQ function.
1 = analog EQ enabled.
X<15:13>: Don’t-care bits.
0 = analog EQ disabled (default).
BDAC3:BDACꢀ<12:9>: Sets the input bias voltage for
AC-coupled signals when ENBIAS_ is set to 1.
MODG1:MODGꢀ<6:5>: ADC modulator gain.
00 = 1 (default).
0000 = 33% of AVDD.
0001 = 35% of AVDD.
0010 = 38% of AVDD.
0011 = 40% of AVDD.
0100 = 42% of AVDD.
0101 = 44% of AVDD.
0110 = 46% of AVDD.
0111 = 48% of AVDD.
1000 = 50% of AVDD.
1001 = 52% of AVDD.
1010 = 54% of AVDD.
1011 = 56% of AVDD.
1100 = 58% of AVDD.
1101 = 60% of AVDD.
1110 = 62% of AVDD.
1111 = 65% of AVDD.
DꢂFF<8>: Input mode select bit.
1 = normal operation in all modes.
01 = 2.
10 = 4.
11 = 4.
PDPGA<4>: PGA power-down control.
1 = PGA powered down, gain = 1.
0 = PGA powered, PGA gain set by PGAG (default).
FꢂꢁT<3>: Programmable filter select.
1 = use preprogrammed LP filter.
0 = use preprogrammed EQ filter (default).
PGAG<2>: High PGA gain setting.
1 = PGA, gain = 16.
0 = PGA, gain = 8 (default).
EIBꢂASP<1>: Positive input bias enable. Bias voltage
set by BDAC3:BDAC0.
1 = selfbiasing enabled.
0 = selfbiasing disabled (default).
EIBꢂASI<ꢀ>: Negative input bias enable. Bias volt-
age set by BDAC3:BDAC0.
0 = use for a 2x input signal range in LP, gain = 1
mode. Note that THD degrades.
1 = selfbiasing enabled.
0 = selfbiasing disabled (default).
Maxim Integrated
21
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Reference Register (1ꢀh)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
0
0
0
PURGE4
PURGE3
PURGE2
PURGE1
PURGE0
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
EXTREF
EXBUFA
EXBUFB
EXBUFC
EXBUFD
EXBUFDAC
EXBUFDACH
EXBUFDACL
Reserved<15:13>: Reserved. Set to 0.
EXTREF<7>: Main reference selection.
PURGE4:PURGEꢀ<12:8>: Filter purge interval.
Straight binary.
1 = external reference applied to REFBP, internal refer-
ence buffer powered down.
00h = first available sample is presented (default).
1Fh = 31 results are discarded.
0 = internal reference, bypass REFBP with 1µF to
AGND (default).
EXBUF_<6:3>: ADC reference selection for each
channel.
Digital filters retain a history of past input data. At
power-up and when changing the signal path, old data
requires purging before new output data is valid.
PURGE4(MSB):PURGE0 determine the number of sam-
ples to discard before a new result is valid. Each time
CONVRUN is taken high, N results are discarded
before EOC asserts low (where N is the decimal equiva-
lent of the binary representation of PURGE4:PURGE0).
Results prior to N+1 are overwritten. EOC asserts for
results N+1, N+2, N+3, etc., as long as CONVRUN
remains high. Taking CONVRUN low and then high
invokes another purge.
1 = external reference applied to REF_ input, internal
switch open.
0 = using main internal reference, bypass REF_ with
1µF to AGND (default).
EXBUFDAC<2>: Coarse DAC reference selection.
1 = external reference applied to REFDAC, internal ref-
erence buffer powered down.
0 = using main internal reference, bypass REFDAC
with 1µF to AGND (default).
Purging of the sinc 5 filter requires five readings if
DECSEL (configuration register 08h, bit 0) = 1 and
three readings if DECSEL = 0. The minimum total purge
interval of the seven cascaded filters is one reading if
not used. If the filters are used, the total latency of the
programmable filters is the sum of the latency caused
by each stage. Set the appropriate delay for filter purg-
ing and settling time.
EXBUFDACH<1>: High reference for fine DAC.
1 = external reference applied to REFDACH, internal
reference buffer powered down.
0 = using high output from coarse DAC as reference,
bypass REFDACH with 1µF to AGND (default).
EXBUFDACꢁ<ꢀ>: Low reference for fine DAC.
1 = external reference applied to REFDACL, internal
reference buffer powered down.
0 = using low output from coarse DAC as reference,
bypass REFDACL with 1µF to AGND (default).
22
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Fine Gain A/B/C/D Registers (11h–14h)
Fine gain for each channel is a two’s complement binary value (8192 x desired gain).
FꢂIE GAꢂI REGꢂSTER
GAꢂI
(4 – 1/8192)
2
7FFFh
4000h
2001h
2000h
1FFFh
1000h
0800h
8193/8192
1 (default)
8191/8192
0.5
0.25
Filter Coefficient Address Register (15h)
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
CHAN1
CHAN0
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
CHAI_<7:6>: Channel selection.
00 = channel A (default).
01 = channel B.
Filter Coefficient Data Out Register (16h)
This is a 32-bit register that contains the data from a
C-RAM read operation.
10 = channel C.
Filter Coefficient Data ꢂn Register (17h)
This is a 32-bit register that contains the data for a C-RAM
write operation. Default = 0.
11 = channel D.
ADR5:ADRꢀ<5:ꢀ>: Address pointer for C-RAM con-
taining filter coefficients (default = 0).
Maxim Integrated
23
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Flash Mode Register (18h)
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
FM2
FM1
FM0
Flash busy
(read only)
0
X
X
X
(Flashmode2) (Flashmode1) (Flashmode0)
Write allowed only if flash busy bit is zero.
FM2:FMꢀ<7:5>: Flash operation (default 0).
000 = no operation.
110 = transfer data from flash to C-RAM.
111 = no operation.
Reserved<4>: Reserved. Set to 0.
X<3:1>: Don’t-care bits.
Flash busy<ꢀ>: Flash busy flag.
1 = flash busy.
001 = write data in flash data in register to flash.
010 = erase data in the selected page.
011 = mass erase the flash.
100 = no operation.
0 = flash ready.
101 = read data from flash into data out register.
Flash Address Register (19h)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
X
X
X
X
X
PAGE2
PAGE1
PAGE0
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
ADR7
ADR6
ADR5
ADR5
ADR3
ADR2
ADR1
ADR0
Write allowed only if flash busy bit is zero (18h bit 0 or
status register) (default = 0).
011 = page 3.
100 = page 4.
101 = page 5.
110 = page 6.
111 = page 7.
X<15:11> : Don’t-care bits.
PAGE2:PAGEꢀ<1ꢀ:8>: Page selection.
000 = page 0 (default).
001 = page 1.
ADR7:ADRꢀ<7:ꢀ>: Address pointer flash word con-
taining filter coefficients (default = 0).
010 = page 2.
24
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Flash Data ꢂn Register (1Ah)
Write allowed only if flash busy bit is zero.
pensate for manufacturing variations in the analog por-
tion of the IC. These coefficients vary depending on the
PGA gain setting and if the analog equalizer is used. To
allow for these different modes, several sets of stage 1
coefficients are stored in flash. Bits in the CONGIF reg-
ister select which set of stage 1 coefficients are used.
Table 3 shows the C-RAM addresses used for each
CONFIG setting. To maintain optimum performance
when using custom filters, copy the trim data from flash
pages zero and one to the corresponding locations in
flash pages two and three or to C-RAM when writing
directly to C-RAM.
This is a 16-bit register that contains the data for a flash
write operation. Default = 0.
Flash Data Out Register (1Bh)
This is a read-only register. Data is valid only if flash
busy is zero.
This is a 16-bit register that contains the data for a flash
read operation.
Flash and C-RAM Register Map
The flash memory consists of 2048 words by 16 bits. The
3 MSBs of the flash address select one of eight pages of
256 words each. Page zero contains the default filter
coefficients for channels A and B. Page one contains the
default filter coefficients for channels C and D. Use
pages two and three for the coefficients of custom filters.
When the first word on page two contains a nonzero
value, the MAX11043 loads these pages into C-RAM at
power-up instead of the default values from pages zero
and one. Flash pages zero and one include trim data.
Unique trim data optimizes the performance of each
MAX11043. Coefficients for the stage 1 filters and ADC
gain are individually programmed at the factory to com-
For custom filters, use stages 2–7 first, and only change
the stage 1 coefficients when all seven stages require
customization.
To load the coefficients directly to C-RAM, create a 32-
bit data word by concatenating the data in adjacent
flash locations as shown in Table 3. The C-RAM
addresses below are for channel A; for channel B add
40h, for channel C add 80h, and for channel D add C0h.
Multiple addresses exist for some stage 1 filter coeffi-
cients as shown in Table 4. The address accessed by
the filter depends on the configuration bits as shown in
Table 3.
Table 3. Stage 1 Filter Selection
STAGE 1 COEFFꢂCꢂEIT ADDRESS
EQ filter stage 1 (C-RAM address 03h–05h)
EQ
1
PDPGA
MODG
XX
PGAG
0
1
0
0
X
X
0
1
LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dh–1Fh)
LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dh–3Fh)
LP filter for ADC gain of 16; stage 1 (C-RAM address 23h–25h)
X
XX
0
00
0
XX
Table 4. C-RAM and Flash Memory Map for Channel A Flash Page One*
C-RAM
ADDRESS
FꢁASH
ADDRESS
MSB FOR C-RAM
ꢁSB FOR C-RAM
00h
01h*
02h
—
Not used
Not used
Not used
00h
01h
02h
03h
EQ gain trim for gain = 1
—
—
—
—
03h
User trim for EQ gain, default = 2000h
04h
—
05h
Not used
06h*
07h*
—
EQ filter gain for filter stage 1
—
EQ filter coefficient -A2 for filter stage 1
*For channel B add 80h, for channel C add 100h, and for channel D add 180h. To write to pages two and three of flash, add 200h to
these values.
Maxim Integrated
25
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Table 4. C-RAM and Flash Memory Map (continued)
C-RAM
ADDRESS
FꢁASH
ADDRESS
MSB FOR C-RAM
ꢁSB FOR C-RAM
08h
09h*
0Ah*
0Bh*
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
—
Not used
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
EQ filter coefficient -A3 for filter stage 1
—
—
EQ filter coefficient B3 and rectify bit for filter stage 1
EQ filter coefficient B2 for filter stage 1
—
—
EQ filter gain for filter stage 2
EQ filter coefficient -A2 for filter stage 2
—
—
Not used
EQ filter coefficient -A3 for filter stage 2
—
—
EQ filter coefficient B3 and rectify bit for filter stage 2
EQ filter coefficient B2 for filter stage 2
—
—
EQ filter gain for filter stage 3
EQ filter coefficient -A2 for filter stage 3
—
—
Not used
EQ filter coefficient -A3 for filter stage 3
—
—
EQ filter coefficient B3 and rectify bit for filter stage 3
EQ filter coefficient B2 for filter stage 3
—
—
EQ filter gain for filter stage 4
EQ filter coefficient -A2 for filter stage 4
—
—
Not used
EQ filter coefficient -A3 for filter stage 4
—
—
EQ filter coefficient B3 and rectify bit for filter stage 4
EQ filter coefficient B2 for filter stage 4
—
—
EQ filter gain for filter stage 5
EQ filter coefficient -A2 for filter stage 5
—
—
Not used
EQ filter coefficient -A3 for filter stage 5
—
—
EQ filter coefficient B3 and rectify bit for filter stage 5
EQ filter coefficient B2 for filter stage 5
—
—
EQ filter gain for filter stage 6
EQ filter coefficient -A2 for filter stage 6
—
—
Not used
EQ filter coefficient -A3 for filter stage 6
—
—
EQ filter coefficient B3 and rectify bit for filter stage 6
EQ filter coefficient B2 for filter stage 6
—
—
EQ filter gain for filter stage 7
EQ filter coefficient -A2 for filter stage 7
—
—
Not used
EQ filter coefficient -A3 for filter stage 7
—
26
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Table 4. C-RAM and Flash Memory Map (continued)
C-RAM
ADDRESS
FꢁASH
ADDRESS
MSB FOR C-RAM
ꢁSB FOR C-RAM
2Eh
2Fh
—
EQ filter coefficient B3 and rectify bit for filter stage 7
17h
18h
19h
1Ah
1Bh
1Ch
EQ filter coefficient B2 for filter stage 7
—
30h
—
Not used
31h*
32h
ADC gain trim for gain = 1
—
—
Not used
33h*
34h
ADC gain trim for gain = 2
—
—
Not used
35h*
36h
ADC gain trim for gain = 4
—
—
Not used
37h*
38h
EQ gain trim for gain = 2
—
—
EQ gain trim for gain = 4
—
Not used
39h*
3Ah*
—
LP filter gain for filter stage 1, gain = 1, 2, or 4
1Dh
1Eh
LP filter coefficient -A2 for filter stage 1,
gain = 1, 2, or 4
3Bh*
3Ch
—
—
Not used
LP filter coefficient -A3 for filter stage 1,
gain = 1, 2, or 4
3Dh*
—
LP filter coefficient B3 and rectify bit for filter stage 1,
gain = 1, 2, or 4
3Eh*
3Fh*
—
1Fh
LP filter coefficient B2 for filter stage 1,
gain = 1, 2, or 4
—
40h
41h*
42h
43h
44h
45h
46h*
—
Not used
20h
21h
22h
ADC gain trim for gain = 16
—
—
Not used
User trim for ADC gain, default = 2000h
—
—
Not used
Not used
—
—
LP filter gain for filter stage 1, gain = 16
23h
24h
LP filter coefficient -A2 for filter stage 1,
gain = 16
47h*
48h
—
—
Not used
LP filter coefficient -A3 for filter stage 1,
gain = 16
49h*
—
LP filter coefficient B3 and rectify bit for filter stage 1,
gain = 16
4Ah*
4Bh*
—
25h
LP filter coefficient B2 for filter stage 1,
gain = 16
—
4Ch
4Dh
—
LP filter gain for filter stage 2
—
26h
LP filter coefficient -A2 for filter stage 2
Maxim Integrated
27
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Table 4. C-RAM and Flash Memory Map (continued)
C-RAM
ADDRESS
FꢁASH
ADDRESS
MSB FOR C-RAM
ꢁSB FOR C-RAM
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h*
—
Not used
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
LP filter coefficient -A3 for filter stage 2
—
—
LP filter coefficient B3 and rectify bit for filter stage 2
LP filter coefficient B2 for filter stage 2
—
—
LP filter gain for filter stage 3
LP filter coefficient -A2 for filter stage 3
—
—
Not used
LP filter coefficient -A3 for filter stage 3
—
—
LP filter coefficient B3 and rectify bit for filter stage 3
LP filter coefficient B2 for filter stage 3
—
—
LP filter gain for filter stage 4
LP filter coefficient -A2 for filter stage 4
—
—
Not used
LP filter coefficient -A3 for filter stage 4
—
—
LP filter coefficient B3 and rectify bit for filter stage 4
LP filter coefficient B2 for filter stage 4
—
—
LP filter gain for filter stage 5
LP filter coefficient -A2 for filter stage 5
—
—
Not used
LP filter coefficient -A3 for filter stage 5
—
—
LP filter coefficient B3 and rectify bit for filter stage 5
LP filter coefficient B2 for filter stage 5
—
—
LP filter gain for filter stage 6
LP filter coefficient -A2 for filter stage 6
—
—
Not used
LP filter coefficient -A3 for filter stage 6
—
—
LP filter coefficient B3 and rectify bit for filter stage 6
LP filter coefficient B2 for filter stage 6
—
—
LP filter gain for filter stage 7
LP filter coefficient -A2 for filter stage 7
—
—
Not used
LP filter coefficient -A3 for filter stage 7
—
—
LP filter coefficient B3 and rectify bit for filter stage 7
LP filter coefficient B2 for filter stage 7
—
—
Not used
Not used
—
—
Not used
Not used
—
—
—
Not used
ADC gain trim for gain = 8
28
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Table 4. C-RAM and Flash Memory Map (continued)
C-RAM
ADDRESS
FꢁASH
ADDRESS
MSB FOR C-RAM
ꢁSB FOR C-RAM
76h
77h*
78h
—
Not used
Not used
3Bh
3Ch
ADC gain trim for gain = 32
—
—
—
ADC gain trim for gain = 64
—
79h*
7Ah*
LP filter gain for filter stage 1, gain = 8
3Dh
3Eh
LP filter coefficient -A2 for filter stage 1,
gain = 8
7Bh*
7Ch
—
—
Not used
LP filter coefficient -A3 for filter stage 1,
gain = 8
7Dh*
—
LP filter coefficient B3 and rectify bit for filter stage 1,
gain = 8
7Eh*
7Fh*
—
3Fh
LP filter coefficient B2 for filter stage 1,
gain = 8
—
*Recommended copy to C-RAM or flash for optimum custom-filter performance.
2) Write page and word address to the flash address
Flash Erase and Programming
When erasing or programming the flash, maintain the
system clock between 14MHz and 27MHz to satisfy
flash timing requirements and ensure CONVRUN = 0.
The system clock used for all digital timing is twice the
ADC sample clock (2 x EX clock/divider).
register (19h).
3) Write the data to the flash data in register (1Ah).
4) Write 20h to the flash mode register (18h).
5) Read the flash mode register (18h); proceed when
the LSB is zero (approx. 40µs).
Always erase the flash page before writing new data.
The procedure for flash single word read is as follows:
The procedure for flash mass erase is as follows:
1) Read the flash mode register (18h); proceed when
the LSB is zero.
1) Read the flash mode register (18h); proceed when
the LSB is zero.
2) Write page and word address to the flash address
register (19h).
2) Write 0000h to the flash address register (19h).
3) Write 60h to the flash mode register (18h).
4) Wait 200ms for erase to complete.
3) Write A0h to the flash mode register (18h).
4) Read the flash mode register (18h); proceed when
the LSB is zero (approx. 1µs).
5) FFFFh = flash erased state.
The procedure for flash single page erase is as follows:
5) Read the data from the flash data out register (1Bh).
1) Read the flash mode register (18h); proceed when
the LSB is zero.
The procedure for flash to C-RAM transfer is as follows:
1) Read the flash mode register (18h); proceed when
the LSB is zero.
2) Write page address, set word address to 00h in the
flash address register (19h).
2) Write C0h to the flash mode register (18h).
3) Write 40h to the flash mode register (18h).
4) Wait 20ms for page erase to complete.
5) FFFFh = flash erased state.
3) Read the flash mode register (18h); proceed when
the LSB is zero (approx. 1ms).
4) The content of flash is transferred to C-RAM.
The procedure for flash single word write is as follows:
1) Read the flash mode register (18h); proceed when
the LSB is zero.
Maxim Integrated
29
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Digital Filter Coefficients
Table 5. Typical Filter Coefficients Register Map (ꢁP Filter Channel A, Stage 3)
COEFFꢂCꢂEIT FꢁASH ADDRESS
FUICTꢂOI
52h
53h
54h
55h
56h
57h
Gain for channel A, stage 3
A2 coefficient for channel A, stage 3
Not used; set to 0
A3 coefficient for channel A, stage 3
B3 coefficient and rectify flag (RECT) for channel A, stage 3
B2 coefficient for channel A, stage 3
Format for Filter Stage Gain (52h)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
X
GAIN2
GAIN1
GAIN0
X
X
X
X
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
X
X
X
X
X
X
X
X
X<15>: Don’t-care bit. Not used.
100 = 2-4 = 0.0625.
GAꢂI2:GAꢂIꢀ<14:12>: Filter gain.
000 = 24 = 16.
001 = 22 = 4.
101 = 2-6 = 0.015625.
110 = 2-8 = 0.00390625.
111 = 2-10 = 0.0009765625.
010 = 20 = 1.
X<11:ꢀ>: Don’t-care bits. Not used.
011 = 2-2 = 0.25.
30
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
A2, A3, and B2 Filter Coefficient
Format (52h, 54h, 56h)
Example 1:
N = 2.381
Filter coefficients A2, A3, and B2 are stored as 16-bit
A2 = int (2.381 x 213)
A2 = int (19505.152)
A2 = 19505 = 4C31h (two’s complement)
Example 2:
two’s complement values in the -4 to (4 - 2-13) range.
The transfer function equation is as follows:
A2 = int (N x 213)
where N is the decimal coefficient value.
N = -2.381
The following are two examples of the transfer function
equation:
A2 = int (-2.381 x 213)
A2 = int (-19505.152)
A2 = -19505 = B3CFh (two’s complement)
B3 Coefficient (56h)
BꢂT 15
BꢂT 14
BꢂT 13
BꢂT 12
BꢂT 11
BꢂT 1ꢀ
BꢂT 9
BꢂT 8
B31
B30
RECT
X
X
X
X
X
BꢂT 7
BꢂT 6
BꢂT 5
BꢂT 4
BꢂT 3
BꢂT 2
BꢂT 1
BꢂT ꢀ
X
X
X
X
X
X
X
X
B31:B3ꢀ<15:14>: Filter coefficient B3.
X<13>: Don’t-care bit. Not used.
RECT<12>: Rectify bit.
11 = -1.
00 = 0.
01 = 1.
10 = 0.
0 = bipolar output.
1 = output rectified. All samples positive.
X<11:ꢀ>: Don’t-care bits. Not used.
point) at AGND, separate from the logic ground.
Connect all other analog grounds and DGND to this
star ground point. Do not connect other digital system
grounds to this single-point analog ground. The ground
return to the power supply for this ground should be
low impedance and as short as possible for noise-free
operation. Bypass all supplies to ground with high
quality capacitors as close as possible to the device.
Power Supplies, Layout, and
Bypassing Considerations
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separat-
ed from each other. Do not run analog and digital lines
parallel to one another (especially clock lines), and do
not run digital lines underneath the MAX11043 pack-
age. Use a single-point analog ground (star ground
Maxim Integrated
31
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Typical Operating Circuit
TO
TO
DIGITAL ANALOG
SUPPLY SUPPLY
ECHO+
ECHO-
AINAP
DVDD
AVDD
AINAN
REFA
*SEE NOTE
RADAR
FRONT END
ECHO+
ECHO-
AINBP
AGND
AINBN
REFB
*SEE NOTE
*SEE NOTE
*SEE NOTE
MAX11043
CS
UP/DWN
DACSTEP
CONVRUN
ECHO+
ECHO-
AINCP
DSP
EOC
SHDN
SCLK
DOUT
DIN
AINCN
REFC
OSCIN
ECHO+
ECHO-
AINDP
AINDN
REFD
DGND
DVREG
AOUT
REFBP REFDAC REFDACH REFDACL
EXT
REF
*NOTE: CONNECT TO AGND FOR SINGLE-ENDED OPERATION.
Package Information
Chip Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
ꢁAID
PATTERI IO.
PACKAGE
TYPE
PACKAGE
CODE
OUTꢁꢂIE IO.
21-ꢀ141
9ꢀ-ꢀꢀ55
40 TQFN-EP
T4066+5
32
Maxim Integrated
MAX11043
4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Revision History
REVꢂSꢂOI REVꢂSꢂOI
PAGES
CHAIGED
DESCRꢂPTꢂOI
IUMBER
DATE
0
8/08
Initial release
—
Updated Ordering Information with automotive grade information and
clarified/amended data sheet
1, 2–7, 12–15,
21, 25, 30
1
3/10
2
3
3/11
Updated the Flash Erase and Programming section
29
1
11/12
Released the MAX11043ATL/V+
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 33
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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