MAX11044_12 [MAXIM]
4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs; 4- / 6 / 8通道， 16位/ 14位，同时采样ADC
| 型号： | MAX11044_12 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4-/6-/8-Channel, 16-/14-Bit, Simultaneous-Sampling ADCs |
| 文件： | 总27页 (文件大小：1587K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
General Description
Features
The MAX11044/MAX11045/MAX11046 16-bit and
MAX11054/MAX11055/MAX11056 14-bit ADCs offer 4, 6,
or 8 independent input channels. Featuring independent
track and hold (T/H) and SAR circuitry, these parts pro-
vide simultaneous sampling at 250ksps for each channel.
o 16-Bit ADC (MAX11044/MAX11045/MAX11046) and
14-Bit ADC (MAX11054/MAX11055/MAX11056)
8-Channel ADC (MAX11046/MAX11056)
6-Channel ADC (MAX11045/MAX11055)
4-Channel ADC (MAX11044/MAX11054)
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 accept a 5ꢀ input. All inputs
are overrange protected with internal 20mA input
clamps providing overrange protection with a simple
external resistor. Other features include a 4MHz T/H
input bandwidth, internal clock, and internal or external
reference. A 20MHz, bidirectional, parallel interface
provides the conversion results and accepts digital
configuration inputs.
o Single Analog and Digital Supply
o High-Impedance Inputs Up to 1GΩ
o On-Chip T/H Circuit for Each Channel
o Fast 3µs Conversion Time
o High Throughput: 250ksps for Each Channel
o 16-Bit/14-Bit, High-Speed, Parallel Interface
o Internal Clocked Conversions
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 operate with a 4.75ꢀ to 5.25ꢀ
analog supply and a separate flexible 2.7ꢀ to 5.25ꢀ
digital supply for interfacing with the host without a level
shifter. The MAX11044/MAX11045/MAX11046
are available in a 56-pin TQFN and 64-pin TQFP pack-
ages while the MAX11054/MAX11055/MAX11056 are
available in TQFP only and operate over the extended
-40°C to +85°C temperature range.
o 10ns Aperture Delay
o 100ps Channel-to-Channel T/H Matching
o Low Drift, Accurate 4.096V Internal Reference
Providing an Input Range of 5V
o External Reference Range of 3.0V to 4.25V,
Allowing Full-Scale Input Ranges of 4.0V to 5.2V
Applications
o 56-Pin (8mm x 8mm) TQFN and 64-Pin
Automatic Test Equipment
(10mm x 10mm) TQFP Packages
Power-Factor Monitoring and Correction
Power-Grid Protection
Multiphase Motor Control
o Evaluation Kit Available
ꢀibration and Waveform Analysis
Functional Diagram
Ordering Information
PART
PIN-PACKAGE
56 TQFN-EP*
64 TQFP-EP*
56 TQFN-EP*
64 TQFP-EP*
56 TQFN-EP*
64 TQFP-EP*
64 TQFP-EP*
64 TQFP-EP*
64 TQFP-EP*
CHANNELS
AVDD
CH0
DVDD
DB15**
MAX11044ETN+
MAX11044ECB+
MAX11045ETN+
MAX11045ECB+
MAX11046ETN+
MAX11046ECB+
MAX11054ECB+
MAX11055ECB+
MAX11056ECB+
4
4
6
6
8
8
4
6
8
16-/14-BIT ADC
16-/14-BIT ADC
CLAMP
CLAMP
S/H
S/H
DB4
DB3/CR3
†
DB0/CR0
CH7
CONFIGURATION
REGISTERS
WR
AGNDS
AGND
RD
CS
INTERFACE
AND
CONTROL
CONVST
SHDN
EOC
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
DGND
RDC
INT REF
10kΩ
BANDGAP
REFERENCE
REF
BUF
EXT REF
REFIO
RDC_SENSE*
Pin Configurations appear at end of data sheet.
**MAX11044/MAX11045/MAX11046
MAX11046/MAX11056
†
*CONNECTED INTERNALLY TO RDC ON THE TQFN PARTS
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5036; Rev 5; 1/11
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ABSOLUTE MAXIMUM RATINGS
AꢀDD to AGND ........................................................-0.3ꢀ to +6ꢀ
DꢀDD to AGND and DGND .....................................-0.3ꢀ to +6ꢀ
DGND to AGND.....................................................-0.3ꢀ to +0.3ꢀ
AGNDS to AGND...................................................-0.3ꢀ to +0.3ꢀ
CH0–CH7 to AGND...............................................-7.5ꢀ to +7.5ꢀ
REFIO, RDC to AGND ..................................-0.3ꢀ to the lower of
Maximum Current into Any Pin Except AꢀDD, DꢀDD, AGND,
DGND ........................................................................... 50mA
Continuous Power Dissipation
56-Pin TQFN (derate 47.6mW/°C above +70°C) ....3809.5mW
64-Pin TQFP (derate 43.5mW/°C above +70°C)........3478mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
(ꢀ
+ 0.3ꢀ) and +6ꢀ
AꢀDD
EOC, WR, RD, CS, CONꢀST to AGND.........-0.3ꢀ to the lower of
(ꢀ + 0.3ꢀ) and +6ꢀ
DꢀDD
DB0–DB15 to AGND ....................................-0.3ꢀ to the lower of
(ꢀ + 0.3ꢀ) and +6ꢀ
DꢀDD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(ꢀ
= +4.75ꢀ to +5.25ꢀ, ꢀ
= +2.70ꢀ to +5.25ꢀ, ꢀ
= ꢀ
= ꢀ = 0ꢀ, ꢀ
DGND
= internal reference, C
= 4 x
AꢀDD
DꢀDD
AGNDS
AGND
REFIO
RDC
33µF, C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DꢀDD or DGND, unless otherwise
REFIO
AꢀDD
DꢀDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (Note 1)
MAX11044/MAX11045/MAX11046
MAX11054/MAX11055/MAX11056
MAX11044/MAX11045/MAX11046
MAX11054/MAX11055/MAX11056
MAX11044/MAX11045/MAX11046
MAX11054/MAX11055/MAX11056
MAX11044/MAX11045/MAX11046
MAX11054/MAX11055/MAX11056
16
14
Resolution
N
Bits
LSB
LSB
Bits
> -2
-0.8
> -1
-0.6
16
0.4
0.13
0.4
< +2
+0.8
< +1.2
+0.6
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
INL
DNL
0.15
14
Offset Error
0.001
0.001
0.8
0.015
0.015
%FSR
%FSR
µꢀ/°C
%FSR
%FSR
%FSR
%FSR
%FSR
%FSR
ppm/°C
Channel Offset Matching
Offset Temperature Coefficient
Gain Error
0.015
0.015
0.015
0.01
Positive Full-Scale Error
Negative Full-Scale Error
Positive Full-Scale Error Matching
Negative Full-Scale Error Matching
Channel Gain-Error Matching
Gain Temperature Coefficient
DYNAMIC PERFORMANCE
0.01
Between all channels
0.01
0.5
MAX11044/MAX11045/
MAX11046
91
92.3
85.2
92
f
= 10kHz,
IN
Signal-to-Noise Ratio
SNR
dB
dB
full-scale input
MAX11054/MAX11055/
MAX11056
84.5
90.5
84.5
MAX11044/MAX11045/
MAX11046
Signal-to-Noise and Distortion
Ratio
f
IN
= 10kHz,
SINAD
full-scale input
MAX11054/MAX11055/
MAX11056
85.2
2
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +4.75ꢀ to +5.25ꢀ, ꢀ
= +2.70ꢀ to +5.25ꢀ, ꢀ
= ꢀ
= ꢀ = 0ꢀ, ꢀ
DGND
= internal reference, C
= 4 x
AꢀDD
DꢀDD
AGNDS
AGND
REFIO
RDC
33µF, C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DꢀDD or DGND, unless otherwise
REFIO
AꢀDD
DꢀDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MAX11044/MAX11045/
MIN
TYP
MAX
UNITS
98
95
104
MAX11046
f
= 10kHz,
IN
Spurious-Free Dynamic Range
SFDR
dB
full-scale input
MAX11054/MAX11055/
MAX11056
104
-105
-104
MAX11044/MAX11045/
MAX11046
-98
-95
f
= 10kHz,
IN
Total Harmonic Distortion
THD
dB
dB
ꢀ
full-scale input
MAX11054/MAX11055/
MAX11056
f
= 60Hz, full scale and ground on
adjacent channel (Note 2)
IN
Channel-to-Channel Crosstalk
-126
-100
ANALOG INPUTS (CH0–CH7)
1.22 x
Input ꢀoltage Range
(Note 3)
ꢀ
REFIO
Input Leakage Current
Input Capacitance
-1
+1
µA
pF
15
Input-Clamp Protection Current
TRACK AND HOLD
Throughput Rate
Each input simultaneously
Per channel
-20
+20
mA
1
1
250
ksps
µs
Acquisition Time
t
1000
ACQ
-3dB point
4
> 0.2
10
Full-Power Bandwidth
MHz
-0.1dB point
Aperture Delay
ns
ps
Aperture-Delay Matching
Aperture Jitter
100
50
ps
RMS
INTERNAL REFERENCE
REFIO ꢀoltage
ꢀ
ꢀ
4.08
4.096
5
4.112
ꢀ
REF
REF
REFIO Temperature Coefficient
EXTERNAL REFERENCE
Input Current
ppm/°C
-10
+10
4.25
µA
ꢀ
REF ꢀoltage-Input Range
REF Input Capacitance
3.00
15
10
pF
DIGITAL INPUTS (CR0–CR3, RD, WR, CS, CONVST)
Input ꢀoltage High
Input ꢀoltage Low
Input Capacitance
Input Current
ꢀ
ꢀ
ꢀ
= 2.7ꢀ to 5.25ꢀ
= 2.7ꢀ to 5.25ꢀ
2
ꢀ
ꢀ
IH
DꢀDD
DꢀDD
ꢀ
0.8
10
IL
C
pF
µA
IN
I
ꢀ
= 0ꢀ or ꢀ
DꢀDD
IN
IN
Maxim Integrated
3
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +4.75ꢀ to +5.25ꢀ, ꢀ
= +2.70ꢀ to +5.25ꢀ, ꢀ
= ꢀ
= ꢀ = 0ꢀ, ꢀ
DGND
= internal reference, C
= 4 x
AꢀDD
DꢀDD
AGNDS
AGND
REFIO
RDC
33µF, C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DꢀDD or DGND, unless otherwise
REFIO
AꢀDD
DꢀDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DB0–DB15, EOC)
ꢀ
-
DꢀDD
0.4
Output ꢀoltage High
ꢀ
I = 1.2mA
SOURCE
ꢀ
OH
Output ꢀoltage Low
ꢀ
I
= 1mA
SINK
0.25
15
0.4
10
ꢀ
µA
pF
ꢀ
OL
Three-State Leakage Current
Three-State Output Capacitance
Analog Supply ꢀoltage
DB0–DB15, ꢀ ≥ ꢀ or ꢀ ≥ ꢀ
RD IH CS
IH
IH
DB0–DB15, ꢀ ≥ ꢀ or ꢀ ≥ ꢀ
RD
IH
CS
AꢀDD
DꢀDD
4.75
2.70
5.25
5.25
48
Digital Supply ꢀoltage
ꢀ
MAX11046/MAX11056, ꢀ
MAX11045/MAX11055, ꢀ
= 5ꢀ
= 5ꢀ
AꢀDD
AꢀDD
Analog Supply Current
I
mA
39
AꢀDD
MAX11044/MAX11054, ꢀ
= 5ꢀ
AꢀDD
30
MAX11046/MAX11056, ꢀ
MAX11045/MAX11055, ꢀ
MAX11044/MAX11054, ꢀ
= 3.3ꢀ
= 3.3ꢀ
= 3.3ꢀ
7.0
6.5
5.5
10
DꢀDD
DꢀDD
DꢀDD
Digital Supply Current (Note 9)
Shutdown Current
I
mA
µA
DꢀDD
I
DꢀDD
I
10
AꢀDD
MAX11044/MAX11045/
MAX11046
1
ꢀ
= 4.9ꢀ
AꢀDD
to 5.1ꢀ
(Note 5)
Power-Supply Rejection
PSR
LSB
MAX11054/MAX11055/
MAX11056
0.25
TIMING CHARACTERISTICS (Note 4)
CONꢀST Rise to EOC
Acquisition Time
t
Conversion time (Note 6)
Sample quiet time (Note 6)
3
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CON
t
1
1000
ACQ
CS Rise to CONꢀST Rise
CONꢀST Rise to EOC Rise
EOC Fall to CONꢀST Fall
CONꢀST Low Time
t
500
Q
t
47
140
0
1
2
3
4
5
6
7
8
9
t
CONꢀST mode B0 = 0 only (Note 7)
CONꢀST mode B0 = 1 only
0
20
0
t
t
t
t
t
t
t
t
CS Fall to WR Fall
WR Low Time
20
0
CS Rise to WR Rise
Input Data Setup Time
Input Data Hold Time
CS Fall to RD Fall
10
1
0
RD Low Time
30
4
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
ELECTRICAL CHARACTERISTICS (continued)
(ꢀ
= +4.75ꢀ to +5.25ꢀ, ꢀ
= +2.70ꢀ to +5.25ꢀ, ꢀ
= ꢀ
= ꢀ = 0ꢀ, ꢀ
DGND
= internal reference, C
= 4 x
AꢀDD
DꢀDD
AGNDS
AGND
REFIO
RDC
33µF, C
= 0.1µF, C
= 4 x 0.1µF || 10µF, C
= 3 x 0.1µF || 10µF; all digital inputs at DꢀDD or DGND, unless otherwise
REFIO
AꢀDD
DꢀDD
noted, f
= 250ksps. T = -40°C to +85°C, unless otherwise noted. Typical values are at T = +25°C.)
SAMPLE
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
RD Rise to CS Rise
RD High Time
t
t
t
t
10
11
12
13
10
ns
RD Fall to Data ꢀalid
RD Rise to Data Hold Time
35
ns
(Note 7)
5
ns
Note 1: See the Definitions section at the end of the data sheet.
Note 2: Tested with alternating channels modulated at full scale and ground.
Note 3: See the Input Range and Protection section for more details.
Note 4:
C
LOAD
= 30pF on DB0–DB15 and EOC. Inputs (CH0–CH7) alternate between full scale and zero scale. f
= 250ksps.
CONꢀ
All data is read out.
Note 5: Defined as the change in positive full scale caused by a 2% variation in the nominal supply voltage.
Note 6: It is recommended that RD, WR, and CS are kept high for the quiet time (t ) and conversion time (t
).
CON
Q
Note 7: Guaranteed by design.
Typical Operating Characteristics
(ꢀ
= 5ꢀ, ꢀ
= 3.3ꢀ, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AꢀDD
DꢀDD
A
SAMPLE
DIFFERENTIAL NONLINEARITY vs. CODE
(MAX1104_)
INL AND DNL vs. ANALOG SUPPLY VOLTAGE
(MAX1104_)
1.0
INTEGRAL NONLINEARITY vs. CODE
(MAX1104_)
1.000
1.0
0.8
0.800
0.600
0.400
0.200
0
MAX INL
= 3.3V
0.6
0.2
0.6
0.4
V
f
DVDD
MAX DNL
MIN INL
0.2
= 250ksps
SAMPLE
T
A
= +25°C
= 4.096V
0
V
RDC
-0.2
-0.6
-1.0
-0.200
-0.400
-0.600
-0.800
-1.000
-0.2
-0.4
-0.6
-0.8
-1.0
V
V
f
= 5.0V
= 3.3V
V
V
= 5.0V
= 3.3V
= 250ksps
= +25°C
= 4.096V
AVDD
DVDD
AVDD
DVDD
= 250ksps
f
SAMPLE
SAMPLE
MIN DNL
T
A
= +25°C
= 4.096V
T
A
V
V
RDC
RDC
4.75
4.85
4.95
5.05
(V)
5.15
5.25
V
AVDD
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
Maxim Integrated
5
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(ꢀ
= 5ꢀ, ꢀ
= 3.3ꢀ, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AꢀDD
DꢀDD
A
SAMPLE
INL AND DNL vs. TEMPERATURE
(MAX1104_)
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
45
40
35
30
25
20
1.5
1.0
0.5
0
MAX11046 CONVERTING
MAX INL
MAX11045 CONVERTING
MAX11046 STATIC
MIN INL
MAX DNL
T
A
= +25°C
-0.5
-1.0
-1.5
f
= 250ksps
SAMPLE
MAX11045 STATIC
V
V
f
= 5.0V
= 3.3V
AVDD
DVDD
MIN DNL
= 250ksps
SAMPLE
MAX11044 CONVERTING
V
= 4.096V
RDC
MAX11044 STATIC
5.05 5.15 5.25
(V)
4.75
4.85
4.95
V
-40
-15
10
35
60
85
TEMPERATURE (°C)
AVDD
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
45
40
35
30
25
20
12
10
8
MAX11046 CONVERTING
T
f
= +25°C
A
= 250ksps
SAMPLE
MAX11046 CONVERTING
MAX11045 CONVERTING
MAX11046 STATIC
MAX11045 STATIC
6
MAX11045 CONVERTING
V
f
= 5.0V
AVDD
4
= 250ksps
SAMPLE
MAX11044 CONVERTING
2
MAX11044/MAX11045/MAX11046 STATIC
MAX11044 CONVERTING
MAX11044 STATIC
0
-40
-15
10
35
60
85
2.75
3.25
3.75
4.25
(V)
4.75
5.25
TEMPERATURE (°C)
V
DVDD
6
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(ꢀ
= 5ꢀ, ꢀ
= 3.3ꢀ, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AꢀDD
DꢀDD
A
SAMPLE
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. SUPPLY VOLTAGE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
ANALOG AND DIGITAL SHUTDOWN
CURRENT vs. TEMPERATURE
5
4
3
2
1
0
5
4
3
2
1
0
7.2
6.0
4.8
3.6
2.4
1.2
0
MAX11046 CONVERTING
MAX11045 CONVERTING
V
AVDD
V
DVDD
= 5.0V
= 3.3V
T = +25°C
A
I
I
AVDD
AVDD
MAX11044 CONVERTING
V
f
C
= 3.3V
DVDD
= 250ksps
SAMPLE
I
DVDD
= 15pF
I
DBxx
DVDD
MAX11044/MAX11045/MAX11046 STATIC
2.75
3.25
3.75
4.25
4.75
5.25
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
AVDD
OR V
(V)
TEMPERATURE (°C)
DVDD
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGES
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
4.09630
4.09625
4.09620
4.09615
4.09610
4.09605
4.09600
4.09595
4.09590
4.112
4.108
4.104
4.100
4.096
4.092
4.088
4.084
4.080
T
= +25°C
V
= 5.0V
A
AVDD
UPPER TYPICAL LIMIT
LOWER TYPICAL LIMIT
V
RDC
V
REFIO
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
AVDD
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. TEMPERATURE
OFFSET ERROR AND OFFSET ERROR
MATCHING vs. SUPPLY VOLTAGE
0.010
0.006
0.010
0.006
f
= 250ksps
= 5.0V
f
= 250ksps
SAMPLE
V
SAMPLE
T
= +25°C
AVDD
A
V
REFIO
= 4.096V
V
RDC
= 4.096V
OFFSET ERROR MATCHING
OFFSET ERROR MATCHING
OFFSET ERROR
0.002
0.002
-0.002
-0.006
-0.010
-0.002
-0.006
-0.010
OFFSET ERROR
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
Maxim Integrated
7
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(ꢀ
= 5ꢀ, ꢀ
= 3.3ꢀ, T = +25°C, f = 250ksps, internal reference, unless otherwise noted.)
SAMPLE
AꢀDD
DꢀDD
A
GAIN ERROR AND GAIN ERROR
MATCHING vs. TEMPERATURE
GAIN ERROR AND GAIN ERROR
MATCHING vs. SUPPLY VOLTAGE
FFT PLOT (MAX1104_)
0.010
0
-20
0.010
0.006
f
V
V
= 250ksps
f
= 250ksps
SAMPLE
f = 10kHz
IN
SAMPLE
= 5.0V
= 4.096V
T
= +25°C
AVDD
REFIO
f
= 250ksps
A
SAMPLE
V
RDC
= 4.096V
0.006
0.002
T
= +25°C
= 5.0V
A
GAIN ERROR
V
AVDD
-40
GAIN ERROR
0.002
-60
-80
-0.002
-0.006
-0.010
GAIN ERROR MATCHING
-0.002
-0.006
-0.010
GAIN ERROR MATCHING
-100
-120
-140
-40
-15
10
35
60
85
0
25
50
75
100
125
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
FREQUENCY (kHz)
V
AVDD
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. TEMPERATURE (MAX1104_)
TWO-TONE IMD PLOT (MAX1104_)
0
95
f
= 9838Hz
f
f
T
V
V
V
= 10kHz
IN1
IN
f
= 10235Hz
= 250ksps
= 250ksps
= +25°C
-20
-40
IN2
SAMPLE
f
SAMPLE
94
93
92
91
90
A
T
A
= +25°C
= 5.0V
AVDD
V
= 5.0V
= 4.096V
RDC
AVDD
V
IN
= 4.096V
= -0.025dB FROM FS
RDC
IN
SNR
-60
V
= -0.01dBFS
-80
SINAD
-100
-120
-140
7.2 8.0 8.8 9.6 10.4 11.2 12.0 12.8
FREQUENCY (kHz)
-40
-15
10
35
60
85
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE (MAX1104_)
SNR AND SINAD vs. ANALOG SUPPLY
VOLTAGE (MAX1104_)
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
93.0
92.5
92.0
91.5
91.0
f
f
T
V
V
V
= 10kHz
IN
= 250ksps
= +25°C
SAMPLE
SNR
A
= 5.0V
AVDD
= 4.096V
RDC
= -0.025dB FROM FS
IN
SINAD
f
f
T
V
V
= 10kHz
IN
= 250ksps
= +25°C
SAMPLE
A
= 4.096V
RDC
= -0.025dB FROM FS
IN
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
TEMPERATURE (°C)
V
AVDD
8
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Typical Operating Characteristics (continued)
(ꢀ
= 5ꢀ, ꢀ
= 3.3ꢀ, T = +25°C, f
= 250ksps, internal reference, unless otherwise noted.)
AꢀDD
DꢀDD
A
SAMPLE
SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. FREQUENCY (MAX1104_)
THD vs. INPUT FREQUENCY
THD vs. ANALOG SUPPLY VOLTAGE
(MAX1104_)
(MAX1104_)
94
-85
-90
-102
-103
-104
-105
-106
-107
f
f
T
= 10kHz
= 250ksps
SAMPLE
= +25°C
IN
f
T
V
V
V
= 250ksps
SAMPLE
= +25°C
A
92
90
88
86
84
82
A
= 5.0V
AVDD
V
V
= 4.096V
= -0.025dB FROM FS
RDC
= 4.096V
RDC
IN
= -0.025dB from FS
IN
-95
-100
-105
-110
f
= 250ksps
SAMPLE
T
A
= +25°C
V
V
V
= 5.0V
= 4.096V
= -0.025dB from FS
AVDD
RDC
IN
0.1
1
10
100
0.1
1
10
100
4.75
4.85
4.95
5.05
(V)
5.15
5.25
FREQUENCY (kHz)
FREQUENCY (kHz)
V
AVDD
OUTPUT NOISE HISTOGRAM WITH INPUT
CONNECTED TO AGNDS (MAX1104_)
CROSSTALK vs. FREQUENCY
200,000
150,000
100,000
50,000
0
-90
-100
-110
-120
-130
-140
V
V
V
= 0V
CH_
f
f
T
V
V
V
= 60Hz
IN
= 5.0V
AVDD
= 250ksps
SAMPLE
= 4.096V
= 250ksps
RDC
= +25°C
A
f
SAMPLE
= 5.0V
AVDD
= 4.096V
RDC
= -0.025dB FROM FS
IN
INACTIVE CHANNEL AT AGNDS
0.1
1
10
100
FREQUENCY (kHz)
OUTPUT CODE (DECIMAL)
CONVERSION TIME
vs. ANALOG SUPPLY VOLATAGE
CONVERSION TIME vs. TEMPERATURE
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
3.00
2.99
2.98
2.97
2.96
2.95
2.94
2.93
2.92
T
= +25°C
V
= 5.0V
A
AVDD
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
V
AVDD
TEMPERATURE (°C)
Maxim Integrated
9
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description
PIN
NAME
FUNCTION
MAX11044
(TQFN-EP)
MAX11045
(TQFN-EP)
MAX11046
(TQFN-EP)
1
1
1
DB13
DB12
DB11
DB10
DB9
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
2
2
2
3
3
3
4
4
4
5
6
5
6
5
6
DB8
7, 21, 50
7, 21, 50
7, 21, 50
DGND
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DꢀDD input.
8, 20, 51
8, 20, 51
8, 20, 51
DꢀDD
9
9
9
DB7
DB6
DB5
DB4
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
10
11
12
10
11
12
10
11
12
16-Bit Parallel Data Bus Digital Output Bit 3/
Configuration Register Input Bit 3
13
14
15
16
13
14
15
16
13
14
15
16
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
16-Bit Parallel Data Bus Digital Output Bit 2/
Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
17
18
17
18
17
18
EOC
Convert Start Input. Rising edge of CONꢀST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONꢀST is low
and CONꢀST mode = 0.
CONꢀST
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
19
19
19
SHDN
Reference Buffer Decoupling. Connect all RDC outputs
together. Bypass to AGND with at least an 80µF total
capacitance. See the Layout, Grounding, and Bypassing
section.
22, 28, 35, 43,
49
22, 28, 35, 43,
49
22, 28, 35, 43,
49
RDC
23, 27, 33, 38,
44, 48
23, 27, 33, 38,
44, 48
23, 27, 33, 38,
44, 48
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
AGNDS
10
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11044
(TQFN-EP)
MAX11045
(TQFN-EP)
MAX11046
(TQFN-EP)
Analog Supply Input. Bypass AꢀDD to AGND with a
0.1µF capacitor at each AꢀDD input.
24, 30, 41, 47
24, 30, 41, 47
24, 30, 41, 47
AꢀDD
25, 31, 40, 46
25, 31, 40, 46
25, 31, 40, 46
AGND
CH0
CH1
CH2
CH3
Analog Ground. Connect all AGND inputs together.
Channel 0 Analog Input
32
34
37
39
29
32
34
37
26
29
32
34
Channel 1 Analog Input
Channel 2 Analog Input
Channel 3 Analog Input
External Reference Input/Internal Reference Output.
Place a 0.1µF capacitor from REFIO to AGND.
36
36
36
REFIO
—
—
—
—
39
42
—
—
37
39
42
45
CH4
CH5
CH6
CH7
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
52
53
54
52
53
54
52
54
54
WR
CS
RD
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the
ADC. Each rising edge of RD advances the channel
output on the data bus.
55
56
55
56
55
56
—
DB15
DB14
I.C.
16-Bit Parallel Data Bus Digital Output Bit 15
16-Bit Parallel Data Bus Digital Output Bit 14
Internally Connected. Connect to AGND.
26, 29, 42, 45
26, 45
Exposed Pad. Internally connected to AGND. Connect to
a large ground plane to maximize thermal performance.
Not intended as an electrical connection point.
—
—
—
EP
Maxim Integrated
11
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11044
(TQFP-EP)
MAX11045
(TQFP-EP)
MAX11046
(TQFP-EP)
1
1
1
DB14
DB13
DB12
DB11
DB10
DB9
16-Bit Parallel Data Bus Digital Output Bit 14
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
2
2
2
3
3
3
4
4
4
5
5
5
6
7
6
7
6
7
DB8
8, 22, 59
8, 22, 59
8, 22, 59
DGND
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DꢀDD input.
9, 21, 60
9, 21, 60
9, 21, 60
DꢀDD
10
11
12
13
10
11
12
13
10
11
12
13
DB7
DB6
DB5
DB4
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/
Configuration Register Input Bit 3
14
15
16
17
14
15
16
17
14
15
16
17
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
16-Bit Parallel Data Bus Digital Output Bit 2/
Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
18
19
18
19
18
19
EOC
Convert Start Input. Rising edge of CONꢀST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONꢀST is low
and CONꢀST mode = 0.
CONꢀST
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
20
20
20
SHDN
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
AGNDS
AꢀDD
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
Analog Supply Input. Bypass AꢀDD to AGND with a
0.1µF capacitor at each AꢀDD input.
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
AGND
Analog Ground. Connect all AGND inputs together.
Maxim Integrated
12
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11044
(TQFP-EP)
MAX11045
(TQFP-EP)
MAX11046
(TQFP-EP)
Reference Buffer Sense Feedback. Connect to RDC
plane.
26, 55
26, 55
26, 55
RDC_SENSE
Reference Buffer Decoupling. Connect all RDC outputs
together. Bypass to AGND with at least an 80µF total
capacitance. See the Layout, Grounding, and Bypassing
section.
27, 33, 40, 48,
54
27, 33, 40, 48,
54
27, 33, 40, 48,
54
RDC
37
39
34
37
31
34
CH0
CH1
Channel 0 Analog Input
Channel 1 Analog Input
42
44
39
42
37
39
CH2
CH3
Channel 2 Analog Input
Channel 3 Analog Input
External Reference Input/Internal Reference Output.
Place a 0.1µF capacitor from REFIO to AGND.
41
41
41
REFIO
—
—
—
—
44
47
—
—
42
44
47
50
CH4
CH5
CH6
CH7
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
61
62
63
61
62
63
61
62
63
WR
CS
RD
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the
ADC. Each rising edge of RD advances the channel
output on the data bus.
64
64
64
—
DB15
I.C.
16-Bit Parallel Data Bus Digital Output Bit 15
Internally Connected. Connect to AGND.
31, 34, 47, 50
31, 50
Exposed Pad. Internally connected to AGND. Connect to
a large ground plane to maximize thermal performance.
Not intended as an electrical connection point.
—
—
—
EP
Maxim Integrated
13
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11054
(TQFP-EP)
MAX11055
(TQFP-EP)
MAX11056
(TQFP-EP)
1
1
1
DB12
DB11
DB10
DB9
14-Bit Parallel Data Bus Digital Output Bit 12
14-Bit Parallel Data Bus Digital Output Bit 11
14-Bit Parallel Data Bus Digital Output Bit 10
14-Bit Parallel Data Bus Digital Output Bit 9
14-Bit Parallel Data Bus Digital Output Bit 8
14-Bit Parallel Data Bus Digital Output Bit 7
14-Bit Parallel Data Bus Digital Output Bit 6
Digital Ground
2
2
2
3
3
3
4
4
4
5
5
5
DB8
6
7
6
7
6
7
DB7
DB6
8, 22, 59
8, 22, 59
8, 22, 59
DGND
Digital Supply. Bypass to DGND with a 0.1µF capacitor
at each DꢀDD input.
9, 21, 60
9, 21, 60
9, 21, 60
DꢀDD
10
11
12
13
10
11
12
13
10
11
12
13
DB5
DB4
DB3
DB2
14-Bit Parallel Data Bus Digital Output Bit 5
14-Bit Parallel Data Bus Digital Output Bit 4
14-Bit Parallel Data Bus Digital Output Bit 3
14-Bit Parallel Data Bus Digital Output Bit 2
14-Bit Parallel Data Bus Digital Output Bit 1/
Configuration Register Input Bit 3
14
15
14
15
14
15
DB1/CR3
DB0/CR2
14-Bit Parallel Data Bus Digital Output Bit 0/
Configuration Register Input Bit 2
16
17
16
17
16
17
CR1
CR0
Configuration Register Input Bit 1
Configuration Register Input Bit 0
Active-Low End-of-Conversion Output. EOC goes low
when conversion is completed. EOC goes high when a
conversion is initiated.
18
18
18
EOC
Convert Start Input. Rising edge of CONꢀST ends
sample and starts a conversion on the captured sample.
The ADC is in acquisition mode when CONꢀST is low
and CONꢀST mode = 0.
19
19
19
CONꢀST
Shutdown Input. If SHDN is held high, the entire device
will enter and stay in a low-current state. Contents of
the configuration register are not lost when in the
shutdown mode.
20
20
20
SHDN
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
23, 28, 32, 38,
43, 49, 53, 58
Signal Ground. Connect all AGND and AGNDS inputs
together on PCB.
AGNDS
AꢀDD
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
24, 29, 35, 46,
52, 57
Analog Supply Input. Bypass AꢀDD to AGND with a
0.1µF capacitor at each AꢀDD input.
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
25, 30, 36, 45,
51, 56
AGND
Analog Ground. Connect all AGND inputs together.
Reference Buffer Sense Feedback. Connect to RDC plane.
26, 55
26, 55
26, 55
RDC_SENSE
14
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Description (continued)
PIN
NAME
FUNCTION
MAX11054
(TQFP-EP)
MAX11055
(TQFP-EP)
MAX11056
(TQFP-EP)
Reference Buffer Decoupling. Connect all RDC outputs
together. Bypass to AGND with at least an 80µF total
capacitance. See the Layout, Grounding, and Bypassing
section.
27, 33, 40, 48,
54
27, 33, 40, 48,
54
27, 33, 40, 48,
54
RDC
37
39
42
44
34
37
39
42
31
34
37
39
CH0
CH1
CH2
CH3
Channel 0 Analog Input
Channel 1 Analog Input
Channel 2 Analog Input
Channel 3 Analog Input
External Reference Input/Internal Reference Output.
Place a 0.1µF capacitor from REFIO to AGND.
41
41
41
REFIO
—
—
—
—
44
47
—
—
42
44
47
50
CH4
CH5
CH6
CH7
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the
ADC. Configuration registers are loaded on the rising
edge of WR.
61
62
63
61
62
63
61
62
63
WR
CS
RD
Active-Low Chip-Select Input. Drive CS low when
reading from or writing to the ADC.
Active-Low Read Input. Drive RD low to read from the
ADC. Each rising edge of RD advances the channel
output on the data bus.
64
64
64
—
DB13
I.C.
14-Bit Parallel Data Bus Digital Output Bit 13
Internally Connected. Connect to AGND.
31, 34, 47, 50
31, 50
Exposed Pad. Internally connected to AGND. Connect to
a large ground plane to maximize thermal performance.
Not intended as an electrical connection point.
—
—
—
EP
and MAX11054/MAX11055/MAX11056 operate with a
single 4.75ꢀ to 5.25ꢀ supply. A separate 2.7ꢀ to 5.25ꢀ
supply for digital circuitry makes the devices compatible
with low-voltage processors.
Detailed Description
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 are fast, low-power ADCs that
combine 4, 6, or 8 independent ADC channels in a sin-
gle IC. Each channel includes simultaneously sampling
independent T/H circuitry that preserves relative phase
information between inputs making the MAX11044/
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056 ideal for motor control and power monitor-
ing. The MAX11044/MAX11045/MAX11046 and
MAX11054/MAX11055/MAX11056 are available with
5ꢀ input ranges that feature 20mA overrange, fault-
tolerant inputs. The MAX11044/MAX11045/MAX11046
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 perform conversions for all chan-
nels in parallel by activating independent ADCs. Results
are available through a high-speed, 20MHz, parallel
data bus after a conversion time of 3µs following the end
of a sample. The data bus is bidirectional and allows for
easy programming of the configuration register. The
MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 feature a reference buffer, which
Maxim Integrated
15
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
is driven by an internal bandgap reference circuit (ꢀ
FIO
bypass with 0.1µF capacitor to ground when using the
internal reference.
When in external reference mode, drive ꢀ
3.0ꢀ to 4.25ꢀ source, resulting in an input range of
3.662ꢀ to 5.188ꢀ, respectively.
with a
RE-
REFIO
= 4.096ꢀ). Drive REFIO with an external reference or
All analog inputs are fault-protected to up to 20mA.
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 include an input clamping circuit
that activates when the input voltage at the analog input
Analog Inputs
Track and Hold (T/H)
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
is above (ꢀ
+ 300mꢀ) or below –(ꢀ
+ 300mꢀ).
AꢀDD
AꢀDD
The clamp circuit remains high impedance while the
input signal is within the range of and draws lit-
tle or almost no current. However, when the input signal
exceeds , the clamps begin to turn on and
ꢀ
AꢀDD
ꢀ
AꢀDD
shunt current to/from the AꢀDD supply. Consequently,
to obtain the highest accuracy, ensure that the input
voltage does not exceed (ꢀ
+ 0.3ꢀ).
AꢀDD
To make use of the input clamps (see Figure 1), con-
nect a resistor (R ) between the analog input and the
S
Input Range and Protection
The full-scale analog input voltage is a product of the ref-
erence voltage. For the MAX11044/MAX11045/
MAX11046 and MAX11054/MAX11055/MAX11056, the
full-scale input is bipolar in the range of:
voltage source to limit the voltage at the analog input so
that the fault current into the MAX11044/MAX11045/
MAX11046 and MAX11054/MAX11055/MAX11056 does
not exceed 20mA. Note that the voltage at the analog
input pin limits to approximately 7ꢀ during a fault condi-
tion so the following equation can be used to calculate
5
(ꢀ
REFIO
x
)
4.096
the value of R :
S
PIN
VOLTAGE
INPUT
SIGNAL
AVDD
CH0
DVDD
DB15**
R
S
16-/14-BIT ADC
S/H
S/H
CLAMP
CLAMP
SOURCE
DB4
DB3/CR3
†
DB0/CR0
CH7
16-/14-BIT ADC
CONFIGURATION
REGISTERS
WR
AGNDS
AGND
RD
CS
INTERFACE
AND
CONTROL
CONVST
SHDN
EOC
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
INT REF
DGND
RDC
10kΩ
BANDGAP
REFERENCE
REF
BUF
EXT REF
REFIO
RDC_SENSE*
*CONNECTED INTERNALLY ON THE TQFN PARTS TO RDC
**MAX11044/MAX11045/MAX11046
†
MAX11046/MAX11056
Figure 1. Required Setup for Clamp Circuit
16
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
CR2 (Output Data Format)
CR2 selects the output data format. The POR default = 0.
ꢀ
- 7ꢀ
FAULT_MAX
R
S
=
0 = offset binary.
20mA
1 = two’s complement.
where ꢀ
is the maximum voltage that the
FAULT_MAX
source produces during a fault condition.
CR1 (Reserved)
Figures 2 and 3 illustrate the clamp circuit voltage-cur-
CR1 must be set to 0.
rent characteristics for a source impedance R
=
+
S
CR0 (CONVST Mode)
CR0 selects the acquisition mode. The POR default = 0.
1280Ω. While the input voltage is within the (ꢀ
AꢀDD
300mꢀ) range, no current flows in the input clamps.
Once the input voltage goes beyond this voltage range,
the clamps turn on and limit the voltage at the input pin.
0 = CONꢀST controls the acquisition and conversion.
Drive CONꢀST low to start acquisition. The rising edge
of CONꢀST begins the conversion.
Applications Information
1 = acquisition mode starts as soon as the previous
conversion is complete. The rising edge of CONꢀST
begins the conversion.
Digital Interface
The bidirectional, parallel, digital interface, CR0–CR3,
sets the 4-bit configuration register. This interface con-
figures the following control signals: chip select (CS),
read (RD), write (WR), end of conversion (EOC), and
convert start (CONꢀST). Figures 6 and 7 and the
Timing Characteristics in the Electrical Characteristics
table show the operation of the interface.
Programming the Configuration Register
To program the configuration register, bring the CS and
WR low and apply the required configuration data on
CR3–CR0 of the bus and then raise WR once to save
changes.
CAUTION: When the configuration register is not
being programmed, the host driving CR3–CR0 must
relinquish the bus when the conversion results of
the ADC are being read!
DB0–DB15/DB13 output the 16-/14-bit conversion result.
All bits are high impedance when RD = 1 or CS = 1.
CR3 (Int/Ext Reference)
CR3 selects the internal or external reference. The POR
default = 0.
Table 1. Configuration Register
0 = internal reference, REFIO internally driven through a
10kΩ resistor, bypass with 0.1µF capacitor to AGND.
1 = external reference, drive REFIO with a high-quality
reference.
CR3
CR2
CR1
CR0
Int/Ext
Reference
Output
Data Format
Must be set
to 0
CONꢀST
Mode
30
20
30
R = 1280Ω
S
V = 5V
AVDD
R
V
= 1280Ω
AVDD
S
= 5V
20
10
AT CH_ INPUT
AT CH_ INPUT
10
AT SOURCE
AT SOURCE
0
0
-10
-20
-30
-10
-20
-30
-8 -6 -4 -2
0
2
4
6
8
-50
-30
-10
10
30
50
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
SIGNAL VOLTAGE AT SOURCE AND PIN (V)
Figure 2. Input Clamp Characteristics
Maxim Integrated
Figure 3. Input Clamp Characteristics (Zoom In)
17
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Starting a Conversion
Reading Conversion Results
CONꢀST initiates conversions. The MAX11044/
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056 provide two acquisition modes set through
The CS and RD are active-low, digital inputs that con-
trol the readout through the 16-/14-bit, parallel, 20MHz
data bus (D0–D15/D13). After EOC transitions low, read
the conversion data by driving CS and RD low. Each
low period of RD presents the next channel’s result.
When CS or RD are high, the data bus is high imped-
ance. CS may be driven high between individual chan-
nel readouts or left low during the entire 8-channel
readout.
the configuration register. Allow a quiet time (t ) of
Q
500ns prior to the start of conversion to avoid any noise
interference during readout or write operations from
corrupting a sample.
In default mode (CR0 = 0), drive CONꢀST low to place
the MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 into acquisition mode. All the
input switches are closed and the internal T/H circuits
track the respective input voltage. Keep the CONꢀST
Reference
Internal Reference
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 feature a precision, low-drift,
internal bandgap reference. Bypass REFIO with a 0.1µF
capacitor to AGND to reduce noise. The REFIO output
voltage may be used as a reference for other circuits. The
output impedance of REFIO is 10kΩ. Drive only high
impedance circuits or buffer externally when using REFIO
to drive external circuitry.
signal low for at least 1µs (t
) to enable proper set-
ACQ
tling of the sampled voltages. On the rising edge of
CONꢀST, the switches are opened and the
MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 begin the conversion on all the
samples in parallel. EOC remains high until the conver-
sion is completed.
In the second mode (CR0 = 1), the MAX11044/
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056 enter acquisition mode as soon as the previ-
ous conversion is completed. CONꢀST rising edge initi-
ates the next sample and conversion sequence.
CONꢀST needs to be low for at least 20ns to be valid.
External Reference
Set the configuration register to disable the internal ref-
erence and drive REFIO with a high-quality external ref-
erence. To avoid signal degradation, ensure that the
integrated reference noise applied to REFIO is less
than 10µꢀ in the bandwidth of up to 50kHz.
Provide adequate time for acquisition and the requisite
quiet time in both modes to achieve accurate sampling
and maximum performance of the MAX11044/
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056.
CS
(USER SUPPLIED)
CS
t
5
(USER SUPPLIED)
t
10
t
t
t
8
9
11
t
3
t
4
RD
(USER SUPPLIED)
WR
(USER SUPPLIED)
t
13
t
12
t
7
S
S
n + 1
n
t
6
DB0–DB15/DB13
CONFIGURATION
REGISTER
CR0–CR3
(USER SUPPLIED)
Figure 5. Readout Timing Requirements
Figure 4. Programming Configuration-Register Timing
Requirements
18
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
SAMPLE
t
t
CON
ACQ
CONVST
EOC
t
1
t
O
t
Q
CS
RD
DB0–DB15/DB13
S
S
S
S
7
0
1
6
Figure 6. Conversion Timing Diagram (CR0 = 0)
SAMPLE
t
t
CON
ACQ
CONVST
EOC
t
2
t
O
t
Q
CS
RD
DB0–DB15/DB13
S
S
S
S
7
0
1
6
Figure 7. Conversion Timing Diagram (CR0 = 1)
Maxim Integrated
19
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Reference Buffer
The MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056 have a built-in reference buffer
to provide a low-impedance reference source to the
SAR converters. This buffer is used in both internal and
external reference mode. The reference buffer output
feeds five RDC pins. The RDC pins should be all con-
nected together on the PCB. The reference buffer is
externally compensated and requires at least 10µF on
the RDC node. For best performance, provide a total of
at least 80µF on the RDC outputs.
Transfer Functions
Figures 8 and 9 show the transfer functions for all the
formats and devices. Code transitions occur halfway
between successive-integer LSB values.
V
= (10/4.096) x (V /65,536)
REF
LSB
V
= (10/4.096) x (V /65,536)
REF
LSB
FULL-SCALE
TRANSITION
7FFF
7FFE
+FS = 32,767 x V
FULL-SCALE
TRANSITION
LSB
+FS = 32,767 x V
LSB
FFFF
FFFE
-FS = -32,768 x V
OUTPUT CODE =
LSB
-FS = -32,768 x V
OUTPUT CODE =
LSB
V
V
IN
IN
0001
0000
FFFF
FFFE
+ 32,768
8001
8000
7FFF
7FFE
V
V
LSB
LSB
8001
8000
0001
0000
-FS
0
+FS
-FS
0
+FS
-32,767.5 x V
+32,766.5 x V
LSB
-32,767.5 x V
LSB
+32,766.5 x V
LSB
LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 8. Two’s Complement Transfer Function for 16-Bit Devices
Figure 9. Offset-Binary Transfer Function for 16-Bit Devices
V
= (10/4.096) x (V /16,384)
REF
V
= (10/4.096) x (V /16,384)
REF
LSB
LSB
FULL-SCALE
TRANSITION
1FFF
1FFE
+FS = 8191 x V
LSB
FULL-SCALE
TRANSITION
+FS = 8191 x V
3FFF
3FFE
LSB
-FS = -8192 x V
LSB
-FS = -8192 x V
LSB
V
IN
V
0001
0000
3FFF
3FFE
IN
OUTPUT CODE =
+ 8192
2001
2000
1FFF
1FFE
OUTPUT CODE =
V
LSB
V
LSB
2001
2000
0001
0000
-FS
0
+FS
-FS
0
+FS
-8191.5 x V
+8190.5 x V
LSB
LSB
-8191.5 x V
+8190.5 x V
LSB
LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 9b. Offset-Binary Transfer Function for 14-Bit Devices
Figure 8b. Two’s Complement Transfer Function for 14-Bit Devices
20
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
VOLTAGE
TRANSFORMER
PHASE 1
OPT
ADC
OPT
ADC
CURRENT
TRANSFORMER
VN
IN
ADC
ADC
NEUTRAL
LOAD 1
MAX11046/
MAX11056
LOAD 2
LOAD 3
I3
ADC
V3
ADC
I2
PHASE 2
V2
ADC
ADC
PHASE 3
Figure 10. Power-Grid Protection
Maxim Integrated
21
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
MAX11044/
MAX11045/
MAX11046/
MAX11054/
MAX11055/
MAX11056
DSP-BASED DIGITAL
PROCESSING ENGINE
16-/14-BIT
ADC
IGBT CURRENT DRIVERS
16-/14-BIT
ADC
16-/14-BIT
ADC
16-/14-BIT
ADC
16-/14-BIT
ADC
I
PHASE1
I
PHASE3
I
PHASE2
3-PHASE ELECTRIC MOTOR
POSITION
ENCODER
Figure 11. DSP Motor Control
22
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
MAX11045/MAX11046 and MAX11054/MAX11055/
MAX11056 and the DꢀDD power plane from the digital
interface side of the device.
Layout, Grounding, and Bypassing
For best performance use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines paral-
lel to one another (especially clock lines), and avoid run-
ning digital lines underneath the ADC package. A single
solid GND plane configuration with digital signals routed
from one direction and analog signals from the other pro-
vides the best performance. Connect DGND, AGND, and
AGNDS pins on the MAX11044/MAX11045/MAX11046
and MAX11054/MAX11055/MAX11056 to this ground
plane. Keep the ground return to the power supply for this
ground low impedance and as short as possible for noise-
free operation.
For acquisition periods near minimum (1µs) use a 1nF
C0G ceramic chip capacitor between each of the chan-
nel inputs to the ground plane as close as possible to
the MAX11044/MAX11045/MAX11046 and MAX11054/
MAX11055/MAX11056. This capacitor reduces the
inductance seen by the sampling circuitry and reduces
the voltage transient seen by the input source circuit.
Typical Application Circuits
Power-Grid Protection
Figure 10 shows a typical power-grid protection application.
To achieve the highest performance, connect all the
RDC pins (22, 28, 35, 43, 49 for the TQFN package, or
pins 27, 33, 40, 48, 54 for the TQFP package) to a local
RDC plane on the PCB. In addition, on the TQFP pack-
age, the RDC_SENSE pins 26 and 55 should be directly
connected to this RDC plane as well. Bypass the RDC
outputs with a total of at least 80µF of capacitance. If
two capacitors are used, place each as close as possi-
ble to pins 22 and 49 (TQFN) or pins 27 and 54 (TQFP).
If four capacitors are used, place each as close as pos-
sible to pins 22, 28, 43, and 49 (TQFN) or pins 27, 33,
48, and 54 (TQFP). For example, two 47µF, 10ꢀ X5R
capacitors in 1210 case size can be placed as close as
possible to pins 22 and 49 (TQFN package) will provide
excellent performance. Alternatively, four 22µF, 10ꢀ
X5R capacitors in 1210 case size placed as close as
possible to pins 22, 28, 43, and 49 (TQFN package) will
also provide good performance. Ensure that each
capacitor is connected directly into the AGND plane
with an independent via.
DSP Motor Control
Figure 11 shows a typical DSP motor control application.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For these devices, this
straight line is a line drawn between the end points of
the transfer function, once offset and gain errors have
been nullified.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. For these devices, the DNL of
each digital output code is measured and the worst-case
value is reported in the Electrical Characteristics table. A
DNL error specification of greater than -1 LSB guaran-
tees no missing codes and a monotonic transfer func-
tion. For example, -0.9 LSB guarantees no missing code
while -1.1 LSB results in missing code.
If Y5U or Z5U ceramics are used, be aware of the high-
voltage coefficient these capacitors exhibit and select
higher voltage rating capacitors to ensure that at least
80µF of capacitance is on the RDC plane when the
plane is driven to 4.096ꢀ by the built-in reference
buffer. For example, a 22µF X5R with a 10ꢀ rating is
approximately 20µF at 4.096ꢀ, whereas, the same
capacitor in Y5U ceramic is just 13µF. However, a Y5U
22µF capacitor with a 25ꢀ rating cap is approximately
20µF at 4.096ꢀ.
Offset Error
The offset error is defined as the input voltage required
to cause the MAX11044/MAX11045/MAX11046 digital
output to be centered on code 0x8000 (offset binary) or
0x0000 (two’s complement) and the MAX11054/
MAX11055/MAX11056 digital output to be centered on
code 0x0000 (offset binary) or 0x0000 (two’s comple-
ment). Ideally, this input voltage should be 0ꢀ with
respect to AGNDS.
Bypass AꢀDD and DꢀDD to the ground plane with
0.1µF ceramic chip capacitors on each pin as close as
possible to the device to minimize parasitic inductance.
Add at least one bulk 10µF decoupling capacitor to
AꢀDD and DꢀDD per PCB. Interconnect all of the
AꢀDD inputs and DꢀDD inputs using two solid power
planes. For best performance, bring the AꢀDD power
plane in on the analog interface side of the MAX11044/
Gain Error
Gain error is defined as the difference between the
change in analog input voltage required to produce a top
code transition minus a bottom code transition, subtract-
ed from the ideal change in analog input voltage on
(10/4.096) x ꢀ
x (65,534/65,536) for 16-bit, or
REF
(10/4.096) x ꢀ
x (16,382/16,384) for 14-bit devices.
REF
For the MAX11044/MAX11045/MAX11046, top code tran-
Maxim Integrated
23
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
sition is 0x7FFE to 0x7FFF in two’s complement mode
Total Harmonic Distortion (THD)
and 0xFFFE to 0xFFFF in offset binary mode. The bottom
code transition is 0x8000 and 0x8001 in two’s comple-
ment mode and 0x0000 and 0x0001 in offset binary
mode. For the MAX11054/MAX11055/MAX11056, top
code transition is 0x1FFE to 0x1FFF in two’s complement
mode and 0x3FFE to 0x3FFF in offset binary mode. The
bottom code transition is 0x2000 and 0x2001 in two’s
complement mode and 0x0000 and 0x0001 in offset bina-
ry mode. For the MAX11044/MAX11045/MAX11046 and
MAX11054/MAX11055/MAX11056, the analog input volt-
age to produce these code transitions is measured and
the gain error is computed by subtracting (10/4.096) x
THD is the ratio of the RMS of the first five harmonics of
the input signal to the fundamental itself. This is:
expressed as:
⎡
⎢
⎢
⎤
⎥
⎥
2
2
2
2
ꢀ
+ ꢀ + ꢀ + ꢀ
3 4 5
2
THD = 20 × log
ꢀ
1
⎢
⎥
⎣
⎦
where ꢀ is the fundamental amplitude and ꢀ through
1
2
ꢀ are the 2nd- through 5th-order harmonics.
5
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the funda-
mental (maximum signal component) to the RMS value
of the next-largest frequency component.
ꢀ
x (65,534/65,536) or (10/4.096) x ꢀ
x
REF
REF
(16,382/16,384), respectively from this measurement.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, SNR is the ratio of the full-scale analog input
(RMS value) to the RMS quantization error (residual
error). The ideal, theoretical minimum analog-to-digital
noise is caused by quantization noise error only and
results directly from the ADC’s resolution (N bits):
Aperture Delay
Aperture delay (t ) is the time delay from the sampling
AD
clock edge to the instant when an actual sample is
taken.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
aperture delay.
SNR = (6.02 x N + 1.76)dB
Channel-to-Channel Isolation
Channel-to-channel isolation indicates how well each
analog input is isolated from the other channels.
Channel-to-channel isolation is measured by applying
DC to channels 1 to 7, while a -0.4dBFS sine wave at
60Hz is applied to channel 0. A 10ksps FFT is taken for
channel 0 and channel 1. Channel-to-channel isolation
is expressed in dB as the power ratio of the two 60Hz
magnitudes.
where N = 16/14 bits. In reality, there are other noise
sources besides quantization noise: thermal noise, ref-
erence noise, clock jitter, etc. SNR is computed by tak-
ing the ratio of the RMS signal to the RMS noise, which
includes all spectral components not including the fun-
damental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is the ratio of the fundamental input frequency’s
RMS amplitude to the RMS equivalent of all the other
ADC output signals:
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in a manner that ensures that the signal’s slew
rate does not limit the ADC’s performance. The input
frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased 3dB.
⎡
⎢
⎣
⎤
⎥
⎦
Signal
(Noise +Distortion)
RMS
SINAD(dB) = 10 ×log
RMS
Effective Number of Bits (ENOB)
The ENOB indicates the global accuracy of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. With an
input range equal to the full-scale range of the ADC,
calculate the ENOB as follows:
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as full-
power input bandwidth frequency.
SINAD −1.76
ENOB =
6.02
24
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Positive Full-Scale Error
Negative Full-Scale Error
The error in the input voltage that causes the first code
transition of 0000 to 0001 (hex) (in default offset binary
mode) or 8000 to 8001 (hex) for 16-bit or 2000 to 2001
(hex) for 14-bit devices (in two’s complement mode) from
the ideal input voltage of -32,767.5 x (10/4.096) x
The error in the input voltage that causes the last code
transition of FFFE to FFFF (hex) for 16-bit or 3FFE to 3FFF
(hex) for 14-bit devices (in default offset binary mode) or
7FFE to 7FFF (hex) for 16-bit or 1FFE to 1FFF (hex) for 14-
bit devices (in two’s complement mode) from the ideal
input voltage of 32,766.5 x (10/4.096) x (ꢀ
/65,536) for
(ꢀ
/65,536) for 16-bit or -8191.5 x (10/4.096) x
REF
REF
16-bit or 8190.5 x (10/4.096) x (ꢀ
/16,384) for 14-bit
(ꢀ /16,384) for 14-bit devices after correction for offset
REF
REF
devices after correction for offset error.
error.
Chip Information
PROCESS: BiCMOS
Pin Configurations
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
TOP VIEW
AGNDS
CH0*/I.C.
AGND
32
31
30
AGNDS
49
50
42 41 40 39 38 37 36 35 34 33 32 31 30 29
†‡
†‡
I.C. /CH7*
28
27
26
25
24
23
22
21
RDC
RDC
43
44
AGND 51
AVDD 52
AGNDS
AGNDS
CH0*/I.C.
AGND
AVDD
AGNDS
RDC
29 AVDD
†‡
†‡
I.C. /CH7* 45
AGND 46
AVDD 47
AGNDS 48
RDC 49
AGNDS
RDC
28
27
26
25
24
23
22
21
20
19
18
AGNDS 53
RDC 54
RDC_SENSE
AGND
RDC_SENSE 55
AGND 56
MAX11044
MAX11045
MAX11046
MAX11044
MAX11045
MAX11046
AVDD
AVDD 57
DGND 50
DVDD 51
WR 52
DGND
AGNDS
58
AGNDS
DGND
20 DVDD
DGND
DVDD
WR
59
60
61
62
63
19 SHDN
DVDD
CS 53
18 CONVST
17 EOC
SHDN
RD 54
CONVST
EOC
CS
*EP
DB15 55
DB14 56
16 DB0/CR0
15 DB1/CR1
+
*EP
RD
+
DB15 64
17 DB0/CR0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TQFN
8mm x 8mm
‡
†
MAX11044
MAX11045
TQFP
10mm x 10mm
*MAX11046
Maxim Integrated
25
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Pin Configurations (continued)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
AGNDS
CH0*/I.C.
AGND
32
31
30
AGNDS
49
50
51
52
†‡
†‡
I.C. /CH7*
AGND
29 AVDD
AVDD
AGNDS
RDC
28
27
26
25
24
23
22
21
20
19
18
AGNDS 53
RDC 54
RDC_SENSE
AGND
RDC_SENSE 55
AGND 56
MAX11054
MAX11055
MAX11056
AVDD
AVDD 57
AGNDS
58
AGNDS
DGND
DGND
59
DVDD
60
DVDD
SHDN
61
62
63
WR
CS
RD
CONVST
EOC
*EP
+
DB13 64
17 CR0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
TQFP
10mm x 10mm
‡
†
MAX11054
MAX11055
*MAX11056
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
PACKAGE TYPE
56 TQFN-EP
PACKAGE CODE
T5688+3
OUTLINE NO.
21-0135
LAND PATTERN NO.
90-0047
64 TQFP-EP
C64E+6
21-0084
90-0328
26
Maxim Integrated
MAX11044/MAX11045/MAX11046/
MAX11054/MAX11055/MAX11056
4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
2
10/09
3/10
5/10
Initial release
—
Added TQFP package to data sheet
1, 2, 8, 9, 19
1–4, 7, 9–26
Added 14-bit MAX11054/MAX11055/MAX11056
Style edits, specified part numbers in Typical Operating Characteristics, corrected
pin names, clarified layout
1, 3–8,
13–18, 22
3
4
5
9/10
10/10
1/11
Released the TQFP versions of MAX11044, MAX11045, and MAX11046. Revised
the Electrical Characteristics, Typical Operating Characteristics, and the Input
Range and Protection section.
1–8, 15
Released MAX11054, MAX11055, MAX11056. Revised the Electrical
Characteristics and Figures 8b and 9b.
1, 2, 4, 20
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 27
© 2011 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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