MAX11150EVKIT [MAXIM]
High-Speed USB Connector, FMC Connector, and PMOD-Style Connector;
| 型号： | MAX11150EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Speed USB Connector, FMC Connector, and PMOD-Style Connector |
| 文件： | 总33页 (文件大小：6197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Evaluates: MAX11150/MAX11152/MAX11158/
MAX11160/MAX11161/MAX11162/MAX11163/
MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
General Description
Features
The evaluation kit (EV kit) demonstrates the MAX1115X/
MAX1116X family of 18-/16-bit SAR ADCs. The EV kit
includes a graphical user interface (GUI) that provides
communication from the target device to the PC. The EV
kit can operate in multiple modes:
● High-Speed USB Connector, FMC Connector, and
PMOD-Style Connector
●
75MHz SPI Clock Capability through FMC Connector
● 10MHz SPI Clock Capability in Standalone Mode
● Various Sample Sizes and Sample Rates (Up to
500ksps)
● Collects Up to 1 Million samples (with FPGA
Platform)
1) Standalone Mode: In “standalone” mode, the EV kit
is connected to the PC via a USB cable and performs
a subset of the complete EV kit functions with limita-
tion for sample rate, sample size, and no support for
coherent sampling.
● Time Domain, Frequency Domain, and Histogram
Plotting
2) FPGA Mode: In “FPGA” mode, the EV kit is connect-
ed to an Avnet ZedBoard™ through a low-pin-count
FMC connector. The ZedBoard features a Xilinx®
Zynq® -7000 SoC, that connects to the PC through
an Ethernet port, which allows the GUI to perform
different operations with full control over mezzanine
card functions. The EV kit with FPGA platform per-
forms the complete suite of evaluation tests for the
target IC.
3) User-Supplied SPI Mode: In addition to the USB and
FMC interfaces, the EV kit provides a 12-pin PMOD-
style header for user-supplied SPI interface to connect
the signals for SCLKx, DINx, DOUTx, and CNVSTx.
● Sync In/Out for Coherent Sampling (with FPGA plat-
form)
● On-Board Input Buffers (MAX9632 and MAX44242)
● On-Board Voltage References (MAX6126 and
MAX6070)
● Proven PCB Layout
● Fully Assembled and Tested
● Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
Ordering Information appears at end of data sheet.
EV Kit Photo
The EV kit includes Windows XP®-, Windows® 7, and
Windows 8.1-compatible software for exercising the fea-
tures of the IC. The EV kit GUI allows different sample
sizes, adjustable sampling rates, internal or external ref-
erence options (depending upon target device selected),
and graphing software that includes the FFT and histo-
gram of the sampled signals.
The ZedBoard board accepts a +12V AC-DC wall adapter.
The EV kit can be powered by a local +20V supply. The
EV kit has on-board transformers and digital isolators to
separate the IC from the ZedBoard/on-board processor.
The MAX1115X/MAX1116X EV kit comes installed with
a MAX1115XEUB+/MAX1116XEUB+ in a 10-pin µMAX®
package, but can also evaluate other pin-compatible parts
in the family. For a full list of products supported by this
EV kit, see Table 4.
ZedBoard is a trademark of Avnet, Inc.
Xilinx and Zynq are registered trademarks of Xilinx, Inc.
Windows XP and Windows are registered trademarks and reg-
istered service marks of Microsoft Corporation.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
19-7582; Rev 0; 5/15
Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
System Block Diagram
SYNC IN,
SYNC OUT
ISOLATED
DC-DC
MAX9632
-
+
FPGA -
-
+
ZedBoard
SCLK1
CNVST1
DOUT1
DIN1
F
M
C
MAX9632
U10
ADC # 1
MAX44242
DOUT_DAISY
-
+
-
+
I
ADC_EXT_REF
S
O
L
A
T
I
H
E
A
D
E
R
MAX44242
USER-SUPPLIED
SPI
VREF1_ADC
+3.3V/
+2.5V
MAX6126
MAX6070
VREF2_ADC
MAX9632
-
+
-
+
DOUT
SCLK
O
N
DOUT2
MAX9632
SCLK1
U14
PC - USB
ADC # 2
CNVST1
SCLK2
CNVST
DIN
MAX44242
-
+
-
+
USB
FTDI
CNVST2
MAX44242
+3.3V/+2.5V
GND
MAX1115X/MAX1116X EV Kit Files
FILE
MAX1115X_6XEVKitSetupV1.0.exe
Boot.bin
DESCRIPTION
Application Program (GUI)
ZedBoard firmware (SD card to boot Zynq)
Procedure
Quick Start
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
Required Equipment
●
●
●
●
●
●
●
MAX1115X/MAX1116X EV kit
+20V (500mA) power supply
Micro-USB cable
1) Visit http://www.maxim-ic.com/evkitsoftware to
download the latest version of the EV kit software,
MAX1115X_6XEVK.ZIP. Save the EV kit software to
a temporary folder and uncompress the ZIP file.
2) Install the EV kit software and USB driver on your com-
puter by running the MAX1115X_6XEVKitSetupV1.0.exe
program inside the temporary folder. The program
files are copied to your PC and icons are created in
the Windows Start | Programs menu. At the end of
the installation process, the installer will launch the
installer for the FTDIChip CDM drivers.
ZedBoard development board
Function generator (optional)
DMM (for calibration – optional)
Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
Note: In the following section(s), software-related items
are identified by bolding. Text in bold refers to items direct-
ly from the EV system software. Text in bold and under-
line refers to items from the Windows operating system.
Maxim Integrated
│ 2
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
For Standalone Mode:
5) Connect the 12V power supply to the ZedBoard.
Leave the Zedboard powered off.
1) Verify that all jumpers are in their default positions for
the EV kit board (Table 2).
6) Enable the ZedBoard power supply by sliding SW8 to
ON and connect the +20V adapter to the EV kit.
7) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu select
FPGA. Verify that the lower right status bar indicates
the EV Kit hardware is Connected.
2) Connect the PC to the EV kit using a micro USB cable.
3) Connect the +20V adapter to the EV kit.
4) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
in Figure 1.
5) The software should automatically connect to the
hardware and display EV kit Hardware Connected
in the Status bar. If it does not connect, then from the
Device menu, select Standalone and click Search
for USB Device. Then select Standalone again and
select a device in the list. Verify that the lower right
status bar indicates the EV kit hardware is Connect-
ed.
For Either Standalone or FPGA Mode:
1) Connect the positive terminal of the function genera-
tor to the AIN0+ (TP2) test point on the EV kit. Con-
nect the negative terminal of the function generator to
the AIN0- (TP1) test point on the EV kit.
2) Configure the signal source to generate a 1kHz,
1V
sinusoidal wave with +500mV offset.
P-P
For FPGA Mode (When Connected to a Zedboard):
3) Turn on the function generator.
4) In the Configuration group, select Device to match
IC type, select Channel 1 and then click Capture.
5) Click on the Scope tab.
6) Check the Remove DC Offset checkbox to remove
the DC component of the sampled data.
7) Click the Capture button to start the data analysis.
The default sample size is 8192.
8) The EV kit software appears as shown in Figure 1.
9) Verify the frequency is approximately 1kHz is dis-
played on the right. The scope image has buttons in
the upper right corner that allow zooming in to detail.
1) Connect the Ethernet cable from the PC to the Zed-
Board and configure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connec-
tion to IP address 192.168.1.2 and subnet mask to
255.255.255.0.
2) Verify that the ZedBoard SD card contains the Boot.
bin file for the MAX1115X/MAX1116X EV kit.
3) Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
4) Verify that all jumpers are in their default positions for
the ZedBoard (Table 1) and EV kit board (Table 2).
Table 1. ZedBoard Jumper Settings
JUMPER
SHUNT POSITION
DESCRIPTION
J18
1-2
VDDIO set for 3.3V.
Boot from SD card
SD card installed
JP11
JP10
JP9
JP8
JP7
2-3
1-2
1-2
2-3
2-3
JP10
J12
J20
—
—
Connected to 12V wall adapter
SW8
OFF
ZedBoard power switch, OFF while connecting boards
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 2. EV kit Jumper Settings†
JUMPER
JUMPER
DESCRIPTION
POSITION
OPEN*
1-2
Set output of U5 to 3.3V
Set output of U5 to 2.5V
J3 (Red)
J4 (Red)
1-2
Power U23 with 12V for 5V FPGA power (Do not populate 1-2 and 3-4 at same time)
Power U23 with 20V for 5V FPGA power (Do not populate 1-2 and 3-4 at same time)
Connect BIN0- to AGND
3-4*
1-2*
3-4
J5 (Black)
J6 (Black)
J7 (Black)
J8 (Red)
Connect BIN0+ to AGND
1-2*
3-4
Connect BIN2- to AGND
Connect BIN2+ to AGND
1-2*
3-4
Connect BIN3- to AGND
Connect BIN3+ to AGND
1-2
Power U20 with +12V from FPGA
3-4*
1-2*
3-4
Power U20 with 5V from USB
Connect BIN1- to AGND
J9 (Black)
Connect BIN1+ to AGND
1-2
Connects output of U27 (BIN0) to inverting input of U28
Connects BIN1- to inverting input of U28
Connects output of U27 (BIN0) to noninverting input of U28
Connects BIN1+ to noninverting input of U28
Connects output of U26A (BIN2) to inverting input of U26B
Connects BIN3- to inverting input of U26B
Connects output of U26A (BIN2) to noninverting input of U28
Connects BIN3+ to noninverting input of U28
Disable on-board power supplies
3-4*
5-6*
7-8
J10 (Black)
J11 (Black)
1-2
3-4*
5-6*
7-8
OPEN
1-2*
J12 (Black)
J13 (Black)
Enable on-board power supplies
User connect external reference to TP12 – ADC_EXT_REF (If the target device has an internal
reference J13 should be left open)
OPEN*
1-2
2-3**
OPEN
1-2*
1-2
MAX6070 is VREF source
MAX6126 is VREF source
Disable +3V3_USB power for FTDI chip
Enable +3V3_USB power for FTDI chip
Power U2 from EXTERNAL +18V source
Power U2 from T1 +18V output
J14 (Red)
J15 (Red)
J16 (Red)
J17 (Red)
J19 (Black)
3-4*
1-2
Power U3 from EXTERNAL -18V source
Power U3 from T2 -18V output
3-4*
1-2
Use external +10V applied at TP9
Use U2 output for +10V, 100mA supply
Connect U10 SDI to DVDD (CS mode)
Connect U10 SDI to U14 SDO (daisy-chain mode)
3-4*
1-2*
3-4
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 2. EV kit Jumper Settings† (continued)
JUMPER
JUMPER
DESCRIPTION
POSITION
1-2
OPEN*
—
Connects U10 SDO to DVDD (enable busy bit)
No pullup on U10 SDO
J20 (Black)
J21
J22
J23
ADC2 SPI Port Test Points (header – no jumpers)
ADC1 SPI Port Test Points (header – no jumpers)
Serial EEPROM Test Points (header – no jumpers)
Changes the -10V supply to ground
-10V supplied by external test point (TP23)
-10V supplied by U3
—
—
1-2
J24 (Red)
3-4
5-6*
—
J25
PMOD-style connector. Connects to ADC1 and ADC2 SPI ports, 12 pins (no jumpers).
+15V supplied from external test point (TP38)
+15V supplied by U6
1-2
J26 (Red)
3-4*
1-2
Changes the -15V supply to ground
-15V supplied by external test point (TP37)
-15V supplied by U13
J27 (Red)
3-4
5-6*
1-2*
3-4
Connect AIN0- to AGND
J28 (Black)
J29 (Black)
J31 (Black)
Connect AIN0+ to AGND
1-2*
3-4
Connect AIN1- to AGND
Connect AIN1+ to AGND
1-2*
3-4
Connect AIN3- to AGND
Connect AIN3+ to AGND
1-2
Connect U7 output (AIN0) to U8 inverting input
Connect AIN1- to U8 inverting input
Connect U7 output (AIN0) to U8 noninverting input
Connect AIN1+ to U8 noninverting input
Connect AIN2- to AGND
3-4*
5-6*
7-8
J32 (Black)
J33 (Black)
J34 (Black)
1-2*
3-4
Connect AIN2+ to AGND
1-2*
3-4
Connect U8 output to U10 AIN+
Connect U9B output to U10 AIN+
Connect GND_SENSE (TP26) to U10 AIN-
Connect U10 AIN- to AGND
5-6
7-8*
1-2
Connect U14 CVNST to CNVST1_ADC
Connect U14 CVNST to CNVST2_ADC
Connect U14 SCLK to SCLK1_ADC
Connect U14 SCLK to SCLK2_ADC
Connect U14 SDI to AGND
3-4*
5-6
J35 (Black)
7-8*
9-10
11-12*
Connect U14 SDI to DVDD
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 2. EV kit Jumper Settings† (continued)
JUMPER
JUMPER
DESCRIPTION
POSITION
1-2
3-4*
5-6*
7-8
Connect U9A output (AIN2) to U9B inverting input
Connect AIN3- to U9B inverting input
J36 (Black)
J37 (Black)
Connect U9A output (AIN2) to U9B noninverting input
Connect AIN3+ to U9B noninverting input
Connect ADC_EXT_REF to U10 REF (ADC1)
Connect ADC_EXT_REF to U9 VREF2
Connect ADC_EXT_REF to U8 VREF1
Connect ADC_EXT_REF to U26 VREF4
Connect ADC_EXT_REF to U28 VREF3
Connect ADC_EXT_REF to U14 REF (ADC2)
Connect U14 SDO to DOUT2_ADC
Connect U14 SDO to DOUT_DAISY
Connect U28 output to U14 AIN+
1-2**
3-4
5-6
7-8
9-10
11-12**
1-2*
3-4
J38 (Bue)
1-2*
3-4
Connect U26B output to U14 AIN+
J39 (Black)
5-6
Connect GND_SENSE to U14 AIN-
7-8*
Connect AGND to U14 AIN-
†Red test points and red jumpers are used for power settings. Black test points are used for ground points, white test points are used
for all signal points, black jumper for I/O settings.
*Default positions
**If the target ADC requires an external reference this should be populated (MAX11152 and MAX11162)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
CS Mode (Single ADC Mode)
General Description of Software
The factory-default jumper settings have the ADCs on the
EV kit configured for CS mode, using the Channel 1 device
(U10) and Channel 2 device (U14). In the Configuration
tab the correct selection must be made for CS Mode. If
the busy bit is desired, select CS Mode with Busy and
populate J20.
The main window of the EV kit software contains five
tabs: Configuration, Scope, DMM, Histogram, and FFT.
The Configuration tab provides control for the two ADCs
configuration during data capture. The other four tabs are
used for evaluating the data captured by the ADCs. In
addition, the sample data can be saved to a file.
Daisy-Chain Mode
Configuration Tab
To use the ADCs in daisy-chain mode, move the shunts
described in Table 3 for J19 and J38 so the SDO of U14
(DOUT2_DAISY) connects to the SDI of U10. The SDO
of U10 connects to the SPI MISO for the GUI to read
the data. In the Configuration tab, the correct selection
must be made for Interface Mode set as Daisy-chain.
The channel selection automatically changes to Both
Channels in daisy-chain mode.
The Configuration tab provides an interface for selecting
and configuring the ADC from a functional perspective.
Select the desired Device in the drop-down list and the
corresponding properties of the device are displayed
including Resolution, Input Range, Reference Voltage,
and Max Sample Rate. If the selected ADC uses an
external reference, then use the Reference Voltage
numeric box to enter the measured reference value. The
on-board reference is 5V.
Dual ADC Mode (Sequential or Simultaneous)
The sampling settings are available on the left, which
allow the user to select the Channel, Sample Rate,
Number of Samples, and SCLK Frequency. The SCLK
Frequency selection is required prior to adjusting to the
desired sampling rate.
There are two ADCs on the EV kit. In standalone mode,
the two ADCs are read sequentially, while in FPGA mode
they can be read simultaneously. To use the ADCs in
multichannel mode, move the shunts described in Table 3
for CS Mode. In the Configuration tab, the correct selec-
tion must be made for Both Channels and the Interface
Mode must be in CS mode.
The two ADCs on the EV kit have a variety of interface
modes to the master. The modes include CS mode and
daisy-chain mode.
Table 3. Interface Mode Jumper Settings
INTERFACE MODE
CS Mode, No Busy
CS Mode, With Busy
Daisy Chain
J35
J38
J19
J20
CNVST2 (3-4), SCLK2 (7-8), DVDD (11-12)
CNVST2 (3-4), SCLK2 (7-8), DVDD (11-12)
CNVST1 (1-2), SCLK1 (5-6), AGND (9-10)
DOUT2 (1-2)
DVDD (1-2)
OPEN
SHORT
OPEN
DOUT2 (1-2)
DVDD (1-2)
DOUT_DAISY (3-4)
DOUT_DAISY (3-4)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
4) Enter the Data (V) value into the ADC Data Read
(V) Min numeric box.
5) Apply a full-scale signal (+5V or +10V depending
upon ADC device on the EV kit) to the ADC inputs
and click Read Data.
6) Enter the Data (V) value into the ADC Data Read
(V) Max numeric box.
7) Click Calculate.
8) The GUI will adjust the Gain Coefficient value and
Offset (mV) value.
9) Software calibration is enabled by checking the En-
able Calibration checkbox. This calibration is used
for measurements taken with the Scope, DMM,
Histogram, and FFT tabs.
System Calibration
The purpose of this procedure is to calculate coefficients
to compensate gain and offset error. This procedure
allows the calibration using any two points that fit the input
voltage range. A DC supply and DMM is required for this
procedure.
1) Measure the zero-scale and full-scale signal applied
at the input of the EV kit.
2) Enter the voltage values into the Input Measured
(V) Min and Max numeric boxes (±5V or ±10V de-
pending upon the ADC device on the EV kit).
3) Apply a zero-scale signal (-5V or -10V depending
upon ADC device on the EV kit) to the ADC inputs
and click Read Data.
Figure 1. EV Kit Software (Configuration Tab)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
allows counts and voltages. Once the desired configuration
is set, click on the Capture button. The right side of the tab
sheet displays details of the waveform, such as average,
standard deviation, maximum, minimum, and fundamental
frequency. Figure 2 displays the ADC data when a
sinusoidal signal is applied to the inputs on the EV kit.
Scope Tab
The Scope tab sheet is used to capture data and display it
in the time domain. Sampling rate and number of samples
can also be set in this tab if they were not appropriately
adjusted in other tabs. The Display Unit drop-down list
Figure 2. EV Kit Software (Scope Tab)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
DMM Tab
The DMM tab sheet provides the typical information as a digital multimeter. Once the desired configuration is set, click
on the Capture button.
Figure 3. EV Kit Software (DMM Tab)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
sheet displays details of the histogram such as average,
standard deviation, maximum, minimum, peak-to-peak
noise, effective resolution, and noise-free resolution.
Figure 4 shows data when inputs AIN0+ and AIN0- are
connected to GND.
Histogram Tab
The Histogram tab sheet is used to capture the histogram
of the data. Sampling rate and number of samples can
also be set in this tab if they were not appropriately
adjusted in other tabs. Once the desired configuration is
set, click on the Capture button. The right side of the tab
Figure 4. EV Kit Software (Histogram Tab)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
When coherent sampling is needed, this tab allows the
user to calculate the input frequency or the master clock
coming into the board. Either adjust the input frequency
applied to the signal generator or adjust the master
applied to the SYNC_IN SMA connector. See the Sync
Input and Sync Output section before using this feature.
Figure 13 shows the setup Maxim Integrated uses to cap-
ture data for coherent sampling.
FFT Tab
The FFT tab sheet is used to display the FFT of the data.
Sampling rate and number of samples can also be set in
this tab if they were not appropriately adjusted in other tabs.
Once the desired configuration is set, click on the Capture
button. The right side of the tab displays the performance
based on the FFT, such as fundamental frequency, SNR,
SINAD, THD, SFDR, ENOB, and noise floor.
Figure 5. EV Kit Software (FFT Tab)
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
kit can be used with a FPGA to achieve full speed and a
larger sample depth.
Detailed Description of Hardware
The MAX1115X/MAX1116X EV kit provides a proven
signal path to demonstrate the performance of the
MAX1115X/MAX1116X 18-/16-bit SAR ADCs. Included in
the EV kit are digital isolators, isolated DC-DC converters,
ultra-low-noise LDOs to all supply pins of the IC, on-board
references (MAX6126 and MAX6070), precision ampli-
fiers (MAX9632 for bipolar and MAX44242 for unipolar)
for analog inputs, and sync-in and sync-out signals for
coherent sampling. Two ADCs are on the board to allow
daisy-chain mode operation if desired.
The EV kit supports a number of different devices with a
10-pin µMAX package as listed in Table 4.
For the MAX11156 and MAX11154 in a 12-pin TDFN
package, please refer to the MAX11156EVSYS#
and for the MAX11166, MAX11167, MAX11164, and
MAX11165 in a 12-pin TDFN package, please refer to the
MAX11166EVSYS#. A full 18-bit data acquisition system
featuring the MAX11156 ADC and the MAX5318 DAC
is available as the MAXREFDES74# reference design,
which includes an FMC interface to the FPGA and stand-
alone USB.
An on-board FTDI controller is provided to allow for
evaluation in standalone mode, which has limitations on
maximum sample speed and on sample depth. The EV
Table 4. Products Supported with MAX1115X/MAX1116X EV Kit
RESOLUTION
(BITS)
MAX. SAMPLE RATE
(ksps)
INPUT RANGE
(V)
VOLTAGE
REFERENCE
PART NO.
MAX11150
MAX11152
18
18
18
16
16
16
500
500
0 to +5
0 to +5
±5
Internal REF
External REF
Internal REF
Internal REF
External REF
Internal REF
MAX11158
500
MAX11160 (MAX11161)
MAX11162 (MAX11163)
MAX11168 (MAX11169)
500 (250)
500 (250)
500 (250)
0 to +5
0 to +5
±5
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
USB Interface
Reference
The maximum sample rate is 250ksps and the maximum
sample size is 16384.
Depending upon the target IC on the EV kit, there are
different sources for the voltage reference. As listed in
Table 4, some ADCs have the option to use an internal
reference. In addition, there are two voltage references
on the board and the option to provide a user-supplied
external reference signal.
FMC Interface
The user should confirm compatibility of pin usage
between their own FMC implementation and that of the
MAX1115X/MAX1116X EV kit before connecting the
MAX1115X/MAX1116X EV kit to a different system with
FMC connectors.
For ADCs that require an external reference, the EV kit
includes two on-board references plus the option for a
user-supplied reference. The MAX6126 (U11) is an ultra-
high-precision, ultra-low-noise, series voltage reference
with 3ppm/°C maximum temperature coefficient and the
MAX6070 (U12) low-noise, high-precision series voltage
reference offers the highest performance SOT23 voltage
references with 6ppm/°C maximum temperature coefficient.
User-Supplied SPI Interface
In addition to the USB and FMC interfaces, the EV kit pro-
vides a 12-pin PMOD-style header (J25) for user-supplied
SPI interface. To evaluate the EV kit with a user-supplied
SPI bus, disconnect from the FMC bus and remove
jumper J14. Apply the user-supplied SPI signals to SCLK,
CNVST, DIN, and DOUT at the PMOD header. Make sure
the return ground is connected to the PMOD ground.
To use these voltage reference sources, populate jump-
ers J13 and J37. See Table 5 for jumper settings.
For a user-supplied external reference, remove the
jumper on J13 and connect a reference voltage to
ADC_EXT_REF at TP12. Measure and enter the value
of the external reference voltage into the Reference
Voltage edit box on the Configuration tab of the GUI.
When using devices with an internal reference, remove
all jumpers from J13 and J37.
The on-board FTDI chip used for standalone mode does
not conflict with the user-supplied SPI if it is powered off
by removing jumper J14.
WARNING: DO NOT PLUG THIS HEADER INTO A
STANDARD PMOD INTERFACE FOUND ON OTHER
FPGA OR MICROCONTROLLER PRODUCTS. THE
SIGNAL DEFINITION IS UNIQUE TO THIS EV KIT.
Table 5. Reference Source Options
REF SOURCE
JUMPER
CONNECTION
FUNCTION
Select U12 MAX6070
J13
1-2
1-2 and 11-12
2-3
MAX6070
J37
VREF1_ADC, VREF2_ADC
Select U11 MAX6126
J13
MAX6126
J37
1-2 and 11-12
OPEN
VREF1_ADC, VREF2_ADC
Select ADC_EXT_REF
J13
EXT_REF (TP12)
INT_REF
J37
1-2 and 11-12
OPEN
VREF1_ADC, VREF2_ADC
—
J13
J37
OPEN
MAX11150/MAX11158/MAX11160/MAX11168 only
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
for the MAX9632 op amps, as well +10V and -10V sup-
plies for the MAX44242 op amps. Additional supplies are
generated for +5V, +5.33V, and +3.3V/+2.5 for the ADCs
User-Supplied Power Supply
The EV kit receives power from a single DC source of
20V, 500mA through a J1 power jack. The MAX13256,
H-bridge driver and transformer create an additional
negative rail for +18V and -18V. The power is then recti-
fied and regulated down to a +15V and -15V supplies
and V
. See the EV kit schematics for details. Specific
REF
voltages can be connected to the board for each rail, see
Table 6 for corresponding jumper positions.
Table 6. Power Supply to the Board
POWER
INPUT CONNECTORS
JUMPERS
J12: 1-2
J15: 3-4
J16: 3-4
J26: 3-4
J27: 5-6
J17: 3-4
J24: 5-6
Single +20V input from a wall adapter
(default)
J1
J12: Open
J15: 1-2
J16: 1-2
J26: 3-4
J27: 5-6
J17: 3-4
J24: 5-6
TP35 (+18V)
TP30 (-18V)
An external ±18V
An external ±15V
An external ±10V
J12: Open
J15: Open
J16: Open
J26: 1-2
J27: 3-4
J17: 3-4
TP38 (+15V)
TP37 (-15V)
J24: 5-6
J12: Open
J15: Open
J16: Open
J26: 3-4
TP9 (+10V)
TP23 (-10V)
J27: 5-6
J17: 1-2
J24: 3-4
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
for gain control. Each ADC channel can be configured
as single-ended bipolar, differential bipolar, single-ended
unipolar, and differential unipolar. See Tables 8 and 9 for
these analog input configurations for channels A and B,
respectively.
Analog Input Voltage Ranges
The MAX1115X/MAX1116X are 18-/16-bit, single-chan-
nel, pseudo-differential ADCs. The ADCs convert input
signals on the ADC pin AIN+ (ADx_INP) in the range of
(±5V + AIN-) for bipolar or (5V + AIN-) to AIN- for unipolar.
For accurate conversions, the ADC pin AIN+ should also
The analog front-end consists of two channels (A and B,
one for each ADC) and for each channel there are four
user-selectable input pairs (for example AINx+ and AINx-
where x is 0, 1, 2, or 3) allowing selection between one of
two op amp solutions. The MAX9632, which is a 36V, pre-
cision, low-noise, wide-band amplifier or the MAX44242,
which is a 20V, low input-bias-current, low-noise, dual
op amp. The op amps can be configured as inverting or
noninverting amplifiers by jumper selectors. Both op amps
work as anti-aliasing lowpass filters (LPF) and can be
daisy-chained to create a second-order LPF.
be limited to ±(V
+ 0.1V) for bipolar and (V
+ 0.1V)
DD
DD
to -0.1V for unipolar. The ADC pin AIN- (ADx_INM) has an
input range of -0.1V to +0.1V and is typically connected
to the analog ground plane (AGND) of the EV kit. The
MAX1115X/MAX1116X perform a true differential sample
on inputs between AIN+ and AIN- with good common-
mode rejection and by connecting the EV kit input signal
GND_SENSE to the ground reference of the input signal
source. This allows for improved sampling of remote
transducer inputs. See the jumper settings in Table 2 for
J34 and J39.
The range of possible configurations for Channels A and
B are listed in Tables 8 and 9, and the jumper connections
are shown in Figures 6 to 12.
ADC Input Amplifiers
The input amplifiers allow for significant flexibility, support-
ing bipolar or unipolar input paths, as well as the option
Table 7. Analog Input Voltage Ranges
ADC INPUT
RANGE
MAX9632 INPUT
RANGE
MAX44242 INPUT
COMMENTS
RANGE
ADC
MAX11158,
MAX11168
Beyond-the-Rail ADCs work from
unipolar supply
±5V
±10V
±10V
V
REF
is used to bias the op amp
common mode to support 0 to +5V
input to the ADC.
±5V
±5V
VREF2 bias’s
common mode for U9
(MAX44242) at 2.5V.
VREF4 bias’s common
mode for U26
VREF1 bias’s common
mode for U8 (MAX9632)
at 2.5V.
VREF3 bias’s common
mode for U28
MAX11150,
MAX11152,
MAX11160,
MAX11162
The first ADC (U10) Common Mode
(CM) bias is set with VREF1 and
VREF2 depending upon the op amp
selected, and the second ADC (U14)
CM bias is set with VREF3 and
VREF4 depending upon the op amp
selected.
0 to +5V
(MAX9632) at 2.5V
(MAX44242) at 2.5V
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 8. Analog Input Configurations (Channel A0–A3)
CONFIGURATION
SIGNAL-PATH INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
NO.
DESCRIPTION
J28: 1-2
Noninverting, single-ended,
second-order LPF (default)
CON3: AIN0+ (or TP2)
and AGND (or TP8)
J29: 1-2
J32: 5-6 and 3-4
J34: 1-2 and 7-8
1
MAX9632, Channel A0
MAX9632, Channel A0
MAX9632, Channel A0
MAX9632, Channel A0
MAX9632, Channel A1
MAX9632, Channel A1
MAX9632, Channel A1
MAX44242, Channel A2
MAX44242, Channel A2
MAX44242, Channel A2
J28: Open
J29: 1-2
J32: 5-6 and 3-4
J34: 1-2 and 7-8
Noninverting, differential, second-
order LPF
CON3 (TP2): AIN0+
CON2 (TP1): AIN0-
2
3
J28: 1-2
J29: 3-4
J32: 1-2 and 7-8
J34: 1-2 and 7-8
CON3: AIN0+
or (TP2) and AGND (or
TP8)
Inverting, single-ended, second-
order LPF
J28: Open
J29: 3-4
J32: 1-2 and 7-8
J34: 1-2 and 7-8
Inverting, differential, second-order CON2 (TP1): AIN0-
LPF
4
CON3 (TP2): AIN0+
J28: Open
J29: 1-2
J32: 3-4 and 7-8
J34: 1-2 and 7-8
Noninverting, single-ended, first-
order LPF
CON5: AIN1+ (or TP7)
and AGND (or TP15)
5
J28: Open
J29: Open
J32: 3-4 and 7-8
J34: 1-2 and 7-8
CON5 (TP7): AIN1+
CON4 (TP10): AIN1-
6
Differential, first-order LPF
J28: Open
J29: 3-4
J32: 3-4 and 7-8
J34: 1-2 and 7-8
Inverting, single-ended, first-order
LPF
CON4: AIN1- (or TP10)
and AGND (or TP15)
7
J33: 1-2
J31: 1-2
J36: 5-6 and 3-4
J34: 3-4 and 7-8
Noninverting, single-ended,
second-order LPF (default)
TP19: AIN2+ and AGND
(or TP11)
8
J33: Open
J31: 1-2
J36: 5-6 and 3-4
J34: 3-4 and 7-8
Noninverting, differential, second-
order LPF
TP19: AIN2+
TP18: AIN2-
9
J33: 1-2
J31: 3-4
J36: 1-2 and 7-8
J34: 3-4 and 7-8
Inverting, single-ended, second-
order LPF
TP19: AIN2+ and AGND
(or TP11)
10
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│ 17
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Evaluates: MAX11150/MAX11152/
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 8. Analog Input Configurations (Channel A0–A3) (continued)
CONFIGURATION
SIGNAL-PATH INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
NO.
DESCRIPTION
J33: Open
Inverting, differential, second-order TP18: AIN2-
J31: 3-4
J36: 1-2 and 7-8
J34: 3-4 and 7-8
11
MAX44242, Channel A2
LPF
TP19: AIN2+
J31: 1-2
J36: 3-4 and 7-8
J34: 3-4 and 7-8
Noninverting, single-ended, first-
order LPF
TP14: AIN3+ and AGND
(or TP17)
12
13
14
MAX44242, Channel A3
MAX44242, Channel A3
MAX44242, Channel A3
J31: Open
J36: 3-4 and 7-8
J34: 3-4 and 7-8
TP14: AIN3+
TP16: AIN3-
Differential, first-order LPF
J31: 3-4
J36: 3-4 and 7-8
J34: 3-4 and 7-8
Inverting, single-ended, first-order
LPF
TP16: AIN3- and AGND
(or TP17)
AIN0-
J28
-
1
3
2
4
J32
1
3
2
4
-
MAX9632
J34
1
ADC_INP
2
+
5
7
6
8
AIN0+
MAX9632
3
4
6
8
V
IN
MAX1115X/
MAX1116X
+
5
7
SAR ADC
ADC_INM
VREF
AIN1-
AIN1+
J29
1
3
2
4
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 6. Noninverting, Single-Ended, Second-Order LPF
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
AIN0-
-
J28
2
4
1
3
J32
1
2
4
V
IN
MAX9632
-
3
5
7
J34
+
ADC_INP
ADC_INM
2
1
3
6
8
MAX9632
AIN0+
4
6
8
MAX1115X/
MAX1116X
SAR ADC
+
5
7
VREF
AIN1-
AIN1+
J29
1
3
2
4
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 7. Noninverting, Differential, Second-Order LPF
AIN0-
-
J28
1
3
2
4
J32
1
3
2
-
MAX9632
4
6
8
J34
ADC_INP
ADC_INM
+
2
1
AIN0+
5
7
MAX9632
+
3
5
7
4
6
8
V
IN
MAX1115X/
MAX1116X
SAR ADC
VREF
AIN1-
AIN1+
J29
1
3
2
4
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 8. Inverting, Single-Ended, Second-Order LPF
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
AIN0-
-
J28
1
3
2
4
J32
1
3
2
4
V
IN
-
MAX9632
J34
+
ADC_INP
ADC_INM
2
1
AIN0+
5
7
6
8
MAX9632
3
5
7
4
6
8
MAX1115X/
MAX1116X
SAR ADC
+
VREF
AIN1-
J29
1
3
2
4
AIN1+
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 9. Inverting, Differential, Second-Order LPF
AIN0-
-
J28
1
3
2
4
J32
1
3
2
-
MAX9632
4
J34
+
ADC_INP
ADC_INM
1
3
2
4
AIN0+
5
7
6
8
MAX9632
+
MAX1115X/
MAX1116X
SAR ADC
5
7
6
8
VREF
AIN1-
AIN1+
J29
1
3
2
4
V
IN
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 10. Noninverting, Single-Ended, First-Order LPF
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
AIN0-
-
J28
1
3
2
4
J32
1
3
2
4
-
MAX9632
J34
+
ADC_INP
ADC_INM
2
1
AIN0+
5
7
6
8
MAX9632
3
5
7
4
6
8
MAX1115X/
MAX1116X
SAR ADC
+
VREF
AIN1-
J29
1
3
2
4
V
IN
AIN1+
INPUT FROM MAX44242 Amps
GND_SENSE
Figure 11. Differential, First-Order LPF
AIN0-
J28
-
2
4
1
3
J32
1
3
2
4
MAX9632
-
J34
+
ADC_INP
ADC_INM
1
3
2
4
AIN0+
5
7
6
8
MAX9632
MAX1115X/
MAX1116X
SAR ADC
+
5
7
6
8
VREF
AIN1-
AIN1+
J29
2
4
1
3
V
IN
INPUT FROM MAX44242 AMPS
GND_SENSE
Figure 12. Inverting, Single-Ended, First-Order LPF
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 9. Analog Input Configurations (Channel B0–B3)
CONFIGURATION
SIGNAL-PATH INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
J5: 1-2
No.
DESCRIPTION
Noninverting, single-ended,
second-order LPF (default)
CON11: BIN0+ (or TP54):
and AGND (or TP39)
J9: 1-2
J10: 5-6 and 3-4
J39: 1-2 and 7-8
1
MAX9632, Channel B0
MAX9632, Channel B0
MAX9632, Channel B0
MAX9632, Channel B0
J5: Open
J9: 1-2
J10: 5-6 and 3-4
J39: 1-2 and 7-8
Noninverting, differential,
second-order LPF
CON11 (TP54): BIN0+
CON10 (TP53): BIN0-
2
3
4
J5: 1-2
J9: 3-4
J10: 1-2 and 7-8
J39: 1-2 and 7-8
CON11: BIN0+
or (TP54): and AGND (or
TP39)
Inverting, single-ended, second-
order LPF
J5: Open
J9: 3-4
J10: 1-2 and 7-8
J39: 1-2 and 7-8
Inverting, differential, second-
order LPF
CON10 (TP53): BIN0-
CON11 (TP54): BIN0+
CON13: BIN1+
or (TP56): and AGND (or
TP41)
J9: 1-2
J10: 3-4 and 7-8
J39: 1-2 and 7-8
Noninverting, single-ended, first-
order LPF
5
6
7
MAX9632, Channel B1
MAX9632, Channel B1
MAX9632, Channel B1
J9: Open
J10: 3-4 and 7-8
J39: 1-2 and 7-8
CON13 (TP56): BIN1+
CON12 (TP55): BIN1-
Differential, first-order LPF
J9: 3-4
J10: 3-4 and 7-8
J39: 1-2 and 7-8
Inverting, single-ended, first-
order LPF
CON12: BIN1- or (TP55):
and AGND (or TP41)
J6: 1-2
Noninverting, single-ended,
second-order LPF (default)
TP58: BIN2+ and AGND (or
TP40)
J7: 1-2
J11: 5-6 and 3-4
J39: 3-4 and 7-8
8
9
MAX44242, Channel B2
MAX44242, Channel B2
MAX44242, Channel B2
J6: Open
J7: 1-2
J11: 5-6 and 3-4
J39: 3-4 and 7-8
Noninverting, differential,
second-order LPF
TP58: BIN2+
TP57: BIN2-
J5: 1-2
J7: 3-4
J11: 1-2 and 7-8
J39: 3-4 and 7-8
Inverting, single-ended, second-
order LPF
TP58: BIN2+ and AGND (or
TP40)
10
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Table 9. Analog Input Configurations (Channel B0–B3) (continued)
CONFIGURATION
SIGNAL-PATH INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
No.
DESCRIPTION
J6: Open
Inverting, differential, second-
order LPF
TP57: BIN2-
TP58: BIN2+
J7: 3-4
J11: 1-2 and 7-8
J39: 3-4 and 7-8
11
MAX44242, Channel B2
J7: 1-2
J11: 3-4 and 7-8
J39: 3-4 and 7-8
Noninverting, single-ended, first-
order LPF
TP60: BIN3+ and AGND (or
TP42)
12
13
14
MAX44242, Channel B3
MAX44242, Channel B3
MAX44242, Channel B3
J7: Open
J11: 3-4 and 7-8
J39: 3-4 and 7-8
TP60: BIN3+
TP59: BIN3-
Differential, first-order LPF
J7: 3-4
J11: 3-4 and 7-8
J39: 3-4 and 7-8
Inverting, single-ended, first-
order LPF
TP59: BIN3- and AGND (or
TP42)
Note: Alternate connections are shown in parentheses.
one option should be used at a time. The relationship
between f , f , N , and M is given as
follows:
Sync Input and Sync Output
IN
S
CYCLES
SAMPLES
Sync input and sync output is applicable to the FPGA
(ZedBoard) and is not used in standalone mode. The
SYNC_IN SMA accepts an approximate 100MHz wave-
form signal to generate the system clock of the ZedBoard.
For maximum performance, use a low-jitter clock that
syncs to the user’s analog function generator. The
SYNC_OUT SMA outputs a 10MHz square waveform
that syncs to the user’s analog function generator. Both
options are used for coherent sampling of the IC. Only
f /f = N
/M
IN S
CYCLES SAMPLES
where:
f
= Input frequency
IN
f = Sampling frequency
S
N
= Prime number of cycles in the sampled set
CYCLES
M
= Total number of samples
SAMPLES
LOW-JITTER CLOCK
REF_OUT
~100MHz
ZedBoard/FPGA Board
OUT
10MHz
SIGNAL GENERATOR
_
MASTER_CLOCK
INV-
10kHz
SYNC _IN
FPGA
PC
REF_IN
+
INV+
MAX1115X/MAX1116X EV KIT
ETHERNET CABLE
Figure 13. EV Kit Coherent Sampling Setup
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 14. MAX1115X/MAX1116X EV Kit Component Placement Guide—Top Side
Maxim Integrated
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 15. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 1
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 16. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 2
Maxim Integrated
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 17. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 3
Maxim Integrated
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 18. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 4
Maxim Integrated
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MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 19. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 5
Maxim Integrated
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 20. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 6
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Figure 21. MAX1115X/MAX1116X EV Kit Component Placement Guide—Bottom Side
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Component List and Schematic Diagrams
Refer to files “evkit_bom_max1115x6x_evkit_revA.csv” and “MAX1115X6X_EVKIT_Reva.SCH.pdf” attached to this data
sheet for component information and schematics diagrams.
Contact Avnet to purchase a ZedBoard (AES-Z7EV-7Z020-G) to communicate with the MAX1115X/MAX1116X EV kit.
Ordering Information
PART
TYPE
EVKIT
EVKIT
EVKIT
EVKIT
EVKIT
EVKIT
MAX11150EVKIT#
MAX11152EVKIT#
MAX11158EVKIT#
MAX11160EVKIT#
MAX11162EVKIT#
MAX11168EVKIT#
#Denotes RoHS compliant.
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Evaluates: MAX11150/MAX11152/
MAX11158/MAX11160/MAX11161/MAX11162/
MAX11163/MAX11168/MAX11169
MAX1115X/MAX1116X Family
Evaluation Kit
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
5/15
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
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