MAX11253EVKIT [MAXIM]
High-Speed USB Connector, FMC Connector, and Pmod-Style Connector;
| 型号： | MAX11253EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Speed USB Connector, FMC Connector, and Pmod-Style Connector |
| 文件： | 总36页 (文件大小：4919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
General Description
Features
The MAX11253/MAX11254 evaluation kit (EV kit) pro-
vides a proven design to evaluate the MAX11253/
MAX11254 family of 16-bit/24-bit, 6-channel, 64ksps,
integrated PGA delta-sigma ADCs. The EV kit includes
a graphical user interface (GUI) that provides communi-
cation from the target device to the PC. The EV kit can
operate in multiple modes:
● High-Speed USB Connector, FMC Connector, and
Pmod-Style Connector
● 8MHz SPI Clock Capability through FMC Connector
● 8MHz SPI Clock Capability in Standalone Mode
● Various Sample Sizes and Sample Rates
● Collects Up to 1 Million Samples
(with FPGA Platform)
1) Standalone Mode: in “standalone” mode, the EV
kit is connected to the PC via a USB cable and
performs a subset of the complete EV kit functions
with limitations for sample rate, sample size, and no
support for coherent sampling.
● Time Domain, Frequency Domain, and Histogram
Plotting
● Sync In and Sync Out for Coherent Sampling
(with FPGA Platform)
2) FPGA Mode: in “FPGA” mode, the EV kit is
connected to an Avnet ZedBoard™ through a low-
pin-count FMC connector. ZedBoard features a
● On-Board Input Buffers: MAX9632 and MAX44205
(Fully Differential)
®
®
● On-Board Voltage References
Xilinx Zynq -7000 SoC, which connects to the
PC through an Ethernet port, allowing the GUI to
perform different operations with full control over
mezzanine card functions. The EV kit with FPGA
platform performs the complete suite of evaluation
tests for the target IC.
(MAX6126 and MAX6070)
● Proven PCB Layout
● Fully Assembled and Tested
● Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
3) User-Supplied SPI Mode: In addition to the USB and
FMC interfaces, the EV kit provides a 12-pin Pmod™-
style header for user-supplied SPI interface to con-
nect the signals for SCLK, DIN, DOUT, and CNVST.
Ordering Information appears at end of data sheet.
Pmod is a trademark of Digilent Inc.
ZedBoard is a trademark of Avnet, Inc.
®
®
The EV kit includes Windows XP , Windows 7, and
Windows 8.1-compatible software for exercising the fea-
tures of the IC. The EV kit GUI allows different sample
sizes, adjustable sampling rates, internal or external ref-
erence options, and graphing software that includes the
FFT and histogram of the sampled signals.
Xilinx and Zynq are registered trademarks and Xilinx is a regis-
tered service mark of Xilinx, Inc.
Windows and Windows XP are registered trademarks and reg-
istered service marks of Microsoft Corporation.
The ZedBoard accepts a +12V AC-DC wall adapter. The
EV kit can be powered by a local +12V supply. The EV kit
has on-board transformers and digital isolators to sepa-
rate the IC from the ZedBoard/on-board processor.
The MAX11253/MAX11254 EV kit comes installed with a
MAX11253ATJ+ or MAX11254ATJ+ in a 32-pin TQFN-EP
package.
19-7584; Rev 2; 4/18
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX11253/11254 EV Kit Photo
Maxim Integrated
│ 2
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
System Block Diagram
MAX11253/MAX11254 EV Kit Files
Note: In the following section(s), software-related items
are identified by bolding. Text in bold refers to items direct-
ly from the EV system software. Text in bold and under-
line refers to items from the Windows operating system.
FILE
DECRIPTION
Application Program
(GUI)
MAX11253_54EVKitSetupV1.0.exe
Procedure
ZedBoard firmware
(SD card to boot
Zynq)
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
Boot.bin
1) Visit http://www.maximintegrated.com/evkitsoft-
ware to download the latest version of the EV kit soft-
ware, MAX11253_54EVKITSetupV1.0.zip. Save the
EV kit software to a temporary folder and uncompress
the ZIP file.
Quick Start
Required Equipment
●
●
●
●
MAX11253/MAX11254 EV kit
+12V (500mA) power supply
Micro-USB cable
2) Install the EV kit software and USB driver on your
computer by running the MAX11253_54EVKitSetupV1.0.exe
program inside the temporary folder. The program
files are copied to your PC and icons are created in
the Windows Start | Programs menu. At the end of
the installation process the installer will launch the in-
staller for the FTDIChip CDM drivers.
ZedBoard FPGA platform
(optional – NOT INCLUDED with EVKit)
●
●
Function generator (optional)
Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
Maxim Integrated
│ 3
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
For Standalone mode:
7) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu select
FPGA. Verify that the lower left status bar indicates
the EV Kit hardware is Connected.
1) Verify that all jumpers are in their default positions for
the EV kit board (Table 2).
2) Connect the PC to the EV kit using a micro-USB ca-
ble.
For Either Standalone or FPGA Mode:
3) Connect the +12V adapter to the EV kit.
1) Connect the positive terminal of the function genera-
tor to the AIN0D+ (TP1) test point on the EV kit. Con-
nect the negative terminal of the function generator to
the AIN0D- (TP2) test point on the EV kit.
4) Start the EV kit software by opening its icon in the
Start | Programs menu. The EV kit software appears
as shown in Figure 1. From the Device menu select
Standalone. Verify that the lower left status bar indi-
cates the EV Kit hardware is Connected.
2) Configure the signal source to generate a 100Hz,
1V
sinusoidal wave with +1V offset.
P-P
For FPGA mode (when connected to a Zedboard):
3) Turn on the function generator.
1) Connect the Ethernet cable from the PC to the Zed-
Board and configure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connec-
tion to IP address 192.168.1.2 and subnet Mask to
255.255.255.0.
4) In the Device menu, choose either standalone or the
FPGA option. In the configuration group, select Chan-
nel 0 and click Convert in the serial interface menu.
5) Click on the Scope tab.
2) Verify that the ZedBoard SD card contains the Boot.
6) Check the Remove DC Offset checkbox to remove
bin file for the MAX11253/MAX11254 EV kit.
the DC component of the sampled data.
3) Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
7) Click the Capture button to start the data analysis.
8) The EV kit software appears as shown in Figure 1.
4) Verify that all jumpers are in their default positions for
the ZedBoard (Table 1) and EV kit board (Table 2).
9) Verify that the frequency, which is displayed on the
right, is approximately 100Hz. The scope image has
buttons in the upper right corner that allow zooming
in to detail.
5) Connect the 12V power supply to the ZedBoard.
Leave the Zedboard powered off.
6) Enable the ZedBoard power supply by sliding SW8 to
ON and connect the +12V adapter to the EV kit.
Table 1. ZedBoard Jumper Settings
JUMPER
SHUNT POSITION
DESCIPTION
J18
1-2
VDDIO set for 3.3V.
JP11
JP10
JP9
JP8
JP7
2-3
1-2
1-2
2-3
2-3
Boot from SD Card
J12
J20
NA
NA
SD Card installed
Connected to 12V wall adapter
SW8
OFF
ZedBoard power switch, OFF while connecting boards
Maxim Integrated
│ 4
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 2. MAX11253/MAX11254 Board Jumper Settings
JUMPER
POSITION
JUMPER
POSITION
HEADER
DESCRIPTION
HEADER
DESCRIPTION
Use MAX6126 3.0V as VREF
signal
Short AIN2.3- (J29, TP42) to
AGND and for U12 noninverting
configuration
1-2*
1-2*
3-4*
1-2*
3-4*
1-2*
3-4*
Use MAX6070 3.0V as VREF
signal
JMP1
1-3
1-4
J32
Short AIN2.3+ (J30, TP43) to
AGND and for U12 inverting
configuration
Use MAX6070 1.8V as VREF
signal
Open*
1-2
Generate +3.3V for DVDD
Generate +2.0V for DVDD
Select +3.3V or +2.0V as DVDD
Select +1.8V as DVDD
U1 uses internal clock
Short AIN2.2- (TP40) to AGND
and for U13 noninverting
configuration
J8
1-2*
2-3
J33
J34
J10
Short AIN2.2+ (TP41) to
AGND and for U13 inverting
configuration
Open*
1-2
J11
External clock from FPGA
External clock from U10
Select +3.3V as AVDD
Select +1.8V as AVDD
Select AVSS as REFN
Short AIN2.4- (TP44) to AGND
and for U14 noninverting
configuration
2-3
1-2*
2-3
J12
J13
Short AIN2.4+ (TP45) to
AGND and for U14 inverting
configuration
1-2*
Select REFN_S from J1 as
REFN for external sense point
2-3
Open*
1-2
Connect output of U11 to
inverting input of U13
1-2*
3-4
Use internal 1.8V subregulator if
DVDD ≥ 2.0V
Connect AIN2.2- (TP40) to
inverting input of U13
J14
J15
J16
Use DVDD for internal logic if
DVDD ≤ 2.0V
J35
Connect output of U11 to
noninverting input of U13
5-6
Open*
1-2
Use TP23 as GPIO1
Use external SYNC signal
Connect AIN2.2+ (TP41) to
noninverting input of U13
7-8*
1-2*
3-4
Select REFP_F signal as REFP
input
1-2*
2-3
Connect output of U12 to
inverting input of U14
Select REFP_S signal from J1
as REFP input
Connect AIN2.4- (TP44) to
inverting input of U14
Use AGND as AVSS. Use this
setting if AVDD is +3.3V
1-2*
2-3
J36
Connect output of U12 to
noninverting input of U14
J17
J24
5-6
Use -1.8V as AVSS. Use this
setting if AVDD is +1.8V
Connect AIN2.4+ (TP45) to
noninverting input of U14
7-8*
1-2*
2-3
Use VREF as REFP_F
Use AVDD as REFP_F
No offset to U13 noninverting
input
Open*
1-2
J37
J38
Short AIN2.1- (J27, TP38) to
AGND and for U11 noninverting
configuration
1-2*
3-4*
Offset U13 output by VREF/2
No offset to U14 noninverting
input
J31
Open*
1-2
Short AIN2.1+ (J28, TP39) to
AGND and for U11 inverting
configuration
Offset U14 output by VREF/2
Maxim Integrated
│ 5
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 2. MAX11253/MAX11254 Board Jumper Settings (continued)
JUMPER
POSITION
JUMPER
POSITION
HEADER
DESCRIPTION
HEADER
DESCRIPTION
No offset to U18 noninverting
input
Short AIN3.1- (TP56) to AGND
and for U15 noninverting
configuration
Open*
1-2
1-2*
3-4*
1-2*
3-4*
1-2*
3-4*
1-2*
3-4*
J46
Offset U18 output by VREF/2
J39
Short AIN3.1+ (TP57) to
AGND and for U15 inverting
configuration
Short AIN4+ (J47, TP72) to
AGND
1-2*
J49
Short AIN4- (J48, TP73) to
AGND
3-4*
Short AIN3.3- (TP60) to AGND
and for U16 noninverting
configuration
1-2*
3-4*
Short AIN5+ (TP74) to AGND
Short AIN5- (TP75) to AGND
Use external +12V source
Use +12V from ZedBoard
J50
J63
J40
J41
J42
Short AIN3.3+ (TP61) to
AGND and for U16 inverting
configuration
Open*
1-2
Short AIN3.2- (TP58) to AGND
and for U17 noninverting
configuration
Open
If connected to ZedBoard FPGA
J64
J65
If connected to PC through USB
interface
1-2*
Short AIN3.2+ (TP59) to
AGND and for U17 inverting
configuration
Enable U28 H-bridge transformer
driver to use onboard ±15V
supply generation
1-2*
Short AIN3.4- (TP62) to AGND
and for U18 noninverting
configuration
Disable U28 and use and
external ±15V supply to TP83,
TP86, and TP87
2-3
Short AIN3.4+ (TP63) to
AGND and for U18 inverting
configuration
Use an external -15V power
supply, connected to TP86
1-2
3-4*
1-2
J66
J67
J68
Use U28 driver to generate
isolated -15V
Connect output of U15 to
inverting input of U17
1-2*
3-4
Use an external +15V power
supply, connected to TP83
Connect AIN3.2- (TP58) to
inverting input of U17
J43
Use U28 driver to generate
isolated +15V
Connect output of U15 to
noninverting input of U17
3-4*
1-2
5-6
Connect AIN3.2+ (TP59) to
noninverting input of U17
Use an external +12V power
supply to TP91 as VCC
7-8*
1-2*
3-4
Connect output of U16 to
inverting input of U18
Use onboard +12V from U32
LDO as VCC
3-4*
1-2
3-4
Connect AIN3.4- (TP62) to
inverting input of U18
AGND as VEE
Use an external -12V power
supply to TP90 as VEE
J44
J45
Connect output of U16 to
noninverting input of U18
J69
5-6
Use onboard -12V from U33
LDO as VEE
5-6*
Connect AIN3.4+ (TP63) to
noninverting input of U18
7-8*
*Default configuration
No offset to U17 noninverting
input
Open*
1-2
Offset U17 output by VREF/2
Maxim Integrated
│ 6
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Standby), Reset Registers, and RSTB Reset, Clock/
SYNC (Internal or External Clock, and Disable or Enable
SYNC Mode), and Other for Disable or Enable Current
Sink/Source and CAPREG LDO.
General Description of Software
The main window of the EV kit software contains seven
tabs: Configuration, Scope, DMM, Histogram, FFT, Scan
Mode, and Registers. The Configuration tab provides
control for the ADC configuration including calibration and
data capture. The other six tabs are used for evaluating
the data captured by the ADC.
The sample settings are available on the left of the config-
uration menu, which allow the user to select the Channel,
Sample Rate, Number of Samples and Clock Source if
FPGA device is used.
Configuration Tab
The Read Data and Status information is displayed on
the right, which shows the data in both voltage and Hex,
the sample rate, and power state for the selected chan-
nel. In addition, if there are any errors, the indicator lights
will turn red.
The Configuration tab provides an interface for selecting
and configuring the ADC from a functional perspective.
Select the desired Device for either Standalone or FPGA
in the dropdown menu and the corresponding properties
of the device are displayed including Channel number,
Sample Rate, Number of Samples, Reference Voltage,
Sequencing Mode, Calibration, GPO/GPIO selec-
tion, Input Path (Direct or internal PGA), Delta-Sigma
Modulator type selection for different Data Format and
Conversion Mode, Serial Interface function (Convert,
and Read All), Power setting (NOP, Power Down, and
Channel Selection
To select the desired channel among the six available
channels, click Channel # dropdown menu at the top left
and select the desired channel from 0 to 5. The default
selection is Channel 0.
Figure 1. EV Kit Software (Configuration Tab)
Maxim Integrated
│ 7
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Three conversion modes are provided: Continuous,
Single Cycle, and Single Continuous. Click the
Conversion Modes dropdown menu under the Delta-
Sigma Modulator section to select the desired conver-
sion mode.
Sample Rate (SPS)
To select the desired data rate for single-cycle mode from
50sps to 12800sps and for continuous mode data rate
from 1.9sps to 64000sps, choose the Sample Rate (SPS)
from the dropdown menu below the Channel # selection.
Serial Interface
Reference Voltage
To starting converting, click the Convert button under
the Serial interface section. To read all registers, click the
Read All button.
There are three different reference voltages available
on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+
(3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V,
place JMP1 from position 1 to 4. To select 3.0V MAX6070
with ±0.04% accuracy, place JMP1 from position 1 to 3. To
select 3.0V MAX6126 with ±0.02% accuracy, place JMP1
from position 1 to 2.
Power
The MAX11253/MAX11254 EV kit features three power-
down states: Normal Operating Power (NOP), Power
down, and Standby. Select the desired power state by
clicking the drop-down menu under the Power section.
Sequencer Mode
To change the sequencer mode, click the Sequence
Mode selection below the Sequencing menu and select
Mode 1, 2, or 3 as desired. Check the GPO Sequencer
Mode box to enable GPO/GPIO function in mode 3. In
addition, check the Enable box to enable the MUX and
GPO Delay. Choose the desired delay in microseconds
by clicking on the + or – buttons.
To reset the configuration settings back to default values,
press the Reset Registers button.
To exercise the power-on reset feature, click the RSTB
button.
Clock/SYNC
The internal clock mode is set at default condition. To
use the external clock provided on-board, select External
under the Clock/SYNC section and install jumper J11
from 2-3. To user-supplied external clock, select External
under the Clock/SYNC section and install jumper J11
from 1-2. In addition, the Sync mode can be enabled
or disabled by clicking the drop-down menu under this
Clock/SYNC section and install jumper J15. The Sync
signal should be provided externally.
ADC Calibration
Two types of software calibration for offset and gain are
available: Self calibration and system calibration.
The primary mode for calibration is using the dropdown
list to select a calibration mode, followed by clicking the
Calibrate button. The checkboxes for Self Offset, Self
Gain, System Offset, and System Gain allow for the
user to enable or disable the calibration values. The cali-
bration values can also be changed manually by entering
a hex value in the numeric box.
Other
To enable (J14 open) or disable (J14 installed and V
DDVD
≤ 2.0V) the internal CAPREG LDO for digital and I/O sup-
ply, select this option from the drop-down menu under
the Other section. Additionally, Current Sink/Source can
also be disabled or enabled under this section.
GPO/GPIO
To select GPO or GPIO ports, choose the option under the
GPO/GPIO dropdown menu and check the Enable box.
Input Path
Read Data and Status
Select Direct under the Input Path dropdown menu to
bypass the internal amplifiers and apply the analog input
signals directly to the MAX11253/MAX11254 inputs or to
use the external amplifiers.
The Read Data and Status on the far right hand side of
this Configuration menu depicts the received data and
status of the device such as the selected channel, data
rate, sample rate, and power state. Click the Read Data
and Status button to view the updated status.
Select PGA under the Input Path dropdown menu to use
the internal programmable gain amplifiers.
To save a configuration, select Save ADC Config As… in
the File menu. This saves all the ADC register values to a
XML file. To load a configuration, select Load ADC Config
in the File menu. When the XML file is loaded, all the reg-
ister values in the file are written to the ADC.
Delta-Sigma Modulator
To select the desired data format, click the Data Format
dropdown menu under the Delta-Sigma Modulator
section and choose either Bipolar or Unipolar with two’s
complement or offset binary options.
Maxim Integrated
│ 8
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
set, click on the Capture button. The right side of the tab
sheet displays details of the waveform, such as average,
standard deviation, maximum, minimum, and fundamen-
tal frequency as shown in Figure 2.
Scope Tab
The Scope tab sheet is used to capture data and display it
in the time domain. The desired Channel #, Sample Rate,
Number of Samples, Display Unit, Average Samples,
and Resolution Selection can also be set in this tab if
they were not appropriately adjusted in other tabs. The
Display Unit drop-down list allows counts in LSB and
voltages in V, mV, or µV. Once the desired configuration is
To save the captured data to a file, select Options > Save
Graph > Scope. This saves the setting on the left and the
data captured to a CSV file.
Figure 2. EV Kit Software (ScopeTab)
Maxim Integrated
│ 9
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
click on the Capture button. Figure 3 displays the results
shown by the DMM tab when a 1.5V signal is applied to
AIN0+ and 1.0V to AIN0-.
DMM Tab
The DMM tab sheet provides the typical information as a
digital multimeter. Once the desired configuration is set,
Figure 3. EV Kit Software (DMM Tab)
Maxim Integrated
│ 10
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
The histogram tab is enabled at default. Using the his-
togram will slow down the GUI response. To disable it,
check the Disable Histogram box.
Histogram Tab
The Histogram tab sheet is used to show the histogram
of the data. Sample rate and number of samples can also
be set in this tab if they were not appropriately adjusted
in other tabs. Once the desired configuration is set, click
on the Capture button. The right side of the tab sheet
displays details of the histogram such as average, stan-
dard deviation, maximum, minimum, peak-to-peak noise,
effective resolution, and noise-free resolution as shown
in Figure 4.
To save the histogram data to a file, go to Options > Save
Graph > Histogram. This saves the setting on the left
and the histogram data captured to a CSV file.
Figure 4. EV Kit Software (Histogram Tab)
Maxim Integrated
│ 11
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
To save the FFT data to a file, go to Options > Save
Graph > FFT. This saves the setting on the left and the
FFT data captured to a CSV file.
FFT Tab
The FFT tab sheet is used to display the FFT of the data.
The Sample Rate, Number of Samples, Resolution and
Window Function type can be set as desired. To calcu-
late the Adjusted Input Signal frequency for Coherent
Sampling, enter the Input Signal frequency in Hertz and
push the Calculate button. Once the preferred configura-
tion is set, click on the Capture button. The right side of
the tab displays the performance based on the FFT, such
as fundamental frequency, SNR, SINAD, THD, SFDR,
ENOB, and Noise Floor as shown in Figure 5.
When coherent sampling is needed, this tab allows the
user to calculate the external clock frequency applied
to the board. Adjust the input frequency of the low-
jitter clock to the value as shown in the Adjusted
Master Clock (Hz) and apply it to the EV KIT EXT_
CLK connector. See the Sync Input and Sync Output
section before using this feature.
Figure 5. EV Kit Software (FFT Tab)
Maxim Integrated
│ 12
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Figure 6 shows the setup Maxim Integrated uses to cap-
ture data for coherent sampling.
Calculate button and enter the Adjusted Master Clock
(Hz) frequency of approximately 8.192MHz into our low-
jitter clock. Timing for all SPI timing and sampling rate are
based off the system clock.
For coherent FFT evaluation, use the jumper settings
from Table 2 for proper configurations. The low-jitter clock
is synchronized with the signal generator at 10MHz from
the ZedBoard. To achieve coherent sampling, click on the
LOW-JITTER CLOCK
RF_IN
8.192 MHz
OUT
ZedBoard
PC
SIGNAL GENERATOR
10MHz
RF_IN
-
INV-
EXT_CLK
+
INV+
MAX11253/MAX11254EVKIT
ETHERNET CABLE
Figure 6. EV Kit Coherent Sampling Setup
Maxim Integrated
│ 13
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
In the Read Data section on top, select the desired unit
in either LSB or voltage (V, mV, or µV) under the Display
Unit drop-down menu. Then choose the desired sample
rate by clicking on the Sample Rate drop-down menu
under. Finally, click the Scan button to start convert-
ing and press the Read Data button to view the con-
verted data displayed on the right hand side as shown in
Figure 7.
Scan Mode Tab
The Scan Mode tab is used to perform selected data
conversions and read the converted data.
In the Sequence Setting section at the bottom, set the
desired sequencer mode (1 to 3) from the Sequence
Mode drop-down menu and select whether to assert
the RDYB pin after one channel or after scan com-
pletes options under the RDYB menu. Check the GPO
Sequencer Mode and Enable boxes as desired. Then
set the conversion time delay in µs for MUX and GPO by
clicking on the + or - buttons under the MUX Delay and
GPO Delay menu, allowing for high impedance source
networks to stabilize after the channels are selected.
Finally press the Read All button to view the selected
settings.
Figure 7. EV Kit Software (Scan Mode Tab)
Maxim Integrated
│ 14
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
ADC Registers Tab
Detailed Description of Hardware
The Registers tab sheet shows the device registers on
the left. The middle section shows the descriptions of the
selected register. Click Read All to read all registers and
refresh the window with the register settings. To write a
register first select the hex value in the Value column,
type the desired hex value and press Enter.
The MAX11253/MAX11254 EV kit provides a proven signal
path and board layout to demonstrate the performance of
the MAX11253/MAX11254 16-/24-bit, delta-sigma ADCs.
Included in the EV kit are digital isolators, isolated DC-DC
converters, ultra-low-noise LDOs to all supply pins of the
IC, on-board reference (MAX6126 and MAX6070), preci-
sion amplifiers (MAX9632 and MAX44205) for analog
inputs, and sync-in and sync-out signals for coherent
sampling.
The command byte is on the right side of the tab sheet.
This byte precedes all SPI transactions and is described
in the IC datasheet. To send a command byte enter a
hex value in the numeric box and click the Send button.
The command byte has two different formats includ-
ing Conversion Command and Register Read/Write.
Select the radio button for the desired mode to see the bit
description in the table. See Figure 8.
An on-board FTDI controller is provided to allow for
evaluation in standalone mode, which has limitations on
maximum sample speed and on sample depth. The EV kit
can be used with FPGA to achieve full speed and a larger
sample depth.
The EV kit supports a number of different devices as
listed in Table 3.
Figure 8. EV Kit Software (ADC Registers Tab)
Table 3. Products Supported with MAX11253/MAX11254 EV Kit
PART NO.
MAX11253
MAX11254
RESOLUTION
16-bits
MAX. SAMPLE RATE
64ksps
24-bits
64ksps
Maxim Integrated
│ 15
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
voltages can be connected to the board for each rail, see
Table 4 for corresponding jumper positions.
User-Supplied SPI
To evaluate the EV kit with a user-supplied SPI bus,
disconnect from the FMC bus and remove jumper J64.
Apply the user-supplied SPI signals to SCLK, CSB, DIN,
and DOUT at the PMOD_A header (J60). Make sure the
return ground is connected to PMOD ground.
ADC Input Amplifiers
The input amplifiers allow for significant flexibility, support-
ing bipolar or unipolar input paths, as well as the option
for gain control. Selected input amplifiers can be config-
ured as inverting, noninverting, differential bipolar, and
differential unipolar. See Table 5 for these analog input
configurations for channels 0 to 5.
The on-board FTDI chip used for standalone mode does
not conflict with the user-supplied SPI if it is powered off
by removing jumper J64.
CAUTION: DO NOT PLUG THIS HEADER INTO A
STANDARD PMOD INTERFACE FOUND ON OTHER
FPGA OR MICROCONTROLLER PRODUCTS. THE
SIGNAL DEFINITION IS UNIQUE TO THIS EV KIT.
The analog front-end consists of six channels, 0 to 5, and
there are four user-selectable input pairs (for example
AINx+ and AINx- where x is 2, 3, 4 or 5) allowing selec-
tion between one of two op amp solutions, the MAX9632
a 36V, precision, low-noise, wide-band amplifier or the
MAX44205, a 180MHz, low-noise, low-distortion, fully
differential op amp. The op amps can be configured as
inverting or noninverting amplifiers by jumper selectors.
Both op amps work as anti-aliasing lowpass filters (LPF)
and can be daisy-chained to create a second-order LPF.
FMC Interface:
The users should confirm compatibility of pin-usage between
their own FMC implementation and that of the Maxim
Integrated EV kit before connecting the Maxim Integrated
EV kit to a different system with FMC connectors.
Voltage References
The range of possible configurations are listed in Table 5.
There are three different reference voltages available
on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+
(3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V,
place JMP1 from position 1 to 4. To select 3.0V MAX6070
with ±0.04% accuracy, place JUMP1 from position 1 to
3. To select 3.0V MAX6126 with ±0.02% accuracy, place
JMP1 from position 1 to 2.
Table 4. Reference Source Options
REF
SOURCE
JUMPER
CONNECTION
FUNCTION
JMP1
J13
1-4
1-2
1-2
1-2
1-3
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
1-2
2-3
1-2
1-2
MAX6070
(1.8V)
Select U7
MAX6070
J16
For user-supplied external references, remove jumper
J24 and connect a reference voltage to J24-2. Measure
and enter the value of the external reference voltage into
the Reference Voltage edit box on the Configuration tab
of the GUI. Table 3 depicts the reference source options.
J24
JMP1
J13
MAX6070
(3.0V)
Select U8
MAX6070
J16
External DVDD Power Supply
J24
The internal 1.8V regulator can be replaced by an exter-
nal supply in the range of 1.7V to 2.0V. To use external
DVDD, disable the internal regulator by selecting the
Disable in the CAPREG LDO drop-down menu in the
Other section and install J14.
JMP1
J13
MAX6126
(3.0V)
Select U9
MAX6126
J16
J24
J13
User-Supplied Power Supply
AVDD
J16
Select AVDD
The EV kit receives power from a single DC source of
12V, 500mA through a J61 power jack. The MAX13256,
H-bridge driver and transformer create an additional
negative rail for +15V and -15V. The power is then recti-
fied and regulated down to a +12V and -12V supplies for
the MAX9632 op amps, as well as +5V and -5V supplies
for the MAX44205 op amps. Additional supplies are gen-
erated for +1.8V/-1.8V and +2V/+3.3V for the ADCs and
VREFs. See the EV kit schematic pdf for details. Specific
J24
J13
J16
Select User-
Supplied
Reference
User-
Supplied
Open. Connect
user-supplied
reference
J24
to J24-2
Maxim Integrated
│ 16
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 5. Power Supply to the Board
POWER
INPUT CONNECTORS
JUMPERS
J67: 3-4
J66: 3-4
J68: 3-4
J69: 5-6
J65: 1-2
Single +12V input from a wall
adapter (default)
J61
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
J67: 3-4
J66: 3-4
J68: 1-2
J69: 3-4
J65: 1-2
TP91 (+12V)
TP90 (-12V)
An external ±12V
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
J67: 1-2
J66: 1-2
J68: 3-4
J69: 5-6
J65: 1-2
TP86 (+15V)
TP83 (-15V)
An external ±15V
J64: 1-2 (select onboard FTDI)
J63: 1-2 (select FPGA ZedBoard)
Table 6. Analog Input Configurations (CH0–CH5)
CONFIGURATION
ADC INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
NO.
DESCRIPTION
User-supplied signals,
differential
1
Channel 0
Channel 1
AIN0D+, AIN0D-
AIN1D+, AIN1D-
N/A
N/A
User-supplied signals,
differential
2
3
J31: 1-2
J35: 5-6 and 3-4
J33: 1-2
J32: 1-2
J36: 5-6 and 3-4
J34: 1-2
J28: AIN2.1+ (or TP39):
AIN2.1+ and AGND
J30: AIN2.3+ (or TP43):
AIN2.3+ and AGND
Noninverting, differential,
second-order LPF
MAX9632, Channel 2
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
Maxim Integrated
│ 17
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 6. Analog Input Configurations (CH0–CH5) (continued)
CONFIGURATION
ADC INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
NO.
DESCRIPTION
J31: 3-4
J35: 1-2 and 7-8
J33: 3-4
J32: 3-4
J36: 1-2 and 7-8
J34: 3-4
J27: AIN2.1- (or TP38):
AIN2.1- and AGND
J29: AIN2.3- (or TP42):
AIN2.3- and AGND
Inverting, differential,
second-order LPF
4
MAX9632, Channel 2
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
J35: 7-8 and 3-4
J33: 1-2
J34: 1-2
J36: 7-8 and 3-4
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
AIN2.2+ (or TP41):
AIN2.2+ and AGND
AIN2.4+ (or TP45):
AIN2.4+ and AGND
Noninverting, differential,
first-order LPF
5
MAX9632, Channel 2
J35: 7-8 and 3-4
J33: 3-4
J34: 3-4
J36: 7-8 and 3-4
J4: 3-4 and 5-6
J37: 1-2 (for bipolar signal
or open for unipolar signal)
J38: 1-2 (for bipolar signal
or open for unipolar signal)
AIN2.2- (or TP40):
AIN2.2- and AGND
AIN2.4- (or TP44):
AIN2.4- and AGND
Inverting, differential,
first-order LPF
6
MAX9632, Channel 2
J39: 1-2
J43: 5-6 and 3-4
J41: 1-2
J40: 1-2
J44: 5-6 and 3-4
J42: 1-2
AIN3.1+ (or TP57):
AIN3.1+ and AGND
AIN3.3+ (or TP61):
AIN3.3+ and AGND
Noninverting, differential,
second order LPF
7
MAX9632, Channel 3
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
Maxim Integrated
│ 18
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Table 6. Analog Input Configurations (CH0–CH5) (continued)
CONFIGURATION
ADC INPUT
CONFIGURATION
INPUT CONNECTORS
JUMPER POSITIONS
NO.
DESCRIPTION
J39: 3-4
J43: 1-2 and 7-8
J41: 3-4
J40: 3-4
J44: 1-2 and 7-8
J42: 3-4
AIN3.1- (or TP56):
AIN3.1- and AGND
AIN3.3- (or TP60):
AIN3.3- and AGND
Inverting, differential,
second-order LPF
8
MAX9632, Channel 3
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
J43: 7-8 and 3-4
J41: 1-2
J44: 7-8 and 3-4
J42: 1-2
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
AIN3.2+ (or TP59):
AIN3.2+ and AGND
AIN3.4+ (or TP63):
AIN3.4+ and AGND
Noninverting, differential,
first-order LPF
9
MAX9632, Channel 3
J43: 7-8 and 3-4
J41: 3-4
J44: 7-8 and 3-4
J42: 3-4
J5: 3-4 and 5-6
J45: 1-2 (for bipolar signal
or open for unipolar signal)
J46: 1-2 (for bipolar signal
or open for unipolar signal)
AIN3.2- (or TP58):
AIN3.2- and AGND
AIN3.4- (or TP62):
AIN3.4- and AGND
Inverting, differential,
first-order LPF
10
MAX9632, Channel 3
J48: AIN4- (or TP73):
AIN4- and AGND
J47: AIN4+ (or TP72):
AIN4+ and AGND
J6: 3-4 and 5-6
J49: open
11
12
MAX44205, Channel 4 Differential, first-order LPF
MAX44205, Channel 5 Differential, first-order LPF
AIN5+ (or TP74):
AIN5+ and AGND
AIN5- (or TP75): AIN5-
and AGND
J7: 3-4 and 5-6
J50: open
Maxim Integrated
│ 19
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Sync Input and Sync Output
(For Coherent Sampling)
Ordering Information
PART
TYPE
EVKIT
EVKIT
Sync Input and Sync Output is applicable to the FPGA
(ZedBoard) and is not used in Standalone mode. The
SYNC_IN SMA accepts an approximate 100MHz wave-
form signal to generate the system clock of the ZedBoard.
For maximum performance, use a low-jitter clock that
syncs to the user’s analog function generator. The
SYNC_OUT SMA outputs a 10MHz square waveform
that syncs to the user’s analog function generator. Both
options are used for coherent sampling of the IC. Use
only one option at a time. The relationship between f , f ,
MAX11253EVKIT#
MAX11254EVKIT#
#Denotes RoHS compliant.
Contact Avnet to purchase a ZedBoard to communicate with
the MAX11253/MAX11254 EV kit.
This EV kit comes with two assembly options:
The MAX11253EVKIT# comes with a MAX11253ATJ+ in
a 32-pin TQFN package.
IN
S
N
, and M
is given as follows:
CYCLES
SAMPLES
The MAX11254EVKIT# comes with a MAX11254ATJ+ in
a 32-pin TQFN package..
f
N
CYCLES
IN
=
Both EV kit variations use the same PCB and bill of mate-
rials, and the only variation is the IC assembled at U1.
f
M
SAMPLES
S
where:
= Input frequency
f
IN
f = Sampling frequency
S
N
= Prime number of cycles in the sampled set
CYCLES
M
= Total number of samples
SAMPLES
Maxim Integrated
│ 20
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials
Maxim Integrated
│ 21
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)
Maxim Integrated
│ 22
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)
Maxim Integrated
│ 23
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams
MAX1153/MAX11254 Family EV Kit—Bottom Silkscreen
MAX1153/MAX11254 Family EV Kit—Top Silkscreen
MAX1153/MAX11254 Family EV Kit—Bottom Paste
MAX1153/MAX11254 Family EV Kit—Top Paste
Maxim Integrated
│ 24
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)
MAX1153/MAX11254 Family EV Kit —Internal 3
MAX1153/MAX11254 Family EV Kit—Internal 2
MAX1153/MAX11254 Family EV Kit—Internal 5
MAX1153/MAX11254 Family EV Kit—Internal 4
Maxim Integrated
│ 25
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)
MAX1153/MAX11254 Family EV Kit —Bottom
MAX1153/MAX11254 Family EV Kit—Top
MAX1153/MAX11254 Family EV Kit—Bottom Mask
MAX1153/MAX11254 Family EV Kit—Top Mask
Maxim Integrated
│ 26
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic
ꢀ1
1282834-0
ꢂ1ꢁ
49.9
REFP
ꢊꢋ
1
2
3
4
5
ꢁ
ꢃ
ꢄ
ꢅ
1ꢆ
REFP_S
AIN0D+
AIN0D-
AIN1D+
AIN1D-
REFN_S
ꢇꢈꢉ
ꢇꢈꢉ
ꢇꢈꢉ
ꢇꢈꢉ
ꢇꢈꢉ
ꢇꢈꢉ
ALL INPUTS +/- 3V MAX
ꢂ1ꢃ
ꢂ1ꢄ
ꢂ1ꢅ
49.9
1K
AVSS
GPO0
GPO1
ꢇꢈꢉ
ꢇꢈꢉ
ꢇꢈꢉ
1K
ꢀ25
1282834-0
1
2
3
4
5
ꢁ
ꢃ
ꢄ
ꢅ
1ꢆ
ꢇꢈꢉ AIN2D+
ꢇꢈꢉ AIN2.1+
ꢇꢈꢉ AIN2.1-
ꢇꢈꢉ AIN2.2+
ꢇꢈꢉ AIN2.2-
ꢇꢈꢉ AIN2.3+
ꢇꢈꢉ AIN2.3-
ꢇꢈꢉ AIN2.4+
ꢇꢈꢉ AIN2.4-
ꢇꢈꢉ AIN2D-
ꢀ2ꢁ
1282834-0
1
2
3
4
5
ꢁ
ꢃ
ꢄ
ꢅ
1ꢆ
ꢇꢈꢉ AIN3D+
ꢇꢈꢉ AIN3.1+
ꢇꢈꢉ AIN3.1-
ꢇꢈꢉ AIN3.2+
ꢇꢈꢉ AIN3.2-
ꢇꢈꢉ AIN3.3+
ꢇꢈꢉ AIN3.3-
ꢇꢈꢉ AIN3.4+
ꢇꢈꢉ AIN3.4-
ꢇꢈꢉ AIN3D-
ꢀ2
282834-4
1
2
3
4
AIN4D-
ꢇꢈꢉ
AIN4-
ꢇꢈꢉ
AIN4+
ꢇꢈꢉ
AIN4D+
ꢇꢈꢉ
ꢀ3
282834-4
1
2
3
4
AIN5D-
ꢇꢈꢉ
AIN5-
ꢇꢈꢉ
AIN5+
ꢇꢈꢉ
AIN5D+
ꢇꢈꢉ
Maxim Integrated
│ 27
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
1
1
ꢈ
ꢈ
5
5
ꢁ
ꢁ
4
4
1
1
ꢈ
ꢈ
5
5
ꢁ
ꢁ
4
4
2
3
4
5
2
3
4
5
2
3
4
5
2
3
4
5
Maxim Integrated
│ 28
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
1
1
ꢆ
ꢆ
5
5
ꢇ
ꢇ
4
4
1
1
ꢆ
ꢆ
5
5
ꢇ
ꢇ
4
4
Maxim Integrated
│ 29
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
5
5
3
ꢅ
3
ꢅ
2
ꢃ
2
ꢃ
1 1
1 3
1 1
1 3
ꢂ
ꢂ
2
3
4
5
2
3
4
5
Maxim Integrated
│ 30
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
1
3
1
3
1
3
1
3
1
3
2
ꢊ ꢑ ꢕ ꢒ
ꢓ ꢇ ꢔ K
A ꢎ ꢑ ꢑ
A ꢎ ꢓ ꢓ
ꢊ E F ꢁ
ꢊ E F ꢍ
A ꢌ ꢍ ꢉ ꢍ
A ꢌ ꢍ ꢉ ꢁ
ꢐ ꢁ ꢋ ꢉ
2 4
1
2
3
4
5
ꢈ
ꢄ
ꢅ
ꢐ ꢁ ꢌ ꢋ ꢉ ꢖ ꢇ ꢔ K
2 3
ꢐ ꢁ ꢋ 1
2 2
ꢆ
ꢐ ꢁ ꢋ ꢐ ꢍ ꢑ
2 1
ꢇ A ꢁ ꢁ
2 ꢉ
ꢅ
1
ꢈ
2
ꢇ A ꢁ ꢍ
1 ꢆ
A ꢌ ꢍ 5 ꢁ
1 ꢅ
A ꢌ ꢍ 5 ꢍ
1 ꢄ
2
4
ꢌ . ꢇ .
ꢌ . ꢇ .
ꢅ
5
2
ꢐ ꢍ ꢑ ꢓ
ꢐ ꢍ ꢑ 3
4
2
Maxim Integrated
│ 31
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
2
2
ꢊ
1
ꢊ
1
1 ꢅ
ꢂ
1 ꢅ
ꢂ
1
3
1 5
1 5
Maxim Integrated
│ 32
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
ꢄ53
ꢄ53
ASP-134604-01
ASP-134604-01
ꢍ1
ꢍ2
ꢍ3
ꢋ1
ꢋ2
ꢋ3
1
1
2
2
3
3
ꢁ15ꢉ
ꢁ151
ꢁ152
ꢁ153
ꢁ154
28
ꢍ4
ꢍ5
ꢍꢂ
ꢍꢃ
ꢍꢅ
ꢍꢊ
ꢋ4
ꢋ5
ꢋꢂ
ꢋꢃ
ꢋꢅ
ꢋꢊ
4
4
ꢎꢏ
SYNC_CLK_IN
ꢁ142
ꢁ143
ꢁ144
ꢁ145
ꢁ14ꢂ
ꢁ14ꢃ
28
5
5
ꢐꢀꢆ SYNC_CLK_OUT
ꢂ
ꢂ
28
ꢃ
ꢃ
ꢎꢏ
RDYB_FPGA
RSTB_FPGA
28
ꢅ
ꢅ
ꢐꢀꢆ
ꢊ
ꢊ
28
ꢍ1ꢉ
ꢍ11
ꢍ12
ꢍ13
ꢍ14
ꢍ15
ꢍ1ꢂ
ꢍ1ꢃ
ꢍ1ꢅ
ꢍ1ꢊ
ꢍ2ꢉ
ꢍ21
ꢍ22
ꢍ23
ꢍ24
ꢍ25
ꢍ2ꢂ
ꢍ2ꢃ
ꢍ2ꢅ
ꢍ2ꢊ
ꢍ3ꢉ
ꢍ31
ꢍ32
ꢍ33
ꢍ34
ꢍ35
ꢍ3ꢂ
ꢍ3ꢃ
ꢍ3ꢅ
ꢍ3ꢊ
ꢍ4ꢉ
ꢋ1ꢉ
ꢋ11
ꢋ12
ꢋ13
ꢋ14
ꢋ15
ꢋ1ꢂ
ꢋ1ꢃ
ꢋ1ꢅ
ꢋ1ꢊ
ꢋ2ꢉ
ꢋ21
ꢋ22
ꢋ23
ꢋ24
ꢋ25
ꢋ2ꢂ
ꢋ2ꢃ
ꢋ2ꢅ
ꢋ2ꢊ
ꢋ3ꢉ
ꢋ31
ꢋ32
ꢋ33
ꢋ34
ꢋ35
ꢋ3ꢂ
ꢋ3ꢃ
ꢋ3ꢅ
ꢋ3ꢊ
ꢋ4ꢉ
CSB_FPGA
1ꢉ
11
12
13
14
15
1ꢂ
1ꢃ
1ꢅ
1ꢊ
2ꢉ
21
22
23
24
25
2ꢂ
2ꢃ
2ꢅ
2ꢊ
3ꢉ
31
32
33
34
35
3ꢂ
3ꢃ
3ꢅ
3ꢊ
4ꢉ
1ꢉ
11
12
13
14
15
1ꢂ
1ꢃ
1ꢅ
1ꢊ
2ꢉ
21
22
23
24
25
2ꢂ
2ꢃ
2ꢅ
2ꢊ
3ꢉ
31
32
33
34
35
3ꢂ
3ꢃ
3ꢅ
3ꢊ
4ꢉ
ꢐꢀꢆ
28
28
28
28
28
ꢐꢀꢆ
ꢐꢀꢆ
DIN_FPGA
SYNC_FPGA
DOUT_FPGA
EXT_CLK_FPGA
ꢎꢏ
28
ꢐꢀꢆ
ꢁ155
VDDIO
28
ꢁ15ꢂ
28
ꢈ125
0.1UF
ꢈ124
1UF
ꢁ15ꢃ
28
ꢁ15ꢅ
ꢁ15ꢊ
28
28
ꢀ23
GND_FPGA
93LC66BT-I/OT
ꢁ1ꢂꢉ
28
ꢑꢈꢈ
ꢁ14ꢅ
ꢁ14ꢊ
28
5
4
3
ꢈꢒ
1
ꢈꢓK
ꢍꢎ
ꢍꢐ
ꢐꢀꢆ SO_EEPROM_FPGA
ꢁ1ꢂ1
28
3V3_FPGA
28
ꢑꢒꢒ
GND_FPGA
VADJ
ꢄ55
1
2
3
4
5
ꢂ
SO_EEPROM_FPGA
ꢎꢏ
ꢈ123
1UF
PBC06SAAN
GND_FPGA
GND_FPGA
GND_FPGA
GND_FPGA
ꢄ53
ASP-134604-01
ꢄ53
ASP-134604-01
ꢈ1
ꢌ1
ꢌ2
ꢌ3
ꢌ4
ꢌ5
ꢌꢂ
ꢌꢃ
ꢌꢅ
1
1
2
VDDIO
ꢁ13ꢊ
ꢁ14ꢉ
28
28
ꢈ2
ꢈ3
ꢈ4
ꢈ5
ꢈꢂ
ꢈꢃ
ꢈꢅ
ꢈꢊ
2
3
3
4
4
ꢈ12ꢂ
1000PF
ꢈ12ꢅ
5
5
0.1UF
ꢁ141
28
ꢂ
ꢂ
ꢐꢀꢆ SCLK_FPGA
74LVC2G125DP
ꢆꢇꢃꢊ
ꢃ
ꢃ
ꢀ21
SYNC_CLK_IN
ꢅ
ꢅ
ꢑꢈꢈ
ꢌꢊ
GND_FPGA
ꢊ
ꢊ
ꢄ54
1
2
1ꢐE
ꢈ1ꢉ
ꢈ11
ꢈ12
ꢈ13
ꢈ14
ꢈ15
ꢈ1ꢂ
ꢈ1ꢃ
ꢈ1ꢅ
ꢈ1ꢊ
ꢈ2ꢉ
ꢈ21
ꢈ22
ꢈ23
ꢈ24
ꢈ25
ꢈ2ꢂ
ꢈ2ꢃ
ꢈ2ꢅ
ꢈ2ꢊ
ꢈ3ꢉ
ꢈ31
ꢈ32
ꢈ33
ꢈ34
ꢈ35
ꢈ3ꢂ
ꢈ3ꢃ
ꢈ3ꢅ
ꢈ3ꢊ
ꢈ4ꢉ
ꢌ1ꢉ
ꢌ11
ꢌ12
ꢌ13
ꢌ14
ꢌ15
ꢌ1ꢂ
ꢌ1ꢃ
ꢌ1ꢅ
ꢌ1ꢊ
ꢌ2ꢉ
ꢌ21
ꢌ22
ꢌ23
ꢌ24
ꢌ25
ꢌ2ꢂ
ꢌ2ꢃ
ꢌ2ꢅ
ꢌ2ꢊ
ꢌ3ꢉ
ꢌ31
ꢌ32
ꢌ33
ꢌ34
ꢌ35
ꢌ3ꢂ
ꢌ3ꢃ
ꢌ3ꢅ
ꢌ3ꢊ
ꢌ4ꢉ
1ꢉ
11
12
13
14
15
1ꢂ
1ꢃ
1ꢅ
1ꢊ
2ꢉ
21
22
23
24
25
2ꢂ
2ꢃ
2ꢅ
2ꢊ
3ꢉ
31
32
33
34
35
3ꢂ
3ꢃ
3ꢅ
3ꢊ
4ꢉ
1ꢉ
11
12
13
14
15
1ꢂ
1ꢃ
1ꢅ
1ꢊ
2ꢉ
21
22
23
24
25
2ꢂ
2ꢃ
2ꢅ
2ꢊ
3ꢉ
31
32
33
34
35
3ꢂ
3ꢃ
3ꢅ
3ꢊ
4ꢉ
ꢁ1ꢂ5
1
ꢂ
1
1A
1ꢔ
2ꢔ
ꢐꢀꢆ SYNC_CLK_IN
SYNC_CLK_IN
0
5
4 3 2
ꢃ
5
2ꢐE
2A
3
ꢁ1ꢂ2
SYNC_CLK_IN_SPLIT
ꢌꢏꢍ
49.9
ꢄ5ꢂ
ꢁ1ꢂ4
49.9
1
1
5
4
3
2
GND_FPGA
GND_FPGA
GND_FPGA
5V_TTL
ꢈ12ꢃ
1000PF
ꢈ12ꢊ
0.1UF
74LVC2G125DP
ꢆꢇꢃꢅ
GND_FPGA
ꢀ22
SYNC_CLK_OUT
ꢑꢈꢈ
ꢄ5ꢃ
1
2
1ꢐE
ꢁ1ꢂ3
ꢁ1ꢂꢂ
ꢂ
1
1
1A
1ꢔ
2ꢔ
SYNC_CLK_OUT
ꢎꢏ
ꢆꢇꢅꢉ
0
49.9
GND
5
4
3
2
ꢃ
5
2ꢐE
2A
3
+12V_FPGA
SYNC_CLK_OUT
ꢌꢏꢍ
ꢄ5ꢅ
ꢁ1ꢂꢃ
1
1
VADJ
49.9
5
4
3
2
GND_FPGA
3V3_FPGA
ꢎꢏ
SYNC_CLK_OUT
GND_FPGA
GND_FPGA
GND_FPGA
Maxim Integrated
│ 33
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
1 0 K
ꢈ 1 ꢉ ꢅ
1 0 K
ꢈ 1 ꢉ 5
1 0 K
G R E E N
ꢈ 1 ꢉ 4
A
K
1 0 K
1 0 K
1 0 K
1 0 K
ꢈ 1 ꢉ 3
ꢈ 1 ꢉ 1
ꢈ 1 ꢊ ꢉ
ꢈ 1 ꢊ ꢅ
1 0 K
ꢈ 1 ꢉ 2
ꢈ 1 ꢊ ꢁ
ꢈ 1 ꢊ ꢊ
ꢈ 1 ꢊ 5
1 0 K
1 0 K
1 0 K
ꢑ ꢇ ꢇ ꢍ ꢐ
5 ꢅ
4 2
3 1
2 ꢆ
ꢒ ꢎ ꢂ
5 1
4 ꢊ
3 5
2 5
1 5
1 1
ꢑ ꢇ ꢇ ꢍ ꢐ
ꢑ ꢇ ꢇ ꢍ ꢐ
ꢑ ꢇ ꢇ ꢍ ꢐ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢒ ꢎ ꢂ
ꢑ ꢇ ꢐ ꢈ E
ꢑ ꢇ ꢐ ꢈ E
ꢑ ꢇ ꢐ ꢈ E
ꢅ 4
3 ꢊ
1 2
5
1
ꢑ ꢕ ꢌ ꢌ
ꢑ ꢕ ꢗ ꢋ
ꢁ
4
A ꢒ ꢎ ꢂ
1 ꢆ
1
2
ꢅ
2
ꢌ 1
6 0 0
2
1
ꢁ
ꢅ
ꢊ
ꢉ
ꢁ
ꢅ
ꢊ
ꢉ
1 ꢆ
1 1
1 ꢆ
1 1
Maxim Integrated
│ 34
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
MAX1153/MAX11254 Family EV Kit Schematic (continued)
3
ꢅ
3
ꢅ
E ꢁ
ꢄ
ꢅ
3
4
4
4
ꢌ ꢑ ꢂ
ꢑ ꢂ
ꢐ ꢑ ꢌ
E ꢁ
E ꢁ
ꢄ
ꢅ
3
4
ꢄ
ꢅ
3
4
0 . 0 1 U F
ꢂ 1 ꢅ 5
ꢌ ꢑ ꢂ
ꢑ ꢂ
ꢌ ꢑ ꢂ
ꢑ ꢂ
ꢐ ꢑ ꢌ
ꢐ ꢑ ꢌ
7 3 . 2 K
1 2 3 K
7 3 . 2 K
0 . 0 1 U F
3
ꢅ
5
2
4
ꢘ
ꢌ3
ꢌ1
ꢖ
ꢖ
ꢌ 3
ꢌ 1
ꢘ
ꢌ4
ꢌ2
ꢌ 2
ꢌ 4
ꢗ
ꢖ
E ꢁ
ꢄ
ꢅ
3
4
ꢖ
ꢗ
ꢌ ꢑ ꢂ
ꢑ ꢂ
ꢐ ꢑ ꢌ
0 . 0 1 U F
ꢂ 1 5 ꢆ
E ꢁ
1 1
ꢎ ꢌ ꢌ 2
ꢎ ꢌ ꢌ 1
2
1
ꢐ ꢑ ꢌ 2
ꢄ
ꢐ ꢑ ꢌ 1
ꢅ
3
1
ꢉ ꢊ M ꢁ E ꢇ
4 . 7 U F
ꢂ 1 5 ꢈ
2
1
3
ꢅ
4
Maxim Integrated
│ 35
www.maximintegrated.com
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 Family
Evaluation Kit
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
4/15
5/15
4/18
0
1
2
Initial release
—
Added the MAX11253 EV kit to data sheet
Updated PCB layout diagrams, schematic, and bill of materials
1–22
21-35
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2018 Maxim Integrated Products, Inc.
│ 36
相关型号：
MAX11254ATJ/V+T
24-Bit, 6-Channel, 64ksps, 6.2nV/âHz PGA, Delta-Sigma ADC with SPI Interface
MAXIM
MAX11259AWX+T
ADC, Delta-Sigma, 24-Bit, 1 Func, 6 Channel, Serial Access, CMOS, PBGA36, WLP-36
MAXIM
MAX1125AIBH-T
ADC, Flash Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, CMOS, CQCC44, MO-047AC, CERQUAD-44
MAXIM
©2020 ICPDF网 联系我们和版权申明