MAX1126EGK-TD [MAXIM]
ADC, Proprietary Method, 12-Bit, 1 Func, 4 Channel, Parallel, Word Access, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68;
| 型号： | MAX1126EGK-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Proprietary Method, 12-Bit, 1 Func, 4 Channel, Parallel, Word Access, Bipolar, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68 |
| 文件： | 总25页 (文件大小：790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3143; Rev 1; 3/04
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1126 quad, 12-bit analog-to-digital converter
(ADC) fe a ture s fully d iffe re ntia l inp uts , a p ip e line d
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1126 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.9dB signal-to-noise ratio (SNR) at a
5.3MHz input frequency. In addition to low operating
power, the MAX1126 features an 813µA power-down
mode for idle periods.
♦ Four ADC Channels with Serial LVDS/SLVS
Outputs
♦ Excellent Dynamic Performance
69.9dB SNR at f = 5.3MHz
IN
93.7dBc SFDR at f = 5.3MHz
IN
-90dB Channel Isolation
♦ Ultra-Low Power
135mW per Channel (Normal Operation)
1.5mW Total (Shutdown Mode)
♦ Accepts 20% to 80% Clock Duty Cycle
♦ Self-Aligning Data-Clock to Data-Output Interface
♦ Fully Differential Analog Inputs
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt-
age range.
♦ Wide 1.4V
Differential Input Voltage Range
P-P
♦ Internal/External Reference Option
♦ Test Mode for Digital Signal Integrity
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia-
tions in inp ut-c loc k d uty c yc le . An on-c hip p ha s e -
loc ke d loop (PLL) g e ne ra te s the hig h-s p e e d s e ria l
low-voltage differential signaling (LVDS) clock.
♦ LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
♦ Small, 68-Pin QFN with Exposed Paddle
♦ Evaluation Kit Available (MAX1127EVKIT)
The MAX1126 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Ord e rin g In fo rm a t io n
PART
TEMP RANGE
PIN-PACKAGE
68 QFN 10mm x
x 10mm x 0.9mm
Refer to the MAX1127 data sheet for a pin-compatible
65Msps version of the MAX1126.
MAX1126EGK
-40°C to +85°C
The MAX1126 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
P in Co n fig u ra t io n
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND
IN0P
IN0N
GND
IN1P
IN1N
GND
1
2
51 OUT0P
50 OUT0N
Ap p lic a t io n s
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
EP
3
49 OV
DD
4
48 OUT1P
47 OUT1N
5
6
46 OV
DD
7
45 CLKOUTP
AV
DD
8
CLKOUTN
44
MAX1126
AV
DD
9
OV
43
42
DD
AV
DD
10
FRAMEP
GND 11
IN2P 12
IN2N 13
GND 14
IN3P 15
IN3N 16
GND 17
41 FRAMEN
40 OV
DD
39 OUT2P
38 OUT2N
37 OV
DD
36 OUT3P
35 OUT3N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
10mm x 10mm x 0.9mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ABSOLUTE MAXIMUM RATINGS
AV to GND.........................................................-0.3V to +2.0V
CV to GND ........................................................-0.3V to +3.6V
DD
T/B, LVDSTEST to GND ...........................-0.3V to (AV + 0.3V)
DD
DD
REFIO, INTREF to GND............................-0.3V to (AV + 0.3V)
DD
OV to GND ........................................................-0.3V to +2.0V
I.C. to GND...............................................-0.3V to (AV + 0.3V)
DD
DD
IN_P, IN_N to GND...................................-0.3V to (AV + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
CLK to GND.............................................-0.3V to (CV + 0.3V)
68-Pin QFN 10mm x 10mm x 0.9mm
DD
OUT_P, OUT_N, FRAME_,
CLKOUT_ to GND................................-0.3V to (OV + 0.3V)
DT, SLVS/LVDS to GND...........................-0.3V to (AV + 0.3V)
PLL0, PLL1, PLL2, PLL3 to GND .............-0.3V to (AV + 0.3V)
(derated 41.7mW/°C above +70°C)........................3333.3mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature Range (soldering, 10s)......................+300°C
DD
DD
DD
PD0, PD1, PD2, PD3, PDALL to GND......-0.3V to (AV + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , C
to GND = 0.1µF,
REFIO
DD
DD
DD
REFIO
DD
f
= 40MHz (50% duty cycle), DT = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
N
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
(Note 2)
(Note 2)
0.4
0.25
LSB
% FS
% FS
Fixed external reference (Note 2)
Fixed external reference (Note 2)
1
Gain Error
-1.5
+0.9
+2.5
ANALOG INPUTS (IN_P, IN_N)
Input Differential Range
Common-Mode Voltage Range
Differential Input Impedance
Differential Input Capacitance
CONVERSION RATE
Maximum Conversion Rate
Minimum Conversion Rate
Data Latency
V
Differential input
(Note 3)
1.4
0.75
2
V
P-P
ID
V
CMO
V
R
Switched capacitor load
kΩ
pF
IN
C
12.5
IN
f
40
MHz
MHz
SMAX
f
16
SMIN
6.5
Cycles
DYNAMIC CHARACTERISTICS (differential inputs, 4096-point FFT)
f
= 5.3MHz at -0.5dBFS
69.9
69.2
69.8
69.1
11.4
11.3
IN
Signal-to-Noise Ratio (Note 2)
SNR
dB
dB
f
IN
= 19.3MHz at -0.5dBFS, T ≥ +25°C
66.7
66.7
A
f
IN
= 5.3MHz at -0.5dBFS
Signal-to-Noise and Distortion
(First Four Harmonics) (Note 2)
SINAD
ENOB
f
IN
= 19.3MHz at -0.5dBFS, T ≥ +25°C
A
f
IN
= 5.3MHz at -0.5dBFS
= 19.3MHz at -0.5dBFS
Effective Number of Bits (Note 2)
Bits
f
IN
2
_______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , C
to GND = 0.1µF,
REFIO
DD
DD
DD
REFIO
DD
f
= 40MHz (50% duty cycle), DT = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
= 5.3MHz at -0.5dBFS
MIN
TYP
93.7
89
MAX
UNITS
f
IN
Spurious-Free Dynamic Range
(Note 2)
SFDR
dBc
f
IN
= 19.3MHz at -0.5dBFS, T ≥ +25°C
77.3
A
f
= 5.3MHz at -0.5dBFS
-91.5
-88.7
IN
Total Harmonic Distortion (Note 2)
Intermodulation Distortion
THD
IMD
IM3
dBc
dBc
dBc
f
IN
= 19.3MHz at -0.5dBFS, T ≥ +25°C
-76.3
A
f = 12.40125MHz at -6.5dBFS,
1
87.0
89.3
f = 13.60125MHz at -6.5dBFS (Note 2)
2
f = 12.40125MHz at -6.5dBFS,
1
Third-Order Intermodulation
f = 13.60125MHz at -6.5dBFS (Note 2)
2
Aperture Jitter
t
(Note 2)
<0.4
1
ps
RMS
AJ
Aperture Delay
t
(Note 2)
ns
AD
Small-Signal Bandwidth
Full-Power Bandwidth
Output Noise
SSBW
LSBW
Input at -20dBFS (Notes 2 and 4)
Input at -0.5dBFS (Notes 2 and 4)
IN_P = IN_N
100
100
0.35
MHz
MHz
LSB
RMS
Clock
cycles
Overdrive Recovery Time
t
R
S
= 25Ω, C = 50pF
1
OR
S
INTERNAL REFERENCE (INTREF = GND, bypass REFIO to GND with 0.1µF)
INTREF Internal Reference Mode
(Note 5)
0.1
V
Enable Voltage
INTREF Low-Leakage Current
200
µA
V
REFIO Output Voltage
V
REFIO
1.18
1.24
1.30
Reference Temperature
Coefficient
TC
100
ppm/°C
REFIO
EXTERNAL REFERENCE (INTREF = AV
)
DD
INTREF External Reference Mode
Enable Voltage
AV
0.1V
-
DD
(Note 5)
V
INTREF High-Leakage Current
200
1.24
<1
µA
V
REFIO Input Voltage Range
REFIO Input Current
I
µA
REFIO
CLOCK INPUT (CLK)
0.8 x
Input High Voltage
Input Low Voltage
V
V
V
CLKH
CV
DD
0.2 x
V
CLKL
CV
DD
Clock Duty Cycle
50
%
%
Clock Duty-Cycle Tolerance
±30
_______________________________________________________________________________________
3
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , C
to GND = 0.1µF,
REFIO
DD
DD
DD
REFIO
DD
f
= 40MHz (50% duty cycle), DT = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
MIN
MAX
A
PARAMETER
SYMBOL
DI
CONDITIONS
MIN
TYP
MAX
5
UNITS
µA
Input at GND
Input at AV
Input Leakage
IN
80
DD
Input Capacitance
DC
5
pF
IN
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)
0.8 x
Input High Threshold
Input Low Threshold
V
V
V
IH
AV
DD
0.2 x
V
IL
AV
DD
Input at GND, except PLL2 and PLL3
5
Input Leakage
DI
Input at AV , except PLL2 and PLL3
DD
80
µA
pF
IN
PLL2 and PLL3 only
200
Input Capacitance
DC
5
IN
LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
V
R
TERM
R
TERM
R
TERM
R
TERM
= 100Ω
250
1.125
450
mV
V
OHDIFF
V
= 100Ω
1.375
OCM
t
= 100Ω, C
= 100Ω, C
= 5pF
= 5pF
150
150
ps
ps
R
LOAD
LOAD
t
F
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
Differential Output Voltage
Output Common-Mode Voltage
Rise Time (20% to 80%)
Fall Time (80% to 20%)
POWER-DOWN
V
R
TERM
R
TERM
R
TERM
R
TERM
= 100Ω
240
220
120
120
mV
mV
ps
OHDIFF
V
= 100Ω
OCM
t
= 100Ω, C
= 100Ω, C
= 5pF
= 5pF
R
LOAD
LOAD
t
ps
F
PD Fall to Output Enable
PD Rise to Output Disable
POWER REQUIREMENTS
t
132
10
µs
ns
ENABLE
t
DISABLE
AV Supply Voltage
AV
1.7
1.7
1.7
1.8
1.8
1.8
1.9
1.9
3.6
V
V
V
DD
DD
OV Supply Voltage
OV
DD
DD
CV Supply Voltage
CV
DD
DD
4
_______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , C
to GND = 0.1µF,
REFIO
DD
DD
DD
REFIO
DD
f
= 40MHz (50% duty cycle), DT = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PDALL = 0, all channels
active
246
285
PDALL = 0, all channels
active, DT = 1
246
mA
f
IN
=
AV Supply Current
I
19.3MHz at
-0.5dBFS
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
76
20
DD
AVDD
PDALL = 1, global power
down, PD[3:0] =1111, no
clock input
438
µA
mA
µA
PDALL = 0, all channels
active
51
63
57
PDALL = 0, all channels
active, DT = 1
f
IN
=
OV Supply Current
I
19.3MHz at
-0.5dBFS
PDALL = 0, 1 channel active
PDALL = 0, PD[3:0] = 1111
35
30
DD
OVDD
PDALL = 1, global power-
down, PD[3:0] =1111, no
clock input
375
CV is used only to bias ESD-protection
DD
diodes on CLK input, Figure 2
CV Supply Current
DD
I
0
mA
CVDD
Power Dissipation
P
f
IN
= 19.3MHz at -0.5dBFS
535
616
mW
DISS
TIMING CHARACTERISTICS (Note 6)
(t
/
(t
/
SAMPLE
24)
- 0.15
SAMPLE
24)
+ 0.15
t
/
SAMPLE
24
Data Valid to CLKOUT Rise/Fall
t
f
= 40MHz, Figure 5 (Notes 6 and 7)
ns
OD
CLK
t
/
SAMPLE
12
CLKOUT Output Width High
CLKOUT Output Width Low
t
Figure 5
Figure 5
ns
ns
CH
t
/
SAMPLE
12
t
CL
(t
/
(t
/
/
SAMPLE
24)
- 0.15
SAMPLE
24)
+ 0.15
t
/
SAMPLE
24
FRAME Rise to CLKOUT Rise
Sample CLK Rise to Frame Rise
t
Figure 4 (Note 7)
ns
ns
CF
(t
/ (t
/ (t
SAMPLE SAMPLE SAMPLE
2)
2)
2)
t
Figure 4 (Notes 7 and 8)
SF
+0.9
+1.3
+1.7
_______________________________________________________________________________________
5
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , C
to GND = 0.1µF,
REFIO
DD
DD
DD
REFIO
DD
f
= 40MHz (50% duty cycle), DT = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
CLK
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
(Note 2)
f = 19.3MHz (Note 2)
IN
-90
±0.1
±1
dB
dB
Gain Matching
Phase Matching
f
= 19.3.MHz (Note 2)
Degrees
IN
Note 1: Specifications at T ≥ +25°C are guaranteed by production testing. Specifications at T < +25°C are guaranteed by design
A
A
and characterization and not subject to production testing.
Note 2: See definition in the Parameter Definitions section.
Note 3: The MAX1126 internally sets the common-mode voltage to 0.6V (typ) (see Figure 1). The common-mode voltage can be
overdriven to between 0.55V and 0.85V.
Note 4: Limited by MAX1127EVKIT input circuitry.
Note 5: Connect INTREF to GND directly to enable internal reference mode. Connect INTREF to AV directly to disable the internal
DD
bandgap reference and enable external reference mode.
Note 6: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 7: Guaranteed by design and characterization. Not subject to production testing.
Note 8: Sample CLK Rise to FRAME RISE timing is measured from 50% of sample clock input level to 50% of FRAME output level.
6
_______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
REFIO DD
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
FFT PLOT
FFT PLOT
(32,768-POINT DATA RECORD)
(32,768-POINT DATA RECORD)
0
0
f
= 40.96MHz
= 5.30125MHz
= -0.5dBFS
CLK
f
= 40.96MHz
CLK
-10
-20
-10
-20
f
IN
f
IN
= 19.00125MHz
A
IN
A
= -0.5dBFS
IN
SNR = 69.88dB
SINAD = 69.85dB
THD = -91.46dBc
SFDR = 93.65dBc
-30
SNR = 69.20dB
SINAD = 69.16dB
THD = -88.74dBc
SFDR = 89.04dBc
-30
-40
-40
-50
-50
-60
-60
-70
-70
HD3
HD3
-80
-80
HD2
HD2
-90
-90
-100
-110
-120
-100
-110
-120
0
4
8
12
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
CROSSTALK
(4096-POINT DATA RECORD)
CROSSTALK
(4096-POINT DATA RECORD)
CROSSTALK
(4096-POINT DATA RECORD)
0
0
0
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 0
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 1
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 3
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 39.9997651MHz
f
= 39.9997651MHz
f
= 39.9997651MHz
CLK
CLK
CLK
f
= 5.2831721MHz
= 19.3260584MHz
f
= 5.2831721MHz
= 19.3260584MHz
f
= 5.2831721MHz
= 19.3260584MHz
IN(IN2)
IN(IN2)
IN(IN2)
f
f
f
IN(IN3)
IN(IN0)
IN(IN1)
0
4
8
12
16
20
0
4
8
12
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TWO-TONE INTERMODULATION DISTORTION
(32,768-POINT DATA RECORD)
GAIN BANDWIDTH PLOT
0
1
0
f
= 12.40125MHz
= 13.60125MHz
= -6.5dBFS
= -6.5dBFS
FULL-POWER
BANDWIDTH
-0.5dBFS
IN(IN1)
-10
f
IN(IN2)
-20
A
A
IN1
-30
IN2
IMD = 87.0dBc
IM3 = 89.3dBc
-40
-1
-2
-3
-4
-5
SMALL-SIGNAL
BANDWIDTH
-20dBFS
-50
-60
-70
-80
-90
LIMITED BY
MAX1127EVKIT
INPUT CIRCUITRY
-100
-110
-120
1
10
100
1000
0
4
8
12
16
20
ANALOG INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
7
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
72
72
70
68
66
64
62
60
70
68
66
64
62
60
0
20
40
60
80
100
120
0
20
40
60
80
100
120
f (MHz)
IN
f
IN
(MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
100
95
90
85
80
75
70
65
60
55
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
0
20
40
60
80
100
120
0
20
40
60
80
100
120
f
IN
(MHz)
f
IN
(MHz)
8
_______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SIGNAL-TO-NOISE RATIO
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER
vs. ANALOG INPUT POWER
72
72
67
62
57
52
47
42
37
32
f
IN
= 5.301935MHz
f
IN
= 5.301935MHz
67
62
57
52
47
42
37
32
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
100
95
90
85
80
75
70
65
60
55
f
IN
= 5.301935MHz
f = 5.301935MHz
IN
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
_______________________________________________________________________________________
9
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SIGNAL-TO-NOISE PLUS DISTORTION
vs. SAMPLING RATE
SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
72
71
70
69
68
67
66
65
64
63
62
72
f = 5.301935MHz
IN
f
IN
= 5.301935MHz
71
70
69
68
67
66
65
64
63
62
20
25
30
(MHz)
35
40
20
25
30
(MHz)
35
40
f
f
CLK
CLK
TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
-75
-80
105
100
95
f
IN
= 5.301935MHz
f = 5.301935MHz
IN
-85
-90
90
-95
85
-100
-105
80
75
20
25
30
(MHz)
35
40
20
25
30
(MHz)
35
40
f
f
CLK
CLK
10 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
SIGNAL-TO-NOISE PLUS DISTORTION
vs. CLOCK DUTY CYCLE
72
72
71
70
69
68
67
66
65
64
63
62
f
IN
= 5.301935MHz
f = 5.301935MHz
IN
71
70
69
68
67
66
65
64
63
62
30
40
50
60
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
-75
-80
100
95
90
85
80
75
70
f
IN
= 5.301935MHz
f = 5.301935MHz
IN
-85
-90
-95
-100
-105
30
40
50
60
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
______________________________________________________________________________________ 11
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
SIGNAL-TO-NOISE RATIO
vs. TEMPERATURE
SIGNAL-TO-NOISE PLUS DISTORTION
vs. TEMPERATURE
72
72
70
68
66
64
62
f
= 40.404040404MHz
= 19.29204151MHz
f
= 40.404040404MHz
CLK
CLK
f
f = 19.29204151MHz
IN
IN
4096-POINT DATA RECORD
4096-POINT DATA RECORD
70
68
66
64
62
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
-75
-80
100
95
90
85
80
75
70
f
= 40.404040404MHz
= 19.29204151MHz
f
= 40.404040404MHz
f = 19.29204151MHz
IN
CLK
CLK
f
IN
4096-POINT DATA RECORD
4096-POINT DATA RECORD
-85
-90
-95
-100
-105
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
12 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
ANALOG SUPPLY CURRENT
DIGITAL SUPPLY CURRENT
vs. SAMPLING RATE
vs. SAMPLING RATE
270
70
60
50
40
30
20
10
0
260
250
240
230
220
20
25
30
(MHz)
35
40
20
25
30
(MHz)
35
40
f
f
CLK
CLK
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
0.020
0.015
0.010
0.005
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.005
-0.010
-0.015
-0.020
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.6
0.4
0.2
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
______________________________________________________________________________________ 13
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(AV
= 1.8V, OV
= 1.8V, CV
= 1.8V, GND = 0, external V
= 1.24V, INTREF = AV , differential input at -0.5dBFS,
DD
DD
DD
REFIO DD
f
= 40MHz (50% duty cycle), DT = low, C
= 10pF, T = +25°C, unless otherwise noted.)
LOAD A
CLK
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. REFERENCE LOAD CURRENT
1.239
1.26
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
NEGATIVE CURRENT
FLOWS INTO REFIO
1.238
1.237
1.236
1.235
1.25
1.24
1.23
1.22
AV = OV
AV = OV
DD DD
DD
DD
1.7
1.8
1.9
2.0
2.1
-40
-15
10
35
60
85
-400 -300 -200 -100
I
0
100 200 300 400
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
(µA)
REFIO
P in De s c rip t io n
PIN
NAME
FUNCTION
1, 4, 7, 11,
14, 17, 22,
24, 65, 68
GND
Ground. Connect all GND pins to the same potential.
2
3
5
6
IN0P
IN0N
IN1P
IN1N
Channel 0 Positive Analog Input
Channel 0 Negative Analog Input
Channel 1 Positive Analog Input
Channel 1 Negative Analog Input
Analog Power Input. Connect AV to a 1.7V to 1.9V power supply. Bypass each AV to GND with
DD
DD
8, 9, 10, 18,
20, 25, 26,
27, 58–62
a 0.1µF capacitor as close to the device as possible. Bypass the AV power plane to the GND
DD
AV
DD
ground plane with a bulk ≥2.2µF capacitor as close to the device as possible. Connect all AV pins
DD
to the same potential.
12
13
15
16
19
IN2P
IN2N
IN3P
IN3N
I.C.
Channel 2 Positive Analog Input
Channel 2 Negative Analog Input
Channel 3 Positive Analog Input
Channel 3 Negative Analog Input
Internally Connected. Do not connect.
Clock Power Input. Connect CV to a 1.7V to 3.6V supply. Bypass CV to GND with a 0.1µF
DD
DD
capacitor in parallel with a ≥2.2µF capacitor. Install the bypass capacitors as close to the device as
21
CV
DD
possible.
23
28
CLK
DT
Single-Ended CMOS Clock Input
Double Termination Select Input. Drive DT high to select the internal 100Ω termination between the
differential output pairs. Drive DT low to select no internal output termination.
14 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
Differential Output Signal Format Select Input. Drive SLVS/LVDS high to select SLVS outputs. Drive
SLVS/LVDS low to select LVDS outputs.
29
SLVS/LVDS
30
31
32
33
PLL0
PLL1
PLL2
PLL3
PLL Control Input 0. PLL0 is reserved for factory testing only and must always be connected to GND.
PLL Control Input 1. PLL1 is reserved for factory testing only and must always be connected to GND.
PLL Control Input 2. See Table 1 for details.
PLL Control Input 3. See Table 1 for details.
Output-Driver Power Input. Connect OV to a 1.7V to 1.9V power supply. Bypass each OV to
DD
DD
34, 37, 40,
43, 46, 49,
52
GND with a 0.1µF capacitor as close to the device as possible. Bypass the OV power plane to the
DD
OV
DD
GND ground plane with a bulk ≥2.2µF capacitor as close to the device as possible. Connect all OV
pins to the same potential.
DD
35
36
38
39
OUT3N
OUT3P
OUT2N
OUT2P
Channel 3 Negative LVDS/SLVS Output
Channel 3 Positive LVDS/SLVS Output
Channel 2 Negative LVDS/SLVS Output
Channel 2 Positive LVDS/SLVS Output
Negative Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns
to a valid D0 in the output data stream.
41
42
FRAMEN
FRAMEP
Positive Frame Alignment LVDS/SLVS Output. A rising edge on the differential FRAME output aligns to
a valid D0 in the output data stream.
44
45
47
48
50
51
CLKOUTN Negative LVDS/SLVS Serial Clock Output
CLKOUTP
OUT1N
OUT1P
Positive LVDS/SLVS Serial Clock Output
Channel 1 Negative LVDS/SLVS Output
Channel 1 Positive LVDS/SLVS Output
Channel 0 Negative LVDS/SLVS Output
Channel 0 Positive LVDS/SLVS Output
OUT0N
OUT0P
Channel 0 Power-Down Input. Drive PD0 high to power-down channel 0. Drive PD0 low for normal
operation.
53
54
55
56
57
63
PD0
PD1
Channel 1 Power-Down Input. Drive PD1 high to power-down channel 1. Drive PD1 low for normal
operation.
Channel 2 Power-Down Input. Drive PD2 high to power-down channel 2. Drive PD2 low for normal
operation.
PD2
Channel 3 Power-Down Input. Drive PD3 high to power-down channel 3. Drive PD3 low for normal
operation.
PD3
Global Power-Down Input. Drive PDALL high to power-down all channels and reference. Drive PDALL
low for normal operation.
PDALL
T/B
Output Format Select Input. Drive T/B high to select binary output format. Drive T/B low to select two’s
complement output format.
______________________________________________________________________________________ 15
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
LVDS Test Pattern Enable Input. Drive LVDSTEST high to enable the output test pattern
(000010111101 MSB→LSB). As with the analog conversion results, the test pattern data is output LSB
first. Drive LVDSTEST low for normal operation.
64
LVDSTEST
Reference Input/Output. For internal reference operation (INTREF = GND), the reference output
66
REFIO
voltage is 1.24V. For external reference operation (INTREF = AV ), apply a stable reference voltage
DD
at REFIO. Bypass to GND with a 0.1µF capacitor.
Internal/External Reference Mode Select Input. For internal reference mode, connect INTREF directly
67
—
INTREF
to GND. For external reference mode, connect INTREF directly to AV
.
DD
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve
specified performance.
EP
Fu n c t io n a l Dia g ra m
AV
OV
DD
PDALL PD0 PD1 PD2 PD3
POWER CONTROL
DD
DT
SLVS/LVDS
REFIO
LVDSTEST
T/B
REFERENCE
SYSTEM
OUTPUT
INTREF
MAX1126
CONTROL
12-BIT
PIPELINE
ADC
IN0P
IN0N
OUT0P
OUT0N
12:1
SERIALIZER
T/H
T/H
T/H
T/H
OUT1P
OUT1N
12-BIT
PIPELINE
ADC
IN1P
IN1N
12:1
SERIALIZER
OUT2P
OUT2N
LVDS/SLVS
OUTPUT
DRIVERS
12-BIT
PIPELINE
ADC
IN2P
IN2N
12:1
SERIALIZER
OUT3P
OUT3N
FRAMEP
FRAMEN
12-BIT
PIPELINE
ADC
IN3P
IN3N
12:1
SERIALIZER
CLKOUTP
CLKOUTN
CLOCK
CIRCUITRY
PLL
6x
CLK
CV
DD
PLL0 PLL1 PLL2 PLL3
GND
16 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
ductance amplifier (OTA), and open simultaneously with
S1, sampling the input waveform. Switches S4a, S4b,
De t a ile d De s c rip t io n
The MAX1126 ADC features fully differential inputs, a
S5a, and S5b are then opened before switches S3a and
S3b connect capacitors C1a and C1b to the output of
the amplifier and switch S4c is closed. The resulting dif-
ferential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These
values are then presented to the first-stage quantizers
and isolate the pipelines from the fast-changing inputs.
Analog inputs IN_P to IN_N are driven differentially. For
differential inputs, balance the input impedance of IN_P
and IN_N for optimum performance.
pipelined architecture, and digital error correction for
high-speed signal conversion. The ADC pipeline archi-
tecture moves the samples taken at the inputs through
the pipeline stages every half clock cycle. The convert-
ed digital results are serialized and sent through the
LVDS/SLVS output drivers. The total latency from input
to output is 6.5 input clock cycles.
The MAX1126 offe rs four s e p a ra te fully d iffe re ntia l
c ha nne ls with s ync hronize d inp uts a nd outp uts .
Configure the outputs for binary or two’s complement
with the T/B digital input. Power-down each channel
individually or globally to minimize power consumption.
The MAX1126 analog inputs are self-biased at a com-
mon-mode voltage of 0.6V (typ) and allow a differential
input voltage swing of 1.4V . The common-mode volt-
P-P
In p u t Circ u it
Figure 1 displays a simplified functional diagram of the
input T/H circuits. In track mode, switches S1, S2a, S2b,
S4a, S4b, S5a, and S5b are closed. The fully differential
circuits sample the input signals onto the two capacitors
(C2a and C2b) through switches S4a and S4b. S2a and
S2b set the common mode for the operational transcon-
age can be overdriven to between 0.55V and 0.85V.
Drive the analog inputs of the MAX1126 in AC-coupled
configuration to achieve best dynamic performance.
Se e the Us ing Tra ns forme r Coup ling s e c tion for a
detailed discussion of this configuration.
SWITCHES SHOWN IN TRACK MODE
INTERNALLY
GENERATED
COMMON-MODE
INTERNAL
COMMON-MODE
BIAS*
INTERNAL
LEVEL*
BIAS*
S5a
S2a
AV
DD
MAX1126
C1a
S3a
S4a
S4b
C2a
C2b
IN_P
IN_N
GND
OUT
OUT
OTA
C1b
S4c
S1
S3b
S2b
S5b
INTERNAL
COMMON-MODE
BIAS*
INTERNALLY
GENERATED
COMMON-MODE
LEVEL*
INTERNAL
BIAS*
*NOT EXTERNALLY ACCESSIBLE
Figure 1. Internal Input Circuitry
______________________________________________________________________________________ 17
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
source at REFIO. Bypass REFIO to GND with a 0.1µF
capacitor. The REFIO input impedance is >1MΩ.
Re fe re n c e Co n fig u ra t io n s
(REFIO a n d INTREF)
The MAX1126 provides an internal 1.24V bandgap ref-
erence or can be driven with an external reference volt-
age. The MAX1126 full-scale analog differential input
range is ±FSR. Full-scale range (FSR) is given by the
following equation:
Clo c k In p u t (CLK)
The MAX1126 accepts a CMOS-compatible clock sig-
nal with a wide 20% to 80% input-clock duty cycle.
Drive CLK with an external single-ended clock signal.
Figure 2 shows the simplified clock input diagram.
V
Low clock jitter is required for the specified SNR perfor-
mance of the MAX1126. Analog input sampling occurs
on the rising edge of CLK, requiring this edge to pro-
vide the lowest possible jitter. Jitter limits the maximum
SNR performance of any ADC according to the follow-
ing relationship:
REFIO
FSR = 700mVx
1.24V
where V
is the voltage at REFIO, generated inter-
REFIO
nally or externally. For a V
= 1.24V, the full-scale
REFIO
input range is ±700mV (1.4V ).
P-P
⎛
⎞
Internal Reference Mode
Connect INTREF to GND to use the internal bandgap
reference directly. The internal bandgap reference gen-
erates REFIO to be 1.24V with a 100ppm/°C tempera-
ture coefficient in internal reference mode. Connect an
external ≥0.1µF bypass capacitor from REFIO to GND
for stability. REFIO sources up to 200µA and sinks up
to 200µA for external circuits, and REFIO has a load
regulation of 83mV/mA. The global power-down input
(PDALL) enables and disables the reference circuit.
REFIO ha s > 1MΩ re s is ta nc e to GND whe n the
MAX1126 is in power-down mode. The internal refer-
ence circuit requires 132µs to power-up and settle
when power is applied to the MAX1126 or when PDALL
transitions from high to low.
1
SNR = 20 ×log
⎜
⎟
2 × π × f × t
⎝
⎠
IN
J
where f represents the analog input frequency and t
IN
J
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For example,
assuming that clock jitter is the only noise source, to
obtain the specified 69.2dB of SNR with an input fre-
quency of 19.3MHz, the system must have less than
of clock jitter. In actuality, there are other
noise sources, such as thermal noise and quantization
noise, that contribute to the system noise requiring the
2.8ps
RMS
clock jitter to be less than 1.1ps
fied 69.2dB of SNR at 19.3MHz.
to obtain the speci-
RMS
PLL Inputs (PLLO–PLL3)
The MAX1126 features a PLL that generates an output
clock signal with 6 times the frequency of the input
clock. The output clock signal is used to clock data out
of the MAX1126 (see the System Timing Requirements
section). Set the PLL2 and PLL3 bits according to the
input clock range provided in Table 1. PLL0 and PLL1
are reserved for factory testing and must always be
connected to GND.
External Reference Mode
The external reference mode allows for more control
over the MAX1126 reference voltage and allows multi-
ple converters to use a common reference. Connect
INTREF to AV
to disable the internal reference and
DD
enter external reference mode. Apply a stable 1.24V
Table 1. PLL2 and PLL3 Configuration
AV
DD
CLOCK INPUT RANGE
MAX1126
(MHz)
PLL2
PLL3
CV
DD
MIN
MAX
DUTY-CYCLE
EQUALIZER
0
0
1
1
0
1
0
1
NOT USED
CLK
GND
32.500
24.375
16.000
40.000
32.500
24.375
*PLL0 and PLL11 are reserved for factory testing and must
always be connected to GND.
Figure 2. Clock Input Circuitry
18 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
N + 2
N + 6
N + 3
N
N + 9
N + 8
(V
IN_P
-
N + 5
V
)
IN_N
N + 1
N + 7
N + 4
t
SAMPLE
CLK
6.5 CLOCK-CYCLE DATA LATENCY
(V
FRAMEP
-
V
)*
FRAMEN
(V
CLKOUTP
-
V
)
CLKOUTN
(V
OUT_P
-
V
)
OUT_N
OUTPUT
OUTPUT
DATA FOR
SAMPLE
N - 6
DATA FOR
SAMPLE N
*DUTY CYCLE VARIES DEPENDING ON INPUT CLOCK FREQUENCY.
Figure 3. Global Timing Diagram
N + 2
N
(V - V
)
IN_P IN_N
N + 1
t
t
SF
SAMPLE
CLK
(V
FRAMEP
-
V
)
t
CF
FRAMEN
(V
CLKOUTP
-
V
)
CLKOUTN
(V
V
-
OUT_P
D5
N-7
D6
N-7
D7
N-7
D8
N-7
D9 D10 D11 D0
N-7 N-7 N-7 N-6
D1
N-6
D2
N-6
D3
N-6
D4
N-6
D5
N-6
D6
N-6
D7
N-6
D8
N-6
D9 D10 D11 D0
N-6 N-6 N-6 N-5
D1
N-5
D2
N-5
D3
N-5
D4
N-5
D5
N-5
D6
N-5
)
OUT_N
*DUTY CYCLE DEPENDS ON INPUT CLOCK FREQUENCY.
Figure 4. Detailed Two-Conversion Timing Diagram
Clock Output (CLKOUTP, CLKOUTN)
S ys t e m Tim in g Re q u ire m e n t s
Figure 3 shows the relationship between the analog
inputs, input clock, frame alignment output, serial clock
output, and serial data output. The differential analog
input (IN_P and IN_N) is sampled on the rising edge of
the CLK signal and the resulting data appears at the
digital outputs 6.5 clock cycles later. Figure 4 provides
a detailed, two-conversion timing diagram of the rela-
tionship between the inputs and the outputs.
The MAX1126 provides a differential clock output that
consists of CLKOUTP and CLKOUTN. As shown in
Figure 4, the serial output data is clocked out of the
MAX1126 on both edges of the clock output. The fre-
quency of the output clock is 6 times the frequency
of CLK.
______________________________________________________________________________________ 19
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Frame Alignment Output (FRAMEP, FRAMEN)
t
t
CL
CH
The MAX1126 provides a differential frame alignment
s ig na l tha t c ons is ts of FRAMEP a nd FRAMEN. As
shown in Figure 4, the rising edge of the frame align-
ment signal corresponds to the first bit (D0) of the
12-bit serial data stream. The frequency of the frame
alignment signal is identical to the frequency of the
sample clock.
(V
V
-
)
CLKOUTP
CLKOUTN
t
OD
t
OD
(V
-
OUT_P
V
D0
D1
D2
D3
)
OUT_N
Figure 5. Serialized Output Detailed Timing Diagram
Serial Output Data (OUT_P, OUT_N)
The MAX1126 provides its conversion results through
individual differential outputs consisting of OUT_P and
OUT_N. The results are valid 6.5 input clock cycles
after the sample is taken. As shown in Figure 3, the out-
put data is clocked out on both edges of the output
clock, LSB (D0) first. Figure 5 provides the detailed ser-
ial output timing diagram.
CODE −2048
10
V
− V
= FSR×2 ×
IN_P
IN_N
4096
where CODE is the decimal equivalent of the digital
10
output code as shown in Table 2. FSR is the full-scale
range as shown in Figures 6 and 7.
Keep the capacitive load on the MAX1126 digital out-
puts as low as possible.
Output Data Format (T/B), Transfer Functions
The MAX1126 output data format is either offset binary
or two’s complement, depending on the logic input T/B.
With T/B low, the output data format is two’s comple-
ment. With T/B high, the output data format is offset
binary. The following equations, Table 2, Figure 6, and
Figure 7 define the relationship between the digital
output and the analog input. For two’s complement
(T/B = 0):
LVDS a n d S LVS S ig n a ls (S LVS /LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS
high for scalable low-voltage signaling (SLVS) levels at
the MAX1126 outp uts (OUT_P, OUT_N, CLKOUTP,
CLKOUTN, FRAMEP, and FRAMEN). See the Electrical
Characteristics table for LVDS and SLVS output voltage
levels.
CODE
10
4096
LVDS Te s t P a t t e rn (LVDS TES T)
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0000 1011 1101 MSB→LSB. As with the ana-
log conversion results, the test pattern data is output
V
− V
= FSR×2 ×
IN_P
IN_N
and for offset binary (T/B = 1):
Table 2. Output Code Table (V
= 1.24V)
REFIO
TWO’S COMPLEMENT DIGITAL OUTPUT CODE
OFFSET BINARY DIGITAL OUTPUT CODE
(T/B = 0)
(T/B = 1)
V
(V
- V
(mV)
= 1.24V)
IN_P
IN_P
HEXADECIMAL
EQUIVALENT
OF
DECIMAL
EQUIVALENT
OF
HEXADECIMAL
EQUIVALENT
OF
DECIMAL
EQUIVALENT
OF
REFIO
BINARY
D11 ꢀ D0
BINARY
D11 ꢀ D0
D11 ꢀ D0
D11 ꢀ D0
D11 ꢀ D0
D11 ꢀ D0
0111 1111 1111
0111 1111 1110
0x7FF
0x7FE
+2047
+2046
1111 1111 1111
1111 1111 1110
0xFFF
0xFFE
+4095
+4094
+699.66
+699.32
0000 0000 0001
0000 0000 0000
1111 1111 1111
0x001
0x000
0xFFF
+1
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0x801
0x800
0x7FF
+2049
+2048
+2047
+0.34
0
-1
-0.34
1000 0000 0001
1000 0000 0000
0X801
0x800
-2047
-2048
0000 0000 0001
0000 0000 0000
0x001
0x000
+1
0
-699.66
-700.00
20 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
V
1.24V
V
REFIO
1.24V
2 x FSR
4096
2 x FSR
4096
REFIO
1 LSB =
FSR = 700mV x
1 LSB =
FSR = 700mV x
FSR
FSR
FSR
FSR
0x7FF
0x7FE
0x7FD
0xFFF
0xFFE
0xFFD
0x001
0x000
0xFFF
0x801
0x800
0x7FF
0x803
0x802
0x801
0x800
0x003
0x002
0x800
0x000
-2047 -2045
-1 0 +1
+2045 +2047
-2047 -2045
-1 0 +1
+2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Bipolar Transfer Function with Two’s Complement
Output Code (T/B = 0)
Figure 7. Bipolar Transfer Function with Offset Binary Output
Code (T/B = 1)
directly at the outputs helps eliminate unwanted reflec-
tions down the line. This feature is useful in applications
where trace lengths are long (>5in) or with mismatched
impedance. Drive DT high to select double termination,
or drive DT low to disconnect the internal termination
resistor (single termination). Selecting double termina-
DT
OUT_P/
CLKOUTP/
FRAMEP
Z = 50Ω
0
tion inc re a s e s the OV
s up p ly c urre nt (s e e the
DD
Electrical Characteristics table).
P o w e r-Do w n Mo d e s
The MAX1126 offers two types of power-down inputs,
PD0–PD3 and PDALL. The power-down modes allow
the MAX1126 to efficiently use power by transitioning to
a low-power state when conversions are not required.
100Ω
100Ω
Independent Channel Power-Down (PD0–PD3)
PD0–PD3 control the power-down mode of each chan-
nel independently. Drive a power-down input high to
p owe r d own its c orre s p ond ing inp ut c ha nne l. For
example, to power down channel 1, drive PD1 high.
Drive a power-down input low to place the correspond-
ing input channel in normal operation. The differential
output impedance of a powered-down output channel
is approximately 378Ω, when DT is low. The output
impedance of OUT_P, with respect to OUT_N, is 100Ω
when DT is high. See the Electrical Characteristics
table for typical supply currents with powered-down
channels.
Z = 50Ω
0
OUT_N/
CLKOUTN/
FRAMEN
MAX1126
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
Figure 8. Double Termination
LSB first. Drive LVDSTEST low for normal operation
(test pattern disabled).
Do u b le Te rm in a t io n (DT)
As shown in Figure 8, the MAX1126 offers an optional,
inte rna l 100Ω te rmina tion b e twe e n the d iffe re ntia l
outp ut p a irs (OUT_P a nd OUT_N, CLKOUTP a nd
CLKOUTN, FRAMEP and FRAMEN). In addition to the
termination at the end of the line, a second termination
The state of the internal reference is independent of the
PD0–PD3 inputs. To power down the internal reference
circuitry, drive PDALL high (see the Global Power-
Down (PDALL) section).
______________________________________________________________________________________ 21
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Global Power-Down (PDALL)
PDALL controls the power-down mode of all channels
and the internal reference circuitry. Drive PDALL high to
enable global power-down. In global power-down mode,
the output impedance of all the LVDS/SLVS outputs is
approximately 378Ω, if DT is low. The output impedance
of the differential LVDS/SLVS outputs is 100Ω when DT is
high. See the Electrical Characteristics table for typical
supply currents with global power-down. The following
list shows the state of the analog inputs and digital out-
puts in global power-down mode:
Gro u n d in g , Byp a s s in g , a n d Bo a rd La yo u t
The MAX1126 requires high-speed board layout design
techniques. Refer to the MAX1127 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side as the ADC, using surface-mount devices
for minimum inductance. Bypass AV
to GND with a
DD
0.1µF c e ra mic c a p a c itor in p a ra lle l with a ≥2.2µF
ceramic capacitor. Bypass OV to GND with a 0.1µF
DD
ceramic capacitor in parallel with a ≥2.2µF ceramic
capacitor. Bypass CV to GND with a 0.1µF ceramic
DD
capacitor in parallel with a ≥2.2µF ceramic capacitor.
• IN_P, IN_N analog inputs are disconnected from the
internal input amplifier.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. Connect
MAX1126 ground pins and the exposed backside pad-
dle to the same ground plane. The MAX1126 relies on
the exposed backside paddle connection for a low-
ind uc ta nc e g round c onne c tion. Is ola te the g round
plane from any noisy digital system ground planes.
• REFIO has >1MΩ resistance to GND.
• OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 378Ω between the
output pairs when DT is low. When DT is high, the dif-
ferential output pairs have 100Ω between each pair.
When operating from the internal reference, the wake-
up time from global power-down is typically 132µs.
When using an external reference, the wake-up time is
dependent on the external reference drivers.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90° turns.
Ensure that the differential analog input network layout
is symmetric and that all parasitics are balanced equal-
ly. Refer to the MAX1126 EV kit data sheet for an exam-
ple of symmetric input layout.
Ap p lic a t io n s In fo rm a t io n
Us in g Tra n s fo rm e r Co u p lin g
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX1126
for optimum performance. The MAX1126 input com-
mon-mode voltage is internally biased to 0.6V (typ) with
P a ra m e t e r De fin it io n s
In t e g ra l No n lin e a rit y (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. For the
MAX1126, this straight line is between the end points of
the transfer function, once offset and gain errors have
been nullified. INL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics table.
f
= 40MHz. Although a 1:1 transformer is shown, a
CLK
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion.
Diffe re n t ia l No n lin e a rit y (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function. For
the MAX1126, DNL deviations are measured at every
step and the worst-case deviation is reported in the
Electrical Characteristics table.
10Ω
0.1µF
IN_P
1
2
3
6
5
4
39pF
V
IN
T1
N.C.
MAX1126
0.1µF
MINICIRCUITS
ADT1-1WT
Offs e t Erro r
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. For the MAX1126, the ideal
midscale digital output transition occurs when there is
-1/2 LSB across the analog inputs (Figures 6 and 7).
10Ω
IN_N
39pF
Figure 9. Transformer-Coupled Input Drive
22 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
Bipolar offset error is the amount of deviation between
the measured midscale transition point and the ideal
midscale transition point.
CLK
t
AD
Ga in Erro r
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope
of the ideal transfer function. For the MAX1126, the gain
error is the difference of the measured full-scale and
zero-scale transition points minus the difference of the
ideal full-scale and zero-scale transition points.
ANALOG
INPUT
t
AJ
SAMPLED
DATA
For the bipolar devices (MAX1126), the full-scale transi-
tion point is from 0x7FE to 0x7FF for two’s complement
output format (0xFFE to 0xFFF for offset binary) and the
zero-scale transition point is from 0x800 to 0x801 for
two’s complement (0x000 to 0x001 for offset binary).
T/H
HOLD
TRACK
HOLD
Figure 10. Aperture Jitter/Delay Specifications
Cro s s t a lk
Crosstalk indicates how well each analog input is isolat-
e d from the othe rs . For the MAX1126, a 5.3MHz,
-0.5dBFS analog signal is applied to one channel while
a 19.3MHz, -0.5dBFS analog signal is applied to all
other channels. An FFT is taken on the channel with the
5.3MHz analog signal. From this FFT, the crosstalk is
me a s ure d a s the d iffe re nc e in the 5.3MHz a nd
19.3MHz amplitudes.
For the MAX1126, SNR is computed by taking the ratio
of the RMS s ig na l to the RMS nois e . RMS nois e
includes all spectral components to the Nyquist fre-
quency excluding the fundamental, the first six harmon-
ics (HD2–HD7), and the DC offset.
S ig n a l-t o -No is e P lu s Dis t o rt io n (S INAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
d is tortion inc lud e s a ll s p e c tra l c omp one nts to the
Nyquist frequency, excluding the fundamental and the
DC offset.
Ap e rt u re De la y
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken. See Figure 10.
Effe c t ive Nu m b e r o f Bit s (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Ap e rt u re J it t e r
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the aperture delay. See Figure 10.
S ig n a l-t o -No is e Ra t io (S NR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SINAD−1.76
⎛
⎞
ENOB =
⎜
⎝
⎟
⎠
6.02
To t a l Ha rm o n ic Dis t o rt io n (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
2
2
2
2
2
2
SNR
= 6.02 x N + 1.76
dB
V
+ V + V + V + V + V
3 4 5 6 7
dB[max]
dB
2
THD = 20 × log
V
1
In reality, there are other noise sources besides quantiza-
tion noise: thermal noise, reference noise, clock jitter, etc.
______________________________________________________________________________________ 23
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conver-
sion result has decreased by -3dB.
S p u rio u s -Fre e Dyn a m ic Ra n g e (S FDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset. SFDR is specified in
decibels relative to the carrier (dBc).
Fu ll-P o w e r Ba n d w id t h
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
In t e rm o d u la t io n Dis t o rt io n (IMD)
IMD is the total power of the IM2 to IM5 intermodulation
products to the Nyquist frequency relative to the total
input power of the two input tones, f1 and f2. The indi-
vidual input tone levels are at -6.5dBFS. The intermodu-
lation products are as follows:
Ga in Ma t c h in g
Gain matching is a figure of merit that indicates how
well the gain of all four ADC channels is matched to
each other. For the MAX1126, gain matching is mea-
sured by applying the same 19.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 40MHz and the maximum deviation in
amplitude is reported in dB as gain matching in the
Electrical Characteristics table.
• 2nd-order intermodulation products (IM2): f1 + f2,
f2 - f1
• 3rd-order intermodulation products (IM3): 2 x f1 - f2,
2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1
• 4th-order intermodulation products (IM4): 3 x f1 - f2,
3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1
• 5th-order intermodulation products (IM5): 3 x f1 - 2 x
f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
P h a s e Ma t c h in g
Phase matching is a figure of merit that indicates how
well the phase of all four ADC channels is matched to
each other. For the MAX1126, phase matching is mea-
sured by applying the same 19.3MHz, -0.5dBFS analog
signal to all analog input channels. These analog inputs
are sampled at 40MHz and the maximum deviation in
phase is reported in degrees as phase matching in the
Electrical Characteristics table.
Th ird -Ord e r In t e rm o d u la t io n (IM3 )
IM3 is the total power of the 3rd-order intermodulation
product to the Nyquist frequency relative to the total
input power of the two input tones f1 and f2. The indi-
vidual input tone levels are at -6.5dBFS. The 3rd-order
intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x
f1 + f2, 2 x f2 + f1.
S m a ll-S ig n a l Ba n d w id t h
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
24 ______________________________________________________________________________________
Qu a d , 1 2 -Bit , 4 0 Ms p s , 1 .8 V ADC w it h
S e ria l LVDS Ou t p u t s
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
Note: For the MAX1126 Exposed Pad Variation,
the package code is G6800-4.
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 25
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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