MAX1133BEAP+T [MAXIM]
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20;型号: | MAX1133BEAP+T |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20 |
文件: | 总19页 (文件大小:388K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-2083; Rev 0; 8/01
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
General Description
Features
The MAX1132/MAX1133 are 200ksps, 16-bit ADCs.
These serially interfaced ADCs connect directly to
SPI™, QSPI™, and MICROWIRE™ devices without
external logic. They combine an input scaling network,
internal track/hold, clock, a +4.096V reference, and
three general-purpose digital output pins (for external
multiplexer or PGA control) in a 20-pin SSOP package.
The excellent dynamic performance (SINAD ≥ 85dB),
high-speed (200ksps), and low power (7.5mA) of these
ADCs, make them ideal for applications such as indus-
trial process control, instrumentation, and medical
applications. The MAX1132 accepts input signals of 0
to +12V (unipolar) or 12V (bipolar), while the
MAX1133 accepts input signals of 0 to +4.096V (unipo-
lar) or 4.096V (bipolar). Operating from a single
+4.75V to +5.25V analog supply and a +4.75V to
+5.25V digital supply, power-down modes reduce
current consumption to 1mA at 10ksps and further
reduce supply current to less than 20µA at slower data
rates. A serial strobe output (SSTRB) allows direct con-
nection to the TMS320 family of digital signal proces-
sors. The MAX1132/MAX1133 user can select either the
internal clock, or an external serial-interface clock for
the ADC to perform analog-to-digital conversions.
o 200ksps (Bipolar) and 150ksps (Unipolar)
Sampling ADC
o 16-Bits, No Missing Codes
o 1.5LSB INL Guaranteed
o 85dB (min) SINAD
o +5V Single-Supply Operation
o Low-Power Operation, 7.5mA (Unipolar Mode)
o 2.5µA Shutdown Mode
o Software-Configurable Unipolar and Bipolar Input
Ranges
0 to +12V and 12V (MAꢀ11ꢁ2)
0 to +4.096V and 4.096V (MAꢀ11ꢁꢁ)
Internal or External Reference
o Internal or External Clock
o SPI/QSPI/MICROWIRE-Compatible Serial Interface
o Three User-Programmable Logic Outputs
o Small 20-Pin SSOP Package
The MAX1132/MAX1133 feature internal calibration cir-
cuitry to correct linearity and offset errors. On-demand
calibration allows the user to optimize performance.
Three user-programmable logic outputs are provided
for the control of an 8-channel mux or a PGA.
Ordering Information
INL
PART
TEMP. RANGE PIN-PACKAGE
(LSB)
MAꢀ11ꢁ2ACAP*
0°C to +70°C 20 SSOP
0°C to +70°C 20 SSOP
1.5
2.5
MAX1132BCAP
Applications
Ordering Information continued at end of data sheet.
Industrial Process Control
Industrial I/O Modules
Pin Configuration
Data-Acquisition Systems
Medical Instruments
TOP VIEW
REF
REFADJ
AGND
1
2
20
AIN
Portable and Battery-Powered Equipment
19 AGND
CREF
CS
3
18
17
AV
DD
4
MAX1132
MAX1133
DGND
SHDN
P2
5
16 DIN
15 DV
6
DD
DGND
7
14
13 SCLK
12
Functional Diagram appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.
P1
8
P0
9
RST
11 DOUT
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
SSTRB
10
SSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ABSOLUTE MAꢀIMUM RATINGS
AV
to AGND, DV
to DGND .............................-0.3V to +6V
Operating Temperature Ranges
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND..................................................................... 16.5V
MAX113_CAP ......................................................0°C to +70°C
MAX113_EAP....................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
REFADJ, CREF, REF to AGND.................-0.3V to (AV
+ 0.3V)
DD
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +4.096V, V
= +5V 5ꢀ, ꢁ
= 4.8MHz, external clock (50ꢀ duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
SCLK
DD
DD
V
REF
= AV , C
= 2.2µF, C
= 1µF, T = T
to T
, unless otherwise noted. Typical values are at
REFADJ
DD
REF
CREF
A
MIN
MAX
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
DC ACCURACY (Note 1)
Resolution
16
Bits
LSB
Bits
LSB
MAX113_A
1.5
2.5
Relative Accuracy (Note 2)
No Missing Codes
INL
Bipolar mode
Bipolar mode
MAX113_B
16
-1
-1
MAX113_A
MAX113_B
+1
Diꢁꢁerential Nonlinearity
Transition Noise
DNL
+1.75
0.77
LSB
RMS
MAX1132
MAX1133
MAX1132
MAX1133
4
2
Unipolar
Bipolar
Oꢁꢁset Error
mV
6
5
Unipolar
Bipolar
0.2
0.3
Gain Error (Note 3)
ꢀFSR
Oꢁꢁset Driꢁt (Bipolar and Unipolar)
Gain Driꢁt (Bipolar and Unipolar)
Excluding reꢁerence driꢁt
Excluding reꢁerence driꢁt
1
1
ppm/oC
ppm/oC
DYNAMIC SPECIFICATIONS (5kHz sine-wave input, 200ksps, 4.8MHz clock, bipolar input mode. MAX1132: 24Vp-p.
MAX1133: 8.192Vp-p)
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
= 5kHz
85
87
SINAD
SNR
dB
dB
dB
dB
= 100kHz
= 5kHz
85
92
= 100kHz
= 5kHz
-90
THD
= 100kHz
= 5kHz
-92
96
92
SFDR
= 100kHz
2
_______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +4.096V, V
= +5V 5ꢀ, ꢁ
= 4.8MHz, external clock (50ꢀ duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
SCLK
DD
DD
V
REF
= AV , C
= 2.2µF, C
= 1µF, T = T
to T
, unless otherwise noted. Typical values are at
REFADJ
DD
REF
CREF
A
MIN
MAX
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
ANALOG INPUT
Unipolar
0
-12
0
12
12
MAX1132
MAX1133
MAX1132
MAX1133
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
Input Range
V
4.096
4.096
-4.096
7.5
5.9
100
3.4
10.0
7.9
Input Impedance
kΩ
1000
4.5
Input Capacitance
CONVERSION RATE
Internal Clock Frequency
Aperture Delay
32
pF
4
MHz
ns
t
10
50
AD
Aperture Jitter
t
ps
AS
MODE 1 (24 External Clock Cycles per Conversion)
Unipolar
Bipolar
Unipolar
Bipolar
Unipolar
Bipolar
0.1
0.1
4.17
4.17
8
3
External Clock Frequency
Sample Rate
ꢁ
MHz
ksps
µs
SCLK
4.8
125
200
240
240
ꢁ
= ꢁ
/24
S
SCLK
t
=
CONV+ACQ
24 / ꢁ
Conversion Time (Note 4)
SCLK
5
MODE 2 (Internal Clock Mode)
External Clock Frequency
(Data Transꢁer Only)
8
6
MHz
µs
Conversion Time
SSTRB low pulse width
Unipolar
4
1.82
1.14
Acquisition Time
µs
Bipolar
MODE ꢁ (32 External Clock Cycles per Conversion)
External Clock Frequency
Sample Rate
ꢁ
Unipolar or bipolar
0.1
4.8
MHz
ksps
SCLK
ꢁ
= ꢁ
/32 Unipolar or bipolar
3.125
150
S
SCLK
t
=
CONV+ACQ
Conversion Time (Note 4)
Unipolar or bipolar
6.67
320
µs
32 / ꢁ
SCLK
INTERNAL REFERENCE
Output Voltage
V
4.056
4.096
24
4.136
V
REF
REF Short-Circuit Current
Output Tempco
mA
ppm/oC
20
_______________________________________________________________________________________
ꢁ
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +4.096V, V
= +5V 5ꢀ, ꢁ
= 4.8MHz, external clock (50ꢀ duty cycle), 24 clocks/conversion (200ksps), bipolar input, external
SCLK
DD
DD
V
REF
= AV , C
= 2.2µF, C
= 1µF, T = T
to T
, unless otherwise noted. Typical values are at
REFADJ
DD
REF
CREF
A
MIN
MAX
T
A
= +25°C.)
PARAMETER
Capacitive Bypass at REF
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
0.47
10
µF
Maximum Capacitive Bypass at
REFADJ
10
µF
REFADJ Output Voltage
REFADJ Input Range
4.096
100
V
For small adjustments ꢁrom 4.096V
To power-down the internal reꢁerence
mV
REFADJ Buꢁꢁer Disable
Threshold
AV
0.5V
-
AV
0.1V
-
DD
DD
V
Buꢁꢁer Voltage Gain
1
V/V
EꢀTERNAL REFERENCE (Reꢁerence buꢁꢁer disabled. Reꢁerence applied to REF)
Input Range (Notes 5 and 6)
3.0
2.4
4.096
250
230
0.1
4.2
V
V
V
= 4.096V, ꢁ
= 4.096V, ꢁ
= 4.8MHz
= 0
REF
REF
SCLK
SCLK
Input Current
µA
In power-down, ꢁ
= 0
SCLK
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Leakage
V
V
V
IH
V
0.8
1
IL
I
IN
V
= 0 or DV
DD
µA
V
IN
Input Hysteresis
Input Capacitance
DIGITAL OUTPUTS
V
0.2
10
HYST
C
pF
IN
DV
0.5
-
DD
Output High Voltage
V
I
= 0.5mA
V
OH
SOURCE
I
I
= 5mA
0.4
0.8
10
SINK
Output Low Voltage
V
V
OL
= 16mA
SINK
Three-State Leakage Current
I
CS = DV
µA
pF
L
DD
Three-State Output
Capacitance
CS = DV
10
DD
POWER SUPPLIES
Analog Supply (Note 7)
Digital Supply (Note 7)
AV
DV
4.75
4.75
5
5.25
5.25
8
V
V
DD
5
DD
Unipolar mode
Bipolar mode
5
mA
Analog Supply Current
I
8.5
0.3
2.5
2.2
11
ANALOG
SHDN = 0, or soꢁtware power-down mode
10
µA
mA
µA
Unipolar or bipolar mode
3.5
10
Digital Supply Current
I
DIGITAL
PSRR
SHDN = 0, or soꢁtware power-down mode
Power-Supply Rejection Ratio
(Note 8)
AV
= DV
= 4.75V to 5.25V
DD
72
dB
DD
4
_______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
TIMING CHARACTERISTICS (Figures 5 and 6)
(AV
= DV
= +5V 5ꢀ, T = T
to T
, unless otherwise noted.)
MAX
DD
DD
A
MIN
PARAMETER
SYMBOL
t
CONDITIONS
MIN
1.14
50
TYP
MAꢀ
UNITS
µs
Acquisition Time
ACQ
DIN to SCLK Setup
t
ns
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Fall to SSTRB
t
70
80
80
ns
t
C
C
= 50pF
= 50pF
ns
DV
LOAD
LOAD
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
t
80
80
ns
CH
t
CL
ns
t
C
C
C
= 50pF
80
80
80
ns
SSTRB
LOAD
LOAD
LOAD
CS Fall to SSTRB Enable
CS Rise to SSTRB Disable
SSTRB Rise to SCLK Rise
RST Pulse Width
t
= 50pF, external clock mode
= 50pF, external clock mode
ns
SDV
t
ns
STR
SCK
t
Internal clock mode
0
ns
t
208
ns
RS
Note 1: Tested at AV = DV = +5V, bipolar input mode.
DD
DD
Note 2: Relative accuracy is the deviation oꢁ the analog value at any code ꢁrom its theoretical value aꢁter the gain error and oꢁꢁset
error have been nulled.
Note ꢁ: Oꢁꢁset nulled.
Note 4: Conversion time is deꢁined as the number oꢁ clock cycles multiplied by the clock period, clock has 50ꢀ duty cycle.
Includes the acquisition time.
Note 5: ADC perꢁormance is limited by the converter’s noise ꢁloor, typically 300µVp-p.
Note 6: When an external reꢁerence has a diꢁꢁerent voltage than the speciꢁied typical value, the ꢁull scale oꢁ the ADC will scale
proportionally.
Note 7: Electrical characteristics are guaranteed ꢁrom AV
= DV
to AV
= DV
. For operations beyond
DD(MIN)
DD(MIN)
DD(MAX)
DD(MAX)
this range, see the Typical Operating Characteristics. For guaranteed speciꢁications beyond the limits, contact the ꢁactory.
Note 8: Deꢁined as the change in positive ꢁull scale caused by a 5ꢀ variation in the nominal supply voltage.
_______________________________________________________________________________________
5
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Typical Operating Characteristics
(MAX1132/MAX1133: AV
= DV
= +5V , ꢁ
= 4.8MHz, external clock (50ꢀ duty cycle), 24 clocks/conversion (200ksps),
DD
DD
SCLK
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T = 25°C, unless otherwise noted.)
A
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
11.5
11.3
11.1
10.9
10.7
10.5
10.3
10.1
9.9
1.5
1.0
0.5
0
A: AV , DV = +4.75V
DD
DD
B: AV , DV = +5.00V
DD
DD
0.6
C: AV , DV = +5.25V
DD
DD
0.4
0.2
C
0
B
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
-1.0
-1.5
A
9.7
9.5
1
13729
27457
41185
54913
61777
1
13729
20593
DIGITAL OUTPUT CODE
27457
41185
54913
61777
0
TEMPERATURE (°C)
-40
20
40
60
80
-20
6865
20593
34321
48049
6865
34321
48049
DIGITAL OUTPUT CODE
TOTAL SUPPLY CURRENT vs.
CONVERSION RATE (USING SHUTDOWN)
GAIN ERROR vs. TEMPERATURE
OFFSET VOLTAGE vs. TEMPERATURE
0.04
0.03
0.02
0.01
0
100
10
0
-1
-2
-3
-4
A: AV , DV = +4.75V
A: AV , DV = +4.75V
DD
DD
DD
DD
B: AV , DV = +5.00V
B: AV , DV = +5.00V
DD
DD
DD
DD
C: AV , DV = +5.25V
C: AV , DV = +5.25V
DD
DD
DD
DD
C
B
1.00
0.10
0.01
B
A
C
A
-40
-20
0
20
40
60
80
0
1
10
100
1000
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
CONVERSION RATE (ksps)
TEMPERATURE (°C)
NORMALIZED REF VOLTAGE
vs. TEMPERATURE
SINAD PLOT
FFT PLOT
100
1.010
1.005
1.000
0.995
0.990
0
f
f
= 200kHz
SAMPLE
f
= 200kHz
SAMPLE
90
80
= 5kHz
IN
-20
70
60
-40
-60
50
40
-80
30
20
-100
-120
10
0
0
9
18 27 36 45 54 63 72 81 90 99
FREQUENCY (kHz)
0.1
1
10
100
-40
-20
0
20
40
60
80
FREQUENCY (kHz)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Typical Operating Characteristics (continued)
(MAX1132/MAX1133: AV
= DV
= +5V , ꢁ
= 4.8MHz, external clock (50ꢀ duty cycle), 24 clocks/conversion (200ksps),
DD
DD
SCLK
bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, T = 25°C, unless otherwise noted.)
A
SFDR PLOT
THD PLOT
120
110
100
90
80
70
60
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 200kHz
SAMPLE
f
= 200kHz
SAMPLE
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Pin Description
PIN
NAME
FUNCTION
Reꢁerence Buꢁꢁer Output/ADC Reꢁerence Input. Reꢁerence voltage ꢁor analog-to-digital conversion. In
internal reꢁerence mode, the reꢁerence buꢁꢁer provides a +4.096V nominal output, externally adjustable at
REFADJ. In external reꢁerence mode, disable the internal buꢁꢁer by pulling REFADJ to AV . Bypass to
DD
1
REF
AGND with a 2.2µF capacitor when using the internal reꢁerence.
Bandgap Reꢁerence Output/Bandgap Reꢁerence Buꢁꢁer Input. Bypass to AGND with 0.22µF. When using an
2
REFADJ
AGND
external reꢁerence, connect REFADJ to AV
to disable the internal bandgap reꢁerence.
DD
3
4
5
6
7
8
9
Analog Ground. This is the primary analog ground (Star Ground).
AV
Analog Supply. 5V 5ꢀ. Bypass AV
Digital Ground
to AGND (pin 3) with a 0.1µF capacitor.
DD
DD
DGND
SHDN
P2
Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
User-Programmable Output 2
P1
User-Programmable Output 1
P0
User-Programmable Output 0
Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes
high when the conversion is ꢁinished. In external clock mode, SSTRB pulses high ꢁor one clock period
beꢁore the MSB decision. It is high impedance when CS is high in external clock mode.
10
SSTRB
Serial Data Output. MSB ꢁirst, straight binary ꢁormat ꢁor unipolar input, two’s complement ꢁor bipolar input.
Each bit is clocked out oꢁ DOUT at the ꢁalling edge oꢁ SCLK.
11
12
DOUT
RST
Reset Input. Drive RST low to put the device in the power-on deꢁault mode. See the Power-On Reset section.
_______________________________________________________________________________________
7
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Pin Description (continued)
PIN
NAME
FUNCTION
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge oꢁ SCLK, and serial data is updated
on DOUT on the ꢁalling edge oꢁ SCLK. In external clock mode, SCLK sets the conversion speed.
13
SCLK
14
15
16
DGND
Digital Ground. Connect to pin 5.
DV
Digital Supply. 5V 5ꢀ. Bypass DV
to DGND (pin 14) with a 0.1µF capacitor.
DD
DD
DIN
Serial Data Input. Serial data on DIN is latched on the rising edge oꢁ SCLK.
Chip-Select Input. Drive CS low to enable the serial interꢁace. When CS is high, DOUT is high impedance.
In external clock mode, SSTRB is high impedance when CS is high.
17
CS
18
19
20
CREF
AGND
AIN
Reꢁerence Buꢁꢁer Bypass. Bypass CREF to AGND (pin 3) with 1µF.
Analog Ground. Connect pin 19 to pin 3.
Analog Input
clock or other digital signals change, as might occur iꢁ
more than one clock signal or ꢁrequency is used.
Detailed Description
The MAX1132/MAX1133 analog-to-digital converters
(ADCs) use a successive-approximation technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 16-bit digital output. The MAX1132/MAX1133
easily interꢁaces to microprocessors (µPs). The data
bits can be read either during the conversion in exter-
nal clock mode or aꢁter the conversion in internal clock
mode.
Input Scaler
The MAX1132/MAX1133 have an input scaler which
allows conversion oꢁ true bipolar input voltages while
operating ꢁrom a single +5V supply. The input scaler
attenuates and shiꢁts the input as necessary to map the
external input range to the input range oꢁ the internal
DAC. The MAX1132 analog input range is 0 to +12V
(unipolar) or 12V (bipolar). The MAX1133 analog input
range is 0 to +4.096V (unipolar) or 4.096V (bipolar).
Unipolar and bipolar mode selection is conꢁigured with
bit 6 oꢁ the serial Control Byte.
In addition to a 16-bit ADC, the MAX1132/MAX1133
include an input scaler, an internal digital microcon-
troller, calibration circuitry, an internal clock generator,
and an internal bandgap reꢁerence. The input scaler ꢁor
the MAX1132 enables conversion oꢁ input signals rang-
ing ꢁrom 0 to +12V (unipolar input) or 12V (bipolar
input). The MAX1133 accepts 0 to +4.096V (unipolar
input) or 4.096V (bipolar input). Input range selection
is soꢁtware controlled.
Figure 1 shows the equivalent input circuit oꢁ the
MAX1132/MAX1133. The resistor network on the analog
input provides 16.5V ꢁault protection. This circuit limits
the current going into or out oꢁ the pin to less than 2mA.
The overvoltage protection is active, even iꢁ the device
is in a power-down mode, or iꢁ AV
= 0.
DD
Calibration
To minimize linearity, oꢁꢁset, and gain errors, the
MAX1132/MAX1133 have on-demand soꢁtware calibra-
tion. Initiate calibration by writing a Control-Byte with bit
M1 = 0, and bit M0 = 1 (see Table 1). Select internal or
external clock ꢁor calibration by setting the INT/EXT bit
in the Control Byte. Calibrate the MAX1132/MAX1133
with the clock used ꢁor perꢁorming conversions.
Digital Interface
The digital interꢁace pins consist oꢁ SHDN, RST, SSTRB,
DOUT, SCLK, DIN and CS. Bringing SHDN low, places
the MAX1132/MAX1133 in its 2.5µA shutdown mode. A
logic low on RST halts the MAX1132/MAX1133 opera-
tion and returns the part to its power-on reset state.
In external clock mode, SSTRB is is low and pulses
high ꢁor one clock cycle at the start oꢁ conversion. In
internal clock mode, SSTRB goes low at the start oꢁ the
conversion and goes high to indicate the conversion is
ꢁinished.
Oꢁꢁsets resulting ꢁrom synchronous noise (such as the
conversion clock) are canceled by the MAX1132/
MAX1133’s calibration circuitry. However, because the
magnitude oꢁ the oꢁꢁset produced by a synchronous
signal depends on the signal’s shape, recalibration
may be appropriate iꢁ the shape or relative timing oꢁ the
8
_______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Starting a Conversion
Start a conversion by clocking a Control Byte into the
BIPOLAR
VOLTAGE
S1
device’s internal shiꢁt register. With CS low, each rising
REFERENCE
edge on SCLK clocks a bit ꢁrom DIN into the
UNIPOLAR
MAX1132/MAX1133’s internal shiꢁt register. Aꢁter CS
R1
2.5kΩ
goes low or aꢁter a conversion or calibration completes,
the ꢁirst arriving logic “1” is deꢁined as the start bit oꢁ
C
HOLD
30pF
R2
the Control Byte. Until this ꢁirst start bit arrives, any
number oꢁ logic “0” bits can be clocked into DIN with
no eꢁꢁect. Iꢁ at any time during acquisition or conversion,
CS is brought high and then low again, the part is
placed into a state where it can recognize a new start
bit. Iꢁ a new start bit occurs beꢁore the current conver-
sion is complete, the conversion is aborted and a new
acquisition is initiated.
TRACK
S2
AIN
T/H OUT
HOLD
R3
HOLD
TRACK
S3
S1 = BIPOLAR/UNIPOLAR
S2, S3 = T/H SWITCH
R2 = 7.6kΩ (MAX1132)
Internal and External Clock Modes
The MAX1132/MAX1133 may use either the external
serial clock or the internal clock to perꢁorm the succes-
sive-approximation conversion. In both clock modes,
the external clock shiꢁts data in and out oꢁ the
MAX1132/MAX1133. Bit 5 (INT/EXT) oꢁ the Control Byte
programs the clock mode.
OR 2.5kΩ (MAX1133)
R3 = 3.9kΩ (MAX1132)
OR INFINITY (MAX1133)
Figure 1. Equivalent Input Circuit
The DIN input accepts Control Byte data which is
clocked in on each rising edge oꢁ SCLK. Aꢁter CS goes
low or aꢁter a conversion or calibration completes, the
ꢁirst logic “1” clocked into DIN is interpreted as the
START bit, the MSB oꢁ the 8-bit Control Byte.
External Clock
In external clock mode, the external clock not only
shiꢁts data in and out, but it also drives the ADC con-
version steps. In short acquisition mode, SSTRB pulses
high ꢁor one clock period aꢁter the seventh ꢁalling edge
oꢁ SCLK ꢁollowing the start bit. The MSB oꢁ the conver-
sion is available at DOUT on the eighth ꢁalling edge oꢁ
SCLK (Figure 2).
The SCLK input is the serial data transꢁer clock which
clocks data in and out oꢁ the MAX1132/MAX1133.
SCLK also drives the A/D conversion steps in external
clock mode (see Internal and External Clock Modes
section).
In long acquisition mode, when using external clock,
SSTRB pulses high ꢁor one clock period aꢁter the ꢁiꢁ-
teenth ꢁalling edge oꢁ SCLK ꢁollowing the start bit. The
MSB oꢁ the conversion is available at DOUT on the six-
teenth ꢁalling edge oꢁ SCLK (Figure 3).
DOUT is the serial output oꢁ the conversion result.
DOUT is updated on the ꢁalling edge oꢁ SCLK. DOUT is
high-impedance when CS is high.
CS must be low ꢁor the MAX1132/MAX1133 to accept a
Control Byte. The serial interꢁace is disabled when CS
is high.
In external clock mode, SSTRB is high-impedance
when CS is high. In external clock mode, CS is normally
held low during the entire conversion. Iꢁ CS goes high
during the conversion, SCLK is ignored until CS goes
low. This allows external clock mode to be used with 8-
bit bytes.
User-Programmable Outputs
The MAX1132/MAX1133 have three user-programma-
ble outputs, P0, P1 and P2. The power-on deꢁault state
ꢁor the programmable outputs is zero. These are push-
pull CMOS outputs suitable ꢁor driving a multiplexer, a
PGA, or other signal preconditioning circuitry. The user-
programmable outputs are controlled by bits 0, 1, and
2 oꢁ the Control Byte (Table 2).
Internal Clock
In internal clock mode, the MAX1132/MAX1133 gener-
ates its own conversion clock. This ꢁrees the micro-
processor ꢁrom the burden oꢁ running the SAR conver-
sion clock, and allows the conversion results to be read
back at the processor’s convenience, at any clock rate
up to 8MHz.
The user-programmable outputs are set to zero during
power-on reset (POR) or when RST goes low. During
hardware or soꢁtware shutdown P0, P1, and P2 are
unchanged and remain low-impedance.
SSTRB goes low at the start oꢁ the conversion and goes
high when the conversion is complete. SSTRB will be
_______________________________________________________________________________________
9
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Table 1. Control Byte Format
BIT
NAME
DESCRIPTION
7 (MSB)
START
The ꢁirst logic “1” bit, aꢁter CS goes low, deꢁines the beginning oꢁ the Control Byte
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog
input signals ꢁrom 0 to +12V (MAX1132) or 0 to V
mode analog input signals ꢁrom -12V to +12V (MAX1132) or -V
converted.
(MAX1133) can be converted. In bipolar
REF
6
UNI/BIP
to +V
(MAX1133) can be
REF
REF
5
4
INT/EXT
Selects the internal or external conversion clock. 1 = Internal, 0 = External.
M1
M1
0
M0
0
MODE
24 External clocks per conversion (short acquisition mode)
Start Calibration. Starts internal calibration.
Soꢁtware power-down mode
0
1
3
M0
1
0
1
1
32 External clocks per conversion (long acquisition mode)
2
1
P2
P1
P0
These three bits are stored in a port register and output to pins P2, P1, P0 ꢁor use in addressing
a mux or PGA. These three bits are updated in the port register simultaneously when a new
Control Byte is written.
0(LSB)
Table 2. User-Programmable Outputs
PROGRAMMED
THROUGH
CONTROL BYTE
POWER-ON
OR RST
DEFAULT
OUTPUT
PIN
DESCRIPTION
P2
P1
P0
Bit 2
Bit 1
Bit 0
0
0
0
User-programmable outputs ꢁollow the state oꢁ the Control Byte’s three LSBs
and are updated simultaneously when a new Control Byte is written. Outputs
are push-pull. In hardware and soꢁtware shutdown, these outputs are
unchanged and remain low-impedance.
CS
t
ACQ
1
4
8
12
15
21
24
SCLK
UNI/ INT/
BIP EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
FILLED WITH
ZEROS
B15
MSB
B0
LSB
B14 B13 B12 B11 B10 B9
B4 B3
B2
B1
DOUT
A/D
STATE
IDLE
ACQUISITION
CONVERSION
IDLE
Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode
10 ______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
CS
t
ACQ
1
4
8
15
19
29
32
SCLK
UNI/ INT/
BIP EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
FILLED WITH
ZEROS
B15
MSB
B0
LSB
B14 B13
B4
B3
B2
B1
DOUT
A/D
STATE
IDLE
ACQUISITION
CONVERSION
IDLE
Figure 3. Long Acquisition Mode (32-Clock Cycles) External Clock, Bipolar Mode
low ꢁor a maximum oꢁ 6µs, during which time SCLK
should remain low ꢁor best noise perꢁormance. An inter-
nal register stores data when the conversion is in
progress. SCLK clocks the data out oꢁ the internal stor-
age register at any time aꢁter the conversion is com-
plete.
The ꢁirst high bit clocked into DIN with CS low any-
time the converter is idle, e.g., aꢁter AV
is
DD
applied, or as the ꢁirst high bit clocked into DIN
aꢁter CS is pulsed high, then low.
OR
Iꢁ a ꢁalling edge on CS ꢁorces a start bit beꢁore the
conversion or calibration is complete, then the
current operation will be terminated and a new
one started.
The MSB oꢁ the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 ꢁalling edges on
SCLK shiꢁt the remaining bits out oꢁ the internal storage
register (Figure 4). CS does not need to be held low
once a conversion is started.
Applications Information
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Figure 5 shows the SSTRB timing in internal clock
mode. In internal clock mode, data can be shiꢁted in to
the MAX1132/MAX1133 at clock rates up to 4.8MHz,
Power-On Reset
When power is ꢁirst applied to the MAX1132/MAX1133
or iꢁ RST is pulsed low, the internal calibration registers
are set to their deꢁault values. The user-programmable
registers (P0, P1, and P2) are low, and the device is
conꢁigured ꢁor bipolar mode with internal clocking.
provided that the minimum acquisition time, t
, is
ACQ
kept above 1.14µs in bipolar mode and 1.82µs in
unipolar mode. Data can be clocked out at 8MHz.
Calibration
To compensate the MAX1132/MAX1133 ꢁor temperature
driꢁt and other variations, they should be periodically
calibrated. Aꢁter any change in ambient temperature
more than 10°C the device should be recalibrated. A
100mV change in supply voltage or any change in the
reꢁerence voltage should be ꢁollowed by a calibration.
Calibration corrects ꢁor errors in gain, oꢁꢁset, integral
nonlinearity, and diꢁꢁerential nonlinearity. The MAX1132/
MAX1133 should be calibrated aꢁter power-up or the
assertion oꢁ reset. Make sure the power supplies and
the reꢁerence voltage have ꢁully settled prior to initiating
the calibration sequence.
Output Data
The output data ꢁormat is straight binary ꢁor unipolar
conversions and two’s complement in bipolar mode. In
both modes the MSB is shiꢁted out oꢁ the MAX1132/
MAX1133 ꢁirst.
Data Framing
The ꢁalling edge oꢁ CS does NOT start a conversion on
the MAX1132/MAX1133. The ꢁirst logic high clocked into
DIN is interpreted as a start bit and deꢁines the ꢁirst bit oꢁ
the Control Byte. A conversion starts on the ꢁalling edge
oꢁ SCLK, aꢁter the seventh bit oꢁ the Control Byte (the P1
bit) is clocked into DIN. The start bit is deꢁined as:
Initiate calibration by setting M1 = 0 and M0 = 1 in the
Control-Byte. In internal clock mode, SSTRB goes low at
______________________________________________________________________________________ 11
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
CS
t
ACQ
1
4
8
9
21
24
SCLK
UNI/ INT/
BIP EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
t
CONV
FILLED WITH
ZEROS
B15
MSB
B0
LSB
DOUT
B14 B13
B4
B3
B2
B1
Figure 4. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode
CS
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB
t
SSTRB
SCLK
P0 CLOCK IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 5. Internal Clock Mode SSTRB Detailed Timing
CS
t
t
STR
SDV
SSTRB
SCLK
t
t
SSTRB
SSTRB
P1 CLOCKED IN
Figure 6. External Clock Mode SSTRB Detailed Timing
12 ______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
the beginning oꢁ calibration and goes high to signal the
end oꢁ calibration, approximately 80,000 clock cycles
later. In external clock mode, SSTRB goes high at the
beginning oꢁ calibration and goes low to signal the end
oꢁ calibration. Calibration should be perꢁormed in the
same clock mode as will be used ꢁor conversions.
+5V
MAX1132
REFADJ
510kΩ
100kΩ
0.22µF
Reference
The MAX1132/MAX1133 can be used with an internal
or external reꢁerence. An external reꢁerence can be
connected directly at the REF pin or at the REFADJ pin.
CREF is an internal reꢁerence node and must be
bypassed with a 1µF capacitor when using either the
internal or an external reꢁerence.
24kΩ
Figure 7. MAX1132 Reference-Adjust Circuit
Input Range
Internal Reference
When using the MAX1132/MAX1133’s internal reꢁer-
ence, place a 0.22µF ceramic capacitor ꢁrom REFADJ
to AGND and place a 2.2µF capacitor ꢁrom REF to
AGND. Fine adjustments can be made to the internal
reꢁerence voltage by sinking or sourcing current at
REFADJ. The input impedance oꢁ REFADJ is nominally
9kΩ. The internal reꢁerence voltage is adjustable to
1.5ꢀ with the circuit oꢁ Figure 7.
The analog input range in unipolar mode is 0 to +12V
ꢁor the MAX1132, and 0 to +4.096V ꢁor the MAX1133. In
bipolar mode, the analog input can be -12V to +12V ꢁor
the MAX1132, and -4.096V to +4.096V ꢁor the
MAX1133. Unipolar and bipolar mode is programmed
with the UNI/BIP bit oꢁ the Control Byte. When using a
reꢁerence other than the MAX1132/MAX1133’s internal
+4.096V reꢁerence, the ꢁull-scale input range will vary
accordingly. The ꢁull-scale input range depends on the
voltage at REF and the sampling mode selected (Tables
3 and 4).
External reference
An external reꢁerence can be placed at either the input
(REFADJ) or the output (REF) oꢁ the MAX1132/
MAX1133’s internal buꢁꢁer ampliꢁier.
Input Acquisition and Settling
Clocking in a Control Byte starts input acquisition. In
bipolar mode the main capacitor array starts acquiring
the input as soon as a start bit is recognized. Iꢁ unipolar
mode is selected by the second DIN bit, the part will
immediately switch to unipolar sampling mode and
acquire a sample.
When connecting an external reꢁerence to REFADJ, the
input impedance is typically 9kΩ. Using the buꢁꢁered
REFADJ input makes buꢁꢁering oꢁ the external reꢁerence
unnecessary, however, the internal buꢁꢁer output must
be bypassed at REF with a 2.2µF capacitor.
Acquisition can be extended by eight clock cycles by
setting M1 = 1, M0 = 1 (long acquisition mode). The
sampling instant in short acquisition completes on the
ꢁalling edge oꢁ the sixth clock cycle aꢁter the start bit
(Figure 2).
When connecting an external reꢁerence at REF,
REFADJ must be connected to AV . Then the input
DD
impedance at REF is a minimum oꢁ 164kΩ ꢁor DC cur-
rents. During conversion, an external reꢁerence at REF
must deliver 250µA DC load current and have an out-
put impedance oꢁ 10Ω or less. Iꢁ the reꢁerence has a
higher output impedance or is noisy, bypass it at the
REF pin with a 4.7µF capacitor.
Acquisition is 5.5 clock cycles in short acquisition
mode and 13.5 clock cycles in long acquisition mode.
Short acquisition mode is 24 clock cycles per conver-
sion. Using the external clock to run the conversion
process limits unipolar conversion speed to 125ksps
instead oꢁ 200ksps in bipolar mode. The input resis-
tance in unipolar mode is larger than that oꢁ bipolar
mode (Figure1). The RC time constant in unipolar mode
is larger than that oꢁ bipolar mode, reducing the maxi-
mum conversion rate in 24 external clock mode. Long
acquisition mode with external clock allows both unipo-
lar and bipolar sampling oꢁ 150ksps (4.8MHz/32 clock
cycles) by adding eight extra clock cycles to the con-
version.
Analog Input
The MAX1132/MAX1133 use a capacitive DAC that
provides an inherent track/hold ꢁunction. Drive AIN with
a source impedance less than 10Ω. Any signal condi-
tioning circuitry must settle with 16-bit accuracy in less
than 500ns. Limit the input bandwidth to less than halꢁ
the sampling ꢁrequency to eliminate aliasing. The
MAX1132/MAX1133 has a complex input impedance
which varies ꢁrom unipolar to bipolar mode (Figure 1).
______________________________________________________________________________________ 1ꢁ
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Table ꢁ. Unipolar Full Scale and Zero Scale
PART
REFERENCE
Internal
ZERO SCALE
FULL SCALE
0
0
0
0
+12V
MAX1132
External
+12(V
/4.096)
REF
Internal
+4.096V
+V
MAX1133
External
REF
Table 4. Bipolar Full Scale, Zero Scale, and Negative Scale
NEGATIVE FULL
PART
REFERENCE
ZERO SCALE
FULL SCALE
SCALE
Internal
External
Internal
External
-12V
0
0
0
0
+12V
MAX1132
MAX1133
-12(V
/4.096)
+12(V
/4.096)
REF
REF
-4.096V
+4.096V
+V
-V
REF
REF
Most applications require an input buꢁꢁer ampliꢁier. Iꢁ
the input signal is multiplexed, the input channel should
be switched immediately aꢁter acquistion, rather than
near the end oꢁ or aꢁter a conversion. This allows more
time ꢁor the input buꢁꢁer ampliꢁier to respond to a large
step-change in input signal. The input ampliꢁier must
have a high enough slew-rate to complete the required
output voltage change beꢁore the beginning oꢁ the
acquisition time. At the beginning oꢁ acquisition, the
capacitive DAC is connected to the ampliꢁier output,
causing some output disturbance. Ensure that the sam-
pled voltage has settled to within the required limits
beꢁore the end oꢁ the acquisition time. Iꢁ the ꢁrequency
oꢁ interest is low, AIN can be bypassed with a large
enough capacitor to charge the capacitive DAC with
very little change in voltage. However, ꢁor AC use, AIN
must be driven by a wideband buꢁꢁer (at least 10MHz),
which must be stable with the DACs capacitive load (in
parallel with any AIN bypass capacitor used) and also
settle quickly (Figures 8 or 9).
requires bypassing AIN to AGND, or buꢁꢁering the input
with an ampliꢁier that has a small-signal bandwidth oꢁ
several MHz, or preꢁerably both. AIN has a bandwidth
oꢁ about 4MHz.
Oꢁꢁsets resulting ꢁrom synchronous noise (such as the
conversion clock) are canceled by the MAX1132/
MAX1133’s calibration scheme. The magnitude oꢁ the
oꢁꢁset produced by a synchronous signal depends on
the signal’s shape. Recalibration may be appropriate iꢁ
the shape or relative timing oꢁ the clock or other digital
signals change, as might occur iꢁ more than one clock
signal or ꢁrequency is used.
Distortion
Avoid degrading dynamic perꢁormance by choosing an
ampliꢁier with distortion much less than the MAX1132/
MAX1133’s THD (-90dB) at ꢁrequencies oꢁ interest. Iꢁ
the chosen ampliꢁier has insuꢁꢁicient common-mode
rejection, which results in degraded THD perꢁormance,
use the inverting conꢁiguration to eliminate errors ꢁrom
common-mode voltage. Low temperature-coeꢁꢁicient
resistors reduce linearity errors caused by resistance
changes due to selꢁ-heating. To reduce linearity errors
due to ꢁinite ampliꢁier gain, use an ampliꢁier circuit with
suꢁꢁicient loop gain at the ꢁrequencies oꢁ interest.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals that are
active during input acquisition contribute noise to the
conversion result. Iꢁ the noise signal is synchronous to
the sampling interval, an eꢁꢁective input oꢁꢁset is pro-
duced. Asynchronous signals produce random noise
on the input, whose high-ꢁrequency components may
be aliased into the ꢁrequency band oꢁ interest. Minimize
noise by presenting a low impedance (at the ꢁrequen-
cies contained in the noise signal) at the inputs. This
DC Accuracy
Iꢁ DC accuracy is important, choose a buꢁꢁer with an
oꢁꢁset much less than the MAX1132/MAX1133’s maxi-
mum oꢁꢁset ( 6mV), or whose oꢁꢁset can be trimmed
while maintaining good stability over the required tem-
perature range.
14 ______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
1kΩ
+15V
100pF
0.1µF
2
3
7
4
6
ELANTEC
EL2003
AIN
MAX427
20Ω
IN
0.0033µF
0.1µF
-15V
Figure 8. AIN Buffer for AC/DC Use
Mode 2 Long Acquisition Mode (32 SCLK)
Conꢁigure long acquisition by setting M1 = 1 and M0 =
1. In long acquisition mode, the acquisition time is 13.5
clock cycles. The total period is 32 clock cycles per
conversion.
510Ω
+5V
0.1µF
Calibration Mode
A calibration is initiated through the serial interꢁace by
setting M1 = 0, M0 = 1. Calibration can be done in
either internal or external clock mode, though it is desir-
able that the part be calibrated in the same mode in
which it will be used to do conversions. The part will
remain in calibration mode ꢁor approximately 80,000
clock cycles unless the calibration is aborted.
Calibration is halted iꢁ RST or SHDN goes low, or iꢁ a
valid start condition occurs.
2
3
7
4
22Ω
6
AIN
MAX410
IN
0.1µF
0.1µF
-5V
Software Shutdown
A soꢁtware power-down is initiated by setting M1 = 1,
M0 = 0. Aꢁter the conversion completes, the part shuts
down. It reawakens upon receiving a new start bit.
Conversions initiated with M1 = 1 and M0 = 0 (shut-
down) use the acquisition mode selected ꢁor the previ-
ous conversion.
Figure 9. 5ꢀ Buffer for AC/DC Use Has 3.5ꢀ Swing
Operating Modes and Serial Interfaces
The MAX1132/MAX1133 are ꢁully compatible with
MICROWIRE and SPI/QSPI devices. MICROWIRE and
SPI/QSPI both transmit a byte and receive a byte at the
same time. The simplest soꢁtware interꢁace requires
only three 8-bit transꢁers to perꢁorm a conversion (one
8-bit transꢁer to conꢁigure the ADC, and two more 8-bit
transꢁers to clock out the 16-bit conversion result).
Shutdown Mode
The MAX1132/MAX1133 may be shut down by pulling
SHDN low or by asserting soꢁtware shutdown. In addi-
tion to lowering power dissipation to 13µW, consider-
able power can be saved by shutting down the
converter ꢁor short periods (duration will be aꢁꢁected by
REF startup time with internal reꢁerence) between con-
versions. There is no need to perꢁorm a calibration aꢁter
the converter has been shut down, unless the time in
Short Acquisition Mode (24 SCLK)
Conꢁigure short acquisition by setting M1 = 0 and M0 =
0. In short acquisition mode, the acquisition time is 5.5
clock cycles. The total period is 24 clock cycles per
conversion.
______________________________________________________________________________________ 15
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
shutdown is long enough that the supply voltage or
ambient temperature may have changed.
DNL error speciꢁication oꢁ less than 1LSB guarantees
no missing codes and a monotonic transꢁer ꢁunction.
Supplies, Layout, Grounding
and Bypassing
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
For best system perꢁormance, use separate analog and
digital ground planes. The two ground planes should
be tied together at the MAX1132/MAX1133. Use pins 3
and 14 as the primary AGND and DGND, respectively.
Iꢁ the analog and digital supplies come ꢁrom the same
source, isolate the digital supply ꢁrom the analog with a
low value resistor (10Ω).
Aperture Delay
Aperture delay (t ) is the time between the ꢁalling
AD
edge oꢁ the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveꢁorm perꢁectly reconstructed ꢁrom digital sam-
ples, signal-to-noise ratio (SNR) is the ratio oꢁ ꢁull-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical, minimum analog-
to-digital noise is caused by quantization error only and
results directly ꢁrom the ADCs resolution (N bits):
The MAX1132/MAX1133 are not sensitive to the order
oꢁ AV
and DV
sequencing. Either supply can be
DD
DD
present in the absence oꢁ the other. Do not apply an
external reꢁerence voltage until aꢁter both AV and
DD
DV
are present.
DD
Be sure that digital return currents do not pass through
the analog ground. All return current paths must be
low-impedance. A 5mA current ꢁlowing through a PC
board ground trace impedance oꢁ only 0.05Ω creates
an error voltage oꢁ about 250µV, or about 2LSBs error
with a 4V ꢁull-scale system. The board layout should
ensure as much as possible that digital and analog sig-
nal lines are kept separate. Do not run analog and digi-
tal lines parallel to one another. Iꢁ you must cross one
with the other, do so at right angles.
SNR = (6.02 ✕ N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reꢁerence noise,
clock jitter, etc. Thereꢁore, SNR is calculated by taking
the ratio oꢁ the RMS signal to the RMS noise, which
includes all spectral components minus the ꢁundamen-
tal, the ꢁirst ꢁive harmonics, and the DC oꢁꢁset.
Signal-to-Noise Plus Distortion
Signal-to-Noise Plus Distortion (SINAD) is the ratio oꢁ
the ꢁundamental input ꢁrequency’s RMS amplitude to
the RMS equivalent oꢁ all other ADC output signals:
The ADC is sensitive to high-ꢁrequency noise on the
AV
power supply. Bypass this supply to the analog
DD
ground plane with 0.1µF. Iꢁ the main supply is not ade-
quately bypassed, add an additional 1µF or 10µF low-
ESR capacitor in parallel with the primary bypass
capacitor.
SINAD (dB) = 20 ✕ log (Signal
/Noise
RMS
)
RMS
Effective Number of Bits
Eꢁꢁective number oꢁ bits (ENOB) indicates the global
accuracy oꢁ an ADC at a speciꢁic input ꢁrequency and
sampling rate. An ideal ADCs error consists oꢁ quanti-
zation noise only. With an input range equal to the ꢁull-
scale range oꢁ the ADC, calculate the eꢁꢁective number
oꢁ bits as ꢁollows:
Transfer Function
Figures 10 and 11 show the MAX1132/MAX1133’s
transꢁer ꢁunctions. In unipolar mode, the output data is
binary ꢁormat and in bipolar mode it is two’s comple-
ment.
ENOB = (SINAD - 1.76) / 6.02
Definitions
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio oꢁ the RMS
sum oꢁ the ꢁirst ꢁive harmonics oꢁ the input signal to the
ꢁundamental itselꢁ. This is expressed as:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation oꢁ the values
on an actual transꢁer ꢁunction ꢁrom a straight line. This
straight line can be either a best-straight-line ꢁit or a line
drawn between the end points oꢁ the transꢁer ꢁunction,
once oꢁꢁset and gain errors have been nulliꢁied. INL ꢁor
the MAX1132/MAX1133 is measured using the end-
point method.
2
THD= 20×log
V22 + V32 + V42 + V5 /V
1
Differential Nonlinearity
Diꢁꢁerential nonlinearity (DNL) is the diꢁꢁerence between
an actual step-width and the ideal value oꢁ 1LSB. A
16 ______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
011 . . . 111
11 . . . 110
11 . . . 101
011 . . . 110
+FS = +4.096V
-FS = -4.096V
8.192
1LSB =
000 . . . 010
000 . . . 001
000 . . . 000
65536
FS = +2.048V
111 . . . 111
111 . . . 110
111 . . . 101
FS
65536
1LSB =
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
1
2
3
FS
0V
-FS
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
Figure 11. MAX1133 Bipolar Transfer Function, 4.096ꢀ = Full
Scale
Figure 10. MAX1135 Unipolar Transfer Function, 2.048ꢀ = Full
Scale
where V is the ꢁundamental amplitude, and V through
5
harmonics.
Chip Information
TRANSISTOR COUNT: 21,807
1
2
V
are the amplitudes oꢁ the 2nd- through 5th-order
PROCESS: BiCMOS
Spurious-Free Dynamic Range
Spurious-ꢁree dynamic range (SFDR) is the ratio oꢁ RMS
amplitude oꢁ the ꢁundamental (maximum signal compo-
nent), to the RMS value oꢁ the next largest distortion
component.
______________________________________________________________________________________ 17
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Functional Diagram
AV
DD
AGND
9kΩ
MAX1132
MAX1133
CREF
REFERENCE
REFADJ
REF
AIN
INPUT
DAC
COMPARATOR
SCALING
NETWORK
ANALOG TIMING CONTROL
DV
DD
SSTRB
DOUT
DGND
CS
SERIAL
OUTPUT
PORT
SERIAL
INPUT
PORT
P2
MEMORY
CALIBRATION
ENGINE
SCLK
P1
P0
DIN
RST
CLOCK
GENERATOR
CONTROL
SHDN
Typical Application Circuit
Ordering Information (continued)
INL
(LSB)
+5V
PART
TEMP. RANGE PIN-PACKAGE
MAX1132AEAP*
MAX1132BEAP
MAꢀ11ꢁꢁACAP*
MAX1133BCAP
MAX1133AEAP*
MAX1133BEAP
-40°C to +85°C 20 SSOP
-40°C to +85°C 20 SSOP
0°C to +70°C 20 SSOP
0°C to +70°C 20 SSOP
-40°C to +85°C 20 SSOP
-40°C to +85°C 20 SSOP
1.5
2.5
1.5
2.5
1.5
2.5
0.1µF
AV
DD
SHDN
+5V
DV
DD
MAX1132
MAX1133
0.1µF
AIN
*Future product
MC68HCXX
I/O
CS
SCLK
DIN
DOUT
RST
SCLK
MOSI
MISO
CREF
REF
I/O
SSTRB
REFADJ
1µF
2.2µF
0.22µF
DGND AGND
18 ______________________________________________________________________________________
16-Bit ADC, 200ksps, 5V Single-Supply
with Reference
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark oꢁ Maxim Integrated Products.
相关型号:
MAX1134BCAP+
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
MAX1134BCAP+T
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
MAX1134BCAP-T
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
MAX1134BEAP+
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
MAX1134BEAP+T
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
MAX1134BEAP-T
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20
MAXIM
©2020 ICPDF网 联系我们和版权申明