MAX1134BCAP+ [MAXIM]
ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20;
| 型号： | MAX1134BCAP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 16-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO20, 5.30 MM, 0.65 MM PITCH, SSOP-20 |
| 文件： | 总18页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2464; Rev 0; 4/02
16-Bit ADCs, 150ksps, 3.3V Single Supply
General Description
Features
The MAX1134/MAX1135 are 150ksps, 16-bit ADCs.
These serially interfaced ADCs connect directly to SPI™,
QSPI™, and MICROWIRE™ devices without external
logic. They combine an input scaling network, internal
track/hold (T/H), clock, and three general-purpose digital
output pins (for external multiplexer or PGA control) in a
20-pin SSOP package. The excellent dynamic perfor-
mance (THD ≥ 90dB), high speed (150ksps in bipolar
mode), and low power (8.0mA) of these ADCs make
them ideal for applications such as industrial process
control, instrumentation, and medical applications.
ꢀ 150ksps (Bipolar) and 125ksps (Unipolar)
Sampling ADC
ꢀ 16 Bits, No Missing Codes
ꢀ 1LSB INL (typ) Guaranteed
ꢀ -100dB THD
ꢀ 3.3V Single-Supply Operation
ꢀ Low-Power Operation
4.5mA (typ) (Unipolar Mode)
ꢀ 1.2µA Shutdown Mode
ꢀ Software-Configurable Unipolar and Bipolar Input
Ranges
0 to +6V and 6V (MAꢀ1134)
0 to +2.048V and 2.048V (MAꢀ1135)
ꢀ Internal or External Clock
ꢀ SPI/QSPI/MICROWIRE TMS320-Compatible Serial
Interface
ꢀ Three User-Programmable Logic Outputs
The MAX1134 accepts input signals of 0 to +6V (unipo-
lar) or 6V (bipolar), while the MAX1135 accepts input
signals of 0 to +2.048V (unipolar) or 2.048V (bipolar).
Operating from a single 3.135V to 3.465V analog and
digital supply, power-down modes reduce current con-
sumption to 0.15mA at 10ksps and further reduce sup-
ply current to less than 20µA at slower data rates.
A serial strobe output (SSTRB) allows direct connection
to the TMS320 family digital-signal processors. The
MAX1134/MAX1135 user can select either the internal
clock or an external serial-interface clock for the ADC to
perform analog-to-digital conversions.
ꢀ Small 20-Pin SSOP Package
Ordering Information
The MAX1134/MAX1135 feature internal calibration cir-
cuitry to correct linearity and offset errors. On-demand
calibration allows the user to optimize performance.
Three user-programmable logic outputs are provided
for the control of an 8-channel mux or PGA.
TEMP
PIN-
INL
PART
RANGE
PACKAGE
(LSB)
MAꢀ1134BCAP
0°C to +70°C
20 SSOP
20 SSOP
2.5
2.5
MAX1134BEAP
-40°C to +85°C
The MAX1134/MAX1135 are available in a 20-pin SSOP
package and are fully specified over the -40°C to
+85°C temperature range.
Ordering Information continued at end of data sheet.
Applications
Industrial Process Control
Pin Configuration
TOP VIEW
Industrial I/O Modules
REF
1
2
3
4
5
6
7
8
9
20 AIN
Data-Acquisition Systems
AV
19 AGND
18 CREF
17 CS
DD
Medical Instruments
AGND
Portable and Battery-Powered Equipment
AV
DD
MAX1134
MAX1135
DGND
SHDN
P2
16 DIN
15 DV
Functional Diagram and Typical Application Circuit appear
at end of data sheet.
DD
14
DGND
P1
13 SCLK
12 RST
PO
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
SSTRB 10
11 DOUT
SSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
16-Bit ADCs, 150ksps, 3.3V Single Supply
ABSOLUTE MAꢀIMUM RATINGS
AV
to AGND% DV
to DGND ..............................-0.3V to +6V
Operating Temperature Ranges
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .................................................................... 16.5V
MAX113_ _CAP...................................................0°C to +70°C
MAX113_ _EAP................................................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering% 10s) .................................+300°C
CREF% REF to AGND................................-0.3V to (AV
+ 0.3V)
DD
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DV + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= 3.3V 5ꢀ% ꢁ
= 3.6MHz% external clock (50ꢀ duty cycle)% 24 clocks/conversion (150ksps)% bipolar input% V
=
DD
DD
SCLK
REF
2.048V% C
= 4.7µF% C
= 1µF% T = T
to T
% unless otherwise noted. Typical values are at T = +25°C.)
MAX A
REF
CREF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
1.0
MAꢀ
UNITS
DC ACCURACY (Note 1)
Resolution
16
Bits
LSB
Bits
LSB
Relative Accuracy
No Missing Codes
Diꢁꢁerential Nonlinearity
Transition Noise
INL
Bipolar mode (Note 2)
Bipolar mode
MAX113_B
MAX113_B
2.5
16
-1
DNL
+1.75
1.5
LSB
RMS
Unipolar
4
Oꢁꢁset Error
mV
Bipolar
6
Unipolar
0.2
0.3
Gain Error (Note 3)
ꢀFSR
Bipolar
Oꢁꢁset Driꢁt (Bipolar and Unipolar)
Gain Driꢁt (Bipolar and Unipolar)
Excluding reꢁerence driꢁt
Excluding reꢁerence driꢁt
1
4
ppm/°C
ppm/°C
.
DYNAMIC SPECIFICATIONS (5kHz SINE-WAVE INPUT, 150ksps, 3.6MHz CLOCK, BIPOLAR INPUT MODE. MAꢀ1134, 12V
P-P
MAꢀ1135, 4.096V .)
P-P
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
ꢁ
IN
= 5kHz
= 75kHz
= 5kHz
= 75kHz
= 5kHz
= 75kHz
= 5kHz
= 75kHz
80
80
84
83
Signal-to-Noise Plus Distortion
(SINAD)
dB
dB
dB
dB
84
Signal-to-Noise Ratio (SNR)
83
-100
-93
105
97
-90
Total Harmonic Distortion (THD)
92
Spurious-Free Dynamic Range
(SFDR)
ANALOG INPUT
Unipolar
Bipolar
Unipolar
Bipolar
0
-6
+6
+6
MAX1134
MAX1135
Input Range
V
0
+2.048
+2.048
-2.048
2
_______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 3.3V 5ꢀ% ꢁ
= 3.6MHz% external clock (50ꢀ duty cycle)% 24 clocks/conversion (150ksps)% bipolar input% V
=
DD
DD
SCLK
REF
2.048V% C
= 4.7µF% C
= 1µF% T = T
to T
% unless otherwise noted. Typical values are at T = +25°C.)
MAX A
REF
CREF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
Unipolar
MIN
7.5
TYP
10.5
8.4
MAꢀ
UNITS
kΩ
MAX1134
MAX1135
Bipolar
Unipolar
Bipolar
5.9
Input Impedance
100
3.4
1000
5.3
Input Capacitance
CONVERSION RATE
Internal Clock Frequency
Aperture Delay
32
pF
3
MHz
ns
t
10
50
AD
Aperture Jitter
t
ps
AJ
MODE 1 (24 EꢀTERNAL CLOCK CYCLES PER CONVERSION)
Unipolar
0.1
0.1
3.0
3.6
External Clock Frequency
Sample Rate
ꢁ
MHz
ksps
SCLK
Bipolar
Unipolar
Bipolar
4.17
4.17
125
150
ꢁ =
S
ꢁ
/ 24
SCLK
t
CONV+ACQ
= 24 /
Unipolar
Bipolar
8
240
240
Conversion Time (Note 4)
µs
6.7
ꢁ
SCLK
MODE 2 (INTERNAL CLOCK MODE)
External Clock Frequency
(Data Transꢁer Only)
4
7
MHz
µs
Conversion Time
(SSTRB low pulse width)
Unipolar
5.3
1.67
1.39
Acquisition Time (Note 5)
µs
Bipolar
MODE 3 (32 EꢀTERNAL CLOCK CYCLES PER CONVERSION)
External Clock Frequency
ꢁ
Unipolar or bipolar
0.1
3.6
MHz
ksps
SCLK
ꢁ =
S
Sample Rate
Unipolar or bipolar
3.125
112
ꢁ
/ 32
SCLK
t
CONV+ACQ
= 32 /
Conversion Time (Note 4)
Unipolar or bipolar
(Notes 6% 7)
8.89
1.9
320
2.2
µs
ꢁ
SCLK
EꢀTERNAL REFERENCE
Input Range
2.048
110
100
0.1
V
V
V
= 2.048V% ꢁ
= 2.048V% ꢁ
= 3.6MHz
= 0
REF
REF
SCLK
SCLK
Input Current
µA
In power-down% ꢁ
= 0
SCLK
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Leakage
V
2.4
-1
V
V
IH
V
0.8
+1
IL
I
V
= 0 or DV
DD
µA
IN
IN
_______________________________________________________________________________________
3
16-Bit ADCs, 150ksps, 3.3V Single Supply
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= 3.3V 5ꢀ% ꢁ
= 3.6MHz% external clock (50ꢀ duty cycle)% 24 clocks/conversion (150ksps)% bipolar input% V
=
DD
DD
SCLK
REF
2.048V% C
= 4.7µF% C
= 1µF% T = T
to T
% unless otherwise noted. Typical values are at T = +25°C.)
MAX A
REF
CREF
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.2
10
MAꢀ
UNITS
V
Input Hysteresis
V
HYST
Input Capacitance
DIGITAL OUTPUTS
C
pF
IN
DV
0.5
-
DD
Output High Voltage
Output Low Voltage
V
I
= 0.5mA
V
V
OH
SOURCE
I
I
= 5mA
0.4
0.8
SINK
V
OL
= 16mA
SINK
Three-State Leakage Current
Three-State Output Capacitance
POWER SUPPLIES
Analog Supply
I
CS = DV
CS = DV
-10
+10
µA
pF
L
DD
DD
10
AV
DV
3.135
3.135
3.3
3.3
3.9
7
3.465
3.465
8
V
V
DD
Digital Supply
DD
Unipolar mode
mA
Analog Supply Current
I
ANALOG
Bipolar mode
11
SHDN = 0% or soꢁtware power-down mode
Unipolar or bipolar mode
SHDN = 0% or soꢁtware power-down mode
0.1
1
10
µA
mA
µA
2
Digital Supply Current
I
DIGITAL
PSRR
1.1
10
Power-Supply Rejection Ratio
(Note 8)
AV
= DV
= 3.135V to 3.465V
DD
65
dB
DD
TIMING CHARACTERISTICS (Figures 5 and 6)
(AV
= DV
= 3.3V 5ꢀ% T = T
to T
% unless otherwise noted.)
MAX
DD
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAꢀ
UNITS
ns
DIN to SCLK Setup
t
50
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Fall to SSTRB
t
70
80
80
ns
t
C
C
= 50pF
= 50pF
ns
DV
LOAD
LOAD
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
t
120
120
ns
CH
t
ns
CL
t
C
C
C
= 50pF
80
80
80
ns
SSTRB
LOAD
LOAD
LOAD
CS Fall to SSTRB Enable
CS Rise to SSTRB Disable
SSTRB Rise to SCLK Rise
RST Pulse Width
t
= 50pF% external clock mode
= 50pF% external clock mode
ns
SDV
t
ns
STR
SCK
t
Internal clock mode
0
ns
t
278
70
ns
RS
4
_______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
TIMING CHARACTERISTICS (Figures 5 and 6) (continued)
(AV
= DV
= 3.3V 5ꢀ% T = T
to T
% unless otherwise noted.)
MAX
DD
DD
A
MIN
Note 1: Tested at AV
= DV = 3.3V% bipolar input mode.
DD
DD
Note 2: Relative accuracy is the deviation oꢁ the analog value at any code ꢁrom its theoretical value aꢁter the gain error and oꢁꢁset
error have been nulliꢁied.
Note 3: Oꢁꢁset nulliꢁied.
Note 4: Conversion time is deꢁined as the number oꢁ clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle. Includes
the acquisition time.
Note 5: Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode.
Note 6: Perꢁormance is limited by the converter’s noise ꢁloor% typically 300µV
.
P-P
Note 7: When an external reꢁerence has a diꢁꢁerent voltage than the speciꢁied typical value% the ꢁull scale oꢁ the ADC scales propor-
tionally.
Note 8: Deꢁined as the change in positive ꢁull scale caused by a 5ꢀ variation in the nominal supply voltage.
Typical Operating Characteristics
(MAX1134/MAX1135% AV
= DV
= 3.3V% ꢁ
= 3.6MHz% external clock (50ꢀ duty cycle)% 24 clocks/conversion (150ksps)%
SCLK
DD
DD
bipolar input% REF = 2.048V% 4.7µF on REF% 1µF on CREF% T = +25°C% unless otherwise noted.)
A
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
1.0
0.8
9.0
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
3
2
A: AV , DV = 3.135V
DD
DD
B: AV , DV = 3.3V
DD
DD
C: AV , DV = 3.465V
DD
DD
0.6
0.4
1
C
B
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1
-2
-3
A
1
13273 26545 39817 53089 59725
DIGITAL OUTPUT CODE
1
13649 27297 40945 54593 61417
DIGITAL OUTPUT CODE
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
_______________________________________________________________________________________
5
16-Bit ADCs, 150ksps, 3.3V Single Supply
Typical Operating Characteristics (continued)
(MAX1134/MAX1135% AV
= DV
= 3.3V% ꢁ
= 3.6MHz% external clock (50ꢀ duty cycle)% 24 clocks/conversion (150ksps)%
SCLK
DD
DD
bipolar input% REF = 2.048V% 4.7µF on REF% 1µF on CREF% T = +25°C% unless otherwise noted.)
A
OFFSET VOLTAGE
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
TOTAL SUPPLY CURRENT vs.
CONVERSION RATE (USING SHUTDOWN)
-0.5
0.06
0.05
100
10
A: AV , DV = 3.135V
DD
DD
DD
DD
B: AV , DV = 3.3V
DD
C: AV , DV = 3.465V
DD
-1.0
-1.5
-2.0
B
0.04
0.03
0.02
0.01
0
C
C
1
A
A
0.1
0.01
-2.5
-3.0
A: AV , DV = 3.135V
DD
DD
DD
DD
B: AV , DV = 3.3V
DD
B
C: AV , DV = 3.465V
DD
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
0
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
CONVERSION RATE (ksps)
FFT PLOT
SINAD PLOT
0
100
90
80
70
60
50
40
30
20
10
0
f
= 150kHz
SAMPLE
f
f
= 150kHz
SAMPLE
= 5kHz
IN
-20
-40
-60
-80
-100
-120
0
10
20
30
40
50
60
70
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
SFDR PLOT
THD PLOT
120
110
100
90
80
70
60
50
40
30
20
10
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 150kHz
SAMPLE
f
= 150kHz
SAMPLE
0.1
1
10
100
0.1
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
6
_______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
Pin Description
PIN
NAME
REF
AV
FUNCTION
1
ADC Reꢁerence Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with a 4.7µF capacitor.
2
3
4
5
6
7
8
9
Analog Supply. Connect to pin 4.
DD
AGND Analog Ground. This is the primary analog ground (star ground).
AV Analog Supply% 3.3V 5ꢀ. Bypass AV to AGND (pin 3) with a 0.1µF capacitor.
DD
DD
DGND Digital Ground
SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.
P2
P1
P0
User-Programmable Output 2
User-Programmable Output 1
User-Programmable Output 0
Serial Strobe Output. In internal clock mode% SSTRB goes low when the ADC begins a conversion and goes
10
SSTRB high when the conversion is ꢁinished. In external clock mode% SSTRB pulses high ꢁor one clock period beꢁore
the MSB decision. It is high impedance when CS is high in external clock mode.
Serial Data Output. MSB ꢁirst% straight binary ꢁormat ꢁor unipolar input% two’s complement ꢁor bipolar input.
Each bit is clocked out oꢁ DOUT at the ꢁalling edge oꢁ SCLK.
11
12
13
DOUT
RST
Reset Input. Drive RST low to put the device in the power-on deꢁault mode. See the Power-On Reset section.
Serial Data Clock Input. Serial data on DIN is loaded on the rising edge oꢁ SCLK% and serial data is updated
on DOUT on the ꢁalling edge oꢁ SCLK. In external clock mode% SCLK sets the conversion speed.
SCLK
14
15
16
DGND Digital Ground. Connect to pin 5.
DV Digital Supply% 3.3V 5ꢀ. Bypass DV
to DGND (pin 14) with a 0.1µF capacitor.
DD
DD
DIN
Serial Data Input. Serial data on DIN is latched on the rising edge oꢁ SCLK.
Chip-Select Input. Drive CS low to enable the serial interꢁace. When CS is high% DOUT is high impedance. In
external clock mode% SSTRB is high impedance when CS is high.
17
CS
18
19
20
CREF
Reꢁerence Buꢁꢁer Bypass. Bypass CREF to AGND (pin 3) with a 1µF capacitor.
AGND Analog Ground. Connect to pin 3.
AIN
Analog Input
_______________________________________________________________________________________
7
16-Bit ADCs, 150ksps, 3.3V Single Supply
In addition to a 16-bit ADC% the MAX1134/MAX1135
include an input scaler% an internal digital microcontroller%
calibration circuitry% and an internal clock generator.
Detailed Description
The MAX1134/MAX1135 ADCs use a successive-
approximation technique and input track/hold (T/H) cir-
cuitry to convert an analog signal to a 16-bit digital
output. The MAX1134/MAX1135 easily interꢁace to
microprocessors (µPs). The data bits can be read either
during the conversion in external clock mode or aꢁter the
conversion in internal clock mode.
The input scaler ꢁor the MAX1134 enables conversion
oꢁ input signals ranging ꢁrom 0 to +6V (unipolar input)
or 6V (bipolar input). The MAX1135 accepts 0 to
+2.048V (unipolar input) or 2.048V (bipolar input). The
input range is soꢁtware selectable.
Calibration
To minimize linearity% oꢁꢁset% and gain errors% the
MAX1134/MAX1135 have on-demand soꢁtware calibra-
tion. Initiate calibration by writing a control byte with bit
M1 = 0 and bit M0 = 1 (Table 1). Select internal or exter-
nal clock ꢁor calibration by setting the INT/EXT bit in the
control byte. Calibrate the MAX1134/MAX1135 with the
same clock mode used ꢁor perꢁorming conversions.
BIPOLAR
VOLTAGE
S1
R3
REFERENCE
R1
UNIPOLAR
2.5kΩ
C
HOLD
32pF
Oꢁꢁsets resulting ꢁrom synchronous noise (such as the
conversion clock) are canceled by the MAX1134/
MAX1135’s calibration circuitry. However% because the
magnitude oꢁ the oꢁꢁset produced by a synchronous
signal depends on the signal’s shape% recalibration
may be appropriate iꢁ the shape or relative timing oꢁ the
clock% or other digital signals change% as may occur iꢁ
more than one clock signal or ꢁrequency is used.
TRACK
R2
AIN
S2
T/H OUT
HOLD
TRACK
HOLD
S3
S1 = BIPOLAR/UNIPOLAR
S2, S3 = T/H SWITCH
R2 = 7.6kΩ (MAX1134)
OR 2.5kΩ (MAX1135)
R3 = 3.9kΩ (MAX1134)
OR INFINITY (MAX1135)
Input Scaler
The MAX1134/MAX1135 have an input scaler% which
allows conversion oꢁ true bipolar input voltages while
operating ꢁrom a single 3.3V supply. The input scaler
attenuates and shiꢁts the input as necessary to map the
external input range to the input range oꢁ the internal
ADC. The MAX1134 analog input range is 0 to +6V
(unipolar) or 6V (bipolar). The MAX1135 analog input
Figure 1. Equivalent Input Circuit
Table 1. Control Byte Format
BIT
NAME
DESCRIPTION
7 (MSB)
START
The ꢁirst logic 1 bit aꢁter CS goes low deꢁines the beginning oꢁ the control byte.
1 = unipolar% 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode% analog input
signals ꢁrom 0 to +6V (MAX1134) or 0 to +V (MAX1135) can be converted. In bipolar mode% analog
6
5
4
UNI/BIP
INT/EXT
M1
REF
input signals ꢁrom -6V to +6V (MAX1134) or -V
to +V
(MAX1135) can be converted.
REF
REF
Selects the internal or external conversion clock. 1 = internal% 0 = external.
M1
0
M0
0
Mode
24 external clocks per conversion (short acquisition mode)
Start calibration: starts internal calibration
Soꢁtware power-down mode
0
1
1
0
3
M0
1
1
32 external clocks per conversion (long acquisition mode)
2
1
P2
P1
P0
These 3 bits are stored in a port register and output to pins P2% P1% and P0 ꢁor use in addressing a mux
or PGA. These 3 bits are updated in the port register simultaneously when a new control byte is written.
0 (LSB)
8
_______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
CS
t
ACQ
1
4
8
12
15
21
24
SCLK
UNI/
BIP
INT/
EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
FILLED WITH
ZEROS
B0
LSB
B15
MSB
B14 B13 B12 B11 B10 B9
B4 B3
B2
B1
DOUT
A/D
STATE
IDLE
ACQUISITION
CONVERSION
IDLE
Figure 2. Short Acquisition Mode (24 Clock Cycles) External Clock
Table 2. User-Programmable Outputs
PROGRAMMED
THROUGH CONTROL
BYTE
POWER-ON OR
RST DEFAULT
OUTPUT PIN
DESCRIPTION
User-programmable outputs ꢁollow the state oꢁ the control
byte’s 3 LSBs% and are updated simultaneously when a new
control byte is written. Outputs are push-pull. In hardware and
soꢁtware shutdown% these outputs are unchanged and remain
low impedance.
P2
P1
P0
Bit 2
Bit 1
Bit 0
0
0
0
range is 0 to +2.048V (unipolar) or 2.048V (bipolar).
Unipolar and bipolar mode selection is conꢁigured with
bit 6 oꢁ the serial control byte (Table 1).
low or aꢁter a conversion or calibration completes% the
ꢁirst logic 1 clocked into DIN is interpreted as the
START bit% the MSB oꢁ the 8-bit control byte.
Figure 1 shows the equivalent input circuit oꢁ the
MAX1134/MAX1135. The resistor network on the analog
input provides 16.5V ꢁault protection. This circuit limits
the current going into or out oꢁ the pin to less than 2mA.
The overvoltage protection is active even iꢁ the device
The SCLK input is the serial-data-transꢁer clock% which
clocks data in and out oꢁ the MAX1134/MAX1135.
SCLK also drives the ADC conversion steps in external
clock mode (see the Internal and External Clock Modes
section).
is in a power-down mode% or iꢁ AV
= 0.
DD
DOUT is the serial output oꢁ the conversion result.
DOUT is updated on the ꢁalling edge oꢁ SCLK. DOUT is
high impedance when CS is high.
Digital Interface
The digital interꢁace pins consist oꢁ SHDN% RST%
SSTRB% DOUT% SCLK% DIN% and CS. Bringing SHDN low
places the MAX1134/MAX1135 in its 1.2µA shutdown
mode. A logic low on RST halts the MAX1134/MAX1135
operation and returns the part to its power-on-reset
state.
CS must be low ꢁor the MAX1134/MAX1135 to accept a
control byte. The serial interꢁace is disabled when CS is
high.
User-Programmable Outputs
The MAX1134/MAX1135 have three user-program-
mable outputs: P0% P1% and P2. The power-on deꢁault
state ꢁor the programmable outputs is zero. These are
push-pull CMOS outputs suitable ꢁor driving a multi-
plexer% a PGA% or other signal preconditioning circuitry.
Bits 0% 1% and 2 oꢁ the control byte control the user-pro-
grammable outputs (Tables 1% 2).
In external clock mode% SSTRB is low and pulses high
ꢁor one clock cycle at the start oꢁ conversion. In internal
clock mode% SSTRB goes low at the start oꢁ the conver-
sion% and goes high to indicate that the conversion is
ꢁinished.
The DIN input accepts control byte data% which is
clocked in on each rising edge oꢁ SCLK. Aꢁter CS goes
_______________________________________________________________________________________
9
16-Bit ADCs, 150ksps, 3.3V Single Supply
CS
t
ACQ
15
1
4
8
14
29
32
SCLK
UNI/
BIP
INT/
EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
FILLED WITH
ZEROS
B0
LSB
B15
MSB
B14 B13
B4
B3
B2
B1
DOUT
A/D
STATE
IDLE
ACQUISITION
CONVERSION
IDLE
Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock
CS
t
t
STR
SDV
SSTRB
t
t
SSTRB
SSTRB
SCLK
P1 CLOCKED IN
Figure 4. External Clock Mode SSTRB Detailed Timing
The user-programmable outputs are set to zero during
power-on reset or when RST goes low. During hardware
or soꢁtware shutdown% P0% P1% and P2 are unchanged
and remain low impedance.
Internal and External Clock Modes
The MAX1134/MAX1135 use either the external serial
clock or the internal clock to perꢁorm the successive-
approximation conversion. In both clock modes% the
external clock shiꢁts data in and out oꢁ the
MAX1134/MAX1135. Bit 5 (INT/EXT) oꢁ the control byte
programs the clock mode.
Starting a Conversion
Start a conversion by clocking a control byte into the
device’s internal shiꢁt register. With CS low% each rising
edge on SCLK clocks a bit ꢁrom DIN into the
MAX1134/MAX1135s’ internal shiꢁt register. Aꢁter CS
goes low or aꢁter a conversion or calibration completes%
the ꢁirst arriving logic 1 is deꢁined as the start bit oꢁ the
control byte. Until this ꢁirst start bit arrives% any number oꢁ
logic 0 bits can be clocked into DIN with no eꢁꢁect. Iꢁ at
any time during acquisition or conversion CS is brought
high and then low again% the part is placed into a state
where it can recognize a new start bit. Iꢁ a new start bit
occurs beꢁore the current conversion is complete% the
conversion is aborted and a new acquisition is initiated.
External Clock
In external clock mode% the external clock not only
shiꢁts data in and out% but also drives the ADC conver-
sion steps.
In short acquisition mode% SSTRB pulses high ꢁor one
clock period aꢁter the seventh ꢁalling edge oꢁ SCLK ꢁol-
lowing the start bit. The MSB oꢁ the conversion is avail-
able at DOUT on the eighth ꢁalling edge oꢁ SCLK
(Figure 2).
10 ______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
CS
t
ACQ
1
4
8
9
10
21
24
SCLK
UNI/
BIP
INT/
EXT
M1 M0
P2
P1
P0
START
DIN
SSTRB
t
CONV
FILLED WITH
ZEROS
B0
LSB
B15
MSB
DOUT
B4
B3
B2
B1
B14 B13
Figure 5. Internal Clock Mode Timing, Short Acquisition
CS
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB
t
SSTRB
SCLK
P0 CLOCKED IN
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 6. Internal Clock Mode SSTRB Detailed Timing
In long acquisition mode% when using external clock%
SSTRB pulses high ꢁor one clock period aꢁter the 15th
ꢁalling edge oꢁ SCLK ꢁollowing the start bit. The MSB oꢁ
the conversion is available at DOUT on the 16th ꢁalling
edge oꢁ SCLK (Figure 3).
SSTRB goes low at the start oꢁ the conversion and goes
high when the conversion is complete. SSTRB is low ꢁor
a maximum oꢁ 7µs% during which time SCLK should
remain low ꢁor best noise perꢁormance. An internal reg-
ister stores data when the conversion is in progress.
SCLK clocks the data out oꢁ the internal storage regis-
ter at any time aꢁter the conversion is complete.
In external clock mode% SSTRB is high impedance when
CS is high (Figure 4). CS is normally held low during the
entire conversion. Iꢁ CS goes high during the conver-
sion% SCLK is ignored until CS goes low. This allows
external clock mode to be used with 8-bit bytes.
The MSB oꢁ the conversion is available at DOUT when
SSTRB goes high. The subsequent 15 ꢁalling edges on
SCLK shiꢁt the remaining bits out oꢁ the internal storage
register (Figure 5). CS does not need to be held low
once a conversion is started.
Internal Clock
In internal clock mode% the MAX1134/MAX1135 gener-
ate their own conversion clock. This ꢁrees the micro-
processor ꢁrom the burden oꢁ running the SAR
conversion clock% and allows the conversion results to
be read back at the processor’s convenience% at any
clock rate up to 4MHz.
When internal clock mode is selected% SSTRB does not
go into a high-impedance state when CS goes high.
Figure 6 shows the SSTRB timing in internal clock
mode. In internal clock mode% data can be shiꢁted into
the MAX1134/MAX1135 at clock rates up to 4MHz% pro-
______________________________________________________________________________________ 11
16-Bit ADCs, 150ksps, 3.3V Single Supply
Table 3. Unipolar Full Scale and Zero
Scale
Table 4. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
PART
ZERO SCALE
FULL SCALE
NEGATIVE FULL
SCALE
ZERO
SCALE
PART
FULL SCALE
MAX1134
MAX1135
0
0
+6 (V /2.048)
REF
+V
MAX1134
MAX1135
-6 (V
/2.048)
0
0
+6 (V /2.048)
REF
REF
REF
-V
REF
+V
REF
vided the minimum acquisition time% t
above 1.39µs in bipolar mode and 1.67µs in unipolar
mode. Data can be clocked out at 4MHz.
% is kept
ACQ
power supplies and the reꢁerence voltage have ꢁully
settled prior to initiating the calibration sequence.
Initiate calibration by setting M1 = 0 and M0 = 1 in the
control byte. In internal clock mode% SSTRB goes low at
the beginning oꢁ calibration and goes high to signal the
end oꢁ calibration% approximately 80%000 clock cycles
later. In external clock mode% SSTRB goes high at the
beginning oꢁ calibration and goes low to signal the end
oꢁ calibration. Calibration should be perꢁormed in the
same clock mode that is used ꢁor conversions.
Output Data
The output data ꢁormat is straight binary ꢁor unipolar
conversions and two’s complement in bipolar mode.
The MSB is shiꢁted out oꢁ the MAX1134/MAX1135 ꢁirst
in both modes.
Data Framing
The ꢁalling edge oꢁ CS does not start a conversion on the
MAX1134/MAX1135. The ꢁirst logic high clocked into
DIN is interpreted as a start bit and deꢁines the ꢁirst bit oꢁ
the control byte. A conversion starts on the ꢁalling edge
oꢁ SCLK% aꢁter the seventh bit oꢁ the control byte (the P1
bit) is clocked into DIN. The start bit is deꢁined as:
Reference
The MAX1134/MAX1135 require a 2.048V reꢁerence.
The reꢁerence must be bypassed with a 4.7µF capaci-
tor. The input impedance at REF is a minimum oꢁ 16kΩ
ꢁor DC currents. During conversion% the external reꢁer-
ence at REF must deliver up to 150µA DC load current
and have an output impedance oꢁ 10Ω or less.
•
The ꢁirst high bit clocked into DIN with CS low any-
time the converter is idle% e.g.% aꢁter AV
applied.
is
DD
Analog Input
The MAX1134/MAX1135 use a capacitive DAC that
provides an inherent track/hold ꢁunction. Drive AIN with
a source impedance less than 10Ω. Any signal condi-
tioning circuitry must settle with 16-bit accuracy in less
than 500ns. Limit the input bandwidth to less than halꢁ
the sampling ꢁrequency to eliminate aliasing. The
MAX1134/MAX1135 have a complex input impedance
that varies ꢁrom unipolar to bipolar mode (Figure 1).
•
The ꢁirst high bit clocked into DIN aꢁter CS is pulsed
high then low.
Iꢁ a ꢁalling edge on CS ꢁorces a start bit beꢁore the con-
version or calibration is complete% then the current
operation terminates and a new one starts.
Applications Information
Power-On Reset
When power is ꢁirst applied to the MAX1134/MAX1135%
or iꢁ RST is pulsed low% the internal calibration registers
are set to their deꢁault values. The user-programmable
registers (P0% P1% and P2) are low% and the device is
conꢁigured ꢁor bipolar mode with internal clocking.
Input Range
The analog input range in unipolar mode is 0 to +6V ꢁor
the MAX1134% and 0 to +2.048V ꢁor the MAX1135. In
bipolar mode% the analog input can be -6V to +6V ꢁor
the MAX1134% or -2.048V to +2.048V ꢁor the MAX1135.
Unipolar or bipolar mode is programmed with the
UNI/BIP bit oꢁ the control byte. When using a reꢁerence
other than the suggested 2.048V% the ꢁull-scale input
range varies accordingly. The ꢁull-scale input range
depends on the voltage at REF and the sampling mode
selected (Tables 3 and 4).
Calibration
Periodically calibrate the MAX1134/MAX1135 to com-
pensate ꢁor temperature driꢁt and other variations. Aꢁter
any change in ambient temperature oꢁ more than
+10°C% the device should be recalibrated. A 100mV
change in supply voltage or any change in the reꢁer-
ence voltage should be ꢁollowed by a calibration.
Calibration corrects ꢁor errors in gain% oꢁꢁset% integral
nonlinearity% and diꢁꢁerential nonlinearity.
The MAX1134/MAX1135 should be calibrated aꢁter
power-up or aꢁter the assertion oꢁ reset. Make sure the
12 ______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
1k
V
CC
100pF
0.1 F
2
3
7
4
6
AIN
1k
IN
0.0033 F
0.1 F
V
EE
Figure 7. AIN Buffer for AC/DC Use
Input Acquisition and Settling
Clocking in a control byte starts input acquisition. The
main capacitor array starts acquiring the input as soon
as a start bit is recognized% using the same input range
as the previous conversion. Iꢁ the opposite input range
is selected by the second DIN bit% the part immediately
switches to the new sampling mode. Acquisition time is
one-and-a-halꢁ clock cycles shorter when switching
ꢁrom unipolar to bipolar or bipolar to unipolar modes
than when continuously converting in the same mode.
step change in input signal. The input ampliꢁier must
have a high enough slew rate to complete the required
output voltage change beꢁore the beginning oꢁ the
acquisition time.
At the beginning oꢁ acquisition% the capacitive DAC is
connected to the ampliꢁier output% causing some output
disturbance. Ensure that the sampled voltage has set-
tled to within the required limits beꢁore the end oꢁ the
acquisition time. Iꢁ the ꢁrequency oꢁ interest is low% AIN
can be bypassed with a large enough capacitor to
charge the capacitive DAC with very little change in
voltage. However% ꢁor AC use% AIN must be driven by a
wideband buꢁꢁer (at least 10MHz)% which must be sta-
ble with the DAC’s capacitive load (in parallel with any
AIN bypass capacitor used) and also must settle quickly
(Figure 7).
Acquisition can be extended by eight clock cycles by
setting M1 = 1 and M0 = 1 (long acquisition mode). The
sampling instant in short acquisition completes on the
ꢁalling edge oꢁ the sixth clock cycle aꢁter the start bit
(Figure 2). Acquisition is ꢁive clock cycles in short
acquisition mode and 13 clock cycles in long acquisi-
tion mode. Short acquisition mode is 24 clock cycles
per conversion. Using the external clock to run the con-
version process limits unipolar conversion speed to
125ksps instead oꢁ 150ksps as in bipolar mode. The
input resistance in unipolar mode is larger than that oꢁ
bipolar mode (Figure 1). The RC time constant in unipo-
lar mode is larger than that oꢁ bipolar mode% reducing
the maximum conversion rate in 24 external clock
mode. Long acquisition mode with external clock
allows both unipolar and bipolar sampling oꢁ 112ksps
(3.6MHz / 32 clock cycles) by adding eight extra clock
cycles to the conversion.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals that are
active during input acquisition contribute noise to the
conversion result. Iꢁ the noise signal is synchronous to
the sampling interval% an eꢁꢁective input oꢁꢁset is pro-
duced.
Asynchronous signals produce random noise on the
input% whose high-ꢁrequency components may be
aliased into the ꢁrequency band oꢁ interest. Minimize
noise by presenting a low impedance (at the ꢁrequen-
cies contained in the noise signal) at the inputs. This
requires bypassing AIN to AGND% or buꢁꢁering the input
with an ampliꢁier that has a small-signal bandwidth oꢁ
several MHz% or preꢁerably both. AIN has a bandwidth
oꢁ about 4MHz.
Most applications require an input buꢁꢁer ampliꢁier. Iꢁ
the input signal is multiplexed% the input channel should
be switched immediately aꢁter acquisition% rather than
near the end oꢁ or aꢁter a conversion. This allows more
time ꢁor the input buꢁꢁer ampliꢁier to respond to a large
______________________________________________________________________________________ 13
16-Bit ADCs, 150ksps, 3.3V Single Supply
Oꢁꢁsets resulting ꢁrom synchronous noise (such as the
conversion clock) are canceled by the MAX1134/
MAX1135s’ calibration scheme. However% because the
magnitude oꢁ the oꢁꢁset produced by a synchronous
signal depends on the signal’s shape% recalibration
may be appropriate iꢁ the shape or relative timing oꢁ the
clock or other digital signals change% which can occur
iꢁ more than one clock signal or ꢁrequency is used.
used to do conversions. The part remains in calibration
mode ꢁor approximately 80%000 clock cycles unless the
calibration is aborted. Calibration is halted iꢁ RST or
SHDN goes low% or iꢁ a valid start condition occurs.
Software Shutdown
A soꢁtware power-down is initiated by setting M1 = 1
and M0 = 0. Aꢁter the conversion completes% the part
shuts down. It reawakens upon receiving a new start
bit. Conversions initiated with M1 = 1 and M0 = 0 (shut-
down) use the acquisition mode selected ꢁor the previ-
ous conversion.
Distortion
Avoid degrading dynamic perꢁormance by choosing an
ampliꢁier with distortion much less than the
MAX1134/MAX1135s’ THD (-90dB) at ꢁrequencies oꢁ
interest. Iꢁ the chosen ampliꢁier has insuꢁꢁicient common-
mode rejection% which results in degraded THD perꢁor-
mance% use the inverting conꢁiguration to eliminate errors
ꢁrom common-mode voltage. Low-temperature-coeꢁꢁi-
cient resistors reduce linearity errors caused by resis-
tance changes due to selꢁ-heating. To reduce linearity
errors due to ꢁinite ampliꢁier gain% use an ampliꢁier circuit
with suꢁꢁicient loop gain at the ꢁrequencies oꢁ interest.
Shutdown Mode
The MAX1134/MAX1135 may be shut down by pulling
SHDN low or by asserting soꢁtware shutdown. In addi-
tion to lowering power dissipation to 4.0µW% consider-
able power can be saved by shutting down the
converter ꢁor short periods between conversions. There
is no need to perꢁorm a calibration aꢁter the converter
has been shut down unless the time in shutdown is
long enough that the supply voltage or ambient temper-
ature has changed.
DC Accuracy
Iꢁ DC accuracy is important% choose a buꢁꢁer with an
oꢁꢁset much less than the MAX1134/MAX1135s’ maxi-
mum oꢁꢁset ( 6mV)% or whose oꢁꢁset can be trimmed
while maintaining good stability over the required tem-
perature range.
Supplies, Layout, Grounding,
and Bypassing
For best system perꢁormance% use separate analog and
digital ground planes. The two ground planes should
be tied together at the MAX1134/MAX1135. Use pin 3
and pin 14 as the primary AGND and DGND% respec-
tively. Iꢁ the analog and digital supplies come ꢁrom the
same source% isolate the digital supply ꢁrom the analog
with a low-value resistor (10Ω).
Operating Modes and Serial Interfaces
The MAX1134/MAX1135 are ꢁully compatible with
MICROWIRE and SPI/QSPI devices. MICROWIRE and
SPI/QSPI both transmit a byte and receive a byte at the
same time. The simplest soꢁtware interꢁace requires
only three 8-bit transꢁers to perꢁorm a conversion (one
8-bit transꢁer to conꢁigure the ADC% and two more 8-bit
transꢁers to clock out the 16-bit conversion result).
The MAX1134/MAX1135 are not sensitive to the order
oꢁ AVDD and DVDD sequencing. Either supply can be
present in the absence oꢁ the other. Do not apply an
external reꢁerence voltage until aꢁter both AVDD and
DVDD are present.
Short Acquisition Mode (24 SCLK)
Conꢁigure short acquisition by setting M1 = 0 and M0 =
0. In short acquisition mode% the acquisition time is 5
clock cycles. The total period is 24 clock cycles per
conversion.
Be sure that digital return currents do not pass through
the analog ground. All return-current paths must be low
impedance. A 5mA current ꢁlowing through a PC board
ground trace impedance oꢁ only 0.05Ω creates an error
voltage oꢁ about 250µV% or about 2LSBs error with a 4V
ꢁull-scale system. The board layout should ensure that
digital and analog signal lines are kept separate. Do not
run analog and digital lines parallel to one another. Iꢁ you
must cross one with the other% do so at right angles.
Long Acquisition Mode (32 SCLK)
Conꢁigure long acquisition by setting M1 = 1 and M0 =
1. In long acquisition mode% the acquisition time is 13
clock cycles. The total period is 32 clock cycles per
conversion.
The ADC is sensitive to high-ꢁrequency noise on the
AVDD power supply. Bypass this supply to the analog
ground plane with 0.1µF. Iꢁ the main supply is not ade-
quately bypassed% add an additional 1µF or 10µF low-
ESR capacitor in parallel with the primary bypass
capacitor.
Calibration Mode
A calibration is initiated through the serial interꢁace by set-
ting M1 = 0 and M0 = 1. Calibration can be done in either
internal or external clock mode% though it is desirable that
the part be calibrated in the same mode in which it will be
14 ______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
011 . . . 111
011 . . . 110
+FS = +2.048V
-FS = -2.048V
11 . . . 101
4.096V
65536
1LSB =
000 . . . 010
000 . . . 001
000 . . . 000
FS = 2.048V
FS
65536
111 . . . 111
111 . . . 110
111 . . . 101
1LSB =
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
1
2
3
FS
0
-FS
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
Figure 8. MAX1135 Unipolar Transfer Function, 2.048V = Full
Scale
Figure 9. MAX1135 Bipolar Transfer Function, 4.096V = Full
Scale
Transfer Function
Figures 8 and 9 show the MAX1135s’ transꢁer ꢁunctions.
In unipolar mode% the output data is in binary ꢁormat
and in bipolar mode it is in two’s complement ꢁormat.
Signal-to-Noise Ratio
For a waveꢁorm perꢁectly reconstructed ꢁrom digital
samples% signal-to-noise ratio (SNR) is the ratio oꢁ ꢁull-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal% theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly ꢁrom the ADC’s resolution
(N-bits):
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation oꢁ the values
on an actual transꢁer ꢁunction ꢁrom a straight line. This
straight line can be either a best-straight-line ꢁit or a line
drawn between the end points oꢁ the transꢁer ꢁunction%
once oꢁꢁset and gain errors have been nulliꢁied. INL ꢁor
the MAX1134/MAX1135 is measured using the end-
point method.
SNR = (6.02 x N + 1.76) dB
In reality% there are other noise sources besides quanti-
zation noise% including thermal noise% reꢁerence noise%
clock jitter% etc. Thereꢁore% SNR is calculated by taking
the ratio oꢁ the RMS signal to the RMS noise% which
includes all spectral components minus the ꢁundamen-
tal% the ꢁirst ꢁive harmonics% and the DC oꢁꢁset.
Differential Nonlinearity
Diꢁꢁerential nonlinearity (DNL) is the diꢁꢁerence between
an actual step width and the ideal value oꢁ 1LSB. A
DNL error speciꢁication oꢁ less than 1LSB guarantees
no missing codes and a monotonic transꢁer ꢁunction.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio oꢁ the
ꢁundamental input ꢁrequency’s RMS amplitude to the
RMS equivalent oꢁ all other ADC output signals:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
SINAD (dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge oꢁ the sampling clock and the instant when an
actual sample is taken.
______________________________________________________________________________________ 15
16-Bit ADCs, 150ksps, 3.3V Single Supply
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio oꢁ the RMS
sum oꢁ the ꢁirst ꢁive harmonics oꢁ the input signal to the
ꢁundamental itselꢁ. This is expressed as:
Spurious-Free Dynamic Range
Spurious-ꢁree dynamic range (SFDR) is the ratio oꢁ RMS
amplitude oꢁ the ꢁundamental (maximum signal compo-
nent) to the RMS value oꢁ the next largest distortion
component.
2
2
2
2
V
+ V + V + V
3 4 5
2
THD = 20 × log
V
1
where V1 is the ꢁundamental amplitude% and V through
2
V
are the amplitudes oꢁ the 2nd- through 5th-order
5
harmonics.
Functional Diagram
AV
DD
AGND
CREF
MAX1134
MAX1135
REF
AIN
INPUT
DAC
COMPARATOR
SCALING
NETWORK
ANALOG TIMING CONTROL
DV
DD
SSTRB
DOUT
DGND
CS
SERIAL
INPUT
PORT
SERIAL
OUTPUT
PORT
P2
MEMORY
CALIBRATION
ENGINE
SCLK
P1
P0
DIN
RST
CLOCK
GENERATOR
SHDN
CONTROL
16 ______________________________________________________________________________________
16-Bit ADCs, 150ksps, 3.3V Single Supply
Typical Application Circuit
Ordering Information (continued)
3.3V
TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
PART
0.1µF
MAꢀ1135BCAP
0°C to +70°C
20 SSOP
20 SSOP
2.5
2.5
MAX1135BEAP
-40°C to +85°C
AV
DD
SHDN
3.3V
DV
DD
0.1µF
MC68HCXX
AIN
MAX1134/
MAX1135
CS
SCLK
DIN
I/O
SCLK
MOSI
MISO
I/O
2.048V
DOUT
RST
Chip Information
REF
SSTRB
CREF
TRANSISTOR COUNT: 21%807
DGND AGND
4.7µF
1µF
PROCESS: BiCMOS
______________________________________________________________________________________ 17
16-Bit ADCs, 150ksps, 3.3V Single Supply
Package Information
(The package drawing(s) in this data sheet may not reꢁlect the most current speciꢁications. For the latest package outline inꢁormation%
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark oꢁ Maxim Integrated Products.
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