MAX11358B [MAXIM]
16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor; 16位数据采集系统，带有ADC ， DAC ， UPIOs ， RTC ，电压监测器，以及温度传感器
| 型号： | MAX11358B |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor |
| 文件： | 总70页 (文件大小：3549K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5027; Rev 0; 12/09
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
General Description
Features
♦ +1.8V to +3.6V Single-Supply Operation
The MAX11358B smart data-acquisition system (DAS) is
based on a 16-bit, sigma-delta analog-to-digital converter
(ADC) and system-support functionality for a micro-
processor (µP)-based system. These devices integrate
an ADC, DACs, operational amplifiers, internal selec-
table-voltage reference, temperature sensors, analog
switches, a 32kHz oscillator, a real-time clock (RTC)
with alarm, a high-frequency-locked loop (FLL) clock,
four user-programmable I/Os, an interrupt generator,
and 1.8V and 2.7V voltage monitors in a single chip.
♦ Multichannel, 16-Bit, Sigma-Delta ADC
10sps to 477sps Programmable Conversion Rate
Self- and System Offset and Gain Calibration
PGA with Gains of 1, 2, 4, or 8
Unipolar and Bipolar Modes
10-Input Differential Multiplexer
♦ 10-Bit Force-Sense DACs
♦ Uncommitted Op Amps
♦ Dual SPDT and SPST Analog Switches
The MAX11358B has dual 10:1 differential input multiplex-
ers (muxes) that accept signal levels from 0 to AV . An
DD
on-chip 1x to 8x programmable-gain amplifier (PGA)
allows measuring low-level signals and reduces external
circuitry required.
♦ Selectable References
1.25V, 2.048V, and 2.5V
♦ Internal Charge Pump
♦ System Support
RTC and Alarm Register
Internal/External Temperature Sensor
Internal Oscillator with Clock Output
User-Programmable I/O and Interrupt Generator
The MAX11358B operates from a single +1.8V to +3.6V
supply and consumes only 1.15mA in normal mode and
only 3µA in sleep mode. The MAX11358B has two
DACs with one uncommitted op amp.
V
DD
Monitors
♦ SPI/QSPI/MICROWIRE, 4-Wire Serial Interface
♦ Space-Saving (6mm x 6mm x 0.8mm), 40-Pin
The serial interface is compatible with either SPI™/QSPI™
or MICROWIRE™, and is used to power up, configure,
and check the status of all functional blocks.
TQFN Package
Ordering Information
The MAX11358B is available in a space-saving, 40-pin
TQFN package and is specified over the commercial
(0°C to +70°C) and the extended (-40°C to +85°C) tem-
perature ranges.
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
40 TQFN-EP*
40 TQFN-EP*
MAX11358BCTL+
MAX11358BETL+
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Battery-Powered and Portable Devices
Electrochemical and Optical Sensors
Medical Instruments
Pin Configuration
TOP VIEW
Industrial Control
30 29 28 27 26 25 24 23 22 21
Data-Acquisition Systems
31
20 OUT1
19 SNC2
18 SCM2
17 SNO2
16 SNC1
15 SCM1
14 SNO1
13 32KIN
12 32KOUT
11 RESET
AIN2
AIN1
REF
32
33
34
35
36
37
38
REG
Selector Guide
CF-
MAX11358B
CF+
OP
SPDT/SPST
SWITCHES
PART
DACs
CPOUT
AMPs
DV
DD
MAX11358B_ _ _
2
1
2/2
DGND 39
UPIO1 40
*EP
+
1
2
3
4
5
6
7
8
9
10
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
TQFN
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ABSOLUTE MAXIMUM RATINGS
AV
to AGND .........................................................-0.3V to +4V
Continuous Current Into Any Pin.........................................50mA
DD
DV to DGND.........................................................-0.3V to +4V
Continuous Power Dissipation (T = +70°C)
DD
A
AV
to DV
............................................................-4V to +4V
40-Pin TQFN (derate 25.6mW/°C above +70°C) ....2051.3mW
DD
DD
AGND to DGND.....................................................-0.3V to +0.3V
CLK32K to DGND....................................-0.3V to (DV + 0.3V)
Operating Temperature Range
MAX11358BCTL+ ...............................................0°C to +70°C
MAX11358BETL+ ............................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Soldering Temperature (reflow) .......................................+260°C
DD
UPIO_ to DGND........................................................-0.3V to +4V
Digital Inputs to DGND ............................................-0.3V to +4V
Analog Inputs to AGND ...........................-0.3V to (AV
Digital Output to DGND…........................-0.3V to (DV
Analog Outputs to AGND.........................-0.3V to (AV
+ 0.3V)
+ 0.3V)
+ 0.3V)
DD
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX1358B
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY
Data rate = 10sps, PGA gain = 2;
data rate = 10sps to 60sps, PGA gain = 1;
no missing codes, Table 1 (Note 2)
Noise-Free Resolution
16
10
Bits
sps
Conversion Rate
Output Noise
No missing codes, Table 1
No missing codes
477
Table 1
0.0046
1.0
Unipolar mode, AV
= 3V,
DD
Integral Nonlinearity
INL
%FSR
%FSR
PGA gain = 1, data rate = 40sps
Uncalibrated
Unipolar Offset Error or Bipolar
Zero Error (Note 3)
PGA gain = 1, calibrated,
0.003
T
= +25°C, data rate = 10sps
A
Unipolar Offset-Error or Bipolar
Zero-Error Temperature Drift
(Note 4)
Bipolar
1
1
µV/°C
Unipolar
Uncalibrated
0.6
Gain Error (Notes 3, 5)
%FSR
PGA = 1, calibrated, data rate = 10sps
0.003
Gain-Error Temperature
Coefficient
(Notes 4, 6)
2
ppm/ °C
DC Positive Power-Supply
Rejection Ratio
PGA gain = 1, unipolar mode, measured by
PSRR
85
dB
full-scale error with AV
= 1.8V to 3.6V
DD
ADC ANALOG INPUTS (AIN1, AIN2)
DC Input Common-Mode
Rejection Ratio
CMRR
PGA gain = 1, unipolar mode
85
dB
2
_______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Normal-Mode 60Hz Rejection
Ratio
PGA gain = 1, unipolar mode, data rate =
40sps (Note 2)
100
dB
Normal-Mode 50Hz Rejection
Ratio
Data rate = 10sps or 40sps, PGA gain = 1,
unipolar mode (Note 2)
100
dB
V
Absolute Input Range
V
AV
DD
AGND
-0.05/
Gain
V
Gain
/
REF
Unipolar mode
Differential Input Range
V
-V
/
V
Gain
/
REF
REF
Bipolar mode
Gain
ADC not in measurement mode, mux
±1
±5
enabled, T ꢀ +55°C, inputs = +0.1V to
A
DC Input Current (Note 7)
nA
(AV
- 0.1V)
DD
T
A
= +85°C
Input Sampling Capacitance
Input Sampling Rate
C
5
pF
IN
f
21.94
Table 3
kHz
SAMPLE
External Source Impedance at Input
FORCE-SENSE DAC (R = 10kꢁ and C = 200pF, FBA = OUTA, unless otherwise noted)
L
L
Resolution
Guaranteed monotonic
Code 3D hex to 3FF hex
Code 3D hex to 3FF hex
Reference to code 52 hex
10
Bits
LSB
LSB
mV
Differential Nonlinearity
Integral Nonlinearity
Offset Error
DNL
INL
±1
±4
±20
Offset-Error Tempco
Gain Error
5
μV/°C
LSB
Excludes offset and voltage reference error
Excludes offset and reference drift
Switches open (Notes 7, 8)
±5
Gain-Error Tempco
5.6
ppm/°C
nA
Input Leakage Current at SWA/B
±1
±1
T
A
T
A
T
A
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
nA
V
(AV
(Note 7)
= +0.3V to
- 0.3V)
FBA
Input Leakage Current at FBA/B
±600
±400
DD
pA
nA
V
DAC Output Buffer Leakage
Current
DAC buffer disabled (Note 7)
At FBA
±75
AV
-
DD
Input Common-Mode Voltage
0
0.35
Line Regulation
AV
= +1.8V to +3.6V, T = +25°C
40
175
0.5
μV/V
μV/μA
V
DD
A
Load Regulation
I
= ±2mA, C = 1000pF
OUT L
Output Voltage Range
V
AV
DD
AGND
_______________________________________________________________________________________
3
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
Output Slew Rate
SYMBOL
CONDITIONS
52 hex to 3FF hex code swing rising or
falling, R = 10kꢁ, C = 100pF
MIN
TYP
50
MAX
UNITS
V/ms
μs
L
L
Output-Voltage Settling Time
10% to 90% rising or falling to ±0.5 LSB
65
f = 0.1Hz to
40
Referred to FBA,
10Hz
Input-Voltage Noise
excludes reference
μV
P-P
MAX1358B
f = 10Hz to
10kHz
noise
100
OUTA shorted to AGND
20
18
Output Short-Circuit Current
mA
OUTA shorted to AV
DD
Input-Output SWA/SWB
Switch Resistance
Between SW_ and OUT_, HFCLK enabled
150
ꢁ
SWA/SWB Switch Turn-On/Off
Time
HFCLK enabled
100
12
ns
μs
Power-On Time
Excluding reference
EXTERNAL REFERENCE (REF)
Input Voltage Range
Input Resistance
V
AV
V
AGND
DD
DAC on, internal REF and ADC off
2.5
Mꢁ
nA
DC Input Leakage Current
Internal REF, DAC, and ADC off (Note 7)
100
INTERNAL VOLTAGE REFERENCE (C
= 4.7μF)
REF
AV ꢀ +1.8V,
DD
1.213
1.987
1.25
1.288
2.109
T
A
= +25°C
AV ꢀ +2.2V,
DD
2.048
Reference Output Voltage
V
REF
V
T
A
= +25°C
AV ꢀ +2.7V,
DD
2.425
2.5
25
2.575
T
A
= +25°C
T
T
= -40°C to +85°C
= 0°C to +70°C
A
Output-Voltage Temperature
Coefficient (Note 7)
TC
ppm/oC
13
65
90
A
REF shorted to AGND
REF shorted to AV
mA
μA
Output Short-Circuit Current
Line Regulation
I
RSC
DD
25
μV/V
I
I
= 0 to 500μA
SOURCE
1.2
T
V
= +25°C,
A
Load Regulation
μV/μA
= 1.25V
REF
= 0 to 50μA
1.7
SINK
4
_______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
Long-Term Stability
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ppm/
1000hrs
(Note 9)
f = 0.1Hz to 10Hz, AV
150
= 3V
= 3V
50
DD
Output Noise Voltage
µV
P-P
f = 10Hz to 10kHz, AV
200
100
DD
Turn-On Settling Time
Buffer only, settle to 0.1% of final value
µs
TEMPERATURE SENSOR
Temperature Measurement
Resolution
10sps
0.11
0.5
1
°C/LSB
°C
T
T
= 0°C to +50°C
A
A
Internal voltage
reference, two-
current method
Internal Temperature-Sensor
Measurement Error (Note 10)
= -40oC to +85°C
T
T
T
= +25°C
0.5
0.5
A
A
A
External Temperature-Sensor
Measurement Error (Note 11)
= 0°C to +50°C
= -40°C to +85°C
°C
1.0
Temperature Measurement Noise
0.18
°C
RMS
Temperature Measurement
Power-Supply Rejection Ratio
0.2
°C/V
OP AMP
Input Offset Voltage
Offset-Error Tempco
V
V
= 0.5V
1
6.2
0.006
4
15
mV
µV/oC
nA
OS
CM
T
T
T
T
T
T
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
1
A
A
A
A
A
A
IN1+
IN1-
300
200
1
pA
nA
pA
nA
V
2
Input Bias Current (Note 7)
Input Offset Current
I
BIAS
0.025
20
600
400
1
I
V
= +0.3V to (AV - 0.3V) (Note 7)
OS
IN1_ DD
Input Common-Mode Voltage
Range
AV
-
DD
CMVR
0
0.35
0 ≤ V
≤ 75mV
60
75
75
CM
Common-Mode Rejection Ratio
CMRR
75mV < V
≤ AV - 0.5V, T = +25°C
60
dB
CM
DD
A
AV - 0.5V ≤ V
≤ AV - 0.35V
DD
DD
CM
_______________________________________________________________________________________
5
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
= +1.8V to +3.6V, T = +25°C
MIN
76.5
90
TYP
100
116
MAX
UNITS
dB
Power-Supply Rejection Ratio
Large-Signal Voltage Gain
PSRR
AV
DD
A
A
VOL
100mV ꢀ V
ꢀ AV - 100mV (Note 12)
DD
dB
OUT_
I
I
I
I
I
I
I
I
I
I
= 10μA
= 50μA
= 100μA
= 500μA
= 2mA
0.005
0.025
0.05
0.25
0.5
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
Sourcing
MAX1358B
Output-Voltage Drop
V
V
OUT
= 10μA
0.005
0.025
0.05
0.25
0.5
SINK
SINK
SINK
SINK
SINK
= 50μA
Sinking
= 100μA
= 500μA
= 2mA
Gain Bandwidth Product
Phase Margin
GBW
SR
Unity-gain configuration, C = 1nF
80
60
kHz
L
Unity-gain configuration, C = 1nF (Note 12)
Degrees
V/μs
L
Output Slew Rate
C = 200pF
L
0.05
50
f = 0.1Hz to 10Hz
f = 10Hz to 10kHz
Unity-gain
configuration
Input-Voltage Noise
μV
P-P
100
20
V
V
shorted to AGND
OUT_
OUT_
Output Short-Circuit Current
Power-On Time
mA
shorted to AV
18
DD
12
μs
SPDT SWITCHES (SNO_, SNC_, SCM_, HFCLK enabled)
V
V
V
= 0V
T
T
= 0°C to +50°C
= 0°C to +50°C
= -40°C to +85°C
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
= -40°C to +85°C
= 0°C to +70°C
= 0°C to +50°C
= -40°C to +85°C
45
50
SCM_
SCM_
SCM_
A
A
A
A
A
A
A
A
A
A
On-Resistance
R
ꢁ
= 0.5V
ON
= 0.5V to AV
T
T
T
T
T
T
T
T
150
±1
DD
nA
pA
V
, V
= +0.5V,
= +1.5V,
SNO_ SNC_
I
I
SNO_(OFF)
SNO_, SNC_ Off-Leakage Current
SCM_ Off-Leakage Current
+1.5V; V
SCM_
+0.5V (Note 7)
±600
±400
±2
SNC_(OFF)
V
, V
= +0.5V,
= +1.5V,
SNO_ SNC_
I
nA
nA
+1.5V; V
+0.5V (Note 7)
±1.2
±0.8
±2
SCM_(OFF)
SCM_
V
, V
= +0.5V,
SNO_ SNC_
+1.5V, or unconnected;
V
(Note 7)
SCM_ On-Leakage Current
I
SCM_(ON)
T
A
T
A
= 0°C to +70°C
= 0°C to +50°C
±1.2
±0.8
= +1.5V, +0.5V
SCM_
Input Voltage Range
Turn-On/Off Time
V
AV
V
AGND
DD
t
/t
Break-before-make
100
ns
ON OFF
6
_______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
Input Capacitance
SYMBOL
CONDITIONS
SNO_, SNC_, or SCM_ = AV
MIN
TYP
MAX
UNITS
or AGND;
DD
2.5
pF
switch connected to enabled mux input
CHARGE PUMP
Maximum Output Current
I
10
3.2
3.0
mA
V
OUT
No load
3.3
3.6
50
Output Voltage
I
I
= 10mA
OUT
= 10mA, excluding ESR of external
OUT
Output-Voltage Ripple
Load Regulation
mV
P-P
capacitor
I
= 10mA, excluding ESR of external
OUT
15
20
mV/mA
capacitor
REG Input Voltage Range
REG Input Current
Internal linear regulator disabled
Linear regulator off, charge pump off
Charge pump disabled
1.6
1.8
1.8
V
3
2
nA
V
CPOUT Input Voltage Range
CPOUT Input Leakage Current
SIGNAL-DETECT COMPARATOR
3.6
Charge pump disabled
nA
TSEL[2:0] = 0 hex
TSEL[2:0] = 4 hex
TSEL[2:0] = 5 hex
TSEL[2:0] = 6 hex
TSEL[2:0] = 7 hex
0
50
Differential Input-Detection
Threshold Voltage
mV
mV
100
150
200
Differential Input-Detection
Threshold Error
±10
Common-Mode Input Voltage
Range
V
AV
V
AGND
DD
Turn-On Time
45
μs
VOLTAGE MONITORS
DV Monitor Supply Voltage
DD
Range
For valid reset
1.4
3.6
1.95
V
V
s
Trip Threshold (DV
Falling)
1.80
1.85
1.5
DD
DV
Monitor Timeout Reset
DD
Period
HYSE bit set to logic 1
HYSE bit set to logic 0
225
40
DV
Monitor Hysteresis
mV
DD
_______________________________________________________________________________________
7
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DV
Monitor Turn-On Time
5
ms
DD
CPOUT Monitor Supply Voltage
Range
1.4
2.7
3.6
2.9
V
CPOUT Monitor Trip Threshold
CPOUT Monitor Hysteresis
2.8
35
5
V
mV
ms
V
MAX1358B
CPOUT Monitor Turn-On Time
Internal Power-On Reset Voltage
1.7
32kHz OSCILLATOR (32KIN, 32KOUT)
Clock Frequency
DV
= 2.7V
32.768
25
kHz
ppm
ms
DD
DD
Stability
DV
= 1.8V to 3.6V, excluding crystal
Oscillator Startup Time
Crystal Load Capacitance
1500
6
pF
LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K)
Output Clock Frequency
32.768
kHz
ns
Absolute Input to Output Clock
Jitter
Cycle to cycle
10% to 90%, 30pF load
5
5
Input to Output Rise/Fall Time
Input Duty Cycle
ns
%
%
40
60
Output Duty Cycle
54
HIGH-FREQUENCY CLOCK OUTPUT (CLK)
f
f
f
f
= f
4.8660 4.9152 4.9644
OUT
OUT
OUT
OUT
FLL
= f /2, power-up default
FLL
2.4330 2.4576 2.4822
MHz
FLL Output Clock Frequency
= f /4
FLL
1.2165 1.2288 1.2411
= f /8
FLL
608.25 614.4 620.54
kHz
ns
Cycle to cycle, FLL off
Cycle to cycle, FLL on
10% to 90%, 30pF load
0.1
0.5
10
Absolute Clock Jitter
Rise and Fall Time
Duty Cycle
t /t
R F
ns
f
f
= 4.9152MHz
40
45
60
55
OUT
OUT
%
= 2.4576MHz, 1.2288MHz, 614.4kHz
Uncalibrated CLK Frequency
Error
FLL calibration not performed
35
%
DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K)
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
DV
DD
0.3 x
V
IL
DV
DD
8
_______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
supply voltage
MIN
TYP
MAX
UNITS
0.7 x
DV
DD
DV
DD
UPIO_ Input High Voltage
V
V
0.7 x
CPOUT
CPOUT supply voltage
V
0.3 x
DV
supply voltage
DD
DV
DD
UPIO_ Input Low Voltage
0.3 x
CPOUT
CPOUT supply voltage
DV = 3.0V
V
Input Hysteresis
Input Current
V
200
±0.01
4
mV
nA
pF
HYS
DD
I
IN
V
V
V
= V
DGND
= V
DGND
or DV
or DV
(Note 7)
±100
IN
DD
DD
Input Capacitance
IN
IN
= DV
or V
, pullup enabled
or 0V,
±0.01
1
1
DD
CPOUT
UPIO_ Input Current
UPIO_ Pullup Current
μA
μA
V
= DV
or V
IN
DD
CPOUT
pullup disabled
V
= 0V, pullup enabled, unconnected
UPIO_ inputs are pulled up to DV
CPOUT with pullup enabled
IN
0.1
2
5
or
DD
DIGITAL OUTPUTS (DOUT, RESET, UPIO_, CLK32K, INT, CLK)
Output Low Voltage
V
I
= 1mA
0.4
V
V
OL
SINK
0.8 x
Output High Voltage
V
I
= 500μA
OH
SOURCE
DV
DD
DOUT Three-State Leakage
Current
I
L
±0.01
±1
μA
DOUT Three-State Output
Capacitance
C
4.5
pF
V
OUT
RESET Output Low Voltage
V
I
= 1mA
0.4
0.1
OL
SINK
Open-drain output, RESET deasserted
(Note 7)
RESET Output Leakage Current
μA
I
I
= 1mA, UPIO_ referenced to DV
0.4
0.4
SINK
DD
UPIO_ Output Low Voltage
UPIO_ Output High Voltage
V
V
V
OL
= 4mA, UPIO_ referenced to CPOUT
SINK
I
= 500μA, UPIO_ referenced to
0.8 x
DV
SOURCE
DV
DD
DD
V
OH
I
= 4mA, UPIO_ referenced to
V
SOURCE
CPOUT
- 0.4
CPOUT
POWER REQUIREMENT
Analog Supply Voltage Range
Digital Supply Voltage Range
AV
DV
1.8
1.8
3.6
3.6
V
V
DD
DD
_______________________________________________________________________________________
9
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +1.8V to +3.6V, V
= +1.25V, external reference, CLK32K = 32.768kHz (external clock), C
= 10µF, C
=
DD
DD
REF
REG
CPOUT
10µF, 10µF between CF+ and CF-, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Everything on,
charge pump
unloaded, no digital
pins, sinking/sourcing
current, e.g., RST,
UPIO_, and CLK32K,
max internal temp-
sensor current, clock
output buffers
AV
AV
= DV
= DV
= 3.6V
= 2.7V
1.2
2.0
DD
DD
DD
DD
I
MAX
MAX1358B
Total Supply Current
mA
1.15
1.4
1.5
unloaded, ADC at
477sps
All on except charge pump and temp
sensor, ADC at 477sps, CLK output buffer
enabled, clock output buffers unloaded
I
1.15
3.0
NORMAL
AV
AV
AV
AV
= DV
= DV
= DV
= DV
= 2.7V
= 3.6V
= 2.7V
= 3.6V
5.2
6.7
DD
DD
DD
DD
DD
DD
DD
DD
T
T
= -40°C to +85°C
= +25°C
A
Sleep-Mode Supply Current
(I + I
I
μA
μA
SLEEP
)
DVDD
AVDD
3.0
4.5
A
T
= -40°C to +85°C
= +25°C
2.5
Shutdown Supply Current
(I + I
A
A
I
All off
SHDN
)
DVDD
AVDD
T
1.2
Note 1: Devices are production tested at T = +25°C and T = +85°C. Specifications to T = -40°C are guaranteed by design.
A
A
A
Note 2: Guaranteed by design or characterization.
Note 3: The offset and gain errors are corrected by self-calibration or system calibration. For accurate calibrations, perform cali-
bration at the lowest rate. The calibration error is therefore in the order of peak-to-peak noise for the selected rate.
Note 4: Eliminate drift errors by recalibration at the new temperature.
Note 5: The gain error excludes reference error, offset error (unipolar), and zero error (bipolar).
Note 6: Gain-error drift does not include unipolar-offset drift or bipolar zero-error drift. It is effectively the drift of the part if zero-
scale error is removed.
Note 7: These specifications are obtained from characterization during design or from initial product evaluation. Not production
tested or guaranteed.
Note 8:
V
OUTA
= +0.5V or +1.5V, V
= +1.5V or +0.5V, T = 0°C to +50°C.
SWA
A
Note 9: Long-term stability is characterized using five to six parts. The bandgaps are turned on for 1000hrs at room temperature
with the parts running continuously. Daily measurements are taken and any obvious outlying data points are discarded.
Note 10: Temperature error is the difference in the calculated temperature using the internal circuit vs. measurements made using
precision external voltage and current meters. The same diode and diode equation are used for both measurements.
Note 11: All the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal) and
2) the ADC reference voltage is exactly equal to 1.25V. Any variations to this known reference characteristic and voltage
caused by temperature, loading, or power supply results in errors in the temperature measurement. The actual tempera-
ture calculation is performed externally by the µC.
Note 12: Values based on simulation results and are not production tested or guaranteed.
10 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Table 1. Output Noise (Notes 13 and 14)
OUTPUT NOISE (µV
)
RMS
RATE (sps)
GAIN = 1
1.75
GAIN = 2
GAIN = 4
1.75
GAIN = 8
1.75
1.75
2.92
10
40
2.92
2.92
2.92
3.23
3.60
3.23
3.23
3.60
3.23
3.60
50
3.60
60
56.06
102.36
587.06
951.07
56.06
102.36
587.06
951.07
56.06
102.36
587.06
951.07
56.06
102.36
587.06
951.07
200
240
400
477
Note 13: V
= +1.25V, bipolar mode, V = 1.24912V, PGA gain = 1, T = +25°C.
IN A
Note 14: Assume 3 sigma peak-to-peak variation; noise-free resolution means no code flicker at given bitsꢀ LSB.
REF
Table 2. Peak-to-Peak Resolution
PEAK-TO-PEAK RESOLUTION (BITS)
RATE (sps)
GAIN = 1
17.57
16.83
16.68
16.53
12.57
11.70
9.18
GAIN = 2
16.57
15.83
15.68
15.53
11.57
10.70
8.18
GAIN = 4
15.57
14.83
14.68
14.53
10.57
9.70
GAIN = 8
14.57
13.83
13.68
13.53
9.57
10
40
50
60
200
240
400
477
8.70
7.18
6.18
8.48
7.48
6.48
5.48
Table 3. Maximum External Source Impedance Without 16-Bit Gain Error
EXTERNAL CAPACITANCE (pF)
PARAMETER
0 (Note 15)
350
50
60
100
30
500
10
1000
4
5000
Resistance (kΩ)
1
Note 15: 2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance.
______________________________________________________________________________________ 11
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS (Figures 1 and 19)
(AV
= DV
= +1.8V to +3.6V, external V
= +1.25V, CLK32K = 32.768kHz (external clock), C = 10µF, C
REG
= 10µF,
DD
DD
REF
CPOUT
10µF between CF+ and CF-, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
MAX A
MIN
PARAMETER
SCLK Operating Frequency
SCLK Cycle Time
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
MHz
ns
f
10
SCLK
t
100
40
40
30
0
CYC
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
t
ns
CH
t
ns
CL
DS
t
ns
MAX1358B
DIN to SCLK Hold
t
t
ns
DH
SCLK Fall to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
C = 50pF, Figure 2
40
48
48
ns
DO
L
t
C = 50pF, Figure 2
ns
DV
L
t
TR
C = 50pF, Figure 2
L
ns
t
20
0
ns
CSS
CSH
t
ns
DV
Monitor Timeout Period
t
(Note 16)
1.5
1
s
DD
DSLP
Minimum pulse width required to detect a
wake-up event
Wake-Up (WU) Pulse Width
Shutdown Delay
t
μs
μs
ms
μs
WU
The delay for SHDN to go high after a valid
wake-up event
t
1
DPU
The turn-on time for the high-frequency
clock and FLL (FLLE = 1) (Note 17)
10
10
HFCLK Turn-On Time
t
DFON
If FLLE = 0, the turn-on time for the high-
frequency clock (Note 18)
The delay for CRDY to go low after the
HFCLK clock output has been enabled
(Note 19)
CRDY to INT Delay
t
7.82
ms
DFI
The delay after a shutdown command has
asserted and before HFCLK is disabled
(Note 20)
HFCLK Disable Delay
t
1.95
2.93
ms
ms
DFOF
SHDN Assertion Delay
t
(Note 21)
DPD
Note 16: The delay for the sleep voltage monitor output, RESET, to go high after V
rises above the reset threshold. This is largely
DD
driven by the startup of the 32kHz oscillator.
Note 17: FLLE is gated by an AND function with three inputs—the external RESET signal, the internal DV
monitor output, and the
going high or the external RESET going high,
DD
external SHDN signal. The time delay is timed from the internal LOV
DD
whichever happens later. HFCLK always starts in the low state.
Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT is deasserted.
Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1.
Note 20: t
Note 21: t
gives the µC time to clean up and go into sleep-override mode properly.
is greater than the HFCLK delay to clean up before losing power.
DFOF
DPD
12 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
CS
t
t
t
t
CSH
CSH
CYC
CH
t
CSS
t
CL
SCLK
DIN
t
t
DH
DS
t
t
t
TR
DV
DO
DOUT
Figure 1. Detailed Serial-Interface Timing
DV
DD
6kΩ
DOUT
DOUT
6kΩ
C
LOAD
= 50pF
C
LOAD
= 50pF
a) FOR ENABLE, HIGH IMPEDANCE
TO V AND V TO V
b) FOR ENABLE, HIGH IMPEDANCE
TO V AND V TO V
OH
OL
OH
OL
OH
OL
FOR DISABLE, V TO HIGH IMPEDANCE
FOR DISABLE, V TO HIGH IMPEDANCE
OH
OL
Figure 2. DOUT Enable and Disable Time Load Circuits
Typical Operating Characteristics
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
DV SUPPLY CURRENT
DD
SUPPLY CURRENT vs. SUPPLY VOLTAGE
vs. DV SUPPLY VOLTAGE
DD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
10.000
SLEEP MODE
ALL ON WITH ADC AT 477sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
1.000
0.100
0.010
0.001
I
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
SHUTDOWN MODE: ALL OFF
DVDD
I
AVDD
SHUTDOWN MODE
1.8
2.1
2.4
2.7
3.0
3.3
3.6
1.8
2.1
2.4
2.7
DV (V)
3.0
3.3
3.6
AV , DV (V)
DD
DD
DD
______________________________________________________________________________________ 13
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
AV SUPPLY CURRENT
DD
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
vs. AV SUPPLY VOLTAGE
DD
2.0
1.6
1.2
0.8
0.4
0
3.0
2.5
2.0
1.5
1.0
0.5
1.0
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
SHUTDOWN MODE: ALL OFF
ALL ON WITH ADC AT 512sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
0.9
0.8
0.7
0.6
0.5
MAX1358B
SLEEP MODE
DV = 3.0V
DD
DV = 3.0V
DD
SHUTDOWN MODE
DV = 1.8V
DD
DV = 1.8V
DD
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
DV SUPPLY CURRENT
DD
vs. TEMPERATURE
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
20
16
12
8
2.5
2.1
1.7
1.3
0.9
0.5
0.55
0.53
0.51
0.49
0.47
0.45
SLEEP MODE: ALL OFF EXCEPT
32kHz OSC, RTC, AND 1.8V MONITOR
ALL ON WITH ADC AT 512sps AND
MAXIMUM INTERNAL TEMP-SENSOR
CURRENT SETTING
ALL OFF
DV = 3.0V
DD
DV = 3.0V
DD
DV = 3.0V
DD
DV = 1.8V
DD
DV = 1.8V
DD
4
DV = 1.8V
DD
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
AV SUPPLY CURRENT
DD
vs. TEMPERATURE
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
0.50
2.60
2.55
2.50
2.45
2.40
2.35
2.30
ALL OFF
0.45
0.40
0.35
0.30
0.25
0.20
FLL DISABLED
FLL ENABLED
DV = 3.0V
DD
DV = 1.8V
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
14 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
INTERNAL OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
1.2502
3.0
2.5
2.0
1.5
1.0
50kI LOAD
V
= 2.50V
REF
FLL ENABLED
1.2500
1.2498
1.2496
1.2494
1.2492
V
= 2.048V
REF
V
= 1.25V
REF
FLL DISABLED
V
= 1.25V
50
REF
CLK = 2.4576MHz
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-50
150
250
350
450
550
1.8
2.1
2.4
2.7
3.0
3.3
3.6
AV , DV SUPPLY VOLTAGE (V)
OUTPUT CURRENT (µA)
DD
DD
SUPPLY VOLTAGE (V)
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
2.0496
2.0494
2.0492
2.0490
2.0488
2.0486
2.4970
2.4968
2.4966
2.4964
2.4962
2.4960
1.251
1.250
1.249
1.248
1.247
1.246
1.245
V
= 2.048V
V
= 2.5V
V
= 1.25V
REF
REF
REF
-50
50
150
250
350
450
550
-50
50
150
250
350
450
550
-40
-15
10
35
60
85
OUTPUT CURRENT (µA)
OUTPUT CURRENT (µA)
TEMPERATURE (°C)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
REFERENCE DRIFT (0˚C TO 50˚C)
2.500
2.497
2.494
2.491
2.488
2.485
2.052
2.050
2.048
2.046
2.044
2.042
V
REF
= 1.25V
BOX METHOD
V
= 2.5V
V
= 2.048V
REF
REF
-40
-15
10
35
60
85
6
11
16
21
26
-40
-15
10
35
60
85
TEMPERATURE (°C)
ABSOLUTE DRIFT (ppm/NC)
TEMPERATURE (°C)
______________________________________________________________________________________ 15
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
REFERENCE NOISE DENSITY vs.
REFERENCE VOLTAGE OUTPUT NOISE
ADC INL vs. OUTPUT CODE
FREQUENCY
(0.1Hz TO 10Hz)
MAX11358B toc19
1000
0.002
0
V
REF
= 1.25V
100
10
1
-0.002
-0.004
-0.006
-0.008
-0.010
50µV/div
AC-COUPLED
MAX1358B
V
= 2.048V
REF
UNIPOLAR MODE
GAIN = 1
60sps
10
100
1000
10,000
0
10k 20k 30k 40k 50k 60k 70k
OUTPUT CODE
1s/div
FREQUENCY (Hz)
ADC MAXIMUM INL vs.
SUPPLY VOLTAGE
ADC MAXIMUM INL vs.
SUPPLY VOLTAGE
ADC INL vs. OUTPUT CODE
-0.0040
-0.0044
-0.0048
-0.0052
-0.0056
-0.0060
-0.0025
-0.0024
-0.0023
-0.0022
-0.0021
-0.0020
0.005
0.004
0.003
0.002
0.001
0
V
= 2.048V
UNIPOLAR MODE
GAIN = 1
REF
AV = DV = 1.8V
DD
DD
V
REF
= 1.25V
BIPOLAR MODE
GAIN = 1
60sps
60sps
-0.001
-0.002
-0.003
-0.004
-0.005
V
= 1.25V
BIPOLAR MODE
GAIN = 1
REF
60sps
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
SUPPLY VOLTAGE (V)
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
0
10k 20k 30k 40k 50k 60k 70k
OUTPUT CODE
ADC MAXIMUM INL vs. TEMPERATURE
ADC MAXIMUM INL vs. TEMPERATURE
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
0
-0.001
-0.002
-0.003
-0.004
-0.005
-0.006
-0.007
V
= 2.048V
REF
UNIPOLAR MODE
GAIN = 1
60sps
V
= 1.25V
REF
BIPOLAR MODE
GAIN = 1
60sps
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (NC)
TEMPERATURE (NC)
16 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
ADC MAXIMUM INL vs.
COMMON-MODE INPUT VOLTAGE
ADC MAXIMUM vs.
OUTPUT DATA RATE
ADC MAXIMUM INL vs. PGA GAIN
0.010
0
0.030
0.025
0.020
0.015
0.010
0.005
0
AV = DV = 1.8V
AV = DV = 1.8V
V
= 1.25V
REF
BIPOLAR MODE
GAIN = 1
DD
DD
DD
DD
-0.0005
-0.0010
-0.0015
-0.0020
-0.0025
-0.0030
-0.0035
-0.0040
-0.0045
-0.0050
V
= 1.25V
BIPOLAR MODE
GAIN = 1
V
= 1.25V
REF
REF
BIPOLAR MODE
60sps
0.008
0.006
0.004
0.002
0
60sps
0
2
4
6
8
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
COMMON-MODE VOLTAGE (V)
0
100
200
300
400
500
PGA GAIN
DATA RATE (sps)
ADC OFFSET ERROR vs.
TEMPERATURE
ADC GAIN ERROR vs.
TEMPERATURE
ADC OFFSET ERROR vs.
SUPPLY VOLTAGE
0.0020
0.0015
0.0010
0.0005
0
0.006
0.005
0.004
0.003
0.002
0.001
0
0.0035
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
V
= 2.048V
V
= 2.048V
REF
REF
V
= 1.25V
REF
UNIPOLAR MODE
GAIN = 1
60sps
UNIPOLAR MODE
GAIN = 1
60sps
UNIPOLAR MODE
GAIN = 1
60sps
-0.0005
-0.0010
-0.0005
-40
-15
10
35
60
85
-40
-15
10
35
60
85
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (NC)
TEMPERATURE (NC)
ADC MUX INPUT DC CURRENT vs.
TEMPERATURE
ADC GAIN ERROR vs.
SUPPLY VOLTAGE
1000.00
0.0040
V
= 1.25V
REF
0.0035
0.0030
0.0025
0.0020
0.0015
0.0010
0.0005
0
UNIPOLAR MODE
GAIN = 1
60sps
100.00
10.00
1.000
0.100
0.010
0.001
ADC CONVERTING
ADC OFF
AIN1 = AV /2
DD
MUX+ = AIN1
MUX- = AGND
-40
-15
10
35
60
85
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (NC)
______________________________________________________________________________________ 17
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
FB LEAKAGE CURRENT
vs. INPUT VOLTAGE
AIN_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
SW_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
0.4
0.3
0.2
0.1
0
0.4
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
OUT_ = AV /2
DD
T
A
= +85°C
0.3
0.2
0.1
0
T
A
= +85°C
T
A
= +55°C
T
A
= +85°C
T
A
= +55°C
MAX1358B
T
= +55°C
A
T
= +25°C
A
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
T
= +25°C
A
T
A
= +25°C
-0.5
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
V
FB
V
SW_
AIN_
SNC_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
SCM_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
SNO_ LEAKAGE CURRENT
vs. INPUT VOLTAGE
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
SCM_ = AV /2
SN0_ = SNC_ = AV /2
DD
SCM_ = AV /2
DD
DD
T
A
= +85°C
T
= +85°C
T
= +85°C
A
A
T
A
= +55°C
T = +55°C
A
T
A
= +55°C
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
-0.15
-0.20
T
A
= +25°C
T = +25°C
A
T
A
= +25°C
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
(V)
V
SCM_
V
(V)
SNC_
SNO_
IN1- LEAKAGE CURRENT
vs. INPUT VOLTAGE
DAC INL vs. OUTPUT CODE
0.5
0.20
0.15
0.10
0.05
0
AV = 1.8V
DD
0.4
0.3
0.2
0.1
0
T
A
= +85NC
V
= 1.25V
REF
T = +55NC
A
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
T = +25NC
A
0
100 200 300 400 500 600 700 800 900 10001100
OUTPUT CODE
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
V
IN1-
18 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
DAC INL vs. OUTPUT CODE
DAC DNL vs. OUTPUT CODE
DAC DNL vs. OUTPUT CODE
0.5
0.4
0.5
0.4
0.5
0.4
AV = 1.8V
V
= 2.048V
DD
REF
V
= 2.048V
REF
V
REF
= 1.25V
0.3
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
DAC FB_ INPUT BIAS CURRENT
vs. TEMPERATURE
DAC OUTPUT VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
DAC OUTPUT VOLTAGE
vs. TEMPERATURE
250
200
150
100
50
0.62420
0.62415
0.62410
0.62405
0.62400
0.62395
0.62390
0.62385
0.62380
0.6250
0.6246
0.6242
0.6238
0.6234
0.6230
FB_ = AV
DD
FB_ = 0
V
= 1.25V EXTERNAL
CODE = 0x200
= 10kI
V
= 1.25V
REF
REF
CODE = 0x200
R
0
R
= 10kI
LOAD
LOAD
AV = DV = 1.8V
DD
DD
-50
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
AVDD (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
DAC GAIN ERROR vs.TEMPERATURE
DAC OUTPUT NOISE (0.1Hz TO 10Hz)
MAX11358B toc50
0.5
0.4
0.3
0.2
0.1
0
V
= 1.25V EXTERNAL
REF
REF = 1.25V
AV = DV = 1.8V
DD
DD
AV = DV = 1.8V
DD
DD
CODE = 0x3FF
20µV/div
AC-COUPLED
V
= 2.5V EXTERNAL
REF
-0.1
-0.2
-0.3
AV = DV = 3.0V
DD
DD
OFFSET MEASURED AT CODE 0x52
-15 10 35
TEMPERATURE (°C)
-40
60
85
1s/div
______________________________________________________________________________________ 19
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
DD
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
A
CPOUT
DD
REF
DAC OUTPUT-NOISE DENSITY
vs. FREQUENCY
DAC LARGE-SIGNAL STEP RESPONSE
(0x052 TO 0x3FF)
MAX11358B toc52
1000
100
10
V
= 1.25V
REF
OUT_ = FB_
AV = DV = 1.8V
DD
DD
SCLK
2V/div
CODE = 3FF
MAX1358B
OUTA
500mV/div
0V
1
0.01
0.10
1.00
FREQUENCY (kHz)
10.00
100.00
10µs/div
DAC LARGE-SIGNAL STEP RESPONSE
OP-AMP INPUT OFFSET VOLTAGE
vs. TEMPERATURE
OP-AMP INPUT OFFSET HISTOGRAM
(0x3FF to 0x052)
MAX11358B toc53
35
30
25
20
15
10
5
0
V
= 0.5V
CM
OUT_ = FB_
-0.1
SCLK
-0.2
-0.3
-0.4
-0.5
OUTA
500mV/div
0V
0
10µs/div
-40
-15
10
35
60
85
TEMPERATURE (°C)
OFFSET (mV)
OP-AMP OUTPUT VOLTAGE
vs. LOAD CURRENT
OP-AMP OUTPUT VOLTAGE
vs. LOAD CURRENT
0.89970
0.89968
0.89966
0.89964
0.89962
0.89960
0.89958
0.89956
0.89954
0.89952
0.89950
1.49970
1.49965
1.49960
1.49955
1.49950
1.49945
1.49940
UNITY GAIN
= 0.9V
UNITY GAIN
= 1.5V
V
IN
V
IN
AV = DV = 1.8V
DD
DD
AV = DV = 3.0V
DD
DD
-2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0
-2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0
LOAD CURRENT (mA)
LOAD CURRENT (mA)
20 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
OP-AMP OUTPUT VOLTAGE
vs. TEMPERATURE
OP-AMP OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
OP-AMP OUTPUT NOISE (0.1Hz TO 10Hz)
MAX11358B toc60
0.8987
0.50000
UNITY GAIN
UNITY GAIN
AV = DV = 1.8V
UNITY GAIN
0.49995
V
R
= 0.5V
IN
LOAD
DD
DD
0.8986
0.8985
0.8984
0.8983
0.8982
0.8981
V
IN1+
= 0.5V
= 10kI
V
IN+
R
= AV /2
DD
AV = DV = 1.8V
DD
DD
0.49990
0.49985
0.49980
0.49975
0.49970
0.49965
0.49960
= 10kI
LOAD
20µV/div
AC-COUPLED
-40
-15
10
35
60
85
1s/div
1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
CLOSED-LOOP OP-AMP GAIN AND PHASE
OP-AMP OUTPUT-NOISE DENSITY
vs. FREQUENCY
OP-AMP UNITY-GAIN INPUT RANGE
vs. FREQUENCY
MAX11358B toc63
80
60
180
135
90
10
8
1000
100
10
AV = DV = 3.6V
UNITY GAIN
NO LOAD
DD
DD
V
= 0.5V
IN+
AV = DV = 1.8V
UNITY GAIN
DD
DD
6
GAIN
40
4
20
45
2
0
0
0
-2
-4
-6
-8
-10
-20
-40
-60
-80
-45
-90
-135
-180
PHASE
CLOSED-LOOP GAIN = 1000
R
C
= 10kI
= 200pF
LOAD
LOAD
1
10
100
1k
10k
100k
1M
0
0.6
1.2
1.8
(V)
2.4
3.0
3.6
0.01
0.10
1.00
FREQUENCY (kHz)
10.00
100.00
FREQUENCY (Hz)
V
IN
SPDT ON-RESISTANCE
vs. SCM_ VOLTAGE
SPST ON-RESISTANCE vs. SW_ VOLTAGE
70
65
60
55
50
45
40
35
45
40
35
30
25
20
I
= 1mA
SW_
I
= 1mA
SCM_
AV = 3V
DD
AV = 3V
DD
AV = 1.8V
DD
AV = 1.8V
DD
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
V
(V)
SW_
SCM_
______________________________________________________________________________________ 21
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
SPDT ON-RESISTANCE
vs. TEMPERATURE
SPDT ON-RESISTANCE
vs. TEMPERATURE
SPST LEAKAGE CURRENT
vs. TEMPERATURE
70
60
50
40
30
50
40
30
20
10
1.000
0.100
0.010
0.001
V
I
= AV
DD
= 1mA
V
I
= AV
SCM_ DD
= 1mA
SCM_
V
= AV
DD
SCM_
SCM_
IN
MAX1358B
AV = DV = 3.0V
DD
DD
AV = DV = 3.0V
DD
DD
AV = DV = 1.8V
DD
DD
AV = DV = 1.8V
DD
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SPDT SWITCHING TIME
vs. SUPPLY VOLTAGE
SPST SWITCHING TIME
vs. SUPPLY VOLTAGE
SPDT/SPST SWITCHING TIME
vs. TEMPERATURE
70
60
50
40
30
20
70
60
50
40
30
20
50
40
30
20
10
0
R
C
= 1kI
LOAD
= 35pF
LOAD
t
ON
t
ON
t
ON
t
OFF
t
OFF
t
OFF
1.8
2.1
2.4
2.7
3.0
3.3
3.6
1.8
2.1
2.4
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
AV , DV (V)
AV , DV (V)
TEMPERATURE (°C)
DD
DD
DD
DD
INTERNAL TEMPERATURE SENSOR ERROR
vs. AMBIENT TEMPERATURE
INTERNAL TEMPERATURE SENSOR ERROR
vs. REFERENCE VOLTAGE
2.0
1.5
1.0
0.5
0
15
10
5
V
= 1.250V
T
A
= +85°C
REF
T
= +27°C
A
0
T
A
= -40°C
-0.5
-1.0
-1.5
-2.0
-5
-10
-15
-40
-15
10
35
60
85
1.21
1.23
1.25
1.27
1.29
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
22 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Typical Operating Characteristics (continued)
(DV
= AV = 1.8V, V
= +1.25V, C
= 10µF, T = +25°C, unless otherwise noted.)
DD
DD
A
REF
CPOUT
CHARGE-PUMP OUTPUT VOLTAGE
VOLTAGE SUPERVISOR THRESHOLD
vs. TEMPERATURE
CHARGE-PUMP OUTPUT VOLTAGE
vs. TEMPERATURE
vs. OUTPUT CURRENT
3.5
3.0
2.7
2.4
2.1
1.8
1.5
3.30
3.26
3.22
3.18
3.14
3.10
AV = DV = 1.8V
FALLING
DD
DD
AV = DV = 1.8V
DD
DD
I
= 10mA
LOAD
3.4
3.3
3.2
3.1
3.0
CPOUT SUPERVISOR
DV SUPERVISOR
DD
0
2
4
6
8
10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
OUTPUT CURRENT (mA)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHARGE-PUMP OUTPUT-VOLTAGE
RIPPLE vs. OUTPUT CURRENT
CHARGE-PUMP OUTPUT RESISTANCE
vs. CAPACITANCE
50
100
AV = DV = 1.8V
AV = DV = 1.8V
DD
DD
DD
DD
I
= 10mA
OUT
40
30
20
10
0
80
60
40
20
0
0
2
4
6
8
10
0
5
10
15
20
25
OUTPUT CURRENT (mA)
CAPACITANCE (µF)
______________________________________________________________________________________ 23
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Pin Description
PIN
1
NAME
CLK
FUNCTION
Clock Output. Default is 2.457MHz output clock for the μC.
2
UPIO2
UPIO3
UPIO4
User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality.
User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality.
User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality.
3
4
Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when CS is high, when
UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1.
5
DOUT
6
7
SCLK
DIN
Serial-Clock Input. Clocks data in and out of the serial interface.
Serial-Data Input. Data is clocked in on SCLK’s rising edge.
MAX1358B
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high
impedance. High impedance when CS is high; when UPIO/SPI pass-through mode is enabled, DOUT
mirrors the state of UPIO1.
8
9
CS
INT
Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events.
32kHz Clock Input/Output. Outputs 32kHz clock for the μC. Can be programmed as an input by enabling
the IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the
internal 32kHz clock derived from the 32kHz crystal.
10
CLK32K
Active-Low, Open-Drain Reset Output. Remains low while DV
is below the 1.8V voltage threshold and
DD
11
RESET
stays low for a timeout period (t ) after DV
DSLP
rises above the 1.8V threshold. RESET also pulses low
DD
when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes.
12
13
14
15
16
17
18
19
20
21
22
32KOUT 32kHz Crystal Output. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
32KIN
SNO1
SCM1
SNC1
SNO2
SCM2
SNC2
OUT1
IN1-
32kHz Crystal Input. Connect an external 32kHz watch crystal between 32KIN and 32KOUT.
Analog Switch 1 Normally Open Terminal. Analog input to mux.
Analog Switch 1 Common Terminal. Analog input to mux.
Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Open Terminal. Analog input to mux.
Analog Switch 2 Common Terminal. Analog input to mux (open on POR).
Analog Switch 2 Normally Closed Terminal. Analog input to mux.
Amplifier 1 Output. Analog input to mux.
Amplifier 1 Inverting Input. Analog input to mux.
IN1+
Amplifier 1 Noninverting Input
24 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Pin Description (continued)
PIN
NAME
FUNCTION
23
24
25
26
SWA
FBA
DACA SPST Shunt Switch Input. Connects to OUTA through an SPST switch.
DACA Force-Sense Feedback Input. Analog input to mux.
DACA Force-Sense Output. Analog input to mux.
Analog Ground
OUTA
AGND
Analog Supply Voltage. Also ADC reference voltage during AV
measurement. Bypass to AGND with
DD
27
AV
DD
10μF and 0.1μF capacitors in parallel as close to the pin as possible.
DACB SPST Shunt Switch Input. Connects to OUTB through an SPST switch.
DACB Force-Sense Feedback Input. Analog input to mux.
Force-Sense DACB Ouput. Analog input to mux.
28
29
30
SWB
FBB
OUTB
Analog Input 2. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.
31
32
33
34
AIN2
AIN1
REF
Analog Input 1. Analog input to mux. Inputs have internal programmable current source for external
temperature measurement.
Reference Input/Output. Output of the reference buffer amplifier or external reference input. Disabled at
power-up to allow external reference. Reference voltage for ADC and DACs.
Linear Voltage-Regulator Output. Charge-pump-doubler input voltage. Bypass REG with a 10μF capacitor
to DGND for charge-pump regulation.
REG
35
36
CF-
Charge-Pump Flying Capacitor Terminals. Connect an external 10μF (typ) capacitor between CF+ and CF-.
Charge-Pump Output. Connect an external 10μF (typ) reservoir capacitor between CPOUT and DGND. There is
CF+
a low threshold diode between DV and CPOUT. When the charge pump is disabled, CPOUT is pulled up
DD
37
CPOUT
within 300mV (typ) of DV
.
DD
Digital Supply Voltage. Bypass to DGND with 10μF and 0.1μF capacitors in parallel as close to the pin as
possible.
38
DV
DD
39
40
—
DGND
UPIO1
EP
Digital Ground. Also ground for cascaded linear voltage regulator and charge-pump doubler.
User-Programmable Input/Output 1. See the UPIO1_CTRL Register for functionality.
Exposed Pad. Leave unconnected or connect to AGND.
______________________________________________________________________________________ 25
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
The DAS directly interfaces to various sensor outputs
Detailed Description
and, once configured, provides the stimulus, signal con-
The MAX11358B DAS features a multiplexed differential
ditioning, and data conversion, as well as µP support.
16-bit ADC, 10-bit force-sense DACs, an RTC with an
See the Applications section for sample MAX11358B
alarm, a selectable bandgap voltage reference, a signal-
applications.
detect comparator, 1.8V and 2.7V voltage monitors, and
wake-up control circuitry, all controlled by a 4-wire serial
interface (see Figure 3 for the functional diagram).
The 16-bit ADC features programmable continuous con-
version rates as shown in Table 4, and gains of 1, 2, 4,
and 8 (Table 5) to suit applications with different power
MAX1358B
INT
CLK32K
32KOUT
CLK
AV
DD
32KIN
DV
DD
4.9152MHz HF
OSCILLATOR
AND FLL
CLK32K
INPUT/OUTPUT
CONTROL
M32K
CS
SCLK
DIN
32.768kHz
UPIO1
INTERRUPT
16
OSCILLATOR
UPIO2
UPIO3
UPIO4
SERIAL
INTERFACE
UPIO
HFCLK
4
4
32K
UPR<4:1>
CRDY
CONTROL
LOGIC
PWM
UPF<4:1>
DOUT
STATUS
RTC AND
ALARM
ALD
SDC
ADD
ADOU
WATCHDOG
TIMER
DV (1.8V)
DD
VOLTAGE
MONITOR
RESET
LDVD
LCPD
WDTO
AIN1
AIN2
TEMP
PROG
CURRENT
SOURCE
CPOUT (2.7V)
VOLTAGE
MONITOR
CPOUT
CF+
CF-
TEMP+
TEMP-
CHARGE-
PUMP
DOUBLER
DV
M32K
DD
SENSOR
MAX11358B
LINEAR 1.65V
VOLTAGE
REGULATOR
REG
AIN1
SNO1
FBA
SCM1
FBB
SNC1
AIN1
AIN2
M32K
CMP
PROG. V
OS
PGA
1.25V BANDGAP
REF
10:1
MUX
POS
A = 1, 1.6384, 2 V/V
V
IN1-
TEMP+
REF
SNO1
SNC1
SCM1
REF
REF
10-BIT DAC
AGND
IN+
OUTA
SWA
FBA
BUF
HFCLK
16-BIT ADC
IN-
PGA
TEMP-
SNO2
OUTA
SCM2
OUTB
SNC2
OUT1
AIN2
SPDT1
A = 1, 2, 4, 8 V/V
POLARITY
FLIPPER
V
REF
SNO2
SNC2
SCM2
10:1
MUX
NEG
10-BIT DAC
OUTB
BUF
OP1
SWB
FBB
REF
SPDT2
AGND
IN1+
IN1-
OUT1
DGND
AGND
Figure 3. Functional Diagram
26 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
and dynamic range constraints. The force-sense DAC
provides 10-bit resolution for precise sensor applica-
tions. The ADC and DACs both utilize a low-drift 1.25V
internal bandgap reference for conversions and full-
scale range setting. The RTC has a 138-year range and
provides an alarm function that can be used to wake up
the system or cause an interrupt at a predefined time.
ADC Modulator
The MAX11358B performs analog-to-digital conversions
using a single-bit, 3rd-order, switched-capacitor sigma-
delta modulator. The sigma-delta modulation converts
the input signal into a digital pulse train whose average
duty cycle represents the digitized signal information.
The pulse train is then processed by a digital decimation
filter. The modulator provides 2nd-order frequency shap-
ing of the quantization noise resulting from the single-bit
quantizer. The modulator is fully differential for maximum
signal-to-noise ratio and minimum susceptibility to
power-supply noise.
The power-supply voltage monitor detects when DV
DD
falls below a trip threshold voltage of +1.8V and asserts
RESET. The MAX11358B uses a 4-wire serial interface
to communicate directly among SPI, QSPI, or
MICROWIRE devices for system configuration and
readback functions.
Signal-Detect Comparator
INT asserts (and remains asserted) within 30µs when
the differential voltage on the selected analog inputs
exceeds the signal-detect comparator trip threshold.
The signal-detect comparatorꢀs differential input trip
threshold (i.e., offset) is user selectable and can be pro-
grammed to the following values: 0mV, 50mV, 100mV,
150mV, or 200mV.
Analog-to-Digital Converter (ADC)
The MAX11358B includes a sigma-delta ADC with pro-
grammable conversion rate, a PGA, and a dual 10:1
input mux. When performing continuous conversions at
10sps or single conversions at the 40sps setting (effec-
tively 10sps due to four sample sigma-delta settling),
the ADC has 16-bit noise-free resolution. The noise-free
resolution drops to 10 bits at the maximum sampling
rate of 477sps. Differential inputs support unipolar
Analog Inputs
The ADC provides two external analog inputs: AIN1
and AIN2. The rail-to-rail inputs accept differential or
single-ended voltages, or external temperature-sensing
diodes. The unused op amps, switches, or DAC inputs
and output pins can also be used as rail-to-rail analog
inputs if the associated function is disabled.
(between 0 and V
) and bipolar (between
V
)
REF
REF
modes of operation. Note: Avoid combinations of input
signal and PGA gains that exceed the reference range
at the ADC input. The ADOU bit in the STATUS register
indicates if the ADC has overranged or underranged.
Zero-scale and full-scale calibrations remove offset and
gain errors. Direct access to gain and zero-scale cali-
bration registers allows system-level offset and gain cal-
ibration. The zero-scale adjustment register allows
intentional positive offset skewing to preserve unipolar-
mode resolution for signals that have a slight negative
offset (i.e., unipolar clipping near zero can be removed).
Perform ADC calibration whenever the ADC configura-
Analog Input Protection
Internal protection diodes clamp the analog inputs to
AV
and AGND and allow the channel input to swing
DD
from (AGND - 0.3V) to (AV
+ 0.3V). For accurate
DD
conversions near full scale, the inputs must not exceed
AV by more than 50mV or be lower than AGND by
DD
50mV. If the inputs exceed (AGND - 0.3V) to (AV
0.3V), limit the current to 50mA.
+
DD
tion, temperature, or AV
changes. The ADC-done sta-
DD
tus can be programmed to provide an interrupt on INT
or on any UPIO_.
Analog Mux
The MAX11358B includes a dual 10:1 mux for the positive
and negative inputs of the ADC. Figure 3 illustrates which
signals are present at the inputs of each mux for the
MAX11358B. The MUXP[3:0] and MUXN[3:0] bits of the
MUX register select the input to the ADC and the signal-
detect comparator (Tables 8 and 9). See the MUX register
description in the Register Definitions section for multi-
plexer functionality. The POL bit of the ADC register
swaps the polarity of mux output signals to the ADC.
PGA Gain
An integrated PGA provides four selectable gains (+1V/V,
+2V/V, +4V/V, and +8V/V) to maximize the dynamic
range of the ADC. Bits GAIN1 and GAIN0 set the gain
(see the ADC Register for more information). The PGA
gain is implemented in the digital filter of the ADC.
______________________________________________________________________________________ 27
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Digital Filtering
The MAX11358B contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a sinc4 (sinx/x)4 response. The sinc4 filter has a
settling time of four output data periods (4 x 200ms).
Force-Sense DAC
The MAX11358B incorporates two 10-bit force-sensing
DACs. The DACs reference voltage sets the full-scale
range. Program the DACA_OP register using the serial
interface to set the output voltages of the DAC at OUTA.
Connecting resistors in a voltage-divider configuration
between OUTA, FBA, and GND sets a different closed-
loop gain for the output amplifier (see the Applications
Information section).
The MAX11358B has 25% overrange capability built into
the modulator and digital filter:
4
⎡
⎢
⎢
⎢
⎢
⎤
⎥
⎥
⎥
⎥
⎛
⎞
f
SIN Nπ
⎜
⎟
The DAC output amplifier typically settles to 0.5 LSB
from a full-scale transition within 65µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ could degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
f
⎝
⎛
⎠
1
N
m
H(f) =
⎞
f
MAX1358B
SIN
π
⎜
⎟
f
⎢
⎣
⎥
⎦
⎝
⎠
m
Figure 4 shows the filter frequency response. The sinc4
characteristic -3dB cutoff frequency is 0.228 times the
first notch frequency.
The MAX11358B features a software-programmable
shutdown mode for the DAC. Power down DACA or
DACB independently or simultaneously by clearing the
DAE and DBE bits (see the DACA_OP Register and
DACB_OP Register sections). DAC output OUTA and
OUTB go high impedance when powered down. The
DACs are normally powered down at power-on reset.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filterꢀs fre-
quency response. The notches of the sinc4 filter are
repeated at multiples of the first notch frequency. The
sinc4 filter provides an attenuation of better than 100dB
at these notches. For example, 50Hz is equal to five
times the first notch frequency and 60Hz is equal to six
times the first notch frequency.
Charge Pump
The charge pump provides > 3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DV . See Figures 5 and 6 for block diagrams of
DD
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
0
-40
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (f
=
CLK
= 5Ω), and
-80
32.768kHz/2), switch resistances (R
SWITCH
the external capacitors (10µF) along with their respec-
tive ESRs, as shown below.
-120
-160
-200
V
= I
R
DROOP
OUT OUT
1
R
=
+ 2R
+ 4ESR
+ ESR
C
CPOUT
OUT
SWITCH
C
F
f
C
F
CLK
0
20
40
60
80
100
120
I
OUT
V
=
+ 2I
ESR
RIPPLE
OUT
C
FREQUENCY (Hz)
CPOUT
f
C
CLK CPOUT
Figure 4. Filter Frequency Response
28 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
DV
DD
LDOE
CPE
CPOUT
1.22V
OP
NONOVERLAP
CLOCK GENERATOR
M32K
1.65V
REG
CF+
CF-
REG
LDOE
CHARGE-PUMP DOUBLER
LINEAR 1.65V VOLTAGE REGULATOR
Figure 6. Charge-Pump Block Diagram
Figure 5. Linear-Regulator Block Diagram
set to flag the condition. The CPOUT monitor output
can also be mapped to the interrupt generator and out-
put on INT. The CPOUT monitor can be used as a 3V
Voltage Supervisors
The MAX11358B provides voltage supervisors to monitor
DV
DV
and CPOUT. The first supervisor monitors the
supply voltage. RESET asserts and sets the corre-
DD
DD
AV
monitor in applications where the charge pump is
DD
disabled and CPOUT is connected to AV . AV
sponding LDVD status bit when DV
falls below the
supply voltage
DD
DD
DD
must be greater or equal to DV
when CPOUT is used
1.8V threshold voltage. When the DV
DD
DD
to monitor AV
See Figure 8 for a block diagram of the
rises above the threshold during power-up, RESET
deasserts after a nominal 1.5s timeout period to give the
crystal oscillator time to stabilize. Set the threshold hys-
teresis using the HYSE bit of the PS_VMONS register.
See the PS_VMONS Register section for configuring hys-
DD.
CPOUT voltage supervisor.
Interrupt Generator (INT)
The interrupt generator provides an interrupt to an
external µC. The source of the interrupt is generated by
the status register and can be masked and unmasked
through the IMSK register. CRDY is unmasked by
default, and INT is active-high at power-on reset. INT is
programmable as active-high and active-low. Possible
sources include a rising or falling edge of UPIO_, an
RTC alarm, an ADC conversion completion, or the volt-
age-supervisor outputs. The interrupt causes INT to
assert when configured as an interrupt output.
teresis. There is no separate voltage monitor for AV
,
DD
monitor in
but the analog supply is covered by the DV
DD
many applications where DV
and AV
are externally
DD
DD
connected together. Multiple supply applications where
AV and DV are not connected together require a
DD
DD
separate external voltage monitor for AV . See Figure 7
DD
for a block diagram of the DV voltage supervisor.
DD
The second voltage monitor tracks the charge-pump
output voltage, CPOUT. If CPOUT falls below the 2.7V
threshold, a corresponding register status bit (LCPD) is
______________________________________________________________________________________ 29
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
WDTO
DV
DD
HYSE
POR
RSTE
RESET
LSDE
CMP
1.8VTH
2.0VTH
ANALOG
2:1 MUX
CONTROL
LOGIC
1.25V
MAX1358B
LDVD
LSDE
DV (1.8V) VOLTAGE MONITOR
DD
Figure 7. DV
Voltage-Supervisor Block Diagram
DD
as the C-002RX32-E from Epson Crystal. Using a crys-
tal with a C that is larger than the load capacitance of
L
CPOUT
the oscillator circuit causes the oscillator to run faster
than the specified nominal frequency of the crystal or to
not start up. See Figures 9 and 10 for block diagrams
of the crystal oscillator and the CLK32K I/O.
CPDE
2.7VTH
LCPD
CMP
Real-Time Clock (RTC)
The integrated RTC provides the current time information
from a 32-bit counter and subsecond counts from an
8-bit ripple counter. An internally generated reference
clock of 256Hz (derived from the 32.768kHz crystal) dri-
ves the 8-bit subsecond counter. An overflow of the 8-bit
subsecond counter inputs a 1Hz clock to increment the
32-bit second counter. The RTC 32-bit second counter is
translatable to calendar format with firmware. All 40 bits
(32-bit second counter and 8-bit subsecond counter)
must be clocked in or out for valid data. The RTC and
the 32.768kHz crystal oscillator consume less than 1µA
when the rest of the device is powered down.
1.25V
CPDE
CPOUT (2.7V) VOLTAGE MONITOR
Figure 8. CPOUT Voltage-Supervisor Block Diagram
Crystal Oscillator
The on-chip oscillator requires an external crystal (or
resonator) connected between 32KIN and 32KOUT
with a 32.768kHz operating frequency. This oscillator is
used for the RTC, alarm, PWM, watchdog, charge
pump, and FLL. In any crystal-based oscillator circuit,
the oscillator frequency is sensitive to the capacitive
Time-of-Day Alarm
Program the AL_DAY register with a 20-bit value, which
corresponds to a time 1s to 12 days later than the cur-
rent time with a 1s resolution. The alarm status bit, ALD,
asserts when the 20 bits of the AL_DAY register match-
es the 20 LSBs of the 32-bit second counter. The ADE
bit automatically clears when the time-of-day alarm
trips. The time-of-day alarm causes the device to exit
sleep mode.
load (C ). C is the capacitance that the crystal needs
L
L
from the oscillator circuit and not the capacitance of the
crystal. The input capacitance across 32KIN and
32KOUT is 6pF. Choose a crystal with a 32.768kHz
oscillation frequency and a 6pF capacitive load such
30 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
locked to the 32.768kHz reference. If the FLL is dis-
abled, the high-frequency clock is free-running. At
power-up, the CLK pin defaults to a 2.4576MHz clock
output, which is compatible with most µCs. See Figure
12 for a block diagram of the high-frequency clock.
Watchdog
Enable the watchdog timer by writing a 1 to the WDE
bit in the CLK_CTRL register. After enabling the watch-
dog timer, the device asserts RESET for 250ms, if the
watchdog address register is not written every 500ms.
Due to the asynchronous nature of the watchdog timer,
the watchdog timeout period varies between 500ms
and 750ms. Write a 0 to the WDE bit to disable the
watchdog timer. See Figure 11 for a block diagram of
the watchdog timer.
User-Programmable I/Os
The MAX11358B provides four digital programmable
I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs
or outputs using the UPIO control register. Configure
the internal pullups using the UPIO setup register, if
required. At power-up, the UPIOs are internally pulled
up to DV . UPIO_ outputs can be referenced to DV
High-Frequency Clock
An internal oscillator and an FLL are used to generate a
4.9152MHz 1% high-frequency clock. This clock and
derivatives are used internally by the ADC, analog
switches, and PWM. This clock signal outputs to CLK.
When the FLL is enabled, the high- frequency clock is
DD
DD
or CPOUT. See the UPIO__CTRL Register and
UPIO_SPI Register sections for more details on config-
uring the UPIO_ pins.
OSCE
32K
32KOUT
OSCE
CK32E
IO32E
IO32E
32kHz
32K
OSCILLATOR
0
IO32E
2:1
MUX
M32K
32KIN
CLK32K
1
32.768kHz OSCILLATOR
CLK32K I/O CONTROL
Figure 9. 32kHz Crystal-Oscillator Block Diagram
Figure 10. CLK32K I/O Block Diagram
POR PULSES HIGH DURING POWER-UP.
WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE.
WDTO
D
Q
Q
D
Q
Q
4Hz
CK
32K
DIVIDE-
BY-8192
CK
WDE
R
R
POR
WDW
WATCHDOG TIMER
Figure 11. Watchdog Timer Block Diagram
______________________________________________________________________________________ 31
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
32.768kHz
CKSEL2
CKSEL<1:0>
CLKE
HFCE
0
FLLE
2:1
MUX
1, 2, 4, 8
DIVIDER
CLK
FREQ
ERROR
M32K
TUNE<8:0> DIGITALLY
CONTROLLED
FREQUENCY
COMPARE
FREQUENCY
INTEGRATOR
1
OSCILLATOR
4.9152MHz
HFCLK
CRDY
MAX1358B
4.9152MHz HF OSCILLATOR AND FLL
Figure 12. High-Frequency Clock and FLL Block Diagram
Program each UPIO1–UPIO4 as one of the following:
• General-purpose input
PROGRAMMABLE CURRENT SOURCE
• Power-mode control
• Analog switch (SPST) and SPDT control input
• ADC data-ready output
• General-purpose output
• PWM output
CURRENT
SOURCE
IVAL<1:0>
1:3
DEMUX
IMUX<1:0>
• Alarm output
AIN1
AIN2
AIN1
AIN2
• SPI pass-through
Internal and External (Remote)
Temperature Sensors
An internal transistor or a remote transistor (or diode) is
used with the ADC and a programmable current source
to measure the ambient temperature. Depending on the
method, either two or four currents are passed through
the PN junction. The voltage across the PN junction is
measured at each current. For each current, the voltage
across a series resistor is also measured. Measuring the
voltage across the resistor allows the user to determine
the precise current ratios. A microcontroller can then
use the diode equation to calculate the temperature.
The four-current method eliminates errors caused by
parasitic resistance in series with the diode, which
increases the apparent voltage across the PN junction.
When measuring temperature using the internal transis-
tor for a sensor, the two-current method is usually ade-
quate although the four-current method can also be
used. Refer to Application Note 4296: Measuring
Temperature with the MAX1358 Data Acquisition System
for details on the measurement procedure.
TEMP+
TEMP-
TEMP SENSOR
Figure 13. Temperature-Sensor Measurement Block Diagram
32 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
-19
The temperature equations for the two-current and four-
current methods are as follows:
q = electron charge = 1.60219 x 10
n = diode ideality = 1.000 (typ)
k = Boltzmann's constant = 1.3807 x 10
I1 = Nominal current (4µA)
coulombs
Two-current method:
-23
Joules/Kelvin
T = q(V
- V
)/(n k ln(V /V ))
BE1 R2 R1
BE2
Four-current method:
T = q(V + V
I2 = Nominal current ng (60µA)
I3 = Nominal current (64µA)
- V
- V
)/(n k ln((V
R2
x
BE2
BE3
V
BE1
BE4
)/(V x VR4))
R3
R1
I4 = Nominal current (120µA)
where T is the temperature in degrees Kelvin, V
the base to emitter voltage at current X, V is the volt-
is
BEX
To convert the measured temperature in Kelvin to
degrees Celsius, the following formula is used:
RX
age across the current-sensing resistor at current X, q
is the charge on an electron, k is Boltzmannꢀs constant,
and n is the ideality factor for the diode. From a practi-
cal standpoint, it is easiest to combine all the constants
into one constant that also includes the voltage resolu-
tion of the ADC in unipolar mode. This requires intro-
°C = K - 273.15
For the external temperature measurement, a transistor
such as the 2N3904 is recommended.
Voltage Reference and Buffer
An internal 1.25V bandgap reference has a buffer with
a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, result-
ing in nominally 1.25V, 2.048V, or 2.5V reference volt-
age at REF. The ADC and DACs use this reference
voltage. The state of the internal voltage reference
output buffer at POR is disabled so it can be driven, at
REF, with an external reference between AGND and
ducing the term V
, which is the reference voltage of
REF
the ADC. An N prefix on a term indicates that it is the
integer value read directly from the ADC.
Two-current method:
T = 0.1771 x V
(N
- N
)/ln(N
/N
)
REF VBE2
VBE1
VR2 VR1
Four-current method:
T = 0.1771 x V
AV . The MAX11358B reference has an initial toler-
DD
((N
+ N
- N
-
REF
)/ln(N
VBE2
VBE3
VBE1
)
ance of 1%. Program the reference buffer through
the serial interface. Bypass REF with a 4.7µF capaci-
tor to AGND.
N
VBE4
x N
/N
/N
VR2
VR3 VR1 VR4
The natural log function (ln) is eliminated from the cal-
culation by using an approximation. Due to the small
part-to-part variation in current ratios, this approxima-
tion is extremely accurate.
Uncommitted Operational
Amplifiers (Op Amps)
The MAX11358B includes one op amp. The op amp
features rail-to-rail outputs, near rail-to-rail inputs, and
has an 80kHz (1nF load) input bandwidth. The
DACA_OP (DACB_OP) register controls the power state
of the op amps. When powered down, the outputs of
the op amps is high impedance.
Two-current method without an ln function:
T = 0.1771 x V
(N
– N
VR2 VR1
)/(2.7081 +
REF VBE2
VBE1
/N
2_(N
/N
- 15)/(N
+ 15)
VR2 VR1
Four-current method without an ln function:
T = 0.1771 x V (N + N - N
VBE1
-
REF VBE2
VBE3
N
VBE4
)/(2.0794 + 2(N
x N
/N
/N
- 8)/
VR2
/N
VR3 VR1 VR4
(N
x N
/N
+ 8)
VR2
VR3 VR1 VR4
______________________________________________________________________________________ 33
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Single-Pole/Double-Throw (SPDT) Switches
The MAX11358B provides two uncommitted SPDT switch-
es. Each switch has a typical 35Ω on-resistance. Control
the switches through the SW_CTRL register, the PWM
output, and/or a UPIO port configured to control the
switches (UPIO1–UPIO4_CTRL register).
Serial Interface
The MAX11358B features a 4-wire serial interface con-
sisting of a chip select (CS), serial clock (SCLK), data
in (DIN), and data out (DOUT). CS must be low to allow
data to be clocked into or out of the device. DOUT is
high impedance while CS is high. The data is clocked
in at DIN on the rising edge of SCLK. Data is clocked
out at DOUT on the falling edge of SCLK. The serial
interface is compatible with SPI modes CPOL = 0,
CPHA = 0 and CPOL = 1, CPHA = 1. A write operation
to the MAX11358B takes effect on the last rising edge
of SCLK. If CS goes high before the complete transfer,
the write is ignored. Every data transfer is initiated by
the command byte. The command byte consists of a
start bit (MSB), R/W bit, and 6 address bits. The start
bit must be 1 to perform data transfers to the device.
Zeros clocked in are ignored. For SPI pass-through
mode, see the UPIO_SPI Register section. An address
byte identifies each register. Table 4 shows the com-
plete register address map for this family of DAS.
Figures 14, 15, and 16 provide timing diagrams for
read and write commands.
Pulse-Width Modulator (PWM)
A single 8-bit PWM is available for various system tasks
such as LCD bias control, sensor bias voltage trim,
buzzer drive, and duty-cycled sleep-mode power-con-
trol schemes. PWM input clock sources include the
4.9512MHz FLL output, the 32kHz clock, and frequen-
cy-divided versions of each. Although most µCs have
built-in PWM functions, the MAX11358B PWM is more
flexible by allowing the UPIO outputs to be driven to
MAX1358B
DV
or regulated CPOUT logic-high voltage levels.
DD
For duty-cycled power-control schemes, use the
32kHz-derived input clock. The PWM output is avail-
able independent of µC power state. The FLL is typical-
ly disabled in sleep-override mode.
34 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
CS
SCLK
DIN
X
1
0
A5
A4
A3
A2
A1
A0
D
D
N -1
D
N-2
D
N-3
D
2
D
1
D
0
X
N
DOUT
X = DON’T CARE.
Figure 14. Serial-Interface Register Write with 8-Bit Control Word, Followed by a Variable Length Data Write
CS
SCLK
DIN
X
1
1
A5
A4
A3
A2
A1
A0
X
X
X
X
X
X
X
X
D
N
D
N-1
D
N-2
D
N-3
D
2
D
1
D
0
DOUT
X = DON’T CARE.
Figure 15. Serial-Interface Register Read with 8-Bit Control Word, Followed by a Variable Length Data Read
CS
SCLK
DIN
1
0
A4 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0
1
1 A4 A3 A2 A1 A0 X
ADC
CONV
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CHANGES
DOUT
DRDY
X = DON’T CARE.
Figure 16. Performing an ADC Conversion (DRDY Function Can Be Accessed at UPIO Pins)
______________________________________________________________________________________ 35
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Register Definitions
Table 4. Register Address Map
REGISTER
NAME
CTL
ADR<5:0>
D<39:0>, D<23:0>, D<15:0> OR D<7:0>
(DATA)
START
(R/W)
(ADDRESS)
ADCE STRT
RATE<2:0>
MUXP<3:0>
BIP
POL CONT ADCREF GAIN<1:0>
MODE<2:0>
MUXN<3:0>
ADC<15:0>
OFFSET<23:0>
GAIN<23:0>
ADC
1
R/W
0
0
0
0
0
X
X
X
MUX
DATA
OFFSET CAL
GAIN CAL
RESERVED
1
1
1
1
1
R/W
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
S
X
X
X
X
Reserved. Do not use.
MAX1358B
DAE
DAE
DBE OP1E
X
X
X
X
DACA<9:8>
DACB<9:8>
DACA_OP
DACB_OP
1
1
R/W
R/W
0
0
0
0
1
1
1
1
0
1
X
X
DACA<7:0>
DBE OP1E
X
X
DACB<7:0>
AOFF AON SDCE
ASEC<19:4>
REF_SDC
AL_DAY
1
1
1
1
R/W
R/W
R/W
R/W
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
X
X
X
X
REFV<1:0>
TSEL<2:0>
ASEC<3:0>
X
X
X
X
RESERVED
CLK_CTRL
Reserved. Do not use.
AWE
ADE
X
RWE RTCE
IO32E CK32E
SEC<31:0>
SUB<7:0>
SWAH
OSCE
CLKE
FLLE HFCE
INTP WDE
CKSEL<2:0>
RTC
1
1
1
R/W
R/W
R/W
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
X
X
X
PWME
SPD1 SPD2
FSEL<2:0>
SWAL SWBH SWBL
PWM_CTRL
PWM_THTP
X
X
X
X
X
X
PWMTH<7:0>
PWMTP<7:0>
WATCHDOG
NORM_MD
SLEEP
SLEEP_CFG
UPIO4_CTRL
UPIO3_CTRL
UPIO2_CTRL
UPIO1_CTRL
UPIO_SPI
1
1
1
1
1
1
1
1
1
1
1
1
W
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
W
W
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
SLP SOSCE SCK32E SPWME SHDN
X
X
X
X
X
X
X
X
UP4MD<3:0>
UP3MD<3:0>
UP2MD<3:0>
PUP4
PUP3
PUP2
PUP1
X
SV4
SV3
SV2
SV1
X
ALH4 LL4
ALH3 LL3
ALH2 LL2
ALH1 LL1
UP1MD<3:0>
UP4S UP3S UP2S UP1S
X
X
X
X
X
X
SW_CTRL
SWA
SWB SPDT1<1:0>
IVAL<1:0>
Reserved. Do not use.
MLDVD MLCPD MADO MSDC MCRDY MADD MALD
SPDT2<1:0>
TEMP_CTRL
RESERVED
IMUX<1:0>
X
X
X
IMSK
1
R/W
1
1
0
1
1
X
MUPR<4:1>
Reserved. Do not use.
CPE LSDE CPDE HYSE
Reserved. Do not use.
MUPF<4:1>
RESERVED
PS_VMONS
RESERVED
1
1
1
R/W
R/W
R/W
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
X
X
X
LDOE
RSTE
X
X
X
LDVD LCPD ADOU SDC CRDY
UPR<4:1>
ADD
UPF<4:1>
ALD
STATUS
1
R
1
1
1
1
1
X
X = Donꢀt care.
36 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Register Bit Descriptions
ADC Register (Power-On State: 0000 0000 0000 00XX)
MSB
LSB
ADCE
STRT
BIP
POL
CONT
ADCREF
GAIN<1:0>
RATE<2:0>
MODE<2:0>
X
X
The ADC register configures the ADC and starts
a conversion.
CONT: Continuous conversion bit. CONT = 1 enables
continuous conversions following completion of the first
conversion or calibration(s) initiated by the STRT or S
bit. Set CONT = 0 while asserting the STRT bit, or prior
to asserting the S bit to perform a single conversion or to
prevent conversions following a calibration. Set
CONT = 0 to abort continuous conversions already in
progress. When the ADC is stopped in this way, the last
complete conversion result remains in the DATA register
and the internal ADC state information is lost. Asserting
the CONT bit does not restart the ADC, but results in
continuous conversions once the ADC is restarted with
the STRT or S bit.
ADCE: ADC power-enable bit. ADCE = 1 powers up
the ADC, and ADCE = 0 powers down the ADC.
STRT: ADC start bit. STRT = 1 resets the registers
inside the ADC filter and initiates a conversion or cali-
bration. The conversion begins immediately after the
16th ADC control bit is clocked by the rising edge of
SCLK. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 when STRT is
asserted, the ADC stops after a single conversion and
holds the result in the DATA register. If CONT = 1 when
STRT is asserted, the ADC performs continuous conver-
sions at the rate specified by the RATE<2:0> bits until
CONT is deasserted or ADCE is deasserted, powering
down the ADC. The STRT bit is automatically deasserted
after the initial conversion is complete (four conversion
cycles; the ADC status bit ADD in the STATUS register
asserts). The current ADC configurations are not affect-
ed if the ADC register is written with STRT = 0. This
allows the ADC and mux configurations to be updated
simultaneously with the S bit in the MUX register.
ADCREF: ADC reference source bit. Set ADCREF = 0
to select REF as the ADC reference. Set ADCREF = 1
to select AV
as the ADC reference. To measure the
DD
AV
voltage without having to attenuate the supply
DD
voltage, select REF and AGND as the differential inputs
to the ADC, with POL = 0 and while ADCREF = 1.
GAIN<1:0>: ADC gain-setting bits. These two bits
select the gain of the ADC as shown in Table 5.
Table 5. Setting the Gain of the ADC
BIP: Unipolar/bipolar bit. Set BIP = 0 for unipolar mode
and BIP = 1 for bipolar mode. Unipolar-mode data is
unsigned binary format and bipolar is twoꢀs complement.
See the ADC Transfer Functions section for more details.
GAIN SETTING (V/V)
GAIN1
GAIN0
1
2
4
8
0
0
1
1
0
1
0
1
POL: Polarity flipper bit. POL = 1 flips the polarity of the
differential signal to the ADC and the input to the signal-
detect comparator (SDC). POL = 0 sets the positive mux
output to the positive ADC and SDC inputs, and the neg-
ative mux output to the negative ADC and SDC inputs.
POL = 1 sets the positive mux output to the negative
ADC and SDC inputs, and the negative mux output to
the positive ADC and SDC inputs.
______________________________________________________________________________________ 37
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
RATE<2:0>: ADC conversion-rate-setting bits. These
Table 6a. Setting the ADC Conversion Rate*
three bits set the conversion rate of the ADC as shown
CONTINUOUS
SINGLE
in Table 6. The initial conversion requires four conver-
sion cycles for valid data, and subsequent conversions
require only one cycle (if CONT = 1). A full-scale input
change can require up to five cycles for valid data if
the digital filter is not reset with the STRT or S bit.
CONVERSION CONVERSION
RATE2 RATE1 RATE0
RATE (sps)
RATE (sps)
10
40
2.5
10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
MODE<2:0>: Conversion-mode bits. These three bits
determine the type of conversion for the ADC as shown
in Table 7. When the ADC finishes an offset calibration
and/or gain calibration, the MODE<2:0> bits clear to 0
hex, the ADD bit in the STATUS register asserts, and
an interrupt asserts on INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked. Perform a gain calibra-
tion after achieving the desired offset (calibrated or
not). If an offset and gain calibration are performed
together (MODE<2:0> = 7 hex), the offset calibration is
performed first followed by the gain calibration, and the
µC is interrupted by INT (or UPIO_ if programmed as
DRDY) if MADD is unmasked only upon completion of
both offset and gain calibration. After power-on or cali-
bration, the ADC does not begin conversions until initi-
ated by the user (see the ADCE and STRT bit
descriptions in this section and see the S bit descrip-
tions in the MUX Register section). See the GAIN CAL
Register and OFFSET CAL Register sections for details
on system calibration.
50
12.5
15
60
200
240
400
477
50
MAX1358B
60
100
128
Table 6b. Actual ADC Conversion Rates
NOMINAL
CONTINUOUS
CONVERSION
RATE (sps)
ACTUAL
DECIMATION
RATIO
CONTINUOUS
CONVERSION
RATE (sps)
10
40
1096
274
220
183
55
10.01
40.04
50
49.87
60
59.95
200
240
400
477
199.48
238.51
406.35
477.02
Table 7. Setting the ADC Conversion Mode
46
CONVERSION MODE
MODE2 MODE1 MODE0
27
Normal
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
23
System Offset Calibration
System Gain Calibration
Normal
*Calculate the ADC sampling rate using the following
equation:
f
HFCLK
Normal
f
=
S
448× decimation ratio
= 4.9152MHz nominally.
Self-Offset Calibration
Self-Gain Calibration
where f
HFCLK
Self-Offset and Gain
Calibration
1
1
1
38 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
MUX Register (Power-On State: 0000 0000)
MSB
LSB
S (ADR0)
MUXP3
MUXP2
MUXP1
MUXP0
MUXN3
MUXN2
MUXN1
MUXN0
The MUX register configures the positive and negative
mux inputs and can start an ADC conversion.
specified by the RATE<2:0> bits until CONT deasserts
or ADCE deasserts, powering down the ADC. When a
conversion initiates using the S bit, the STRT bit asserts
and deasserts automatically after the initial conversion
completes. Writing to the MUX register with S = 0 caus-
es the MUX settings to change immediately and the
ADC continues in its prior state with its settings unaf-
fected. When the ADC is powered down, MUX inputs
are open.
S (ADR0): Conversion start bit. The S bit is the LSB of
the MUX register address byte. S = 1 resets the regis-
ters inside the ADC filter and initiates a conversion or
calibration. The conversion begins immediately after
the eighth MUX register data bit, when S = 1 and when
writing to the MUX register. This allows the new MUX
and ADC register settings to take effect simultaneously
for a new conversion, if STRT = 0 during the last write
to the ADC register. If the S bit is asserted and the
command is a read from the MUX register, the conver-
sion starts immediately after the S bit (ADR0) is clocked
in by the rising edge of SCLK.
MUXP<3:0>: MUX positive input bits. These four bits
select one of 10 inputs from the positive MUX to go to the
positive output of the MUX as shown in Table 8. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
Read the MUX register with S = 1 for the fastest method
of initiating a conversion because only 8 bits are
required. The subsequent MUX register read is valid,
but can be aborted by raising CS with no harmful side
effects. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 and S = 1, the
ADC stops after a single conversion and holds the
result in the DATA register. If CONT = 1 and S = 1, the
ADC performs continuous conversions at the rate
MUXN<3:0> MUX negative input bits. These four bits
select one of 10 inputs from the negative MUX to go to
the negative output of the MUX as shown in Table 9. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
The DATA register contains the data from the most
recently completed conversion.
The OFFSET CAL register contains the 24-bit data of
the most recently completed offset calibration.
Table 9. Selecting the Negative MUX Inputs
Table 8. Selecting the Positive MUX Inputs
POSITIVE MUX
NEGATIVE
MUX INPUT
MUXP3
MUXP2
MUXP1
MUXP0
MUXN3
MUXN2
MUXN1
MUXN0
INPUT
AIN1
SNO1
FBA
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
X
X
TEMP-
SNO2
OUTA
SCM2
OUTB
SNC2
OUT1
AIN2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
X
0
1
0
1
0
1
0
1
0
1
X
X
SCM1
FBB
SNC1
IN1-
TEMP+
REF
REF
AGND
AGND
Open
Open
X = Donꢀt care.
X = Donꢀt care.
______________________________________________________________________________________ 39
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DATA Register (Power-On State: 0000 0000 0000 0000)
MSB
ADC15
ADC14
ADC13
ADC12
ADC11
ADC3
ADC10
ADC2
ADC9
ADC1
ADC8
LSB
ADC7
ADC6
ADC5
ADC4
ADC0
ADC<15:0> Analog-to-digital conversion data bits.
These 16 bits are the results from the most recently
completed conversion. The data format is unsigned,
binary for unipolar mode, and twoꢀs complement for
bipolar mode.
MAX1358B
OFFSET CAL Register (Power-On State: 0000 0000 0000 0000 0000 0000)
MSB
OFFSET23
OFFSET15
OFFSET7
OFFSET22
OFFSET14
OFFSET6
OFFSET21
OFFSET13
OFFSET5
OFFSET20
OFFSET12
OFFSET4
OFFSET19
OFFSET11
OFFSET3
OFFSET18
OFFSET10
OFFSET2
OFFSET17
OFFSET9
OFFSET1
OFFSET16
OFFSET8
LSB
OFFSET0
OFFSET<23:0>: Offset-calibration bits. The data format
is twoꢀs complement and is subtracted from the ADC
output before being written to the DATA register. The
offset calibration allows input offset errors between
ibration for the entire signal path. See the ADC
Calibration section for more details.
The ADC input voltage range specifications must
always be obeyed, and the OFFSET CAL register effec-
tively offsets the ADC digital scale to a “zero” value
determined by the calibration.
V
50% to be corrected in unipolar or bipolar mode.
REF
The MAX11358B can perform system offset calibration
or self-offset calibration. Self-calibration performs a cal-
GAIN CAL Register (Power-On State: 1000 0000 0000 0000 0000 0000)
MSB
GAIN23
GAIN15
GAIN7
GAIN22
GAIN14
GAIN6
GAIN21
GAIN13
GAIN5
GAIN20
GAIN12
GAIN4
GAIN19
GAIN11
GAIN3
GAIN18
GAIN10
GAIN2
GAIN17
GAIN9
GAIN1
GAIN16
GAIN8
LSB
GAIN0
GAIN<23:0>: Gain-calibration bits. The data format is
unsigned binary with 23 bits to the right of the decimal
point and scales the ADC output before being written to
the DATA register. The gain calibration allows full-scale
bration for offsets in the ADC, and system calibration
performs a calibration for the entire signal path. See the
ADC Calibration section for more details.
The ADC input voltage range specifications must always
be obeyed, and the GAIN CAL register effectively scales
the ADC digital output to a full-scale value determined
by the calibration. The usable gain-calibration range is
limited to less than the full GAIN CAL register digital-
scaling range by the internal noise of the ADC.
errors between -V
/2 and +V
/2 to be corrected in
REF
REF
unipolar mode and full-scale errors between (+50% x
) and (+200% x V ) in unipolar or bipolar mode.
V
REF
REF
The MAX11358B can perform system gain calibration
or self-gain calibration. Self-calibration performs a cali-
40 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
DACA_OP Register (Power-On State: 000X XX00 0000 0000)
MSB
DAE
DBE
OP1E
X
X
X
DACA9
DACA1
DACA8
LSB
DACA7
DACA6
DACA5
DACA4
DACA3
DACA2
DACA0
Writing to the DACA_OP output register updates DACA
on the rising SCLK edge of the LSB data bit. The output
voltage can be calculated as follows:
DAE: DACA enable bit. Set DAE = 1 to power up the
DACA and the DACA output buffer in the MAX11358B.
DBE: DACB enable bit. Set DBE = 1 to power up the
DACB and the DACB output buffer in the MAX11358B.
This bit is mirrored in the DACB_OP register.
V
OUTA
= V
x N/210
REF
where V
is the reference voltage for the DAC, and N
REF
is the integer value of the DACA<9:0> output register.
The output buffer is in unity gain. The DACA data is 10
bits long and right justified.
OP1E: OP1 power-enable bit. Set OP1E = 1 to power
up OP1 in the MAX11358B. This bit is mirrored in the
DACB_OP register.
DACA<9:0>: DACA data bits.
DACB_OP Register (Power-On State: 000X XX00 0000 0000)
MSB
DAE
DBE
OP1E
X
X
X
DACA9
DACA1
DACA8
LSB
DACA7
DACA6
DACA5
DACA4
DACA3
DACA2
DACA0
Writing to the DACB_OP output register updates DACB
on the rising SCLK edge of the LSB. The output voltage
can be calculated as follows:
DAE: DACA enable bit. Set DAE = 1 to power up
DACA and the DACA output buffer in the MAX11358B.
This bit is mirrored in the DACA_OP register.
10
V
OUTB
= V
x N/2
DBE: DACB enable bit. Set DBE = 1 to power up DACB
and the DACB output buffer in the MAX11358B. This bit
is mirrored in the DACA_OP register.
REF
where V
is the reference voltage for the DAC, and N
REF
is the integer value of DACB<9:0> output register. The
output buffer is in unity gain. The DACB data is 10 bits
long and right justified.
OP1E: OP1 power-enable bit. Set OP1E = 1 to power
up OP1 in the MAX11358B. This bit is mirrored in the
DACA_OP register.
DACB<9:0>: DACB data bits.
______________________________________________________________________________________ 41
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
REF_SDC Register (Power-On State: 0000 0000)
MSB
LSB
REFV1
REFV0
AOFF
AON
SDCE
TSEL2
TSEL1
TSEL0
The REF_SDC register contains bits to control the refer-
ence voltage and signal-detect comparator.
AON: ADC and DAC/op-amp power-on bit. This bit pro-
vides a method of turning on several analog functions
with a single write. Setting AON = 1 asserts the ADCE
bit in the ADC register and DAE, DBE, and OP1E bits in
the DACA_OP and DACB_OP register, powering up
these blocks. Setting AON = 0 has no effect. The AON
bit has priority when both AON and AOFF bits are
asserted.
REFV<1:0>: Reference buffer voltage gain and enable
bits. Enables the output buffer, and sets the gain and
the voltage at the REF pin as shown in Table 10. Power-
on state is off to enable an external reference to drive
the REF pin without contention.
MAX1358B
AOFF: ADC and DAC/op-amp power-off bit. This bit pro-
vides a method for turning off several analog functions
with a single write. Setting AOFF = 1 deasserts the
ADCE in the ADC register and the DAE, DBE, and OP1E
bits in the DACA_OP and DACB_OP registers, powering
down these analog blocks. Setting AOFF = 0 has no
effect. The AON bit has priority when both AON and
AOFF bits are asserted.
Most of the analog functions can be enabled with a sin-
gle write to the REF_SDC register using AON,
REFV<1:0>, and SDCE.
SDCE: Signal-detect comparator power-enable bit. Set
SDCE = 1 to power up the signal-detect comparator,
and set SDCE = 0 to power down the signal-detect
comparator. The ADCE bit in the ADC register must be
set to 1 to use the signal-detect comparator.
Most of the analog functions can be disabled with a
single write to the REF_SDC register by using AOFF,
REFV<1:0>, and SDCE.
TSEL<2:0>: Threshold-select bits. These bits select the
threshold for the signal-detect comparator as shown in
Table 11.
Table 10. Setting the Reference Output
Voltage
Table 11. Setting the Signal-Detect
Comparator Threshold
NOMINAL
REFERENCE
TSEL2
TSEL1
TSEL0
REF OUTPUT
VOLTAGE (V)
THRESHOLD (mV)
BUFFER GAIN
(V/V)
REFV1
REFV0
0
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
50
Off (High
Impedance
at REF)
100
150
200
Disabled
0
0
1.0
1.638
2.0
1.25
2.048
2.5
0
1
1
1
0
1
X = Donꢀt care.
42 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX)
MSB
ASEC19
ASEC11
ASEC3
ASEC18
ASEC10
ASEC2
ASEC17
ASEC9
ASEC1
ASEC16
ASEC8
ASEC0
ASEC15
ASEC7
X
ASEC14
ASEC6
X
ASEC13
ASEC5
X
ASEC12
ASEC4
LSB
X
The AL_DAY register stores the second information of
the time-of-day alarm.
existing value remains. When the lower 20 bits in the RTC
second counter match the contents of this register, the
alarm triggers and asserts ALD in the STATUS register. It
also asserts an interrupt on the INT pin unless masked by
the MALD bit in the IMSK register. The part enters normal
mode if an alarm triggers while in sleep mode. The time-
of-day alarm is intended to trigger single events.
Therefore, once it triggers, in the CLK_CTRL register, the
ADE bit is automatically cleared, disabling the time-of-
day alarm. Implement a recurring alarm with repeated
software writes over the serial interface each time the
time-of-day alarm triggers. The time-of-day alarm can
also be programmed to output at the UPIO pins.
ASEC<19:0>: Alarm-second bits. These 20 bits store
the time-of-day alarm, which corresponds to the lower
20 bits of the RTC second counter or SEC<19:0>.
Program the time-of-day alarm trigger between 1s to
just over 12 days beyond the current RTC second
counter value in increments of 1s.
Assert the AWE bit in the CLK_CTRL register (see the
CLK_CTRL Register section) to enable writing to the
AL_DAY register. Enabling the time-of-day alarm requires
two writes to the CLK_CTRL register. Write the 20 alarm-
second bits in 3 bytes, MSB first. If CS is raised before
the LSB is written, the alarm write is aborted, and the
When configured this way the MALD bit does not mask
the UPIO alarm output.
______________________________________________________________________________________ 43
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
CLK_CTRL Register (Power-On State: 00X0 1111 0010 1110)
MSB
AWE
ADE
X
RWE
RTCE
OSCE
CLKE
FLLE
INTP
HFCE
LSB
CKSEL2
CKSEL1
CKSEL0
IO32E
CK32E
WDE
The CLK_CTR register contains the control bits for the
RTC alarms and clocks.
therefore, a second write to this register is required to
change the value of the RTCE bit. The power-on default
state is 0.
AWE: Alarm write-enable bit. Set AWE = 1 to write data
to the AL_DAY register as well as the ADE bit in this
register. When AWE = 0, all writes are prevented to the
AL_DAY register and the ADE bit in this register. A sec-
ond write to this register is required to change the value
of the ADE bit. The power-on default state is 0.
MAX1358B
RTCE: Real-time-clock enable bit. Set RTCE = 1 to
enable the RTC, and set RTCE = 0 to disable the RTC.
The RTC has a 32-bit second and an 8-bit subsecond
counter. The power-on default state is 1.
OSCE: 32kHz crystal-oscillator enable bit. Set OSCE =
1 to power up the 32kHz oscillator, and set OSCE = 0
to power down the oscillator. The power-on default
state is 1.
ADE: Alarm (time-of-day) enable bit. Set ADE = 1 to
enable the time-of-day alarm, and set ADE = 0 to dis-
able the time-of-day alarm. When enabled, the ALD bit
in the STATUS register asserts when the RTC second
counter time matches AL_DAY register. The device
wakes up from sleep to normal mode if not already
awake. The ADE bit can only be written if the AWE = 1
from a previous write. The power-on default state is 0.
FLLE: Frequency-locked-loop enable bit. Set FLLE = 1
to enable the FLL, and set FLLE = 0 to disable the FLL.
If HFCE = 1 and FLLE = 0, the internal high-frequency
oscillator is enabled, but it is not frequency-locked to
the 32kHz clock. When FLLE is asserted, it typically
takes 3.5ms for the high-frequency clock to settle to
within 1% of the 32kHz reference clock frequency.
Switching the FLL on or off with this bit does not cause
high-frequency clock glitching. The power-on default
state is 1.
RWE: RTC write-enable bit. Set RWE = 1 prior to writing
to the RTC register and the RTCE bit in this register. If
RWE = 0, all writes are prevented to the RTC register
as well as the RTCE bit in this register. The RWE signal
takes effect after the rising edge of the 16th clock;
44 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
HFCE: High-frequency-clock enable bit. Set HFCE = 1
to enable the internal high-frequency clock source, and
set HFCE = 0 to disable the high-frequency clock
source.
power in cases where the high-frequency clock is used
internally but is not needed externally. If HFCE = 0, or if
CLKE = 0, CLK remains low. The power-on default
state is 1.
If HFCE = 1 and CLKE = 1, the internal high-frequency
oscillator is enabled and is present at CLK. The power-
on default state is 1.
INTP: Interrupt pin polarity bit. Set INTP = 1 to make
INT an active-high output when asserted, and set INTP
= 0 to make INT an active-low output when asserted.
The power-on default state is 1.
CKSEL<2:0>: Clock selection bits. These bits select
the FLL-based output clock frequency at the high-fre-
quency CLK pin as shown in Table 12. The power-on
default state is 001.
WDE: Watchdog-enable bit. Set WDE = 1 to enable the
watchdog timer, which asserts RESET low within 500ms
if the WATCHDOG register is not written. Set WDE = 0
to disable the watchdog timer. The power-on default
state is 0.
IO32E: Input/output 32kHz clock select bit. Set IO32E
= 0 to configure the CLK32K pin as an output, and set
IO32E = 1 to configure the CLK32K pin as an input,
regardless of the signal on the 32KIN pin as shown in
Table 13.
Table 12. Setting the CLK Frequency
CLOCK FREQUENCY
CKSEL2
CKSEL1
CKSEL0
External clock frequencies applied to CLK32K are
clock sources to the FLL, charge pump, and the signal-
detect comparator. The default power-on state is 0.
(kHz)
4915.2
2457.6
1228.8
614.4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CK32E: CLK32K output-buffer enable bit. Set CK32E =
1 to enable the CLK32K output buffer as long as OSCE
= 1 and IO32E = 0; otherwise, the CK32E bit is not
asserted. Set CK32E = 0 to disable the CLK32K output
buffer. The power-on default state is 1.
32.768
16.384
8.192
CLKE: CLK output-buffer enable bit. Set CLKE = 1 to
enable the CLK output buffer. Set CLKE = 0 to disable
the buffer. Disabling the buffer is useful for saving
4.096
Table 13. Configuring the CLK32K as an Input or Output
RTC, PWM, WDT
CLOCK SOURCE
FLL, C/P, SDC INPUT
SOURCE
CLK32K CLK32K
IO32E
32KIN, 32KOUT
ADC CLOCK SOURCE
Output
Input
1
0
0
1
XTAL attached
XTAL attached
XTAL
XTAL
XTAL
FLL/HFCLK
FLL/HFCLK
CLK32K
______________________________________________________________________________________ 45
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
RTC Register (Power-On State: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000)
MSB
SEC31
SEC23
SEC15
SEC7
SEC30
SEC22
SEC14
SEC6
SEC29
SEC21
SEC13
SEC5
SEC28
SEC20
SEC12
SEC4
SEC27
SEC19
SEC11
SEC3
SEC26
SEC18
SEC10
SEC2
SEC25
SEC17
SEC9
SEC1
SUB1
SEC24
SEC16
SEC8
SEC0
LSB
MAX1358B
SUB7
SUB6
SUB5
SUB4
SUB3
SUB2
SUB0
The RTC register stores the 40-bit second and subsec-
ond count of the respective time-of-day and system
clocks.
of the RTC register in less than 1ms. The power-on
default state is 0000 0000 hex.
SUB<7:0>: The subsecond bits store the system clock.
This 8-bit binary counter has 3.9ms resolution (1/256Hz)
and a span of 1s. The subsecond counter increments in
single counts from 00 hex to FF hex before rolling over
again to 00 hex, at which time the RTC second counter
(SEC<31:0>) increments. The RTC runs continuously
(as long as RTCE = 1) and does not stop for reads or
writes. A 256Hz clock, derived from the 32kHz crystal,
increments this counter. Set the RWE = 1 bit to enable
writing to the RTC register. After writing to RWE, perform
another write, setting RTCE = 1, to enable the RTC. A
40-bit burst write operation, starting with SEC31 and fin-
ishing with SUB0, is required to set the RTC second and
subsecond bits. If CS is brought high before the 40th
rising SCLK edge, the write is aborted and the RTC con-
tents are unchanged. The RTC register is loaded on the
rising SCLK edge of the 40th bit (SUB0). A 40-bit burst
read operation, starting with SEC31 and finishing with
SUB0, is required to retrieve the current RTC second
and subsecond counts. The read command can be
aborted prior to receiving the 40th bit (SUB0) by raising
CS, and any RTC data read to that point is valid. When
the read command is received, a snapshot of a valid
RTC second count is latched to avoid reading an erro-
neous, transitioning RTC value. Due to the asynchro-
nous nature of RTC reads, it is possible to have a
maximum 1s error between the actual and reported
times from the time-of-day clock. To prevent the data
from changing during a read operation, complete reads
of the RTC registers occur in less than 1ms. The power-
on default state is 00 hex.
SEC<31:0>: The second bits store the time-of-day
clock settings. It is a 32-bit binary counter with 1s reso-
lution that can keep time for a span of over 136 years.
Firmware in the µC can translate this time count to units
that are meaningful to the system (i.e., translate to cal-
endar time or as an elapsed time from some predefined
time = 0, such as January 1, 2000). The RTC runs con-
tinuously as long as RTCE = 1 (see the CLK_CNTL
Register section) and does not stop for reads or writes.
The counter increments when the subsecond counter
overflows. Set RWE = 1 to enable writing to the RTC
register. After writing to RWE, perform another write
and set RTCE = 1 to enable the RTC. A 40-bit burst
write operation, starting with SEC31 and finishing with
SUB0 is required to set the RTC second and subsec-
ond bits. If CS is brought high before the 40th rising
SCLK edge, the write is aborted and the RTC contents
are unchanged. The RTC register is loaded on the ris-
ing SCLK edge of the 40th bit (SUB0). A 40-bit burst
read operation, starting with SEC31 and finishing with
SUB0, is required to retrieve the current RTC second
and subsecond counts. The read command can be
aborted prior to receiving the 40th bit (SUB0) by raising
CS and any RTC data read to that point is valid. When
the read command is received, a snapshot of a valid
RTC second count is latched to avoid reading an erro-
neous, transitioning RTC value. Due to the asynchro-
nous nature of RTC reads, it is possible to have a
maximum 1s error between the actual and reported
times from the time-of-day clock. To prevent the data
from changing during a read operation, complete reads
46 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
PWM_CTRL Register (Power-On State: 0000 0000 00XX XXXX)
MSB
PWME
FSEL2
SPD2
FSEL1
X
FSEL0
X
SWAH
X
SWAL
X
SWBH
X
SWBL
LSB
X
SPD1
The PWM_CTRL register contains control bits for the
8-bit PWM.
SWAH: SWA-switch PWM-high control bit. Set SWAH =
1 to enable the PWM output to directly control the SWA
switch. When SWAH = SWAL, the PWM output is dis-
abled from controlling the SWA switch. When SWAH =
1, a PWM high output closes the SWA switch and a
PWM low output opens the SWA switch. The PWM high
output refers to the beginning of the period when the
output is logic-high. See Table 17 for more details. The
power-on default is 0.
PWME: PWM-enable bit. Set PWME = 1 to enable the
internal PWM, and set PWME = 0 to disable the internal
PWM. Enable the high-frequency clock before enabling
the PWM when using input clock frequencies above
32.768kHz. The power-on default state is 0.
FSEL<2:0>: Frequency selection bits. Selects the PWM
input clock frequency as shown in Table 14. The
power-on default is 000.
SWAL: SWA-switch PWM-low control bit. Set SWAL = 1
to enable the inverted PWM output to directly control
the SWA switch. When SWAH = SWAL, the PWM output
is disabled from controlling the SWA switch. When
SWAL = 1, a PWM low output closes the SWA switch
and a PWM high output opens the SWA switch. The
PWM low output refers to the end of the period when
the output is logic-low. See Table 17 for more details.
The power-on default is 0.
Table 14. Setting the PWM Frequency
PWM INPUT FREQUENCY*
FSEL2
FSEL1
FSEL0
(kHz)
4915.2**
2457.6**
1228.8**
32.768
8.192
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SPD1: SPDT1-switch PWM drive control bit. Set SPD1
= 1 to enable the PWM output to directly control the
SPDT1 switch, and set SPD1 = 0 to disable the PWM
output controlling the SPDT1 switch. The SPDT1<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT1-switch state. See
Table 18 for more details. The power-on default is 0.
1.024
0.256
0.032
*The lower PWM frequencies are useful for power-supply duty
cycling to conserve battery life and enable a single-battery cell-
powered system. The higher frequencies allow reasonably small,
external components for RC filtering when used as a DAC for bias
adjustments.
**When the part is in sleep mode, the HFCLK is shut down. In this
case, PWM frequencies above 32kHz are not available (see
SPWME in the SLEEP_CFG Register section).
SPD2: SPDT2-switch PWM drive control bit. Set SPD2
= 1 to enable the PWM output to directly control the
SPDT2 switch, and set SPD2 = 0 to disable the PWM
output controlling the SPDT2 switch. The SPDT2<1:0>
bits, the UPIO pins (if programmed), and the PWM out-
put (if enabled), determine the SPDT2-switch state. See
Table 19 for more details. The power-on default is 0.
______________________________________________________________________________________ 47
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
PWM_THTP Register (Power-On State: 0000 0000 0000 0000)
MSB
PWMTH7
PWMTH6
PWMTH5
PWMTH4
PWMTH3
PWMTH2
PWMTP2
PWMTH1
PWMTP1
PWMTH0
LSB
PWMTP7
PWMTP6
PWMTP5
PWMTP4
PWMTP3
PWMTP0
The PWM_THTP register contains the bits that set the
PWM on-time and period.
WATCHDOG Register (Power-On State: N/A)
Writing to the WATCHDOG register address sets the
watchdog timer to 0ms. If the watchdog is enabled
(WDE = 1) and the WATCHDOG register is not written
to before the 750ms expiration, RESET asserts low for
250ms and the watchdog timer restarts at 0ms when
the watchdog timer is enabled. There are no data bits
for this register, and the watchdog timer is reset on the
rising edge of SCLK during the ADR0 bit in the
WATCHDOG register address control byte. Figure 17
shows an example of watchdog timing.
PWMTH<7:0>: PWM time high bits. These bits define
the PWM on (or high)-time and when combined with the
PWMTP<7:0> bits, they determine the duty cycle and
period. The on-time duty cycle is defined as:
MAX1358B
(PWMTH<7:0> + 1)/(PWMTP<7:0> + 1)
To get 50% duty cycle, set PWMTH<7:0> to 126 deci-
mal and PWMTP<7:0> to 253 decimal. Note that setting
PWMTP<7:0> to 255 decimal is not valid as the denom-
inator in the above formula becomes 0. A 100% duty
cycle (i.e., always on) is possible with a value of
PWMTH<7:0> ≥ PWMTP<7:0> > 0. A 0% duty cycle is
possible by setting PWMTH<7:0> = 0 or PWME = 0 in
the PWM_CTRL register. If the PWM is selected to drive
the UPIO_ pin(s), the ALH_ bit(s) (UPIO_CTRL register)
determine the on-time polarity at the beginning of the
PWM cycle. If ALH_ = 1, the on-time at the start of the
NORM_MD Register (Power-On State: N/A)
Exit sleep mode and enter normal mode by writing to
the NORM_MD register. The specific normal-mode
state of all circuit blocks is set by the user, who must
configure the individual power-enable bits before enter-
ing sleep mode (Table 15). There are no data bits for
this register, and normal mode begins on the rising
edge of SCLK during the ADR0 bit in the NORM_MD
register address control byte.
PWM period causes a logic-high level (DV
or
DD
CPOUT) at the UPIO_ pin. When ALH_ = 0, it causes a
logic-low level (DGND) during the on-time. When the
PWM output drives the SWA/B switches, the SWA(B)H
or SWA(B)L bits in the PWM_CTRL register determine
which PWM phase closes these switches. The SPDT1
and SPDT2 switches do not have PWM polarity inver-
sion bits (see the SPDT1<1:0> and SPDT2<1:0> bit
descriptions in the SW_CTRL Register section), but
their effective polarity is set by how the switches are
connected externally. The power-on default is 00 hex.
SLEEP Register (Power-On State: N/A)
Enter sleep mode by writing to the SLEEP register. This
low-power state overrides most of the normal power-
control bits. Table 15 shows which functions are off,
which functions are unaffected (ADE, RTCE, LSDE, and
HYSE), and which functions are controlled by special
sleep-mode bits (SOSCE, SCK32E, and SPWME) while
in sleep mode. There are no data bits for this register,
and sleep mode begins on the rising edge of SCLK
during the ADR0 bit in the SLEEP register address con-
trol byte.
PWMTP<7:0>: PWM time period bits. These bits con-
trol the PWM output period defined. The PWM output
period is defined as:
(PWMTP<7:0> + 1)/(PWM input frequency)
Set the PWM input frequency by selecting the
FSEL<2:0> bits as described in Table 14. The power-
on default is 00 hex.
48 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Table 15. Normal-Mode and Sleep-Register Summary
REGISTER
NAME
CIRCUIT BLOCK
DESCRIPTION
POR DEFAULT
NORMAL MODE
SLEEP
ADC
ADC
DACA
DACB
OP1
ADCE = 0
DAE = 0
DBE = 0
OP1E = 0
ADCE
DAE
OFF
OFF
OFF
OFF
DACA_OP,
DACB_OP
DBE
OP1E
Reference Buffer Gain and
Enable
REFV<1:0> = 00
REFV<1:0>
OFF
REF_SDC
Signal-Detect Comparator
Time-of-Day Alarm Enable
RTC
SDCE = 0
ADE = 0
SDCE
ADE
OFF
ADE
RTCE = 1
OSCE = 1
CK32E = 1
HFCE = 1
RTCE
OSCE
CK32E
HFCE
RTCE
SOSCE
SCK32E
OFF
CK32 XTAL Oscillator
CK32 Output Buffer
High-Frequency Clock
CLK_CTRL
High-Frequency Clock Output
Buffer
CLKE = 1
CLKE
OFF
FLL Enable
Watchdog Timer
PWM
FLLE = 1
WDE = 0
FLLE
WDE
OFF
OFF
PWM_CTRL
PS_VMONS
PWME = 0
LDOE = 0
PWME
LDOE
SPWME
OFF
Linear Regulator
Charge-Pump Doubler
CPOUT Voltage Monitor
CPE = 0
CPE
OFF
CPDE = 0
CPDE
OFF
1.8V DV
Monitor
LSDE = 1
LSDE
LSDE
HYSE
OFF
DD
1.8V Monitor Hysteresis
Temperature Sense Source
UPIO_ Function
HYSE = 0
HYSE
TEMP_CTRL
UPIO_CTRL
IMUX<1:0> = 00
UP_MD<3:0> = 0 hex
PUP_ = 1
IMUX<1:0>
UP_MD<3:0>
PUP_
UP_MD<3:0>
PUP_
SV_
UPIO_ Pullup
UPIO_ Supply Voltage
UPIO_ Assertion Level
SV_ = 0
SV_
ALH_ = 0
ALH_
ALH_
______________________________________________________________________________________ 49
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SLEEP_CFG Register (Power-On State: 1100 XXXX)
MSB
LSB
SLP (ADR0)
SOSCE
SCK32E
SPWME
SHDN
X
X
X
X
The SLEEP_CFG register allows users to program spe-
cific behavior for the 32kHz oscillator, buffer, and PWM
in sleep mode. It also contains a sleep-control bit (SLP)
to enable sleep mode.
SPWME: Sleep-mode PWM enable bit. SPWME = 1
enables the internal PWM in sleep mode, and
SPWME = 0 disables it in sleep mode, regardless of the
state of the PWME bit.
SLP (ADR0): Sleep bit. The SLP bit is the LSB in the
SLEEP_CFG address control byte. Set SLP = 1 to
assert the SHDN bit and enter sleep mode. Writing the
register with SLP = 0 or reading with SLP = 0 or
SLP = 1 has no effect on the SHDN bit.
Input frequencies are limited to 32.768kHz or lower
since the high-frequency clock is disabled in sleep
mode. SOSCE must be asserted to have 32kHz avail-
able as an input to the PWM. The power-on default is 0.
MAX1358B
SHDN: Shutdown bit. This bit is read only. SHDN is
asserted by writing to the SLEEP register address or by
writing to the SLEEP_CFG register with SLP = 1. When
SHDN is asserted, the device is in sleep mode even if
the SLEEP or SLEEP function on the UPIO is deassert-
ed. The SHDN bit is deasserted by writing to the
NORM_MD register or by other defined events. Events
that cause SHDN to be deasserted are a day alarm or
an edge on the UPIO wake-up pin causing wake-up to
be asserted. The power-on default is 0.
SOSCE: Sleep-mode 32kHz crystal oscillator enable
bit. SOSCE = 1 enables the 32kHz oscillator in sleep
mode, and SOSCE = 0 disables it in sleep mode,
regardless of the state of the OSCE bit. The power-on
default is 1.
SCK32E: Sleep-mode CK32K-pin output-buffer enable
bit. SCK32E = 1 enables the 32kHz output buffer in
sleep mode, and SCK32E = 0 disables it in sleep
mode, regardless of the state of the CK32E bit. The
power-on default is 1.
RESET
Q
Q
D
D
Q
Q
4Hz
CK
32K
DIVIDE-
BY-8192
CK
WDE
R
R
POR
WDW
WATCHDOG TIMER
750ms
1
4Hz CLOCK
2-BIT COUNTER
X
0
1
2
0
1
0
2
3
0
1
2
0
SPI WRITES
RESET
WATCHDOG
ADDRESS
WATCHDOG
ADDRESS
WDE = 1
WATCHDOG
ADDRESS
250ms
Figure 17. Watchdog Timer Architecture
50 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
UPIO4_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP4MD3
UP4MD2
UP4MD1
UP4MD0
PUP4
SV4
ALH4
LL4
The UPIO4_CTRL register configures the UPIO4 pin
functionality.
ALH4: Active logic-level assertion high UPIO4 bit. Set
ALH4 = 0 to define the input or output assertion level
for UPIO4 as low except when in GPI and GPO modes.
Set ALH4 = 1 to define the input or output assertion
level as high. For example, asserting ALH4 defines the
UPIO4 output signal as ALARM, while deasserting
ALH4 defines it as ALARM. Similarly, asserting ALH4
defines the UPIO4 input signal as WU, while deassert-
ing ALH4 defines it as WU. The power-on default is 0.
UP4MD<3:0>: UPIO4-mode selection bits. These bits
configure the mode for the UPIO4 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP4: Pullup UPIO4 control bit. Set PUP4 = 1 to enable
a weak pullup resistor on the UPIO4 pin, and set PUP4
= 0 to disable it. The pullup resistor is connected to
either DV
or CPOUT as programmed by the SV4 bit.
DD
LL4: Logic-level UPIO4 bit. When UPIO4 is configured
as GPO, LL4 = 0 sets the output to a logic-low and LL4
= 1 sets the output to a logic-high. A read of LL4
returns the voltage level at the UPIO4 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
The pullup is enabled only when UPIO4 is configured as
an input. Open-drain behavior can be simulated at
UPIO4 by setting the mode to GPO with LL4 = 0 and by
changing the mode to GPI with PUP4 = 0, allowing
external high pullup. The power-on default is 1.
SV4: Supply-voltage UPIO4 selection bit. Set SV4 = 0
to select DV
as the supply voltage for the UPIO4 pin,
DD
and set SV4 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO4 pin. The power-on default is 0.
UPIO3_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP3MD3
UP3MD2
UP3MD1
UP3MD0
PUP3
SV3
ALH3
LL3
The UPIO3_CTRL register configures the UPIO3 pin
functionality.
ALH3: Active logic-level assertion high UPIO3 bit. Set
ALH3 = 0 to define the input or output assertion level
for UPIO3 as low except when in GPI and GPO modes.
Set ALH3 = 1 to define the input or output assertion
level as high. For example, asserting ALH3 defines the
UPIO3 output signal as ALARM, while deasserting
ALH3 defines it as ALARM. Similarly, asserting ALH3
defines the UPIO3 input signal as WU, while deassert-
ing ALH3 defines it as WU. The power-on default is 0.
UP3MD<3:0>: UPIO3-mode selection bits. These bits
configure the mode for the UPIO3 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP3: Pullup UPIO3 control bit. Set PUP3 = 1 to enable
a weak pullup resistor on the UPIO3 pin, and set PUP3
= 0 to disable it. The pullup resistor is connected to
either DV
or CPOUT as programmed by the SV3 bit.
DD
LL3: Logic-level UPIO3 bit. When UPIO3 is configured
as GPO, LL3 = 0 sets the output to a logic-low and LL3
= 1 sets the output to a logic-high. A read of LL3
returns the voltage level at the UPIO3 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
The pullup is enabled only when UPIO3 is configured as
an input. Open-drain behavior can be simulated at
UPIO3 by setting the mode to GPO with LL3 = 0 and by
changing the mode to GPI with PUP3 = 0, allowing
external high pullup. The power-on default is 1.
SV3: Supply-voltage UPIO3 selection bit. Set SV3 = 0
to select DV
as the supply voltage for the UPIO3 pin,
DD
and set SV3 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO3 pin. The power-on default is 0.
______________________________________________________________________________________ 51
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO2_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP2MD3
UP2MD2
UP2MD1
UP2MD0
PUP2
SV2
ALH2
LL2
The UPIO2_CTRL register configures the UPIO2 pin
functionality.
ALH2: Active logic-level assertion high UPIO2 bit. Set
ALH2 = 0 to define the input or output assertion level
for UPIO2 as low except when in GPI and GPO modes.
Set ALH2 = 1 to define the input or output assertion
level as high. For example, asserting ALH2 defines the
UPIO2 output signal as ALARM, while deasserting
ALH2 defines it as ALARM. Similarly, asserting ALH2
defines the UPIO2 input signal as WU, while deassert-
ing ALH2 defines it as WU. The power-on default is 0.
UP2MD<3:0>: UPIO2-mode selection bits. These bits
configure the mode for the UPIO2 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
PUP2: Pullup UPIO2 control bit. Set PUP2 = 1 to enable
a weak pullup resistor on the UPIO2 pin, and set PUP2
= 0 to disable it. The pullup resistor is connected to
MAX1358B
either DV
or CPOUT as programmed by the SV2 bit.
DD
LL2: Logic-level UPIO2 bit. When UPIO2 is configured
as GPO, LL2 = 0 sets the output to a logic-low and LL2
= 1 sets the output to a logic-high. A read of LL2
returns the voltage level at the UPIO2 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
The pullup is enabled only when UPIO2 is configured as
an input. Open-drain behavior can be simulated at
UPIO2 by setting the mode to GPO with LL2 = 0 and by
changing the mode to GPI with PUP2 = 0, allowing
external high pullup. The power-on default is 1.
SV2: Supply-voltage UPIO2 selection bit. Set SV2 = 0
to select DV
as the supply voltage for the UPIO2 pin,
DD
and set SV2 = 1 to select CPOUT as the supply volt-
age. The selected supply voltage applies to all modes
for the UPIO2 pin. The power-on default is 0.
UPIO1_CTRL Register (Power-On State: 0000 1000)
MSB
LSB
UP1MD3
UP1MD2
UP1MD1
UP1MD0
PUP1
SV1
ALH1
LL1
The UPIO1_CTRL register configures the UPIO1 pin
functionality.
age. The selected supply voltage applies to all modes
for the UPIO1 pin. The power-on default is 0.
UP1MD<3:0>: UPIO1-mode selection bits. These bits
configure the mode for the UPIO1 pin. See Table 16 for
a detailed description. The power-on default is 0 hex.
ALH1: Active logic-level assertion high UPIO1 bit. Set
ALH1 = 0 to define the input or output assertion level
for UPIO1 as low except when in GPI and GPO modes.
Set ALH1 = 1 to define the input or output assertion
level as high. For example, asserting ALH1 defines the
UPIO1 output signal as ALARM, while deasserting
ALH1 defines it as ALARM. Similarly, asserting ALH1
defines the UPIO1 input signal as WU, while deassert-
ing ALH1 defines it as WU. The power-on default is 0.
PUP1: Pullup UPIO1 control bit. Set PUP1 = 1 to enable
a weak pullup resistor on the UPIO1 pin, and set PUP1
= 0 to disable it. The pullup resistor is connected to
either DV
or CPOUT as programmed by the SV1 bit.
DD
The pullup is enabled only when UPIO1 is configured as
an input. Open-drain behavior can be simulated at
UPIO1 by setting the mode to GPO with LL1 = 0 and by
changing the mode to GPI with PUP1 = 0, allowing
external high pullup. The power-on default is 1.
LL1: Logic-level UPIO1 bit. When UPIO1 is configured
as GPO, LL1 = 0 sets the output to a logic-low and LL1
= 1 sets the output to a logic-high. A read of LL1
returns the voltage level at the UPIO1 pin at the time of
the read, regardless of how it is programmed. The
power-on default is 0.
SV1: Supply-voltage UPIO1 selection bit. Set SV1 = 0
to select DV
as the supply voltage for the UPIO1 pin,
DD
and set SV1 = 1 to select CPOUT as the supply volt-
52 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Table 16. UPIO Mode Configuration
UP4MD<3:0>,
UP3MD<3:0>,
MODE
DESCRIPTION
UP2MD<3:0>, UP1MD<3:0>
General-purpose digital input. Active edges detected by UPR_ or UPF_
status register bits. ALH_ has no effect with this setting.
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
GPI
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no
effect with this setting.
GPO
Digital input. DAC A buffer switch control. See the SWA bit description in
the SW_CTRL Register section.
SWA or SWA
SWB or SWB
SPDT1 or SPDT1
SPDT2 or SPDT2
Digital input. DAC B buffer switch control. See the SWB bit description in
the SW_CTRL Register section.
Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the
SW_CTRL Register section.
Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the
SW_CTRL Register section.
Sleep-mode digital input. Overrides power-control register and puts the
part into sleep mode when asserted. The clock buffers must be powered
down separately. When deasserted, power mode is determined by the
SHDN bit.
0
1
1
0
SLEEP or SLEEP
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
WU or WU
Wake-up digital input. Asserted edge clears SHDN bit.
Reserved
Reserved. Do not use these settings.
PWM digital output. Signal defined by the PWM_CTRL register. PWM on
(or high or “1”); assertion level defined by the ALH_ bit. When PWM is
1
1
0
1
1
0
1
0
PWM or PWM
disabled (PWME = 0), the UPIO pin idles high (DV
ALH = 1, and low (DGND) if ALH = 0.
or CPOUT) if
DD
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on
default of GPI with pullup ensures initial power-supply turn-on when UPIO
is connected to a power supply with a SHDN input.
SHDN or SHDN
RTC alarm digital output. Asserts for time-of-day alarm events; equivalent
to ALD in STATUS register.
1
1
1
1
1
1
0
1
1
1
0
1
AL_DAY or AL_DAY
Reserved
Reserved. Do not use these settings.
ADC data-ready digital output. Asserts when analog-to-digital conversion
or calibration completes. Not masked by MADD bit.
DRDY or DRDY
Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together.
______________________________________________________________________________________ 53
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO_SPI Register (Power-On State: 0000 XXXX)
MSB
LSB
UP4S
UP3S
UP2S
UP1S
X
X
X
X
The UPIO_SPI pass-through control register bits map
the serial interface signals to the UPIO pins, allowing
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
the DAS to drive other devices at CPOUT or DV
volt-
DD
age levels, depending on the SV_ bit setting found in
the UPIO_CTRL register. Individual bits are provided to
set only the desired UPIO inputs to the SPI pass-
through mode. This mode becomes active when CS is
driven high to complete the write to this register, and
remains active as long as CS stays high (i.e., multiple
pass-through writes are possible). The SPI pass-
through mode is deactivated immediately when CS is
pulled low for the next DAS write.
through mode is active, and is high (near DV
or
DD
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
MAX1358B
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 18 for an SPI pass-through timing diagram.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
WRITE TO DAS TO ENABLE SPI MODE
NORMAL WRITE TO DAS
WRITE THROUGH DAS TO UPIO DEVICE
CS
SCLK
DIN
D
N
D
N-1
D
N-2
D
N-3
D
3
D
2
D
D
0
E
N
E
N-1
E
E
X
X
X
E
X
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
N-2
N-3
E
3
E
2
E
0
DOUT
1
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
UPIO4
UPIO3
UPIO2
UPIO1
SET BY UPIO4_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
SET BY UPIO2_CTRL REGISTER
SET BY UPIO1_CTRL REGISTER
E
E
N-1
E
E
N-3
X
X
X
E
X
N
N-2
E
3
E
2
E
0
1
Figure 18. SPI Pass-Through Timing Diagram
54 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
SW_CTRL Register (Power-On State: 0000 00XX)
MSB
LSB
SWA
SWB
SPDT11
SPDT10
SPDT21
SPDT20
X
X
The switch-control register controls the two SPDT
switches (SPDT1 and SPDT2) and the DACA output
buffer SPST switch (SWA). Control this switch by the
serial bits in this register, by any of the UPIO pins that
are enabled for that function, or by the PWM.
Table 17. SWA States
SW_ BIT*
UPIO_*
PWM*
SW_ SWITCH STATE
Switch open
0
0
X
1
X
0
1
X
X
X
Switch closed
Switch closed
Switch closed
SWA: DACA output buffer SPST-switch A control bit.
The SWA bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWA switch
as shown in Table 17. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit of the
UPIO_CTRL register. If a UPIO is not configured for this
mode, its value applied to the table is 0. The PWM
states of 0 and 1 in the table correspond to the respec-
tive PWM off (or low) and on (or high) states defined by
the SWAH and SWAL bits (see the PWM_CTRL Register
section). If the PWM is not configured for this mode, its
value applied to the table is 0. The power-on default is 0.
X
1
X = Donꢀt care.
*Switch SW_ control is effectively an OR of the SW_ bit, UPIO_
pins, and PWM.
Table 18. SPDT Switch 1 States
SPDT1<1:0> UPIO_* PWM* SPDT1 SWITCH STATE
0
0
0
0
1
1
1
1
0
X
X
1
0
X
X
1
0
X
1
X
0
X
1
X
0
1
X
X
0
1
X
X
SNO1 open, SNC1 open
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNO1 closed, SNC1 closed
SNC1 closed, SNO1 open
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
SNC1 open, SNO1 closed
SWB: DACB output buffer SPST-switch B control bit.
The SWB bit, the UPIO inputs (if configured), and the
PWM (if configured) control the state of the SWB switch
as shown in Table 18. The UPIO_ states of 0 and 1 in the
table correspond to respective deasserted and asserted
logic states as defined by the ALH_ bit (see the
UPIO_CTRL Register section). If a UPIO is not config-
ured for this mode, its value applied to the table is 0.
The PWM states of 0 and 1 in the table correspond to
the respective PWM off (or low) and on (or high) states
defined by the SWBH and SWBL bits (see the
PWM_CTRL Register section). If the PWM is not config-
ured for this mode, its value applied to the table is 0.
The power-on default is 0.
X = Donꢀt care.
*Switch SPDT1 control is effectively an OR of the SPDT10 bit, the
UPIO_ pins, and the PWM output. The SPDT11 bit determines if
the switches open and close together or if they toggle.
Table 19. SPDT Switch 2 States
SPDT2<1:0> UPIO_* PWM* SPDT2 SWITCH STATE
SPDT1<1:0>: Single-pole double-throw switch 1 con-
trol bits. The SPDT1<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 18. The UPIO_ states of 0
and 1 in the table correspond to respective deasserted
and asserted logic states as defined by the ALH_ bit of
the UPIO_CTRL register. If a UPIO is not configured for
this mode, its value applied to Table 18 is 0. The PWM
states of 0 and 1 in Table 18 correspond to the respec-
tive PWM off (low) and on (high) states defined by the
SPD1 bit in the PWM_CTRL register. If the PWM is not
configured for this mode, its value applied to Table 18
is 0. The power-on default is 00.
0
0
0
0
1
1
1
1
0
X
X
1
0
X
X
1
0
X
1
X
0
X
1
X
0
1
X
X
0
1
X
X
SNO2 open, SNC2 open
SNO2 closed, SNC2 closed
SNO2 closed, SNC2 closed
SNO2 closed, SNC2 closed
SNC2 closed, SNO2 open
SNC2 open, SNO2 closed
SNC2 open, SNO2 closed
SNC2 open, SNO2 closed
X = Donꢀt care.
*Switch SPDT2 control is effectively an OR of the SPDT20 bit, the
UPIO_ pins, and the PWM output. The SPDT21 bit determines if
the switches open and close together or if they toggle.
______________________________________________________________________________________ 55
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
SPDT2<1:0>: Single-pole double-throw switch 2 control
bits. The SPDT2<1:0> bits, the UPIO pins (if config-
ured), and the PWM (if configured) control the state of
the switch as shown in Table 19. The UPIO_ states of 0
and 1 in the table correspond to respective deasserted
and asserted logic states as defined by the ALH_ bit in
the UPIO_CTRL register. If a UPIO is not configured for
this mode, its value applied to Table 19 is 0. The PWM
states of 0 and 1 in Table 19 correspond to the respec-
tive PWM off (low) and on (high) states defined by the
SPD2 bit in the PWM_CTRL register. If the PWM is not
configured for this mode, its value applied to Table 19 is
0. The power-on default is 00.
TEMP_CTRL Register (Power-On State: 0000 XXXX)
MSB
LSB
MAX1358B
IMUX1
IMUX0
IVAL1
IVAL0
X
X
X
X
The temperature-sensor control register controls the
internal and external temperature measurement.
IVAL<1:0>: Internal current-source value bits. Selects
the value of the internal current source as shown in
Table 21. The power-on default is 00.
IMUX<1:0>: Internal current-source MUX bits. Selects
the pin to be driven by the internal current sources as
shown in Table 20. The power-on default is 00.
Table 20. Selecting Internal Current Source
Table 21. Setting the Current Level
CURRENT SOURCE
IMUX1
IMUX0
CURRENT
TYPICAL CURRENT (µA)
IVAL1
IVAL0
Disabled
Internal temperature sensor
0
0
1
1
0
1
0
1
I
I
I
I
4
0
0
1
1
0
1
0
1
1
2
3
4
60
AIN1
AIN2
64
120
56 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
IMSK Register (Power-On State: 1111 011X 1111 1111)
MSB
MLDVD
MLCPD
MADO
MSDC
MCRDY
MUPF4
MADD
MALD
X
LSB
MUPR4
MUPR3
MUPR2
MUPR1
MUPF3
MUPF2
MUPF1
The IMSK register determines which bits of the STATUS
register generate an interrupt on INT. The bits in this
register do not mask output signals routed to UPIO
since the output signals are masked by disabling that
UPIO function.
MCRDY = 1 to mask the CRDY status bit interrupt. The
power-on default value is 0.
MADD: ADD status bit mask. Set MADD = 0 to enable
the ADD status bit interrupt to INT, and set MADD = 1
to mask the ADD status bit interrupt. The power-on
default value is 1.
MLDVD: LDVD status bit mask. Set MLDVD = 0 to
enable the LDVD status bit interrupt to INT, and set
MLDVD = 1 to mask the LDVD status bit interrupt. The
power-on default value is 1.
MALD: ALD status bit mask. Set MALD = 0 to enable
the ALD status bit interrupt to INT, and set MALD = 1 to
mask the ALD status bit interrupt. The power-on default
value is 1.
MLCPD: LCP status bit mask. Set MLCPD = 0 to
enable the LCP status bit interrupt to INT, and set
MLCPD = 1 to mask the LCP status bit interrupt. The
power-on default value is 1.
MUPR<4:1>: UPR<4:1> status bits mask. Set MUPR_ =
0 to enable the UPR_ status bit interrupt to INT, and set
MUPR_ = 1 to mask the UPR_ status bit interrupt. (_ =
1, 2, 3, or 4 and corresponds to the UPIO1, UPIO2,
UPIO3, or UPIO4 pins, respectively.) The power-on
default value is F hex.
MADO: ADO status bit mask. Set MADO = 0 to enable
the ADO status bit interrupt to INT, and set MADO = 1
to mask the ADO status bit interrupt. The power-on
default value is 1.
MUPF<4:1>: UPF<4:1> status bits mask. Set MUPF_ =
0 to enable the UPF_ status bit interrupt to INT, and set
MUPF_ = 1 to mask the UPF_ status bit interrupt. (_ = 1,
2, 3, or 4 and corresponds to the UPIO1, UPIO2,
UPIO3, or UPIO4 pins, respectively.) The power-on
default value is F hex.
MSDC: SDC status bit mask. Set MSDC = 0 to enable
the SDC status bit interrupt to INT, and set MSDC = 1
to mask the SDC status bit interrupt. The power-on
default value is 1.
MCRDY: CRD status bit mask. Set MCRDY = 0 to
enable the CRDY status bit interrupt to INT, and set
PS_VMONS Register (Power-On State: 0010 01XX)
MSB
LSB
LDOE
CPE
LSDE
CPDE
HYSE
RSTE
X
X
This register is the power-supply and voltage monitors
control register.
disable the DV
low-supply-voltage detector. The
DD
power-on default value is 1.
LDOE: Low-dropout linear-regulator enable bit. Set
LDOE = 1 to enable the low-dropout linear regulator to
provide the internal source voltage for the charge
pump. Set LDOE = 0 to disable the LDO, allowing an
external drive to the charge-pump input through REG.
The power-on default value is 0.
CPDE: CPOUT low-supply voltage-detector power-
enable bit. Set CPDE = 1 to enable the +2.7V CPOUT
low-supply voltage-detector comparator, and set CPDE
= 0 to disable the CPOUT low-supply voltage-detector
comparator. The power-on default value is 0.
HYSE: DV
low-supply voltage-detector hysteresis-
DD
CPE: Charge-pump enable bit. Set CPE = 1 to enable the
charge-pump doubler, and set CPE = 0 to disable the
charge-pump doubler. The power-on default value is 0.
enable bit. Set HYSE = 1 to set the hysteresis for the
+1.8V (DV ) low-supply-voltage detector to +200mV,
DD
and set HYSE = 0 to set the hysteresis to +20mV. On initial
power-up, the hysteresis is +20mV and can be pro-
grammed to 200mV once RESET goes high. Once pro-
LSDE: DV
low-supply voltage-detector power-
DD
enable bit. Set LSDE = 1 to enable the +1.8V (DV
)
DD
grammed to +200mV, the DV
falling threshold is +1.8V
DD
low-supply-voltage detector, and set LSDE = 0 to
nominally and the rising threshold is +2.0V nominally. The
______________________________________________________________________________________ 57
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
hysteresis helps eliminate chatter when running directly off
unregulated batteries. If DV falls below +1.3V (typ), the
RSTE: RESET output enable bit. Set RSTE = 1 to
enable RESET to be controlled by the +1.8V DV low-
DD
DD
power-on reset circuitry is enabled and the HYSE bit is
deasserted setting the hysteresis back to +20mV. The
power-on default is 0.
supply-voltage detector, and set RSTE = 0 to disable
this control. The power-on default is 1.
STATUS Register (Power-On State: 0000 000X 0000 0000)
MSB
LDVD
LCPD
ADOU
SDC
CRDY
UPF4
ADD
ALD
X
LSB
UPF1
MAX1358B
UPR4
UPR3
UPR2
UPR1
UPF3
UPF2
The STATUS register contains the status bits of events in
various system blocks. Any status bits not masked in the
IMSK register cause an interrupt on INT. Some of the
status bit setting events (GPI, WAKEUP, ALARM, DRDY)
can be directed to UPIO_ to provide multiple µC inter-
rupt inputs. There are no specific mask bits for the UPIO
interrupt signals since the bits are effectively masked by
selecting a different function for UPIO. The STATUS bits
always record the triggering event(s), even for masked
bits, which do not generate an interrupt on INT. It is pos-
sible to set multiple STATUS bits during a single INT
interrupt event. Clear all STATUS bits except for ADD
and ADOU by reading the STATUS register. During a
STATUS register read, INT deasserts when the first
STATUS data bit (LDVD) reads out (9th rising SCLK) and
remains deasserted until shortly after the last STATUS
data bit (~15ns). At this point, INT reasserts if any
STATUS bit is set during the STATUS register read. If the
STATUS register is partially read (i.e., the read is aborted
midway), none of the STATUS bits are cleared. New
events occurring during a STATUS register read, or
events that persist after reading the STATUS bits result in
another interrupt immediately after the STATUS register
read finishes. This is a read-only register.
ADOU: ADC overflow/underflow status bit. ADOU = 1
indicates an ADC underflow or overflow condition in the
current ADC result. New conversions that are valid
clear the ADOU bit. ADOU = 0 when the ADC data is
valid or the ADC is disabled (ADCE = 0). An underflow
condition occurs when the ADC data is theoretically
less than 0000 hex in unipolar mode and less than
8000 hex in bipolar mode. An overflow condition occurs
when the ADC data is theoretically greater than FFFF
hex in unipolar mode and greater than 7FFF hex in
bipolar mode. Use this bit to determine the validity of
an ADC result at the maximum or minimum code values
(i.e., 0000 hex or FFFF hex for unipolar mode and 8000
hex and 7FFF hex for bipolar mode). The power-on
default is 0. Reading the STATUS register does not
clear the ADOU bit.
SDC: Signal-detect comparator status bit. When
SDC = 1, the positive input to the signal-detect compara-
tor exceeds the negative input plus the programmed
threshold voltage. The SDC bit clears during the STATUS
register read unless the condition remains true. The SDC
bit also deasserts when the signal-detect comparator
powers down (SDCE = 0). The power-on default is 0.
CRDY: High-frequency-clock ready status bit.
CRDY = 1 indicates a locked high-frequency clock to
the 32kHz reference frequency by the FLL. The CRDY
bit clears during the STATUS register read. This bit only
asserts after power-up or after enabling the FLL using
the FLLE bit. The power-on default is 0.
LDVD: Low DV
voltage-detector status bit. LDVD = 1
DD
indicates DV
is below the +1.8V threshold; otherwise
DD
LDVD = 0. LDVD clears during the STATUS register
read as long as the condition does not persist.
Otherwise, the LDVD bit reasserts immediately. If the
DV
low voltage detector is disabled, LDVD = 0. The
DD
ADD: ADC-done status bit. ADD = 1 indicates a com-
pleted ADC conversion or calibration. Clear the ADD bit
by reading the appropriate ADC data, offset, or gain-cali-
bration registers. The ADC status bit also clears when a
new ADC result updates to the data or calibration regis-
ters (i.e., it follows the assertion level of the UPIO =
DRDY signal). Reading the STATUS register does not
clear this bit. This bit is equivalent to the DRDY signal
available through UPIO_. The power-on default is 0.
power-on default is 0.
LCPD: Low CPOUT voltage-detector status bit. LCPD =
1 indicates CPOUT is below the +2.7V threshold; other-
wise LCPD = 0. LCPD clears during the STATUS regis-
ter read as long as the condition does not persist.
Otherwise the LCPD bit reasserts immediately. LCPD =
0 when the CPOUT low voltage detector is disabled.
The power-on default is 0.
58 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
ALD: Alarm (day) status bit. ALD = 1 when the value
programmed in ASEC<19:0> in the AL_DAY register
matches SEC<19:0> in the RTC register. Clear the ALD
bit by reading the STATUS register or by disabling the
day alarm (ADE = 0). The power-on default is 0.
When placing passive components in front of the
MAX11358B, ensure a low enough source impedance
to prevent introducing gain errors to the system. This
configuration significantly limits the amount of passive
anti-aliasing filtering that can be applied in front of the
MAX11358B. See Table 3 for acceptable source
impedances.
UPR<4:1>: User-programmable I/O rising-edge status
bits. UPR_ = 1 indicates a rising edge on the respec-
tive UPIO_ pin has occurred. Clear UPR_ by reading
the STATUS register. Rising edges are detected inde-
pendent of UPIO_ configuration, providing the ability to
capture and record rising input (e.g., WU) or output
(e.g., PWM) edge events on the UPIO_. Set the appro-
priate mask to determine if the edge will generate an
interrupt on INT. If the UPIO_ is configured as an out-
put, INT provides confirmation that an intended rising
edge output occurred and has reached the desired
Power-On Reset or Power-Up
After a power-on reset, the DV
voltage supervisor is
DD
enabled and all UPIOs are configured as inputs with
pullups enabled. The internal oscillators are enabled and
are output at CLK and CLK32K once the DV
voltage
DD
supervisor is cleared and the subsequent timeout period
has expired. All interrupts are masked except CRDY.
Figure 19 illustrates the timing of various signals during
initial power-up, sleep mode, and wake-up events. The
ADC, charge pump, internal reference, op amp(s), DAC,
and switches are disabled after power-up.
DV
or CPOUT level (i.e., was not loaded down exter-
DD
nally). The power-on default is 0.
UPF<4:1>: User-programmable I/O falling-edge status
bit. UPF_ = 1 indicates a falling edge on the respective
UPIO_ has occurred. Clear UPF_ by reading the
STATUS register. Falling edges are detected indepen-
dent of UPIO_ configuration, providing the ability to cap-
ture and record falling input (e.g., WU) or output (e.g.,
PWM) edge events on the UPIO_. Set the appropriate
mask to determine if that edge should generate an inter-
rupt on the INT pin. If the UPIO is configured as an out-
put, INT provides confirmation that an intended falling
edge output occurred at the pin and it reached the
desired DGND level. The power-on default is 0.
Power Modes
Two power modes are available for the MAX11358B:
sleep and normal mode. In sleep mode, all functional
blocks are powered down except the serial interface,
data registers, internal bandgap, wake-up circuitry (if
enabled), DV
voltage supervisor (if enabled), and
DD
the 32kHz oscillator (if enabled), which remain active.
See Table 15 for details of the sleep-mode and normal-
mode power states of the various internal blocks.
Each analog block can be shut down individually
through its respective control register with the excep-
tion of the bandgap reference.
Applications Information
Sleep Mode
Analog Filtering
The internal digital filter does not provide rejection
close to the harmonics of the modulator sample fre-
quency. However, due to high oversampling ratios in
the MAX11358B, these bands typically occupy a small
fraction of the spectrum and most broadband noise is
filtered. Therefore, the analog filtering requirements in
front of the MAX11358B are considerably reduced
compared to a conventional converter with no on-chip
filtering. In addition, because the deviceꢀs common-
mode rejection (60dB) extends out to several kHz, the
common-mode noise susceptibility in this frequency
range is substantially reduced.
Sleep mode is entered one of three ways:
• Writing to the SLEEP register address. The result is
the SHDN bit is set to 1.
• Asserting the SLEEP or SLEEP function on a UPIO
(SLEEP takes precedence over software writes or
wake-up events). The SHDN bit is unaffected.
• Asserting the SHDN bit by writing SLP = 1 in the
SLEEP_CFG register.
Entering sleep mode is an OR function of the UPIO or
SHDN bit. Before entering sleep mode, configure the
normal mode conditions.
Exit sleep mode and enter normal mode by one of the
following methods:
Depending on the application, provide filtering prior to the
MAX11358B to eliminate unwanted frequencies the digital
filter does not reject. Providing additional filtering in some
applications ensures that differential noise signals outside
the frequency band of interest do not saturate the analog
modulator.
• With the SHDN bit = 0, deassert the SLEEP or
SLEEP function on UPIO, only if SLEEP or SLEEP
function is used for entering sleep mode.
______________________________________________________________________________________ 59
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
INITIAL POWER, WAKE-UP, AND SLEEP
2
1
XTAL BETWEEN 32KIN AND 32KOUT PIN
1.8V
AV
DV
DD
DD
0V
2
1.8V
1
0V
HI
POR
MAX1358B
LO
OSCE = 1
SOSCE = 1
SCK32E = 0
OSCE = 1
CK32E = 1
HI
XIN, XOUT
(32kHz)
LO
CK32E = 1
HI
CK32K
(32kHz)
BUFFER DISABLED
LO
HI
LO
HI
RESET
(OPEN DRAIN)
INTERNAL
EXTERNAL
OUTPUT DISABLED,
BUT
PULLED LOW
INTERNAL
LOW DV DETECTOR
OUTPUT ENABLED
DD
LO
HI
UPIO (WU)
(INT. PULLUP)
t
WU
LO
t
DPU
HI
UPIO (SHDN)
CLK
INTERNAL
LO
t
DPD
HI
INTERNAL
LO
t
t
t
DFON
DFON
DFOF
INTERNAL
CRDY
HFCE = 1, FLLE = 1
HI
IF FLLE = 0, CRDY WILL
STAY LOW, DFON = 0
LO
t
t
DFI
DFI
HI
INT
LO
PWME = 0
PWME = 0
POWER SUPPLY OFF
SPWME = 1
UPIO (PWM)
CONNECTED TO POWER
SUPPLY SHDN PIN
HI
LO
HI
POWER SUPPLY OFF
INTERNAL
DRDY
LO
HI
DOUT
CS
THREE-STATED
LO
HI
SLEEP
WRITE
LO
HI
SCLK,
DIN
LO
Figure 19. Initial Power-Up, Sleep Mode, and Wake-Up Timing Diagram with AV
> 1.8V
DD
60 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
V
/GAIN
V
/GAIN
V
/GAIN
REF
REF
REF
1111 1111 1111 1111
1111 1111 1111 1110
1111 1111 1111 1101
1111 1111 1111 1100
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
FULL-SCALE TRANSITION
V
V
REF
REF
1 LSB =
1 LSB =
x 2
(GAIN x 65,536)
(GAIN x 65,536)
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
0
65,533 65,535
-32,768
-1
0
+1
+32,765 +32,767
1
2
3
-32,766
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 20. ADC Unipolar Transfer Function
Figure 21. ADC Bipolar Transfer Function
• With the SLEEP or SLEEP function deasserted on
UPIO, clear the SHDN bit by writing to the normal-
mode register address control byte.
MAX11358B
FBA
FBB
• With the SLEEP or SLEEP function deasserted,
assert WU or WU (wake-up) function on UPIO.
OUTA
OUTB
DAC A
• With the SLEEP or SLEEP function deasserted, the
day alarm triggers.
REF
Wake-Up
A wake-up event, such as an assertion of a UPIO con-
figured as WU or a time-of-day alarm causes the
MAX11358B to exit sleep mode, if in sleep mode. A
wake-up event in normal mode results only in a wake-up
event being recorded in the STATUS register.
DAC B
Figure 22. DAC Unipolar Output Circuit
RESET
Supply Voltage Measurement
The RESET output pulls low for any one of the following
The AV
supply voltage can be measured with the
DD
cases: power-on reset, DV
monitor trips and
RSTE = 0, watchdog timer expires, crystal oscillator is
attached, and 32kHz clock not ready.
DD
ADC by reversing the normal input and reference sig-
nals. The REF voltage is applied to one multiplexer
input, and AGND is selected in the other. The AV
DD
The RESET output can be turned off through the RSTE
signal is then switched in as the ADC reference voltage
bit in the PS_VMONS register, causing DV
low sup-
DD
and a conversion is performed. The AV
then be calculated directly as:
value can
DD
ply voltage events to issue an interrupt or poll through
the LDVD status bit. This allows brownout detection
V
AVDD
= (V
x Gain x 65,536)/N
REF
µCs that operate with DV
< 1.8V.
DD
where V
is the reference voltage for the ADC, Gain
REF
Driving UPIO Outputs to AV
Levels
DD
is the PGA gain before the ADC, and N is the ADC
result. Note the AV voltage must be greater than the
UPIO outputs can be driven to AV
levels in systems
DD
DD
with separate AV
and DV
supplies. Disable the
DD
DD
gained-up REF voltage (AV
measurement must be done in unipolar mode.
> V
x Gain). This
REF
DD
charge-pump doubler by setting CPE = 0 in the
PS_VMONS register, and connect the systemꢀs analog
supply to AV
and CPOUT. Setting UPIO outputs to
DD
drive to CPOUT results in AV -referenced logic levels.
DD
______________________________________________________________________________________ 61
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V
REF
R
1
R
2
10kΩ
FBA
MAX11358B
FB_
+3.3V
10kΩ
V
OUT
OUTA
OUTB
DAC A
DAC_
OUT_
-3.3V
10kΩ
REF
FBB
R = R
2
1
V
REF
= 1.25V
MAX11358B
10kΩ
5
DAC B
Figure 24. DAC Bipolar Output Circuit
In unipolar mode, the output code ranges from 0 to
65,535 for inputs from zero to full-scale. In bipolar
mode, the output code ranges from -32,768 to +32,767
for inputs from negative full-scale to positive full-scale.
V
= 1.25V
REF
Figure 23. DAC Unipolar Rail-to-Rail Output Circuit
Power Supplies
DAC Unipolar Output
For a unipolar output, the output voltages and the refer-
ence have the same polarity. Figure 22 shows the
unipolar output circuit of the MAX11358B, which is also
the typical operating circuit for the DAC. Table 22 lists
some unipolar input codes and their corresponding
output voltages.
AV
and DV
provide power to the MAX11358B. The
DD
DD
AV powers up the analog section, while the DV pow-
DD
DD
ers up the digital section. The power supply for both AV
DD
and
and DV
ranges from +1.8V to +3.6V. Both AV
DD
DD
DV
must be greater than +1.8V for device operation.
DD
AV
and DV
can connect to the same power supply.
to AGND with a 10µF electrolytic capacitor
DD
DD
Bypass AV
DD
For larger output swing, see Figure 23. This circuit
shows the output amplifiers configured with a closed-
loop gain of +2V/V to provide 0 to 2.5V full-scale range
with the 1.25V reference.
in parallel with a 0.1µF ceramic capacitor, and bypass
DV to DGND with a 10µF electrolytic capacitor in paral-
lel with a 0.1µF ceramic capacitor. For improved perfor-
mance, place the bypass capacitors as close to the device
as possible.
DD
DAC Bipolar Output
The MAX11358B DAC output can be configured for
bipolar operation using the application circuit in
Figure 24:
ADC Transfer Functions
Figures 20 and 21 provide the ADC transfer functions
for unipolar and bipolar mode. The digital output code
format is binary for unipolar mode and twoꢀs comple-
ment for bipolar mode. Calculate 1 LSB using the fol-
lowing equations:
⎡
⎢
⎣
⎤
2N
1024
⎛
⎞
V
= V
− 1
⎜
⎝
⎟
⎠
⎥
⎦
OUT
REF
1 LSB (Unipolar Mode) = V /(Gain x 65,536)
REF
where N is the decimal value of the DACꢀs binary input code.
1 LSB (Bipolar Mode) = 2V
/(Gain x 65,536)
REF
Table 23 shows digital codes (offset binary) and corre-
sponding output voltages for Figure 24 assuming
R = R .
where V
equals the reference voltage at REF and
REF
Gain equals the PGA gain.
1
2
Table 22. Unipolar Code
Table 23. Bipolar Code
DAC CONTENTS
DAC CONTENTS
ANALOG OUTPUT
ANALOG OUTPUT
MSB
LSB
MSB
LSB
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
+V
(511/512)
(1/512)
0
1111 1111 11
1000 0000 01
1000 0000 00
0111 1111 11
0000 0000 01
0000 0000 00
+V
+V
(1023/1024)
(513/1024)
REF
REF
REF
REF
+V
(512/1024) = +V
/2
REF
REF
-V
(1/512)
+V
+V
(511/1024)
(1/1024)
REF
REF
-V
REF
(511/512)
REF
-V
(512/512) = -V
REF
0
REF
62 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
Clocking with a CMOS Signal
A CMOS signal can be used to drive 32KIN if it is divid-
ed down. Figure 25 is an example circuit, which works
well.
Temperature Measurement with
Two Remote Sensors
Use two diode-connected 2N3904 transistors for exter-
nal temperature sensing in Figure 29. Select AIN1 and
AIN2 through the positive and negative mux, respec-
tively. For internal temperature sensor measurements,
set MUXP<3:0> to 0111, and set MUXN<3:0> to 0000.
The analog input signals feed through a PGA to the
ADC for conversion.
Input Multiplexer
The mux inputs can range between AGND and AV
.
DD
However, when the internal temperature sensor is
enabled, AIN1 and AIN2 cannot exceed 0.7V. This
necessitates additional circuitry to divide down the
input signal. See Figure 26 for an example circuit that
The MAX11358B integrated PWM is available for LCD
bias control, sensor-bias voltage trimming, buzzer drive,
and duty-cycled sleep-mode power-control schemes.
Figure 31 shows the MAX11358B performing LCD bias
control. A sensor-bias voltage trimming application is
shown in Figure 32. Figures 34 and 35 show the PWM
circuitry being used in a single-ended and differential
piezoelectric buzzer-driving application.
divides down backlight V
AIN1 pin.
to work properly with the
DD
Optical Reflectometry Application with
Dual LED and Single Photodiode
Figure 27 illustrates the MAX11358B in a complete opti-
cal reflectometry application with two transmitting LEDs
and one receiving photodiode. The LEDs transmit light
at a specific wavelength onto the sample strip, and the
photodiode receives the reflections from the strip. Set
the DAC to provide appropriate bias currents for the
LEDs. Always keep the photodiodes reverse-biased or
zero-biased. SPDT1 and SPDT2 switch between the
two LEDs.
ADC Calibration
Internal to the MAX11358B, the ADC is 24 bits and is
always in bipolar mode. The OFFSET CAL and GAIN
CAL data is also 24 bits. The conversion to unipolar and
the gain are performed digitally. The default values for
the OFFSET CAL and GAIN CAL registers in the
MAX11358B are 00 0000h and 80 0000h, respectively.
Electrochemical Sensor Operation
The MAX11358B family interface with electrochemical
sensors. The 10-bit DAC with the force-sense buffers
have the flexibility to connect to many different types of
sensors. An external precision resistor completes the
transimpedance amplifier configuration to convert the
current generated by the sensor to a voltage measure-
ment using the ADC. The induced error from this source
is negligible due to FBAꢀs extremely low input bias cur-
rent. Internally, the ADC can differentially measure
directly across the external transimpedance resistor,
RF, eliminating any errors due to voltages drifting over
time, temperature, or supply voltage.
The calibration works as follows:
ADC = (RAW - OFFSET) x Gain x PGA
where ADC is the conversion result in the DATA register,
RAW is the output of the decimation filter internal to the
MAX11358B, OFFSET is the value stored in the OFFSET
CAL register, Gain is the value stored in the GAIN CAL
register, and PGA is the selected PGA gain found in the
ADC register as GAIN<1:0>. In unipolar mode, all nega-
tive values return a zero result and an additional gain of 2
is added.
BACKLIGHT
V
BATT2
V
DD
100kΩ
V
BATT1
CMOS CLOCK
32KIN
GPIOn
(0 TO DV
)
DD
UPIO1
MAX11358B
NOTE:
100kΩ
GPIOn IS LOW = LED ON,
HIGH-Z = LED OFF
BATTVCHECK < 0.6125V
MAX11358B
x2
AIN1
V
REF
= 1.25V
μP
Figure 25. Clocking with a CMOS Signal
______________________________________________________________________________________ 63
Figure 26. Input Multiplexer
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
V
CP
TXD
RXD
SERIAL-PORT INTERFACE
V
SS
V
SS
μC
V
BAT
EEPROM
V
SS
MOSI
V
CC
SI
SO
MISO
SCK
CS1
SCK
CS
GND
MAX1358B
V
SS
V
CP
MAX11358B
LCD MODULE
BDIN
BDOUT
BSCLK
BCS2
UPIO1
UPIO2
UPIO3
UPIO4
DIN
DOUT
SCLK
CS
V
SS
CS2
CS2
MEM
UP
RESET
INT
RESET
INPUT
X2IN
INPUT
INPUT
INPUT
HIGH-FREQUENCY MICRO CLOCK
32kHz MICRO CLOCK
DOWN
CLK
IN1-
32KIN
CLK32K
V
SS
IN1+
AV
DD
V
BAT
OUT1
V
SS
DV
DD
V
SS
V
DD
2 AAA OR
1 LITHIUM
COIN CELL
1nF
SNO2
SCM2
ADC
TEST
STRIP
V
SS
AGND
DGND
V
SS
SNC2
V
SS
PWM
DACA
AIN1
AIN2
AMBIENT LIGHT
LED SOURCES
V
CP
OUTA
32KIN
LED
SWA
FBA
V
CP
32.768kHz
SNO1
LED
SCM1
SNC1
32KOUT
DV
DD
LINEAR
REG
REG
CF+
REF
CHARGE-
V
SS
PUMP
DOUBLER
BG
CF-
CPOUT
V
CP
V
SS
V
SS
V
SS
Figure 27. Optical Reflectometry Application with Dual LED and Single Photodiode
64 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
μC
V
CP
LCD GLA SS
COM<3:0>
SEG<23:0>
LCDBIAS
RX_WAKEUP
SERIAL-PORT INTERFACE
RXD
V
SS
LCD
DRIVERS
V
SS
BUZ_HI
BUZ_LO
PIEZO
ALARM
V
BAT
EEPROM
MOSI
V
CC
SI
V
SS
SO
MISO
SCK
CS1
SCK
CS
GND
V
SS
MAX11358B
CPOUT
UPIO2
DIN
TXD
CS2
DOUT
UPIO1
UPIO3
RX_WAKEUP
CPOUT
PWM
LCDBIAS
SCLK
CS
CS2
STRIP INSERTED
UPIO4
V
SS
MEM
UP
RESET
INT
OUTA
SWA
FBA
RESET
INPUT
X2IN
INPUT
TEST
STRIP
INPUT
INPUT
HIGH-FREQUENCY MICRO CLOCK
32kHz MICRO CLOCK
DOWN
CLK
32KIN
CLK32K
V
SS
AV
DD
V
BAT
V
SS
DV
DACA
DD
V
DD
OUTB
SWB
FBB
2 AAA OR
1 LITHIUM
COIN CELL
ADC
V
AGND
DGND
SS
V
SS
DACB
SNO1
SCM1
SNC1
32KIN
OUT1
IN1-
IN1+
REF
32.768kHz
32KOUT
DV
DD
LINEAR
REG
BG
REG
CF+
SNO2
SCM2
SNC2
CHARGE-
PUMP
DOUBLER
V
SS
CF-
CPOUT
V
CP
V
AIN1
AIN2
SS
V
SS
REMOTE TEMPERATURE-
MEASUREMENT DIODE
V
SS
Figure 28. Electrochemical Meter Application Circuit (Traditional and Counter Configuration)
______________________________________________________________________________________ 65
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
For self-calibration, the offset value is the RAW result
when the inputs are shorted internally and the gain value
is 1/(RAW - OFFSET) with the reference connected to the
input. This is done automatically when these modes are
selected. The self-offset and gain calibration corrects for
errors internal to the ADC and the results are stored and
used automatically in the OFFSET CAL and GAIN CAL
registers. For best results, use the ADC in the same con-
figuration as the calibration. This pertains to conversion
rate only because the PGA gain and unipolar/bipolar
modes are performed digitally.
log ground plane under the MAX11358B to minimize
coupling of digital noise. Make the power-supply lines
to the MAX11358B as wide as possible to provide low-
impedance paths and reduce the effects of glitches on
the power-supply line.
Shield fast-switching signals such as clocks with digital
ground to avoid radiating noise to other sections of the
board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Good decoupling is important when using high-resolu-
tion ADCs. Decouple all analog supplies with 10µF
capacitors in parallel with 0.1µF HF ceramic capacitors
to AGND. Place these components as close to the
device as possible to achieve the best decoupling.
MAX1358B
For system calibration, the offset and gain values cor-
rect for errors in the whole signal path including the
internal ADC and any external circuits in the signal
path. For the system calibration, a user-provided zero-
input condition is required for the offset calibration and
a user-provided full-scale input is required for the gain
calibration. These values are automatically written to
the OFFSET CAL and GAIN CAL registers. The order of
the calibrations should be offset followed by gain.
Crystal Layout
Follow basic layout guidelines when placing a crystal
on a PCB with a DAS to avoid coupled noise:
1) Place the crystal as close as possible to 32KIN and
32KOUT. Keeping the trace lengths between the
crystal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae”. Keep the 32KIN and 32KOUT
lines close to each other to minimize the loop area
of the clock lines. Keeping the trace lengths short
also decreases the amount of stray capacitance.
The offset correction value is in twoꢀs complement. The
default value is 000000h, 00...00b, or 0 decimal.
The gain correction value is an unsigned binary number
with 23 bits to the right of the decimal point. The largest
number is therefore 1.1111...1b = 2 - 2-23 and the small-
est is 0.000...0b = 0, although it does not make sense to
use a number smaller than 0.1000...0b = 0.5. The default
value is 800000h, 1.000...0b or 1 decimal.
2) Keep the crystal solder pads and trace width to
32KIN and 32KOUT as small as possible. The larg-
er these bond pads and traces are, the more likely
it is that noise will couple from adjacent signals.
Changing the offset or gain calibration values does not
affect the value in the DATA register until a new conver-
sion has completed. This applies to all the mode bits
for PGA gain, unipolar/bipolar, etc.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled
from adjacent signals.
Grounding and Layout
For best performance, use a PCB with separate analog
and digital ground planes.
4) Ensure that no signals on other PCB layers run
directly below the crystal or below the traces to
32KIN and 32KOUT. The more the crystal is isolat-
ed from other signals on the board, the less likely it
is that noise will be coupled into the crystal.
Maintain a minimum distance of 5mm between any
digital signal and any trace connected to 32KIN or
32KOUT.
Design the PCB so that the analog and digital sections
are separated and confined to different areas of the
board. Join the digital and analog ground planes at one
point. If the DAS is the only device requiring an AGND-to-
DGND connection, connect planes to the AGND pin of the
DAS. In systems where multiple devices require AGND-to-
DGND connections, the connection should still be made
at only one point. Make the star ground as close as possi-
ble to the MAX11358B.
5) Place a local ground plane on the PCB layer imme-
diately below the crystal guard ring. This helps to
isolate the crystal from noise coupling from signals
on other PCB layers.
Avoid running digital lines under the device because
these may couple noise onto the device. Run the ana-
Note: The ground plane must be in the vicinity of the
crystal only and not on the entire board.
66 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
AIN1
PGA
16-BIT ADC
MUX
MUX
REF
AGND
AIN2
A = 1, 2, 4, 8
V
2N3904
2N3904
MAX11358B
AGND
A = 1, 1.638, 2
V
C
REF
REF
TEMP
SENSOR
1.25V
REF
Figure 29. Temperature Measurement with Two Remote Sensors
Gain Error
Parameter Definitions
Gain error is the amount of deviation between the mea-
sured full-scale transition point and the ideal full-scale
transition point.
INL
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line is either a best-straight-line fit or a line drawn
between the end points of the transfer function, once off-
set and gain errors have been nulled. INL for the
MAX11358B is measured using the end-point method.
Common-Mode Rejection
Common-mode rejection (CMR) is the ability of a
device to reject a signal that is common to both input
terminals. The common-mode signal can be either an
AC or a DC signal or a combination of the two. CMR is
often expressed in decibels.
DNL
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A DNL
error specification of greater than -1 LSB guarantees no
missing codes and a monotonic transfer function.
Power-Supply Rejection Ratio (PSRR)
Power-supply rejection ratio (PSRR) is the ratio of the
input supply change (in volts) to the change in the
converter output (in volts). It is typically measured in
decibels.
______________________________________________________________________________________ 67
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX11358B
DV CPOUT
DD
CPOUT
UPIO_
MUX
SV_
100kΩ
200kΩ
(1.8V
TO
μC
PWM
0.01μF
100kΩ
2.6V)
MAX1358B
EN_
SEG
n
ALH_
LCD
DRIVERS
100kΩ
100kΩ
LCD
COM
m
Figure 30. LCD Contrast-Adjustment Application
~1.25V
REF
~19kHz
VOLTAGE
MAX11358B
240kΩ
RIPPLE < 1mV
SNO1
350kΩ
SCM1
SNC1
PWM
~0.3V
60kΩ
SPDT1
0.1μF
AGND
IN1+
IN1-
OUT1
I
T
TRANSDUCER
0.300V ( 1mV)
Figure 31. Sensor-Bias Voltage Trim Application
68 ______________________________________________________________________________________
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
MAX1358B
V
DD
AV
DV
DD
DD
MAX11358B
DV
< 10μA
CPOUT
DD
V
DD
V
OUT
V
IN
MUX
SV_
V
BATT
μC
100μF
POWER SUPPLY
10MΩ
UPIO_
EN_
SHDN
PWM
PSCTL
ON-TIME <100ms TYP
10s PERIOD TYP
PSCTL
+3.3V
V
ALH_
DD
+2.3V
Figure 32. Power-Supply Sleep-Mode Duty-Cycle Control
DV
CPOUT
DD
MAX11358B
SV_
MUX
CPOUT(+3.2V)
0V
1kHz TO 8kHz TYP
~10,000pF
1kΩ
UPIO_
PWM
ALH_
Figure 33. Single-Ended Piezoelectric Buzzer Drive
______________________________________________________________________________________ 69
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
DV CPOUT
DD
CPOUT(+3.2V)
0V
MAX11358B
MUX
SV_
1kHz TO 8kHz TYP
1kΩ
UPIO_
PWM
MAX1358B
CPOUT
+
6.4V DIFF
-
~10,000pF
ALH_
-CPOUT
DV CPOUT
DD
MUX
SV_
1kΩ
UPIO_
CPOUT(~+3.2V)
0V
1kHz TO 8kHz TYP
ALH_
Figure 34. Differential Piezoelectric Buzzer Drive
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 TQFN-EP
T4066+5
21-0141
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
70 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明