MAX1157BCUI [MAXIM]
Analog to Digital Converter ; 模拟数字转换器\n
| 型号： | MAX1157BCUI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Analog to Digital Converter
|
| 文件： | 总15页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2653; Rev 0; 10/02
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
General Description
Features
o Analog Input Voltage Range 1ꢀVꢁ ꢂVꢁ oꢃ ꢀ to 1ꢀV
o 14-Bit Wide Paꢃallel Inteꢃface
The MAX1157/MAX1159/MAX1175 14-bit, low-power,
successive-approximation analog-to-digital converters
(ADCs) feature automatic power-down, factory-trimmed
internal clock, and 14-bit wide parallel interface. The
devices operate from a single +4.75V to +5.25V analog
supply and feature a separate digital supply input for
direct interface with +2.7V to +5.25V digital logic.
o Single +4.7ꢂV to +ꢂ.2ꢂV Analog Supply Voltage
o Inteꢃfaces with +2.7V to +ꢂ.2ꢂV Digital Logic
o
o
1LSB IꢄL ꢅ(aꢆx
1LSB DꢄL ꢅ(aꢆx
The MAX1157 accepts an analog input voltage range
from 0 to +10V while the MAX1159 accepts a bipolar
analog input voltage range of 10V. The MAX1175
accepts a bipolar analog input voltage range of 5V.
All devices consume only 23mW at a sampling rate
of 135ksps when using an external reference and
29mW when using the internal +4.096V reference.
AutoShutdown™ reduces supply current to 0.4mA at
10ksps. The MAX1157/MAX1159/MAX1175 are ideal for
high-performance, battery-powered data-acquisition
applications. Excellent AC performance (THD = -100dB)
and DC accuracy ( 1ꢀSB ꢁIꢀ) make the MAX1157/
MAX1159/MAX1175 ideal for industrial process control,
instrumentation, and medical applications.
o Low Supply Cuꢃꢃent ꢅMAX11ꢂ9x
ꢂ.3(A ꢅEꢆteꢃnal Refeꢃencex
6.2(A ꢅInteꢃnal Refeꢃencex
ꢂµA AutoShutdown Mode
o S(all Footpꢃint
28-Pin TSSOP Package
Pin Configuration
TOP VIEW
The MAX1157/MAX1159/MAX1175 are available in a
28-pin TSSOP package and are fully specified over the
-40°C to +85°C extended temperature range and the
0°C to +70°C commercial temperature range.
D6
D7
1
2
3
4
5
6
7
8
9
28 D5
27 D4
26 D3
25 D2
24 D1
23 D0
22 N.C.
21 N.C.
D8
D9
D10
D11
D12
D13
R/C
MAX1157
MAX1159
MAX1175
Applications
Temperature Sensing and Monitoring
ꢁndustrial Process Control
ꢁ/O Modules
20 DV
DD
EOC 10
AV 11
19 DGND
18 CS
Data-Acquisition Systems
Precision ꢁnstrumentation
DD
AGND 12
AIN 13
17 RESET
16 REF
AGND 14
15 REFADJ
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
TSSOP
Ordering Information
IꢄPUT VOLTAGE
RAꢄGE
PART
TEMP RAꢄGE
PIꢄ-PACKAGE
IꢄL ꢅLSBx
MAX11ꢂ7ACUI*
0°C to +70°C
0°C to +70°C
28 TSSOP
28 TSSOP
0 to +10V
0 to +10V
1
2
MAX1157BCUI*
Ordering Information continued at end of data sheet.
*Future product—contact factory for availability.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Continuous Power Dissipation (T = +70°C)
28-Pin TSSOP (derate 12.8mW/°C above +70°C) .....1026mW
A
AGND to DGND.....................................................-0.3V to +0.3V
AIN to AGND .....................................................-16.5V to +16.5V
Operating Temperature Range
MAX11_ _CUI......................................................0°C to +70°C
MAX11_ _EUI...................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
REF, REFADJ to AGND............................-0.3V to (AV
+ 0.3V)
DD
CS, R/C, RESET to DGND ........................................-0.3V to +6V
D_, EOC to DGND ...................................-0.3V to (DV + 0.3V)
DD
Maximum Continuous Current Into Any Pin ........................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +5V, external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , T = T
to T
, unless
MAX
DD
DD
REF
REFADJ
REFADJ
DD
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
DC ACCURACY
SYMBOL
COꢄDITIOꢄS
MIꢄ
TYP
MAX
UꢄITS
Resolution
RES
DNL
14
-1
-1
-2
Bits
Differential Nonlinearity
No missing codes over temperature
MAX11_ _A
+1
+1
+2
LSB
Integral Nonlinearity
Transition Noise
Offset Error
INL
LSB
MAX11_ _B
RMS noise, external reference
Internal reference
0.32
0.34
0
LSB
RMS
MAX1159
-10
-10
+10
+10
0.2
mV
MAX1157/MAX1175
Gain Error
Offset Drift
Gain Drift
0
16
1
%FSR
µV/°C
ppm/°C
AC ACCURACY ꢅf = 1kHzꢁ V
Iꢄ
= full ꢃangeꢁ 13ꢂkspsx
AIꢄ
Signal-to-Noise Plus Distortion
Signal-to-Noise Ratio
SINAD
SNR
81
82
85
85
dB
dB
dB
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
AꢄALOG IꢄPUT
THD
-100
103
-86
SFDR
87
MAX1157
0
-10
-5
+10
+10
+5
Input Range
V
V
MAX1159
AIN
AIN
MAX1175
MAX1157/MAX1175
MAX1175
Normal operation
5.3
3
6.9
10
9.2
Shutdown mode
Normal operation
Shutdown mode
Input Resistance
R
kΩ
7.8
6
13.0
MAX1159
2
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS ꢅcontinuedx
(AV
= DV
= +5V, external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , T = T
to T
, unless
MAX
DD
DD
REF
REFADJ
REFADJ
DD
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
COꢄDITIOꢄS
MIꢄ
-0.1
-1.8
-1.8
-1.8
-1.8
TYP
MAX
+2.0
+1.2
+1.8
+0.4
+1.8
UꢄITS
MAX1157, 0 ≤ V
≤ +10V
AIN
Normal operation
Shutdown mode
Normal operation
Shutdown mode
MAX1159,
-10V ≤ V
≤ +10V
Input Current
I
AIN
mA
AIN
MAX1175,
-5V ≤ V
≤ +5V
AIN
MAX1159, V
operating mode
= +10V, shutdown mode to
AIN
0.5
0.7
1.4
Input Current Step at Power-Up
I
mA
pF
PU
MAX1175, V
= +5V, shutdown mode to
AIN
1
operating mode
Input Capacitance
C
10
IN
IꢄTERꢄAL REFEREꢄCE
REF Output Voltage
V
4.056
3.8
4.096
35
4.136
V
REF
REF Output Tempco
ppm/°C
mA
REF Short-Circuit Current
EXTERꢄAL REFEREꢄCE
I
10
REF-SC
REF and REFADJ Input Voltage
Range
4.2
V
V
AV
-
AV
-
DD
DD
REFADJ Buffer Disable Threshold
REF Input Current
0.4
0.1
Normal mode, f
= 135ksps
60
0.1
16
100
10
SAMPLE
I
µA
µA
REF
Shutdown mode (Note 1)
REFADJ = AV
REFADJ Input Current
I
REFADJ
DD
DIGITAL IꢄPUTS/OUTPUTS
I
= 0.5mA, DV
= +5.25V
= +2.7V to +5.25V, DV
DD DD
-
SOURCE
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
V
V
V
V
V
OH
AV
0.4
DD
I
= 1.6mA, DV
= +5.25V
= +2.7V to +5.25V,
DD
SINK
V
0.4
OL
AV
DD
0.7 ×
V
IH
DV
DD
0.3 ×
V
IL
DV
DD
Input Leakage Current
Input Hysteresis
Digital input = DV
or 0
-1
+1
µA
V
DD
V
0.2
15
HYST
Input Capacitance
C
pF
µA
pF
IN
Three-State Output Leakage
Three-State Output Capacitance
I
10
OZ
C
15
OZ
_______________________________________________________________________________________
3
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
ELECTRICAL CHARACTERISTICS ꢅcontinuedx
(AV
= DV
= +5V, external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , T = T
to T
, unless
MAX
DD
DD
REF
REFADJ
REFADJ
DD
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
POWER SUPPLIES
SYMBOL
COꢄDITIOꢄS
MIꢄ
TYP
MAX
UꢄITS
Analog Supply Voltage
Digital Supply Voltage
AV
DV
4.75
2.70
5.25
5.25
2.9
V
V
DD
DD
MAX1157
External reference,
135ksps
MAX1159/MAX1175
MAX1157
4.0
5.3
Analog Supply Current
I
mA
AVDD
3.8
Internal reference,
135ksps
MAX1159/MAX1175
5.2
0.5
3.7
6.2
Shutdown mode (Note 1), digital input =
DV or 0
5
µA
Shutdown Supply Current
I
DD
SHDN
DVDD
Standby mode
mA
mA
Digital Supply Current
Power-Supply Rejection
I
0.75
AV
= DV
= +4.75V to +5.25V
DD
1
LSB
DD
TIMIꢄG CHARACTERISTICS ꢅFiguꢃes 1 and 2x
(AV
= +4.75V to +5.25V, DV
= +2.7V to AV , external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV
,
DD
DD
DD
REF
REFADJ
REFADJ
DD
C
LOAD
= 20pF, T = T
to T
.)
A
MIN
MAX
PARAMETER
SYMBOL
COꢄDITIOꢄS
MIꢄ
TYP
MAX
UꢄITS
ksps
µs
Maximum Sampling Rate
Acquisition Time
f
135
SAMPLE-MAX
t
2
ACQ
Conversion Time
t
4.7
µs
CONV
CS Pulse Width High
t
(Note 2)
(Note 2)
40
40
60
0
ns
CSH
DV
DV
= +4.75V to +5.25V
= +2.7V to +5.25V
DD
DD
CS Pulse Width Low
t
ns
ns
ns
CSL
R/C to CS Fall Setup Time
R/C to CS Fall Hold Time
t
DS
DV
DV
DV
DV
= +4.75V to +5.25V
= +2.7V to +5.25V
= +4.75V to +5.25V
= +2.7V to +5.25V
40
60
DD
DD
DD
DD
t
DH
40
80
CS to Output Data Valid
EOC Fall to CS Fall
t
ns
ns
ns
DO
t
0
DV
DV
DV
DV
DV
= +4.75V to +5.25V
= +2.7V to +5.25V
= +4.75V to +5.25V
= +2.7V to +5.25V
40
80
40
80
DD
DD
DD
DD
CS Rise to EOC Rise
t
EOC
Bus Relinquish Time
t
ns
BR
ꢄote 1: Maximum specification is limited by automated test equipment.
ꢄote 2: To ensure best performance, finish reading the data and wait t before starting a new acquisition.
BR
4
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Typical Operating Characteristics
(AV
= DV
= +5V, external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , C
= 20pF, T = T
MIN
to
DD
DD
REF
REFADJ
REFADJ
DD
LOAD
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.) (Typical Application Circuit)
A
SUPPLY CURRENT (AV + DV
DD
)
DD
INL vs. CODE
DNL vs. CODE
vs. TEMPERATURE
4.80
4.75
4.70
4.65
4.60
4.55
4.50
4.45
4.40
2.5
1.0
0.8
2.0
1.5
5.25V
5.0V
0.6
1.0
0.4
4.75V
0.5
0.2
0
0
-0.5
-1.0
-1.5
-2.0
-2.5
-0.2
-0.4
-0.6
-0.8
-1.0
f
= 135ksps
SAMPLE
SHUTDOWN MODE BETWEEN
CONVERSIONS
-40
-20
0
20
40
60
80
0
4096
8192
12288
16384
0
4096
8192
12288
16384
TEMPERATURE (°C)
CODE
CODE
SUPPLY CURRENT (AV + DV
DD
)
SHUTDOWN CURRENT (AV + DV )
DD DD
DD
vs. SAMPLE RATE
vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
1
10
8
NO CONVERSIONS
MAX1159
STANDBY
MODE
6
4
0.1
2
0
SHUTDOWN
MODE
0.01
0.001
0.0001
-2
-4
-6
-8
-10
V
= 0V
AIN
-40
-20
0
20
40
60
80
0.01
0.1
1
10
100
1000
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
SAMPLE RATE (ksps)
TEMPERATURE (°C)
INTERNAL REFERENCE
vs. TEMPERATURE
FFT AT 1kHz
GAIN ERROR vs. TEMPERATURE
0
-20
0.20
0.15
0.10
0.05
0
4.136
4.126
4.116
4.106
4.096
4.086
4.076
4.066
4.056
f
= 135ksps
SAMPLE
-40
-60
-80
-100
-120
-140
-160
-180
-0.05
-0.10
-0.15
-0.20
0
20
40
60
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
FREQUENCY (kHz)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
ꢂ
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Typical Operating Characteristics
(AV
= DV
= +5V, external reference = +4.096V, C
= 10µF, C
= 0.1µF, V
= AV , C
= 20pF, T = T
to
MIN
DD
DD
REF
REFADJ
REFADJ
DD
LOAD
A
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.) (Typical Application Circuit)
A
SPURIOUS-FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
SINAD vs. FREQUENCY
vs. FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
1
10
100
1
10
100
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
Pin Description
PIꢄ
1
ꢄAME
FUꢄCTIOꢄ
D6
D7
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
Three-State Digital Data Output
2
3
D8
4
D9
5
D10
D11
D12
D13
6
7
8
Three-State Digital Data Output (MSB)
Read/Convert Input. Power up and place the MAX1157/MAX1159/MAX1175 in acquisition mode by
holding R/C low during the first falling edge of CS. During the second falling edge of CS, the level on
R/C determines whether the reference and reference buffer power down or remain on after
conversion. Set R/C high during the second falling edge of CS to power down the reference and
buffer, or set R/C low to leave the reference and buffer powered up. Set R/C high during the third
falling edge of CS to put valid data on the bus.
9
R/C
10
11
12
13
14
EOC
End of Conversion. EOC drives low when conversion is complete.
Analog Supply Input. Bypass with a 0.1µF capacitor to AGND.
Analog Ground. Primary analog ground (star ground).
Analog Input
AV
DD
AGND
AIN
AGND
Analog Ground. Connect pin 14 to pin 12.
6
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Pin Description (continued)
PIꢄ
ꢄAME
FUꢄCTIOꢄ
Reference Buffer Output. Bypass REFADJ with a 0.1µF capacitor to AGND for internal reference
15
REFADJ
mode. Connect REFADJ to AV
to select external reference mode.
DD
Reference Input/Output. Bypass REF with a 10µF capacitor to AGND. REF is the external reference
input when in external reference mode.
16
17
REF
RESET
Reset Input. Logic high resets the device.
Convert Start. The first falling edge of CS powers up the device and enables acquisition when R/C
is low. The second falling edge of CS starts conversion. The third falling edge of CS loads the result
onto the bus when R/C is high.
18
CS
19
20
DGND
Digital Ground
DV
Digital Supply Voltage. Bypass with a 0.1µF capacitor to DGND.
No Connection. Make no connection to these pins.
Three-State Digital Data Output (LSB)
Three-State Digital Data Output
DD
21, 22
23
N.C.
D0
D1
D2
D3
D4
D5
24
25
Three-State Digital Data Output
26
Three-State Digital Data Output
27
Three-State Digital Data Output
28
Three-State Digital Data Output
Detailed Description
DV
DD
Converter Operation
1mA
The MAX1157/MAX1159/MAX1175 use a successive-
approximation (SAR) conversion technique with an
inherent track-and-hold (T/H) stage to convert an analog
input into a 14-bit digital output. Parallel outputs provide
a high-speed interface to most microprocessors (µPs).
The Functional Diagram at the end of the data sheet
shows a simplified internal architecture of the MAX1157/
MAX1159/ MAX1175. Figure 3 shows a typical applica-
tion circuit for the MAX1157/MAX1159/MAX1175.
D0–D13
1mA
D0–D13
C
= 20pF
C
= 20pF
LOAD
LOAD
DGND
DGND
A)
B)
HIGH-Z TO V
HIGH-Z TO V
,
,
OL
OH
V
V
TO V , AND
V
V
TO V , AND
OL
OH
OH
OH
OL
OL
TO HIGH-Z
TO HIGH-Z
Analog Input
Figure 1. Load Circuits
Input Scaler
The MAX1157/MAX1159/MAX1175 have an input scaler
which allows conversion of true bipolar input voltages
and input voltages greater than the power supply, while
operating from a single +5V analog supply. The input
scaler attenuates and shifts the analog input to match
the input range of the internal DAC. The MAX1157 has
a unipolar input voltage range of 0 to +10V. The
MAX1175 input voltage range is 5V while the
MAX1159 input voltage range is 10V. Figure 4 shows
the equivalent input circuit of the MAX1157/
MAX1159/MAX1175. This circuit limits the current going
into or out of AIN to less than 1.8mA.
_______________________________________________________________________________________
7
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
t
t
CSH
CSL
CS
t
ACQ
REF POWER-
DOWN CONTROL
R/C
tEOC
t
t
t
DV
DH
DS
EOC
t
BR
t
t
DO
CONV
HIGH-Z
HIGH-Z
D0–D13
DATA VALID
Figure 2. MAX1157/MAX1159/MAX1175 Timing Diagram
Power-Down Modes
+5V ANALOG
+5V DIGITAL
Select standby mode or shutdown mode with R/C during
the second falling edge of CS (see Selecting Standby or
Shutdown Mode section). The MAX1157/MAX1159/
MAX1175 automatically enter either standby mode (refer-
ence and buffer on), or shutdown (reference and buffer
off) after each conversion depending on the status of
R/C during the second falling edge of CS.
0.1µF
0.1µF
µP DATA
BUS
AV
DD
DV
DD
14-BIT
WIDE
ANALOG
INPUT
D0–D13
AIN
Internal Clock
The MAX1157/MAX1159/MAX1175 generate an internal
conversion clock to free the microprocessor from the bur-
den of running the SAR conversion clock. Total conver-
sion time after entering hold mode (second falling edge
of CS) to end-of-conversion (EOC) falling is 4.7µs (max).
MAX1157
MAX1159
MAX1175
R/C
CS
EOC
REF
RESET
REFADJ
AGND DGND
0.1µF
10µF
Applications Information
Starting a Conversion
CS and R/C control acquisition and conversion in the
MAX1157/MAX1159/MAX1175 (see Figure 2). The first
falling edge of CS powers up the device and puts it in
acquire mode if R/C is low. The convert start CS is
ignored if R/C is high. The MAX1157/MAX1159/
Figure 3. Typical Application Circuit for the MAX1157/MAX1159/
MAX1175
Track and Hold (T/H)
In track mode, the internal hold capacitor acquires the
analog signal (see Figure 4). In hold mode, the T/H
switches open and the capacitive DAC samples the
analog input. During the acquisition, the analog input
MAX1175 need at least 6ms (C
= 0.1µF, C
=
REF
REFADJ
10µF) for the internal reference to wake up and settle
before starting the conversion if powering up from shut-
down. Reset the MAX1157/MAX1159/MAX1175 by tog-
gling RESET with CS high. The next falling edge of CS
begins acquisition.
(AIN) charges capacitor C
. The acquisition ends
HOLD
on the second falling edge of CS. At this instant, the
T/H switches open. The retained charge on C rep-
Selecting Standby or Shutdown Mode
The MAX1157/MAX1159/MAX1175 have a selectable
standby or low-power shutdown mode. In standby
mode, the ADC’s internal reference and reference
buffer do not power down between conversions, elimi-
nating the need to wait for the reference to power up
before performing the next conversion. Shutdown mode
powers down the reference and reference buffer after
HOLD
resents a sample of the input. In hold mode, the capac-
itive DAC adjusts during the remainder of the
conversion time to restore node T/H OUT to zero within
the limits of 14-bit resolution. Force CS low to put valid
data on the bus after conversion is complete.
8
_______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
REF
MAX1157
MAX1159/MAX1175
3.4kΩ
3.4kΩ
C
C
HOLD
30pF
R2
R2
HOLD
30pF
161Ω
161Ω
TRACK
TRACK
AIN
AIN
S1
S1
T/H OUT
HOLD
S2
T/H OUT
HOLD
S2
HOLD
HOLD
S3
POWER-
DOWN
S3
TRACK
TRACK
R3
R3
POWER-
DOWN
S1, S2 = T/H SWITCH
S3 = POWER DOWN
(MAX1159/MAX1175
ONLY)
R2 = 7.85kΩ (MAX1159)
OR 3.92kΩ (MAX1157/MAX1175)
R3 = 5.45kΩ (MAX1159)
OR 17.79kΩ (MAX1157/MAX1175)
Figure 4. Equivalent Input Circuit
DATA
OUT
ACQUISITION
CONVERSION
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 5. Selecting Standby Mode
completing a conversion. The reference and reference
buffer require a minimum of 12ms (C = 0.1µF,
REF
Standby Mode
While in standby mode, the supply current is less than
3.7mA (typ). The next falling edge of CS with R/C low
causes the MAX1157/MAX1159/MAX1175 to exit stand-
by mode and begin acquisition. The reference and ref-
erence buffer remain active to allow quick turn-on time.
REFADJ
C
= 10µF) to power up and settle from shutdown.
The state of R/C during the second falling edge of CS
selects which power-down mode the MAX1157/
MAX1159/MAX1175 enters upon conversion comple-
tion. Holding R/C low causes the MAX1157/MAX1159/
MAX1175 to enter standby mode. The reference and
buffer are left on after the conversion completes. R/C
high causes the MAX1157/MAX1159/MAX1175 to enter
shutdown mode and power down the reference and
buffer after conversion (see Figures 5 and 6). Set the
voltage at REF high during the second falling edge of
CS to realize the lowest current operation.
_______________________________________________________________________________________
9
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
DATA
OUT
ACQUISITION
CONVERSION
CS
R/C
EOC
REF AND
BUFFER
POWER
Figure 6. Selecting Shutdown Mode
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1157/
MAX1159/MAX1175’s internal buffer amplifier. Using
the buffered REFADJ input makes buffering the external
reference unnecessary. The internal buffer output must
be bypassed at REF with a 10µF capacitor.
MAX1157
MAX1159
MAX1175
+5V
68kΩ
100kΩ
REFADJ
0.1µF
Connect REFADJ to AV
to disable the internal buffer.
DD
150kΩ
Directly drive REF using an external reference. During
conversion, the external reference must be able to drive
100µA of DC load current and have an output imped-
ance of 10Ω or less. The input impedance of REFADJ is
typically 5kΩ. The DC input impedance of REF is a min-
imum 40kΩ.
Figure 7. MAX1157/MAX1159/MAX1175 Reference Adjust
Circuit
For optimal performance, buffer the reference through
an op amp and bypass REF with a 10µF capacitor.
Consider the MAX1157/MAX1159/MAX1175’s equivalent
input noise (0.6LSB) when choosing a reference.
Shutdown Mode
In shutdown mode, the reference and reference buffer
shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The first falling edge of CS with R/C low
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 14-bit accuracy, allow
Reading the Conversion Result
EOC flags the microprocessor when a conversion is
complete. The falling edge of EOC signals that the data
is valid and ready to be output to the bus. D0–D13 are
the parallel outputs of the MAX1157/MAX1159/
MAX1175. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conver-
sion. Data is loaded onto the bus with the third falling
12ms (C
= 0.1µF, C
= 10µF) for the internal
REF
REFADJ
reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1157/MAX1159/
MAX1175 is internally buffered to provide +4.096V out-
put at REF. Bypass REF to AGND and REFADJ to
AGND with 10µF and 0.1µF, respectively.
edge of CS with R/C high (after t ). Bringing CS high
DO
forces the output bus back to high impedance. The
MAX1157/MAX1159/MAX1175 then wait for the next
falling edge of CS to start the next conversion cycle
(see Figure 2).
Sink or source current at REFADJ to make fine adjust-
ments to the internal reference. The input impedance of
REFADJ is nominally 5kΩ. Use the circuit of Figure 7 to
adjust the internal reference to 1.5%.
1ꢀ ______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
INPUT RANGE = -10V TO +10V
INPUT RANGE = 0 TO +10V
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
FULL-SCALE
TRANSITION
11 . . . 1111
11 . . . 111
11 . . . 1110
11 . . . 1101
11 . . . 110
11 . . . 101
10 . . . 0001
10 . . . 0000
01 . . . 1111
FULL-SCALE RANGE
(FSR) = +20V
FULL-SCALE RANGE
(FSR) = +10V
FSR x V
16384 x 4.096
FSR x V
16384 x 4.096
REF
REF
1LSB =
1LSB =
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
-8192 -8190
0
+8190 +8192
+8191
0
1
2
3
16382 16384
16383
-8191 -8189
-1
+1
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
Figure 8. MAX1157 Transfer Function
Figure 9. MAX1159 Transfer Function
step-change in input signal. The input amplifier must
have a high enough slew rate to complete the required
output voltage change before the beginning of the
acquisition time. Figure 11 shows an example of this
circuit using the MAX427.
INPUT RANGE = -5V TO +5V
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 1111
11 . . . 1110
11 . . . 1101
Figures 12a and 12b show how the MAX1175 and
MAX1159 analog input current varies depending on
whether the chip is operating or powered down. The
part is fully powered down between conversions if the
voltage at R/C is set high during the second falling
edge of CS. The input current abruptly steps to the
powered up value at the start of acquisition. This step
in the input current can disrupt the ADC input, depend-
ing on the driving circuit’s output impedance at high
frequencies. If the driving circuit cannot fully settle by
the end of acquisition time, the accuracy of the system
can be compromised. To avoid this situation, increase
the acquisition time, use a driving circuit that can settle
10 . . . 0001
10 . . . 0000
01 . . . 1111
FULL-SCALE RANGE
(FSR) = +10V
FSR x V
16384 x 4.096
REF
1LSB =
00 . . . 0011
00 . . . 0010
00 . . . 0001
00 . . . 0000
-8192 -8190
0
+8190 +8192
+8191
-8191 -8189
-1
+1
INPUT VOLTAGE (LSB)
Figure 10. MAX1175 Transfer Function
within t
, or leave the MAX1175/MAX1159 powered
ACQ
up by setting the voltage at R/C low during the second
falling edge of CS.
Transfer Function
Figures 8, 9, and 10 show the MAX1157/MAX1159/
MAX1175’s output transfer functions. The MAX1159
and MAX1175 outputs are coded in offset binary, while
the MAX1157 is coded on standard binary.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Do not run analog and digital lines parallel to each
other, and do not lay out digital signal paths under-
neath the ADC package. Use separate analog and dig-
ital ground planes with only one point connecting the
two ground systems (analog and digital) as close to the
device as possible.
Input Buffer
Most applications require an input buffer amplifier to
achieve 14-bit accuracy and prevent loading the
source. Switch the channels immediately after acquisi-
tion, rather than near the end of or after a conversion
when the input signal is multiplexed. This allows more
time for the input buffer amplifier to respond to a large
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
______________________________________________________________________________________ 11
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1157/MAX1159/
MAX1175 are measured using the endpoint method.
REF
MAX1157
MAX1159
MAX1175
**
MAX427
AIN
ANALOG
INPUT
*
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
*MAX1157 ONLY.
**MAX1159/MAX1175 ONLY.
Figure 11. MAX1157/MAX1159/MAX1175 Fast-Settling Input
Buffer
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
onto the analog lines. If the analog and digital sections
share the same supply, isolate the digital and analog
supply by connecting them with a low value (10Ω)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV
supply. Bypass AV
to AGND with a 0.1µF
DD
DD
SNR = ((6.02 ✕ N) + 1.76)dB
capacitor in parallel with a 1µF to 10µF low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
where N = 14 bits.
In reality, there are other noise sources besides quanti-
MAX1175
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
2.0
MAX1159
ANALOG INPUT CURRENT
vs. ANALOG INPUT VOLTAGE
1.5
1.5
1.0
1.0
0.5
0.5
SHUTDOWN MODE
0
SHUTDOWN MODE
0
STANDBY MODE
-0.5
-0.5
STANDBY MODE
-1.0
-1.0
-1.5
-1.5
-2.0
-5.0
-2.5
0
2.5
5.0
-10
-5
0
5
10
ANALOG INPUT VOLTAGE (V)
ANALOG INPUT VOLTAGE (V)
Figure 12b. MAX1159 Analog Input Current
12 ______________________________________________________________________________________
Figure 12a. MAX1175 Analog Input Current
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
zation noise: thermal noise, reference noise, clock jitter,
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
2
2
2
2
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
V
+ V + V + V
3 4 5
2
=
THD 20 × log
V
1
Signal
(Noise + Distortion)
RMS
where V1 is the fundamental amplitude and V2 through
V5 are the 2nd- through 5th-order harmonics.
SINAD(db) = 20 × log
RMS
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Chip Information
TRANSISTOR COUNT: 15,383
SINAD -1.76
6.02
=
PROCESS: BiCMOS
ENOB
Ordering Information (continued)
IꢄPUT VOLTAGE
PART
TEMP RAꢄGE
PIꢄ-PACKAGE
IꢄL ꢅLSBx
RAꢄGE
MAX1157AEUI*
MAX1157BEUI*
MAX11ꢂ9ACUI
MAX1159BCUI
MAX1159AEUI*
MAX1159BEUI*
MAX117ꢂACUI*
MAX1175BCUI*
MAX1175AEUI*
MAX1175BEUI*
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
28 TSSOP
0 to +10V
0 to +10V
10V
1
2
1
2
1
2
1
2
1
2
10V
10V
10V
5V
5V
5V
5V
*Future product—contact factory for availability.
______________________________________________________________________________________ 13
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Functional Diagram
REFADJ
AV
AGND DV
DGND
DD
DD
5kΩ
REFERENCE
14 BITS
14 BITS
OUTPUT
REGISTERS
D0–D13
REF
MAX1157
MAX1159
MAX1175
CAPACITIVE
DAC
INPUT
SCALER
AIN
AGND
RESET
SUCCESSIVE-
APPROXIMATION
REGISTER AND
CONTROL LOGIC
CLOCK
CS
EOC
R/C
14 ______________________________________________________________________________________
14-Bit, 135ksps, Single-Supply ADCs with
Bipolar Analog Input Range
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.(aꢆi(-ic.co(/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 1ꢂ
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明