MAX11605EEE/V+
更新时间:2024-09-18 13:07:47
品牌:MAXIM
描述:D/A Converter, 8-Bit, 1 Func, 12 Channel, Serial Access, BICMOS, PDSO16, ROHS COMPLIANT, QSOP-16
MAX11605EEE/V+ 概述
D/A Converter, 8-Bit, 1 Func, 12 Channel, Serial Access, BICMOS, PDSO16, ROHS COMPLIANT, QSOP-16 模数转换器
MAX11605EEE/V+ 规格参数
是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Not Recommended | 零件包装代码: | SSOP |
包装说明: | SSOP, SSOP16,.25 | 针数: | 16 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.3 |
最大模拟输入电压: | 1.8 V | 最小模拟输入电压: | -1.8 V |
最长转换时间: | 6.1 µs | 转换器类型: | D/A CONVERTER |
JESD-30 代码: | R-PDSO-G16 | JESD-609代码: | e3 |
长度: | 4.9 mm | 最大线性误差 (EL): | 0.3906% |
湿度敏感等级: | 1 | 模拟输入通道数量: | 12 |
位数: | 8 | 功能数量: | 1 |
端子数量: | 16 | 最高工作温度: | 85 °C |
最低工作温度: | -40 °C | 输出位码: | 2'S COMPLEMENT BINARY |
输出格式: | SERIAL | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | SSOP | 封装等效代码: | SSOP16,.25 |
封装形状: | RECTANGULAR | 封装形式: | SMALL OUTLINE, SHRINK PITCH |
峰值回流温度(摄氏度): | 260 | 电源: | 3/3.3 V |
认证状态: | Not Qualified | 采样速率: | 0.188 MHz |
采样并保持/跟踪并保持: | TRACK | 筛选级别: | AEC-Q100 |
座面最大高度: | 1.75 mm | 子类别: | Analog to Digital Converters |
表面贴装: | YES | 技术: | BICMOS |
温度等级: | INDUSTRIAL | 端子面层: | Matte Tin (Sn) |
端子形式: | GULL WING | 端子节距: | 0.635 mm |
端子位置: | DUAL | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 3.89 mm | Base Number Matches: | 1 |
MAX11605EEE/V+ 数据手册
通过下载MAX11605EEE/V+数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载19-4554; Rev 1; 7/09
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
General Description
Features
o High-Speed I2C-Compatible Serial Interface
The MAX11600–MAX11605 low-power, 8-bit, multichan-
nel, analog-to-digital converters (ADCs) feature internal
track/hold (T/H), voltage reference, clock, and an
I2C-compatible 2-wire serial interface. These devices
operate from a single supply and require only 350µA at
the maximum sampling rate of 188ksps. Auto-
Shutdown™ powers down the devices between conver-
sions, reducing supply current to less than 1µA at low
throughput rates. The MAX11600/MAX11601 provide 4
analog input channels each, the MAX11602/MAX11603
provide 8 analog input channels each while the
MAX11604/MAX11605 provide 12 analog input channels.
The analog inputs are software configurable for unipolar or
bipolar and single-ended or pseudo-differential operation.
400kHz Fast Mode
1.7MHz High-Speed Mode
o Single Supply
2.7V to 3.6V (MAX11601/MAX11603/MAX11605)
4.5V to 5.5V (MAX11600/MAX11602/MAX11604)
o Internal Reference
2.048V (MAX11601/MAX11603/MAX11605)
4.096V (MAX11600/MAX11602/MAX11604)
o External Reference: 1V to V
o Internal Clock
DD
o 4-Channel Single-Ended or 2-Channel Pseudo-
Differential (MAX11600/MAX11601)
o 8-Channel Single-Ended or 4-Channel Pseudo-
The full-scale analog input range is determined by the
internal reference or by an externally applied reference
Differential (MAX11602/MAX11603)
voltage ranging from 1V to V . The MAX11601/
DD
o 12-Channel Single-Ended or 6-Channel Pseudo-
MAX11603/MAX11605 feature a 2.048V internal refer-
ence and the MAX11600/MAX11602/MAX11604 feature
a 4.096V internal reference.
Differential (MAX11604/MAX11605)
o Internal FIFO with Channel-Scan Mode
o Low Power
The MAX11600/MAX11601 are available in 8-pin SOT23
packages. The MAX11602–MAX11605 are available in
16-pin QSOP packages. The MAX11600–MAX11605 are
guaranteed over the extended industrial temperature
range (-40°C to +85°C). Refer to the MAX11606–
MAX11611 for 10-bit devices and to the MAX11612–
MAX11617 for 12-bit devices.
350µA at 188ksps
110µA at 75ksps
8µA at 10ksps
1µA in Power-Down Mode
o Software Configurable Unipolar/Bipolar
o Small Packages
8-Pin SOT23 (MAX11600/MAX11601)
16-Pin QSOP (MAX11602–MAX11605)
Applications
Handheld Portable Applications
Medical Instruments
Battery-Powered Test Equipment
Solar-Powered Remote Systems
Received-Signal-Strength Indicators
System Supervision
Pin Configurations and Typical Operating Circuit appear
at end of data sheet.
Ordering Information/Selector Guide
TUE
(LSB)
INPUT
CHANNELS
INTERNAL
REFERENCE (V)
TOP
MARK
PART
TEMP RANGE
PIN-PACKAGE
MAX11600EKA+
MAX11601EKA+
MAX11602EEE+
MAX11603EEE+
MAX11604EEE+
MAX11605EEE+
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 SOT23
8 SOT23
16 QSOP
16 QSOP
16 QSOP
16 QSOP
2
2
1
1
1
1
4
4
4.096
2.048
4.096
2.048
4.096
2.048
AAJE
AAJG
—
8
8
—
12
12
—
—
+Denotes a lead(Pb)-free/RoHS-compliant package.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
AIN0–AIN11, REF to
GND ......................-0.3V to the lower of (V
+ 0.3V) and +6V
DD
SDA, SCL to GND.....................................................-0.3V to +6V
Maximum Current into Any Pin ......................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW
16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
DD
(V
= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V
= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
DD
V
= 2.048V (MAX11601/MAX11603/MAX11605), V
= 4.096V (MAX11600/MAX11602/MAX11604). External clock, f
=
SCL
REF
REF
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
8
Bits
LSB
LSB
LSB
Relative Accuracy
Differential Nonlinearity
Offset Error
INL
(Note 2)
No missing codes over temperature
1
1
–MAX1605
DNL
1.5
Offset-Error Temperature
Coefficient
3
ppm/°C
Gain Error
(Note 3)
1
LSB
Gain Temperature Coefficient
1
ppm/°C
MAX11600/MAX11601
MAX11602/MAX11603
MAX11604/MAX11605
0.5
0.5
0.5
2
1
1
Total Unadjusted Error
TUE
LSB
Channel-to-Channel Offset
Matching
0.1
0.5
75
LSB
LSB
dB
Channel-to-Channel Gain
Matching
Input Common-Mode Rejection
Ratio
CMRR
Pseudo-differential input mode
DYNAMIC PERFORMANCE (f (sine wave) = 25kHz, V = V
f
= 188ksps, R = 100Ω)
IN
IN
REF(P-P), SAMPLE
IN
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Full-Power Bandwidth
SINAD
THD
49
-69
69
dB
dB
Up to the 5th harmonic
SFDR
dB
(Note 4)
75
dB
-3dB point
SINAD > 49dB
2.0
200
MHz
kHz
Full-Linear Bandwidth
CONVERSION RATE
Internal clock
External clock
6.1
Conversion Time (Note 5)
t
µs
CONV
4.7
2
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V
= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
DD
DD
V
= 2.048V (MAX11601/MAX11603/MAX11605), V
= 4.096V (MAX11600/MAX11602/MAX11604). External clock, f
=
SCL
REF
REF
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Internal clock, SCAN[1:0] = 01
(MAX11600/MAX11601)
76
SCAN[1:0] = 00 CS[3:0] = 0111
(MAX11602/MAX11603)
76
Throughput Rate
f
ksps
SAMPLE
Internal clock, SCAN[1:0] = 00
CS[3:0] = 1011 (MAX11604/MAX11605)
77
External clock
188
Track/Hold Acquisition Time
Internal Clock Frequency
588
ns
2.25
45
MHz
External clock, fast mode
Aperture Delay
t
ns
V
AD
External clock, high-speed mode
30
ANALOG INPUT (AIN0–AIN11)
Unipolar
Bipolar
0
V
REF
Input Voltage Range, Single
Ended and Differential (Note 6)
V
/2
REF
On/off-leakage current, V _ = 0 or V
AIN
DD,
Input Multiplexer Leakage Current
0.01
18
1
µA
pF
no clock, f
= 0
SCL
Input Capacitance
C
IN
INTERNAL REFERENCE (Note 7)
MAX11601/MAX11603/MAX11605
MAX11600/MAX11602/MAX11604
1.925
3.850
2.048
4.096
2.171
4.342
Reference Voltage
V
T
A
= +25°C
V
REF
Reference Temperature
Coefficient
TC
120
ppm/°C
REF
Reference Short-Circuit Current
Reference Source Impedance
EXTERNAL REFERENCE
Reference Input Voltage Range
REF Input Current
10
mA
(Note 8)
(Note 9)
675
Ω
V
1.0
V
V
REF
DD
I
f
= 188ksps
14
15
30
µA
REF
SAMPLE
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Current
V
0.7 x V
0.1 x V
V
V
IH
DD
DD
V
0.3 x V
DD
IL
V
V
HYST
I
V
= 0 to V
DD
10
µA
pF
V
IN
IN
Input Capacitance
Output Low Voltage
C
IN
V
I
= 3mA
0.4
OL
SINK
_______________________________________________________________________________________
3
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V
= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
DD
DD
V
= 2.048V (MAX11601/MAX11603/MAX11605), V
= 4.096V (MAX11600/MAX11602/MAX11604). External clock, f
=
SCL
REF
REF
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
MAX11601/MAX11603/MAX11605
MAX11600/MAX11602/MAX11604
2.7
4.5
3.6
5.5
Supply Voltage (Note 10)
V
V
DD
Internal REF, external clock
External REF, external clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
External REF, external clock
External REF, internal clock
350
250
110
150
8
650
f
=
=
=
=
SAMPLE
188ksps
f
SAMPLE
75ksps
Supply Current
I
µA
DD
f
SAMPLE
10ksps
10
2
f
SAMPLE
1ksps
2.5
1
Power-down
(Note 11)
10
1
Power-Supply Rejection Ratio
PSRR
0.25
LSB/V
–MAX1605
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1a and 2)
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
t
1.3
BUF
Hold Time for START Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t
t
0.6
1.3
0.6
µs
µs
µs
HD.STA
t
LOW
t
HIGH
Setup Time for a Repeated START
Condition (Sr)
0.6
µs
SU.STA
Data Hold Time
Data Setup Time
t
(Note 12)
0
150
ns
ns
HD.DAT
t
100
SU.DAT
Rise Time of Both SDA and SCL
Signals, Receiving
t
(Note 13)
(Note 13)
20 + 0.1C
300
300
ns
R
B
B
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
20 + 0.1C
0.6
ns
µs
pF
ns
F
t
SU.STO
C
400
50
B
t
SP
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1b and 2)
Serial-Clock Frequency
f
(Note 14)
1.7
MHz
ns
SCLH
Hold Time (Repeated) START
Condition
t
160
HD.STA
Low Period of the SCL Clock
High Period of the SCL Clock
t
320
120
ns
ns
LOW
t
HIGH
Setup Time for a Repeated START
Condition (Sr)
t
.
160
ns
SU STA
4
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11601/MAX11603/MAX11605), V
= 4.5V to 5.5V (MAX11600/MAX11602/MAX11604). External reference,
DD
DD
V
= 2.048V (MAX11601/MAX11603/MAX11605), V
= 4.096V (MAX11600/MAX11602/MAX11604). External clock, f
=
SCL
REF
REF
1.7MHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
Data Hold Time
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
t
.
(Note 12)
150
HD DAT
Data Setup Time
t
.
10
ns
SU DAT
Rise Time of SCL Signal
(Current Source Enabled)
t
(Note 13)
(Note 13)
20
20
80
ns
ns
RCL
Rise Time of SCL Signal After
Acknowledge Bit
t
160
RCL1
Fall Time of SCL Signal
t
(Note 13)
(Note 13)
(Note 13)
20
20
80
ns
ns
ns
ns
pF
ns
FCL
Rise Time of SDA Signal
t
160
160
RDA
Fall Time of SDA Signal
t
20
FDA
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t
,
160
SU STO
C
400
10
B
t
0
SP
Note 1: The MAX11600/MAX11602/MAX11604 are tested at V
= 5V and the MAX11601/MAX11603/MAX11605 are tested at V
DD
DD
= 3V. All devices are configured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to V
.
DD
Note 7: When AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) is configured to be an inter-
nal reference (SEL[2:1] = 11), decouple AIN_/REF or REF to GND with a 0.01µF capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF or REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mV
.
P-P
Note 10: Electrical characteristics are guaranteed from V
Operating Characteristics.
to V
. For operation beyond this range, see the Typical
DD(MIN)
DD(MAX)
Note 11: Power-supply rejection ratio is measured as:
N
2
V
3.3V − V 2.7V
×
(
)
(
)
]
[
FS
FS
V
REF
3.3V− 2.7V
,
for the MAX11601/MAX11603/MAX11605, where N is the number of bits.
Power-supply rejection ratio is measured as:
N
2
V
5.5V − V 4.5V
×
(
)
(
)
]
[
FS
FS
V
REF
5.5V− 4.5V
,
for the MAX11600/MAX11602/MAX11604, where N is the number of bits.
Note 12: A master device must provide a data hold time for SDA (referred to V of SCL) to bridge the undefined region of
IL
SCL’s falling edge (Figure 1).
Note 13: C = total capacitance of one bus line in pF. t , t
, and t measured between 0.3V
and 0.7V . The minimum value is
DD DD
B
R
FDA
F
specified at T = +25°C with C = 400pF.
A
B
Note 14: f
must meet the minimum clock low time plus the rise/fall times.
SCLH
_______________________________________________________________________________________
5
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Typical Operating Characteristics
(V = 3.3V (MAX11601/MAX11603/MAX11605), V = 5V (MAX11600/MAX11602/MAX11604), f
= 1.7MHz, external clock (33% duty
DD
DD
SCL
cycle), f
= 188ksps, single ended, unipolar, T = +25°C, unless otherwise noted.)
SAMPLE
A
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. VOLTAGE
450
400
350
300
250
200
150
5
4
3
2
1
0
450
400
350
300
250
200
150
SDA = SCL = V
DD
A) INTERNAL 4.096V
B) INTERNAL 2.048V
C) EXTERNAL 4.096V
D) EXTERNAL 2.048V
REF
REF
REF
REF
A
B
INTERNAL 4.096V
REF
INTERNAL 2.048V
REF
C
EXTERNAL 4.096V
REF
D
EXTERNAL 2.048V
REF
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
V
DD
V
(V)
DD
–MAX1605
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (INTERNAL CLOCK)
AVERAGE SUPPLY CURRENT VS.
CONVERSION RATE (EXTERNAL CLOCK)
350
300
250
200
150
100
50
5
4
3
2
1
0
500
450
400
350
300
250
200
150
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
SDA = SCL = V
DD
A) INTERNAL REF ALWAYS ON
B) INTERNAL REF AUTOSHUTDOWN
C) EXTERNAL REF
A
A
B
B
C
C
V
DD
= 5V
100
50
0
INTERNAL CLOCK MODE
EXTERNAL CLOCK MODE
f
= 1.7MHz
V
DD
= 3.3V
10
SCL
f
= 1.7MHz
SCL
0
-40
-15
35
60
85
0
10
20
30
40
50
60
0
50
100
150
200
TEMPERATURE (°C)
CONVERSION RATE (ksps)
CONVERSION RATE (ksps)
NORMALIZED 4.096V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.0100
INTERNAL 4.096V REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL 2.048V REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
1.0100
1.0075
1.0050
1.0025
1.0000
0.9975
0.9950
0.9925
0.9900
1.0075
1.0050
1.0025
1.0000
0.9975
0.9950
0.9925
0.9900
4.00 4.25 4.50 4.75 5.00 5.25 5.50
(V)
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
TEMPERATURE (°C)
V
DD
DD
6
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Typical Operating Characteristics (continued)
(V = 3.3V (MAX11601/MAX11603/MAX11605), V = 5V (MAX11600/MAX11602/MAX11604), f = 1.7MHz, external clock (33% duty
SCL
DD
DD
cycle), f
= 188ksps, single ended, unipolar, T = +25°C, unless otherwise noted.)
SAMPLE
A
INTERNAL 2.048V REFERENCE VOLTAGE
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
0.5
0.4
0.5
1.020
1.015
1.010
1.005
1.000
0.995
0.990
0.985
0.980
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-40
-15
10
35
60
85
0
50
100
150
200
250
300
0
50
100
150
200
250
300
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
FFT PLOT
OFFSET ERROR vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-20
V
= 2.048V
f
REF
SAMPLE = 188ksps
f
IN = 25kHz
-40
-60
-80
-100
-120
0
20k
40k
60k
80k
100k
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
FREQUENCY (Hz)
V
DD
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.1
V
V
= 3.3V
DD
V
= 2.048V
REF
= 2.048V
REF
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
TEMPERATURE (°C)
V
DD
_______________________________________________________________________________________
7
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Pin Description
PIN
NAME
FUNCTION
MAX11600 MAX11602 MAX11604
MAX11601 MAX11603 MAX11605
1, 2, 3
—
12, 11, 10
9–5
12, 11, 10 AIN0, AIN1, AIN2
9–5
AIN3–AIN7
Analog Inputs
—
—
4, 3, 2
AIN8–AIN10
Analog Input 3/Reference Input/Output. Selected in the setup register
(see Tables 1 and 6).
4
—
1
—
—
1
AIN3/REF
REF
Reference Input/Output. Selected in the setup register (see Tables 1
and 6).
—
—
Analog Input 11/Reference Input/Output. Selected in the setup
register (see Tables 1 and 6).
—
AIN11/REF
5
6
13
14
13
14
15
16
—
SCL
SDA
GND
Clock Input
Data Input/Output
7
15
Ground
8
16
V
Positive Supply. Bypass to GND with a 0.1µF capacitor.
No Connection
DD
–MAX1605
—
2, 3, 4
N.C.
charge on C
is referenced to GND when converted. In
T/H
Detailed Description
pseudo-differential mode, the analog input multiplexer
connects C to the positive analog input selected by
The MAX11600–MAX11605 ADCs use successive-
approximation conversion techniques and input T/H cir-
cuitry to capture and convert an analog signal to a
serial 8-bit digital output. The MAX11600/MAX11601
are 4-channel ADCs, the MAX11602/MAX11603 are
8-channel ADCs and the MAX11604/MAX11605 are
12-channel ADCs. These devices feature a high-speed
2-wire serial interface supporting data rates up to
1.7MHz. Figure 3 shows the simplified functional dia-
gram for the MAX11604/MAX11605.
T/H
CS[3:0]. The charge on C
tive analog input when converted.
is referenced to the nega-
T/H
The MAX11600–MAX11605 input configuration is
pseudo-differential in that only the signal at the positive
analog input is sampled with the T/H circuitry. The nega-
tive analog input signal must remain stable within
0.5 LSB ( 0.1 LSB for best results) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from the negative analog input to GND.
See the Single-Ended/Pseudo-Differential Input section.
Power Supply
The MAX11600–MAX11605 operate from a single supply
and consume 350µA at sampling rates up to 188ksps.
The MAX11601/MAX11603/MAX11605 feature a 2.048V
internal reference and the MAX11600/MAX11602/
MAX11604 feature a 4.096V internal reference. All
devices can be configured for use with an external refer-
During the acquisition interval, the T/H switches are in
the track position and C
charges to the analog input
T/H
signal. At the end of the acquisition interval, the T/H
switches move to the hold position retaining the charge
on C
as a sample of the input signal.
T/H
During the conversion interval, the switched capacitive
DAC adjusts to restore the comparator input voltage to
zero within the limits of 8-bit resolution. This action
requires eight conversion clock cycles and is equiva-
ence from 1V to V
.
DD
Analog Input and Track/Hold
The MAX11600–MAX11605 analog input architecture
contains an analog input multiplexer (MUX), a T/H
capacitor, T/H switches, a comparator, and a switched
capacitor digital-to-analog converter (DAC) (Figure 4).
lent to transferring a charge of 18pF ꢀ (V + - V -)
IN
IN
from C
to the binary weighted capacitive DAC, form-
T/H
ing a digital representation of the analog input signal.
In single-ended mode, the analog input multiplexer con-
Sufficiently low source impedance is required to ensure
an accurate sample. A source impedance below 1.5kΩ
does not significantly degrade sampling accuracy. To
nects C
to the analog input selected by CS[3:0] (see
T/H
the Configuration/Setup Bytes (Write Cycle) section). The
8
_______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
2
a) F/S-MODE I C SERIAL-INTERFACE TIMING
t
R
t
t
F
SDA
t
t
HD.DAT
SU.DAT
t
t
BUF
HD.STA
t
LOW
t
t
SU.STA
SU.STO
SCL
t
HD.STA
2
t
HIGH
t
t
R
F
S
Sr
A
P
S
b) HS-MODE I C SERIAL-INTERFACE TIMING
SDA
t
t
RDA
FDA
t
t
HD.DAT
SU.DAT
t
t
BUF
HD.STA
t
LOW
t
t
SU.STO
SU.STA
SCL
t
t
HIGH
HD.STA
t
t
FCL
t
RCL
RCL1
S
Sr
A
S
F/S MODE
HS MODE
2
Figure 1. I C Serial-Interface Timing
minimize sampling errors with higher source imped-
ances, connect a 100pF capacitor from the analog
input to GND. This input capacitor forms an RC filter
with the source impedance limiting the analog input
bandwidth. For larger source impedances, use a buffer
amplifier to maintain analog input signal integrity.
V
DD
I
= 3mA
OL
V
SDA
When operating in internal clock mode, the T/H circuitry
enters its tracking mode on the ninth falling clock edge
of the address byte (see the Slave Address section).
The T/H circuitry enters hold mode two internal clock
cycles later. A conversion or a series of conversions is
then internally clocked (eight clock cycles per conver-
sion) and the MAX11600–MAX11605 hold SCL low.
When operating in external clock mode, the T/H circuit-
ry enters track mode on the seventh falling edge of a
valid slave address byte. Hold mode is then entered on
the falling edge of the eighth clock cycle. The conver-
sion is performed during the next eight clock cycles.
OUT
400pF
I
= 0mA
OH
Figure 2. Load Circuit
t
≥ 6.25 ꢀ (R
+ R ) ꢀ C
SOURCE IN IN
ACQ
where R
IN
is the analog input source impedance,
SOURCE
= 2.5kΩ, and C = 18pF. t
The time required for the T/H circuitry to acquire an
input signal is a function of input capacitance. If the
analog input source impedance is high, the acquisition
time lengthens and more time must be allowed
R
is 1/f
for external
IN
ACQ
SCL
clock mode. For internal clock mode, the acquisition
time is two internal clock cycles. To select R
,
SOURCE
allow 625ns for t
for clock frequency variations.
in internal clock mode to account
ACQ
between conversions. The acquisition time (t
) is the
ACQ
minimum time needed for the signal to be acquired. It is
calculated by:
_______________________________________________________________________________________
9
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
SDA
SCL
INPUT SHIFT REGISTER
V
DD
INTERNAL
OSCILLATOR
CONTROL
LOGIC
SETUP REGISTER
GND
CONFIGURATION REGISTER
AIN0
AIN1
OUTPUT SHIFT
REGISTER AND
12-BYTE RAM
8-BIT
ADC
AIN2
T/H
AIN3
AIN4
ANALOG
INPUT
MUX
AIN5
REF
AIN6
AIN7
AIN8
REFERENCE
4.096V (MAX11604)
2.048V (MAX11605)
MAX11604
MAX11605
AIN9
THE MAX11600/MAX11601/MAX11604/MAX11605
USE THE SAME PIN FOR AIN_ AND REF, WHILE THE
MAX11602/MAX11603 USE DIFFERENT PINS.
SEE THE PIN DESCRIPTION SECTION.
AIN10
AIN11/REF
–MAX1605
Figure 3. MAX11604/MAX11605 Simplified Functional Diagram
ANALOG INPUT MUX
REF
C
T/H
AIN0
CAPACITIVE
DAC
AIN1
AIN2
AIN3/REF
GND
MAX11600
MAX11601
Figure 4. Equivalent Input Circuit
Analog Input Bandwidth
The MAX11600–MAX11605 feature input tracking cir-
cuitry with a 2MHz small signal bandwidth. The 2MHz
input bandwidth makes it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to
and GND. These diodes allow the analog inputs to
V
DD
swing from (GND - 0.3V) to (V
+ 0.3V) without caus-
DD
ing damage to the device. For accurate conversions,
the inputs must not go more than 50mV below GND or
above V . If the analog input exceeds V
by more
DD
DD
than 50mV, the input current should be limited to 2mA.
10 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Table 1. Setup Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
REG
SEL2
SEL1
SEL0
CLK
BIP/UNI
RST
X
BIT
7
NAME
REG
SEL2
SEL1
SEL0
CLK
DESCRIPTION
Register bit. 1 = setup byte, 0 = configuration byte (Table 2).
6
Three bits select the reference voltage and the state of AIN_/REF
(MAX11600/MAX11601/MAX11604/MAX11605) or REF (MAX11602/MAX11603) (Table 6).
Default to 000 at power-up.
5
4
3
1 = external clock, 0 = internal clock. Defaulted to zero at power-up.
1 = bipolar, 0 = unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section).
1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged.
Don’t care; can be set to 1 or 0.
2
BIP/UNI
RST
1
0
X
Single-Ended/Pseudo-Differential Input
The SGL/DIF bit of the configuration byte configures the
MAX11600–MAX11605 analog input circuitry for single-
ended or pseudo-differential inputs (Table 2). In single-
ended mode (SGL/DIF = 1), the digital conversion results
are the difference between the analog input selected by
CS[3:0] and GND (Table 3). In pseudo-differential mode
(SGL/DIF = 0), the digital conversion results are the differ-
ence between the positive and the negative analog inputs
selected by CS[3:0] (Table 4). The negative analog input
signal must remain stable within 0.5 LSB ( 0.1 LSB for
best results) with respect to GND during a conversion.
Digital Interface
The MAX11600–MAX11605 feature a 2-wire interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate bidirectional communi-
cation between the MAX11600–MAX11605 and the mas-
ter at rates up to 1.7MHz. The MAX11600–MAX11605 are
slaves that transmit and receive data. The master (typical-
ly a microcontroller) initiates data transfer on the bus and
generates SCL to permit that transfer.
SDA and SCL must be pulled high. This is typically
done with pullup resistors (500Ω or greater) (see
Typical Operating Circuit). Series resistors (R ) are
S
optional. They protect the input architecture of the
MAX11600–MAX11605 from high-voltage spikes on the
bus lines and minimize crosstalk and undershoot of the
bus signals.
Unipolar/Bipolar
When operating in pseudo-differential mode, the BIP/
UNI bit of the setup byte (Table 1) selects unipolar or
bipolar operation. Unipolar mode sets the differential
analog input range from zero to V
. A negative differ-
REF
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data in or out of the MAX11600–MAX11605. The data
on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). Both SDA and SCL idle high when
the bus is not busy.
ential analog input in unipolar mode causes the digital
output code to be zero. Selecting bipolar mode sets the
differential input range to
V
REF
/2, with respect to the
negative input. The digital output code is binary in
unipolar mode and two’s complement binary in bipolar
mode (see the Transfer Functions section).
In single-ended mode, the MAX11600–MAX11605
always operate in unipolar mode regardless of the
BIP/UNI setting, and the analog inputs are internally ref-
erenced to GND with a full-scale input range from zero
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP
condition (P), a low-to-high transition on SDA, while
to V
.
REF
______________________________________________________________________________________ 11
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
SCL is high (Figure 5). A repeated START condition (Sr)
S
Sr
P
can be used in place of a STOP condition to leave the
bus active and in its current timing mode (see the HS
Mode section).
SDA
SCL
Acknowledge Bits
Successful data transfers are acknowledged with an
acknowledge bit (A) or a not-acknowledge bit (A). Both
the master and the MAX11600–MAX11605 (slave) gener-
ate acknowledge bits. To generate an acknowledge bit,
the receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the clock
pulse (Figure 6). To generate a not acknowledge bit, the
receiver allows SDA to be pulled high before the rising
edge of the acknowledge-related clock pulse and leaves
it high during the high period of the clock pulse.
Figure 5. START and STOP Conditions
S
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
8 9
1
2
SCL
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication at a later time.
Figure 6. Acknowledge Bits
–MAX1605
addressing all devices on the bus with the HS mode
master code 0000 1XXX (X = don’t care). After success-
fully receiving the HS-mode master code, the
MAX11600–MAX11605 issues a not acknowledge,
allowing SDA to be pulled high for one clock cycle
(Figure 8). After the not acknowledge, the
MAX11600–MAX11605 are in HS mode. The master must
then send a repeated START followed by a slave
address to initiate HS mode communication. If the mas-
ter generates a STOP condition, the MAX11600–
MAX11605 return to F/S mode.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address. When idle, the MAX11600–MAX11605
continuously wait for a START condition followed by
their slave address. When the MAX11600–MAX11605
recognize their slave address, they are ready to accept
or send data. The slave address has been factory pro-
grammed and is always 1100100 for the MAX11600/
MAX11601, 1101101 for MAX11602/MAX11603, and
1100101 for MAX11604/MAX11605 (Figure 7). The least
significant bit (LSB) of the address byte (R/W) deter-
mines whether the master is writing to or reading from
the MAX11600–MAX11605 (R/W = zero selects a write
condition. R/W = 1 selects a read condition). After
receiving the address, the MAX11600–MAX11605
(slave) issue an acknowledge by pulling SDA low for
one clock cycle.
Configuration/Setup Bytes (Write Cycle)
Write cycles begin with the master issuing a START
condition followed by 7 address bits (Figure 7) and 1
write bit (R/W = zero). If the address byte is successful-
ly received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then writes to the slave. The
slave recognizes the received byte as the setup byte
(Table 1) if the most significant bit (MSB) is 1. If the
MSB is zero, the slave recognizes that byte as the con-
figuration byte (Table 2). The master can write either 1
or 2 bytes to the slave in any order (setup byte then
configuration byte; configuration byte then setup byte;
setup byte only; configuration byte only; Figure 9). If the
slave receives bytes successfully, it issues an acknowl-
edge. The master ends the write cycle by issuing a
STOP condition or a repeated START condition. When
operating in HS mode, a STOP condition returns the
bus to F/S mode (see the HS Mode section).
Bus Timing
At power-up, the MAX11600–MAX11605 bus timing
defaults to fast mode (F/S mode), allowing conversion
rates up to 44ksps. The MAX11600–MAX11605 must
operate in high-speed mode (HS mode) to achieve
conversion rates up to 188ksps. Figure 1 shows the bus
timing for the MAX11600–MAX11605 2-wire interface.
HS Mode
At power-up, the MAX11600–MAX11605 bus timing is
set for F/S mode. The master selects HS mode by
12 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
DEVICE
SLAVE ADDRESS
1100100
MAX11600/MAX11601
MAX11602/MAX11603
MAX11604/MAX11605
1101101
1100101
SLAVE ADDRESS
S
1
1
0
0
1
0
0
R/W
A
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7. Slave Address Byte
HS MODE MASTER CODE
S
0
0
0
0
1
X
X
X
A
Sr
SDA
SCL
F/S MODE
HS MODE
Figure 8. F/S Mode to HS Mode Transfer
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by 7 address bits and a
read bit (R/W = 1). If the address byte is successfully
received, the MAX11600–MAX11605 (slave) issue an
acknowledge. The master then reads from the slave.
After the master has received the results, it can issue
an acknowledge if it wants to continue reading or a not
acknowledge if it no longer wishes to read. If the
MAX11600–MAX11605 receive a not acknowledge,
they release SDA, allowing the master to generate a
STOP or repeated START. See the Clock Mode and
Scan Mode sections for detailed information on how
data is obtained and converted.
Clock Mode
The clock mode determines the conversion clock, the
acquisition time, and the conversion time. The clock
mode also affects the scan mode. The state of the
setup byte’s CLK bit determines the clock mode (Table
1). At power-up, the MAX11600–MAX11605 default to
internal clock mode (CLK = zero).
Internal Clock
When configured for internal clock mode (CLK = zero),
the MAX11600–MAX11605 use their internal oscillator
as the conversion clock. In internal clock mode, the
MAX11600–MAX11605 begin tracking analog input on
the ninth falling clock edge of a valid slave address
byte. Two internal clock cycles later, the analog signal
is acquired and the conversion begins. While tracking
and converting the analog input signal, the
MAX11600–MAX11605 hold SCL low (clock stretching).
After the conversion completes, the results are stored in
______________________________________________________________________________________ 13
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. 1-BYTE WRITE CYCLE
1
7
1
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
B. 2-BYTE WRITE CYCLE
1
7
1
1
8
1
8
1
1
NUMBER OF BITS
SETUP OR
CONFIGURATION BYTE
SETUP OR
CONFIGURATION BYTE
S
SLAVE ADDRESS W A
A
A
P OR Sr
MSB DETERMINES WHETHER
SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
–MAX1605
random access memory (RAM). If the scan mode is set
for multiple conversions, they all happen in succession
with each additional result being stored in RAM. The
MAX11600/MAX11601 contain 8 bytes of RAM, the
MAX11602/MAX11603 contain 8 bytes of RAM, and the
MAX11604/MAX11605 contain 12 bytes of RAM. Once
all conversions are complete, the MAX11600–
MAX11605 release SCL, allowing it to be pulled high.
The master can now clock the results out of the output
shift register at a clock rate of up to 1.7MHz. SCL is
stretched for a maximum acquisition and conversion
time of 7.6µs per channel (Figure 10).
External Clock
When configured for external clock mode (CLK = 1),
the MAX11600–MAX11605 use SCL as the conversion
clock. In external clock mode, the MAX11600–
MAX11605 begin tracking the analog input on the sev-
enth falling clock edge of a valid slave address byte.
One SCL clock cycle later, the analog signal is
acquired and the conversion begins. Unlike internal
clock mode, converted data is available immediately
after the slave-address acknowledge bit. The device
continuously converts input channels dictated by the
scan mode until given a not acknowledge. There is no
need to re-address the device with a read command to
obtain new conversion results (Figure 11).
The device RAM contains all of the conversion results
when the MAX11600–MAX11605 release SCL. The con-
verted results are read back in a first-in-first-out (FIFO)
sequence. If AIN_/REF is set to be a reference input or
output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF. RAM contents can be read continu-
ously. If reading continues past the last result stored in
RAM, the pointer wraps around and points to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The conversion must complete in 9ms or droop on the
T/H capacitor degrades conversion results. Use internal
clock mode if the SCL clock period exceeds 1ms.
The MAX11600–MAX11605 must operate in external
clock mode for conversion rates up to 188ksps.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan-mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded
from a multichannel scan. This does not apply to the
MAX11602/MAX11603 as each provides separate pins
for AIN7 and REF.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the master
(typically a microcontroller) from the burden of running
the conversion clock.
14 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Table 2. Configuration Byte Format
BIT 7
(MSB)
BIT 0
(LSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
REG
SCAN1
SCAN0
CS3
CS2
CS1
CS0
SGL/DIF
BIT
7
NAME
REG
DESCRIPTION
Register bit. 1 = setup byte (Table 1), 0 = configuration byte.
6
SCAN1
SCAN0
CS3
Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at
power-up.
5
4
Channel select bits. Four bits select which analog input channels are to be used for conversion
(Tables 3 and 4). Default to 0000 at power-up. For the MAX11600/MAX11601, CS3 and CS2 are
internally set to 0. For the MAX11602/MAX11603, CS3 is internally set to zero.
3
CS2
2
1
CS1
CS0
1 = single-ended, 0 = pseudo-differential (Tables 3 and 4). Default to 1 at power-up (see the
Single-Ended/Pseudo-Differential Input section).
0
SGL/DIF
Automatic shutdown results in dramatic power savings,
Applications Information
particularly at slow conversion rates. For example, at a
conversion rate of 10ksps, the average supply current
for the MAX1036 is 8µA and drops to 2µA at 1ksps.
At 0.1ksps the average supply current is just 1µA (see
Average Supply Current vs. Conversion Rate in the
Typical Operating Characteristics section).
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con-
version on AIN0 using the internal clock with V
as the
DD
reference and AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) configured as an analog input.
For the MAX11602/MAX11603, the REF pin is floating
after power-up. The RAM contents are unknown after
power-up.
Reference Voltage
SEL[2:0] of the setup byte (Table 1) controls the refer-
ence and the AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603)
configuration (Table 6). When AIN_/REF (MAX11600/
MAX11601/MAX11604/MAX11605) is configured to be
a reference input or reference output (SEL1 = 1), con-
versions on AIN_/REF appear as if AIN_/REF is con-
nected to GND (see note 2 of Tables 3 and 4).
Automatic Shutdown
SEL[2:0] of the setup byte (Tables 1 and 6) controls the
state of the reference and AIN_/REF (MAX11600/
MAX11601/MAX11604/MAX11605) or REF (MAX11602/
MAX11603). If automatic shutdown is selected (SEL[2:0] =
100), shutdown occurs between conversions when the
MAX11600–MAX11605 are idle. When operating in exter-
nal clock mode, a STOP condition must be issued to place
the devices in idle mode and benefit from automatic shut-
down. A STOP condition is not necessary in internal clock
mode to benefit from automatic shutdown because power-
down occurs once all contents are written to memory
(Figure 10). All analog circuitry is inactive in shutdown and
supply current is less than 1µA. The digital conversion
results are maintained in RAM during shutdown and are
available for access through the serial interface at any
time prior to a STOP or repeated START condition.
Internal Reference
The internal reference is 4.096V for the MAX11600/
MAX11602/MAX11604 and 2.048V for the MAX11601/
MAX11603/MAX11605. SEL1 of the setup byte controls
whether AIN_/REF (MAX11600/MAX11601/MAX11604/
MAX11605) is used for an analog input or a reference
(Table 6). When AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603) is
configured to be an internal reference output (SEL[2:1] =
11), decouple AIN_/REF (MAX11600/MAX11601/
MAX11604/MAX11605) or REF (MAX11602/MAX11603)
to GND with a 0.01µF capacitor. Due to the decoupling
capacitor and the 675Ω reference source impedance,
allow 80µs for the reference to stabilize during initial
power-up. Once powered up, the reference always
remains on until reconfigured. The reference should not
be used to supply current for external circuitry. When the
MAX11602/MAX11603 is in shutdown, the internal refer-
ence output is in a high-impedance state.
When idle, the MAX11600–MAX11605 wait for a START
condition followed by their slave address (see the
Slave Address section). Upon reading a valid address
byte, the MAX11600–MAX11605 power up. The analog
circuits do not require any wakeup time from shutdown,
whether using external or internal reference.
______________________________________________________________________________________ 15
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
1
1
8
1
1
NUMBER OF BITS
S
SLAVE ADDRESS R A CLOCK STRETCH
RESULT
A
P or Sr
t
t
CONV
ACQ
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
1
1
8
8
1
1
1
8
1
NUMBER OF BITS
S
SLAVE ADDRESS
R
A
CLOCK STRETCH
t
CLOCK STRETCH RESULT 1
A
RESULT 2
A
RESULT N
A
P OR Sr
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONVN
CONV1
CONV2
–MAX1605
NOTE: t
+ t
≤ 7.6μs PER CHANNEL.
ACQ CONV
Figure 10. Internal Clock Mode Read Cycles
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
1
1
8
1
1
NUMBER OF BITS
S
R
A
A
SLAVE ADDRESS
RESULT
P OR Sr
t
t
CONV
ACQ
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
1
1
8
1
8
1
8
1
1
NUMBER OF BITS
S
R
A
A
A
A
P OR Sr
SLAVE ADDRESS
RESULT 1
RESULT 2
RESULT N
t
t
t
ACQ1
ACQ2
ACQN
t
t
t
CONV1
CONV2
CONVN
Figure 11. External Clock Mode Read Cycles
16 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS31 CS21
CS1
0
CS0
0
AIN0 AIN1 AIN2 AIN32 AIN4
AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
+
+
+
+
+
-
-
-
-
-
0
1
1
0
1
1
0
0
0
1
+
-
-
-
-
-
-
-
1
0
+
1
1
+
0
0
+
0
1
+
1
0
+
1
1
+
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
0
1
1
1
2
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
When SEL1 = 1, a single-ended read of AIN3/REF (MAX11600/MAX11601) or AIN11/REF (MAX11604/MAX11605) returns GND. This
does not apply to the MAX11602/MAX11603 as each provides separate pins for AIN7 and REF.
______________________________________________________________________________________ 17
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
1
Table 4. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0)
CS32
CS22
CS1
0
CS0
0
AIN0
AIN1
AIN2 AIN32
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9 AIN10 AIN113
0
0
+
-
-
0
0
0
1
+
0
0
1
0
+
-
-
0
0
1
1
+
0
1
0
0
+
-
-
0
1
0
1
+
0
1
1
0
+
-
-
0
1
1
1
+
1
0
0
0
+
-
-
1
0
0
1
+
1
0
1
0
+
-
-
1
0
1
1
+
1
1
0
0
Reserved
1
1
0
1
Reserved
Reserved
Reserved
1
1
1
0
–MAX1605
1
1
1
1
1
When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned, while CS0 = 1
causes the odd-numbered channel-select bits to be scanned. For example, if the MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] =
1010, a pseudo-differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7, AIN8–AIN9, and AIN10–AIN11. If the
MAX11604/MAX11605 SCAN[1:0] = 00 and CS[3:0] = 1011, a pseudo-differential read returns AIN1–AIN0, AIN3–AIN2, AIN5–AIN4,
AIN7–AIN6, AIN9–AIN8, and AIN11–AIN10.
For the MAX11600/MAX11601, CS3 and CS2 are internally set to zero. For the MAX11602/MAX11603, CS3 is internally set to zero.
When SEL1 = 1, a pseudo-differential read between AIN2 and AIN3/REF (MAX11600/MAX11601) or AIN10 and AIN11/REF
(MAX11604/MAX11605) returns the difference between GND and AIN2 or AIN10, respectively. For example, a pseudo-differential
read of 1011 returns the negative difference between AIN10 and GND. This does not apply to the MAX11602/MAX11603 as each pro-
vides separate pins for AIN7 and REF.
2
3
18 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Table 5. Scanning Configuration
SCAN1
SCAN0
SCANNING CONFIGURATION
Scans up from AIN0 to the input selected by CS3–CS0 (default setting).
Converts the input selected by CS3–CS0 eight times.*
0
0
0
1
MAX11600/MAX11601: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and
AIN2, the scanning stops at AIN2 (MAX11600/MAX11601).
MAX11602/MAX11603: Scans upper quartile of channels.
1
1
0
1
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11602/MAX11603).
MAX11604/MAX11605: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the scanning
stops at AIN6 (MAX11604/MAX11605).
Converts the channel selected by CS3–CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues
until a not acknowledge occurs.
Table 6. Reference Voltage, AIN_/REF, and REF Format
AIN_/REF
(MAX11600/
MAX11601/
MAX11604/
MAX11605)
REF
(MAX11602/
MAX11603)
REFERENCE
VOLTAGE
INTERNAL
REFERENCE STATE
SEL2
SEL1
SEL0
0
0
1
1
1
0
1
0
0
1
X
X
0
1
X
V
Analog input
Reference input
Analog input
Not connected
Reference input
Not connected
Not connected
Reference output
Always off
Always off
DD
External reference
Internal reference
Internal reference
Internal reference
AutoShutdown
Always on
Analog input
Reference output
Always on
X = Don’t care.
External Reference
Transfer Functions
The external reference can range from 1.0V to V . For
DD
Output data coding for the MAX11600–MAX11605 is
binary in unipolar mode and two’s complement binary in
maximum conversion accuracy, the reference must be
able to deliver up to 30µA and have an output impedance
of 1kΩ or less. If the reference has a higher output imped-
ance or is noisy, bypass it to GND as close as possible to
AIN_/REF (MAX11600/MAX11601/MAX11604/MAX11605)
or REF (MAX11602/MAX11603) with a 0.1µF capacitor.
bipolar mode with 1 LSB = V
/2N where N is the num-
REF
ber of bits (8). Code transitions occur halfway between
successive-integer LSB values. Figures 12 and 13 show
the input/output (I/O) transfer functions for unipolar and
bipolar operations, respectively.
______________________________________________________________________________________ 19
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
OUTPUT CODE
(TWO'S COMPLEMENT)
V
REF
V
REF
1 LSB =
OUTPUT CODE
REF
1 LSB =
256
256
REF
0...111
0...110
0...101
0...100
1...111
1...110
1...101
1...100
0...001
0...000
1...111
1...011
1...010
1...001
0...011
0...010
0...001
0...000
1...000
-128 -127 -126 -125
-1
0
+1
+124 +125 +126 +127 +128
0
1
2
3
252 253 254 255 256
NEGATIVE INPUT
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
–MAX1605
Figure 12. Unipolar Transfer Function
Figure 13. Bipolar Transfer Function
Layout, Grounding, and Bypassing
For best performance, use PC boards. Wire-wrap config-
urations are not recommended since the layout should
ensure proper separation of analog and digital traces. Do
not run analog and digital lines parallel to each other, and
do not lay out digital signal paths underneath the ADC
package. Use separate analog and digital PCB ground
sections with only one star point (Figure 14) connecting
the two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short as
possible. Route digital signals far away from sensitive
analog and reference inputs.
SUPPLIES
3V/5V
V
= 3V/5V
LOGIC
GND
R* = 5Ω
0.1μF
GND
V
DD
3V/5V DGND
High-frequency noise in the power supply (V ) could
DD
influence the proper operation of the ADC’s fast
DIGITAL
CIRCUITRY
comparator. Bypass V
to the star ground with a
DD
MAX11600–
MAX11605
0.1µF capacitor located as close as possible to the
MAX11600–MAX11605 power-supply pin. Minimize
capacitor lead length for best supply-noise rejection,
and add an attenuation resistor (5Ω) if the power sup-
ply is extremely noisy.
*OPTIONAL
Figure 14. Power-Supply and Grounding Connections
20 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The INL
is measured using the end point method.
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
ꢀ
SINAD (dB) = 20 log (Signal
/Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
⎛
⎞
Aperture Delay
2
2
2
2
⎞
⎛
×
THD = 20 log
V
+ V + V + V
/V
1
2
3
4
5
⎜
⎟
⎝
⎠
Aperture delay (t ) is the time between the rising
AD
⎝
⎠
edge of the sampling clock and the instant when an
actual sample is taken.
where V is the fundamental amplitude, and V through
1
2
V
are the amplitudes of the 2nd- through 5th-order
5
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-
to-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
ꢀ
SNR = (6.02 N + 1.76)dB
Chip Information
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is computed by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
PROCESS: BiCMOS
______________________________________________________________________________________ 21
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
Pin Configurations
Typical Operating Circuit
5V
TOP VIEW
V
+
DD
AIN0
AIN1
1
2
3
4
8
7
6
5
V
DD
AIN0
*R
*R
S
MAX11600–
MAX11605
AIN1
SDA
SCL
ANALOG
INPUTS
GND
SDA
SCL
MAX11600
MAX11601
AIN2
AIN2
AIN3/REF
S
GND
5V
AIN3/REF
5V
R
P
SOT23
+
R
P
(REF) AIN11/REF
(N.C.) AIN10
(N.C.) AIN9
(N.C.) AIN8
AIN7
1
16
V
DD
2
3
4
5
6
7
8
15 GND
14 SDA
13 SCL
12 AIN0
11 AIN1
10 AIN2
SDA
SCL
μC
–MAX1605
MAX11602–
MAX11605
*OPTIONAL
AIN6
AIN5
AIN4
9
AIN3
Package Information
For the latest package outline information and land patterns, go
QSOP
to www.maxim-ic.com/packages.
( ) INDICATES PINS ON THE MAX11602/MAX11603.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 SOT23
16 QSOP
K8CN+2
E16+4
21-0078
21-0055
22 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs
–MAX1605
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
4/09
7/09
Introduction of the MAX11600/MAX11601/MAX11603
Introduction of the MAX11602/MAX11604/MAX11605
—
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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