MAX11637EEE+T [MAXIM]
12-Bit, 300ksps ADCs with Differential; 12位，高达300ksps ADC，带有差分
| 型号： | MAX11637EEE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 12-Bit, 300ksps ADCs with Differential |
| 文件： | 总24页 (文件大小：1298K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5962; Rev 1; 9/11
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
General Description
Features
The MAX11634–MAX11637 are serial 12-bit analog-to-
digital converters (ADCs) with an internal reference and
true differential track/hold. These devices feature on-chip
FIFO, scan mode, internal clock mode, internal averag-
ing, and AutoShutdown™. The maximum sampling rate is
300ksps using an external clock. The MAX11636/
MAX11637 have 8 input channels and the MAX11634/
MAX11635 have 4 input channels. These four devices
operate from either a +3V supply or a +5V supply, and
contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-compati-
ble serial port.
o Analog Multiplexer with True Differential Track/Hold
8-/4-Channel Single-Ended
4-/2-Channel True Differential
Unipolar or Bipolar Inputs
o Single Supply
2.7V to 3.6V (MAX11635/MAX11637)
4.75V to 5.25V (MAX11634/MAX11636)
o External Reference: 1V to V
DD
o 16-Entry First-In/First-Out (FIFO)
The MAX11634–MAX11637 are available in a 16-pin
QSOP package. All four devices are specified over the
extended -40°C to +85°C temperature range.
o Scan Mode, Internal Averaging, and Internal Clock
o Accuracy: 1 ꢀSB Iꢁꢀ, 1 ꢀSB Dꢁꢀ, ꢁo Missing
Codes Over Temperature
Applications
System Supervision
o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible
Interface
o Small 16-Pin QSOP Package
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
Data Logging
Instrumentation
Ordering Information/Selector Guide
PART
ꢁUMBER OF IꢁPUTS
SUPPꢀY VOꢀTAGE (V)
TEMP RAꢁGE
PIꢁ-PACKAGE
4 Single-Ended/
2 Differential
MAX11634EEE+T
4.75 to 5.25
-40°C to +85°C
16 QSOP
4 Single-Ended/
2 Differential
MAX11635EEE+T
MAX11636EEE+T
MAX11637EEE+T
2.7 to 3.6
4.75 to 5.25
2.7 to 3.6
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
8 Single-Ended/
4 Differential
8 Single-Ended/
4 Differential
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
ABSOꢀUTE MAXIMUM RATIꢁGS
DD
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (V
AIN0–AIN5, REF-/AIN6, CNVST/AIN7,
REF+ to GND.........................................-0.3V to (V
Maximum Current into any Pin............................................50mA
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
+ 0.3V)
DD
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
QSOP (single-layer board)
(derate 8.3mW/°C above +70°C).................................667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAꢀ CHARACTERISTICS (ꢁote 1)
QSOP
Junction-to-Ambient Thermal Resistance (θ )...............105°C/W
JA
Junction-to-Case Thermal Resistance (θ )......................37°C/W
JC
ꢁote 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
4–MAX1637
EꢀECTRICAꢀ CHARACTERISTICS
(V
= 2.7V to 3.6V (MAX11635/MAX11637), V
= 4.75V to 5.25V (MAX11634/MAX11636), f
= 300kHz, f
= 4.8MHz
SCLK
DD
DD
SAMPLE
(external clock, 50% duty cycle), V
= 2.5V (MAX11635/MAX11637), V
= 4.096V (MAX11634/MAX11636) T = T
to T
,
REF
REF
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY (Note 3)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RES
INL
12
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
1.0
1.0
4.0
4.0
DNL
No missing codes over temperature
(Note 4)
0.5
0.5
Gain Error
Offset Error Temperature
Coefficient
ppm/°C
FSR
2
Gain Temperature Coefficient
0.8
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, f
= 4.8MHz)
SCLK
MAX11635/MAX11637
MAX11634/MAX11636
71
73
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
SINAD
THD
dB
MAX11635/MAX11637
MAX11634/MAX11636
-80
-88
81
Up to the 5th
harmonic
dBc
dBc
MAX11635/MAX11637
MAX11634/MAX11636
Spurious-Free Dynamic Range
SFDR
IMD
89
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
f
= 29.9kHz, f
= 30.2kHz
IN2
76
dBc
MHz
kHz
IN1
-3dB point
S/(N + D) > 68dB
1
100
2
_______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
EꢀECTRICAꢀ CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11635/MAX11637), V
= 4.75V to 5.25V (MAX11634/MAX11636), f
= 300kHz, f
= 4.8MHz
SCLK
DD
DD
SAMPLE
(external clock, 50% duty cycle), V
= 2.5V (MAX11635/MAX11637), V
= 4.096V (MAX11634/MAX11636) T = T
to T
,
REF
REF
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
External reference
0.8
65
Power-Up Time
Acquisition Time
Conversion Time
t
µs
µs
µs
PU
Internal reference (Note 5)
t
0.6
ACQ
Internally clocked
3.5
t
CONV
Externally clocked (Note 6)
Externally clocked conversion
Data I/O
2.7
0.1
4.8
10
External Clock Frequency
f
MHz
SCLK
Aperture Delay
Aperture Jitter
ANALOG INPUT
30
ns
ps
< 50
Unipolar
0
V
REF
Input Voltage Range
V
Bipolar (Note 7)
-V /2
REF
+V /2
REF
Input Leakage Current
Input Capacitance
V
= V
0.01
24
1
µA
pF
IN
DD
During acquisition time (Note 8)
INTERNAL REFERENCE
MAX11634/MAX11636
MAX11635/MAX11637
MAX11634/MAX11636
MAX11635/MAX11637
4.024
2.48
4.096
2.50
20
4.168
2.52
REF Output Voltage
V
REF Temperature Coefficient
TC
ppm/°C
REF
30
Output Resistance
6.5
kꢀ
REF Output Noise
200
-70
µV
RMS
REF Power-Supply Rejection
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
PSRR
dB
V
REF-
0
500
mV
V
V
REF+
1.0
V
DD
+ 50mV
V
REF+
V
REF+
= 2.5V (MAX11635/MAX11637),
= 4.096V (MAX11634/MAX11636),
40
100
f
= 300ksps
SAMPLE
REF+ Input Current
I
µA
V
REF+
V
V
f
= 2.5V (MAX11635/MAX11637),
= 4.096V (MAX11634/MAX11636),
= 0
REF+
REF+
0.1
5
SAMPLE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST (Note 9)
MAX11634/MAX11636
MAX11635/MAX11637
MAX11634/MAX11636
MAX11635/MAX11637
0.8
Input Voltage Low
V
IL
V
DD
x 0.3
2.0
Input Voltage High
Input Hysteresis
V
V
IH
V
DD
x 0.7
V
200
mV
HYST
_______________________________________________________________________________________
3
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
EꢀECTRICAꢀ CHARACTERISTICS (continued)
(V
= 2.7V to 3.6V (MAX11635/MAX11637), V
= 4.75V to 5.25V (MAX11634/MAX11636), f
= 300kHz, f
= 4.8MHz
SCLK
DD
DD
SAMPLE
(external clock, 50% duty cycle), V
= 2.5V (MAX11635/MAX11637), V
= 4.096V (MAX11634/MAX11636) T = T
to T
,
REF
REF
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
Input Leakage Current
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
0.01
15
MAX
UNITS
µA
I
V
= 0V or V
DD
1.0
IN
IN
C
pF
IN
DIGITAL OUTPUTS (DOUT, EOC)
I
I
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Voltage Low
V
V
OL
SINK
Output Voltage High
V
= 1.5mA
V - 0.5
DD
V
OH
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
I
CS = V
CS = V
0.05
15
1
µA
pF
L
DD
DD
C
OUT
MAX11634/MAX11636
MAX11635/MAX11637
4.75
2.7
5.25
3.6
Supply Voltage
V
DD
V
f
f
= 300ksps
= 0, REF on
1750
1000
0.2
2000
1200
5
SAMPLE
SAMPLE
Internal
reference
4–MAX1637
MAX11635/MAX11637
Supply Current (Note 10)
I
µA
Shutdown
= 300ksps
DD
f
1050
0.2
1200
5
External
reference
SAMPLE
Shutdown
f
f
= 300ksps
= 0, REF on
2300
1050
0.2
2550
1350
5
SAMPLE
SAMPLE
Internal
reference
MAX11634/MAX11636
Supply Current (Note 10)
I
Shutdown
= 300ksps
µA
DD
1700
f
1500
0.2
External
reference
SAMPLE
Shutdown
5
V
V
= 2.7V to 3.6V, full-scale input
= 4.75V to 5.25V, full-scale input
0.2
1
DD
Power-Supply Rejection
PSR
mV
0.2
1.4
DD
ꢁote 2: Limits at T = -40°C are guaranteed by design and not production tested.
A
ꢁote 3: Tested at V
= 3V (MAX11635/MAX11637); V
= 5V (MAX11634/MAX11636), unipolar input mode.
DD
DD
ꢁote 4: Offset nulled.
ꢁote 5: Time for reference to power up and settle to within 1 LSB.
ꢁote 6: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
ꢁote 7: The operational input voltage range for each individual input of a differentially configured pair is from GND to V . The
DD
operational input voltage difference is from -V
/2 to +V
REF
/2.
REF
ꢁote 8: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
ꢁote 9: When CNVST is configured as a digital input, do not apply a voltage between V and V
.
IH
IL
ꢁote 10: Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
Temperature measurements always use the internal reference.
4
_______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
TIMIꢁG CHARACTERISTICS (Figure 1)
PARAMETER
SYMBOL
CONDITIONS
Externally clocked conversion
Data I/O
MIN
208
100
40
TYP
MAX
UNITS
SCLK Clock Period
t
ns
CP
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS Low to SCLK Setup
CS High to SCLK Setup
CS High After SCLK Hold
CS Low After SCLK Hold
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
CH
t
40
CL
t
C
LOAD
C
LOAD
C
LOAD
= 30pF
= 30pF
= 30pF
40
40
40
DOT
t
DOD
t
DOE
t
40
0
DS
DH
t
t
t
40
40
0
CSS0
CSS1
CSH1
CSH0
t
t
0
4
t
CKSEL = 00
40
1.4
CSPW
CNVST Pulse-Width Low
CKSEL = 01
Voltage conversion
Reference power-up
7
CS or CNVST Rise to EOC
Low (Note 11)
µs
65
ꢁote 11: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal
reference needs to be powered up, the total time is additive. The internal reference is always used for temperature
measurements.
Typical Operating Characteristics
(V
= 3V, V
= 2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C for MAX11635/MAX11637, unless otherwise noted. V
= 5V,
DD
REF
SCLK
LOAD
A
DD
V
REF
= 4.096V, f
= 4.8MHz, C = 30pF, T = +25°C for MAX11634/MAX11636, unless otherwise noted.)
LOAD A
SCLK
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.0
1.0
0.8
1.0
0.8
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
MAX11634/MAX11636
MAX11634/MAX11636
MAX11635/MAX11637
f
= 300ksps
SAMPLE
f
= 300ksps
SAMPLE
f
= 300ksps
SAMPLE
0
1024
2048
3072
4096
0
1024
2048
3072
4096
0
1024
2048
3072
4096
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
_______________________________________________________________________________________
5
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Typical Operating Characteristics (continued)
(V
= 3V, V
= 2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C for MAX11635/MAX11637, unless otherwise noted. V
= 5V,
DD
REF
SCLK
LOAD
A
DD
V
REF
= 4.096V, f
= 4.8MHz, C = 30pF, T = +25°C for MAX11634/MAX11636, unless otherwise noted.)
LOAD A
SCLK
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SINAD vs. FREQUENCY
SFDR vs. FREQUENCY
1.0
80
75
70
65
60
55
50
100
90
80
70
60
50
MAX11634/MAX11636
0.8
0.6
MAX11634/MAX11636
0.4
0.2
MAX11635/MAX11637
0
-0.2
-0.4
-0.6
-0.8
-1.0
MAX11635/MAX11637
100 1000
MAX11635/MAX11637
f
= 300ksps
SAMPLE
0
1024
2048
3072
4096
1
10
100
1000
1
10
OUTPUT CODE (DECIMAL)
FREQUENCY (kHz)
FREQUENCY (kHz)
4–MAX1637
THD vs. FREQUENCY
SUPPLY CURRENT vs. SAMPLING RATE
-50
-60
3000
2500
2000
1500
1000
500
MAX11634/MAX11636
V
= 5V
DD
MAX11635/MAX11637
-70
INTERNAL REFERENCE
-80
EXTERNAL REFERENCE
-90
MAX11634/MAX11636
100
-100
0
1
10
1000
1
10
100
1000
FREQUENCY (kHz)
SAMPLING RATE (ksps)
SUPPLY CURRENT vs. SAMPLING RATE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1800
1600
1400
1200
1000
800
2600
2400
2200
2000
1800
1600
1400
1200
1000
MAX11635/MAX11637
INTERNAL REFERENCE
V
= 3V
DD
INTERNAL REFERENCE
EXTERNAL REFERENCE
600
EXTERNAL REFERENCE
400
MAX11634/MAX11636
200
f
= 300ksps
SAMPLE
0
1
10
100
1000
4.75
4.85
4.95
5.05
5.15
5.25
SAMPLING RATE (ksps)
V
(V)
DD
6
_______________________________________________________________________________________
12-Bit 300ksps ADCs with FIFO,
Temp Sensor, Internal Reference
4–MAX1637
Typical Operating Characteristics (continued)
(V
= 3V, V
= 2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C for MAX11635/MAX11637, unless otherwise noted. V
= 5V,
DD
REF
SCLK
LOAD
A
DD
V
REF
= 4.096V, f
= 4.8MHz, C = 30pF, T = +25°C for MAX11634/MAX11636, unless otherwise noted.)
LOAD A
SCLK
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
2000
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
1800
1600
1400
1200
1000
800
INTERNAL REFERENCE
EXTERNAL REFERENCE
600
400
MAX11635/MAX11637
= 300ksps
MAX11634/MAX11636
MAX11635/MAX11637
200
f
SAMPLE
V
= 5V
V
= 3V
DD
DD
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
4.75
4.85
4.95
5.05
(V)
5.15
5.25
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
(V)
V
V
DD
DD
V
DD
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
1800
1600
1400
1200
1000
800
2500
2200
1900
1600
1300
1000
INTERNAL REFERENCE
INTERNAL REFERENCE
MAX11635/MAX11637
V
DD
= 3V
f
= 300ksps
SAMPLE
EXTERNAL REFERENCE
MAX11634/MAX11636
EXTERNAL REFERENCE
V
= 5V
DD
f
= 300ksps
SAMPLE
600
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
2.5
2.0
1.5
1.0
0.5
0
MAX11635/MAX11637
MAX11634/MAX11636
V
= 3V
V
= 5V
DD
DD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Typical Operating Characteristics (continued)
(V
= 3V, V
= 2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C for MAX11635/MAX11637, unless otherwise noted. V
= 5V,
DD
REF
SCLK
LOAD
A
DD
V
REF
= 4.096V, f
= 4.8MHz, C = 30pF, T = +25°C for MAX11634/MAX11636, unless otherwise noted.)
LOAD A
SCLK
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
4.099
2.502
2.501
2.500
2.499
2.498
2.497
4.12
4.11
4.10
4.09
4.08
4.07
4.098
4.097
4.096
4.095
4.094
MAX11634/MAX11636
MAX11635/MAX11637
MAX11634/MAX11636
V
= 5V
V
DD
= 3V
V
DD
= 5V
DD
4.75
4.85
4.95
5.05
(V)
5.15
5.25
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
V
DD
V
DD
(V)
TEMPERATURE (°C)
4–MAX1637
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.6
0.4
0.2
0
2.52
2.51
2.50
2.49
2.48
2.47
-0.2
-0.4
-0.6
MAX11634/MAX11636
MAX11635/MAX11637
= 3V
f
= 300ksps
SAMPLE
V
DD
4.75
4.85
4.95
5.05
5.15
5.25
-40
-15
10
35
60
85
V
DD
(V)
TEMPERATURE (°C)
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
1.10
1.05
1.00
0.95
0.90
1.0
0.6
0.2
-0.2
-0.6
-1.0
MAX11635/MAX11637
MAX11634/MAX11636
f
= 300ksps
SAMPLE
f
= 300ksps
SAMPLE
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
DD
8
_______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
Typical Operating Characteristics (continued)
(V
= 3V, V
= 2.5V, f
= 4.8MHz, C
= 30pF, T = +25°C for MAX11635/MAX11637, unless otherwise noted. V
= 5V,
DD
REF
SCLK
LOAD
A
DD
V
REF
= 4.096V, f
= 4.8MHz, C = 30pF, T = +25°C for MAX11634/MAX11636, unless otherwise noted.)
LOAD A
SCLK
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. SUPPLY VOLTAGE
1.5
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
1.3
1.1
0.9
0.7
0.5
MAX11635/MAX11637
f = 300ksps
SAMPLE
MAX11634/MAX11636
MAX11635/MAX11637
f
= 300ksps
SAMPLE
f
= 300ksps
SAMPLE
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
5.15
5.25
2.7
3.0
3.3
3.6
TEMPERATURE (°C)
V
DD
(V)
V
DD
(V)
SAMPLING ERROR
vs. SOURCE IMPEDANCE
GAIN ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
1.0
0.6
0.5
0.3
2
0
MAX11635/MAX11637
f
= 300ksps
SAMPLE
-2
0.2
0.1
-4
-0.2
-0.6
-1.0
-0.1
-0.3
-0.5
-6
-8
MAX11634/MAX11636
f
= 300ksps
SAMPLE
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
0
2
4
6
8
10
TEMPERATURE (°C)
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
_______________________________________________________________________________________
9
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Pin Configuration
TOP VIEW
+
AIN0
1
2
3
4
5
6
7
8
16 EOC
AIN1
AIN2
15 DOUT
14 DIN
13 SCLK
12 CS
AIN3
MAX11634–
MAX11637
AIN4 (N.C.)
AIN5 (N.C.)
REF-/AIN6 (REF-)
11
10 GND
REF+
V
DD
CNVST/AIN7 (CNVST)
9
QSOP
( ) PINOUT FOR THE MAX11634/MAX11635.
4–MAX1637
Pin Description
PIN
MAX11634
MAX11635
NAME
FUNCTION
MAX11636
MAX11637
1–4
5, 6
7
—
—
—
AIN0–AIN3
N.C.
Analog Inputs
No Connection. Not internally connected.
REF-
External Differential Reference Negative Input
Active-Low Conversion Start Input. See Table 3 for details on programming the
setup register.
8
—
CNVST
9
9
REF+
GND
Positive Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
10
11
12
10
11
12
V
DD
Power Input. Bypass to GND with a 0.1µF capacitor.
Active-Low Chip-Select Input. When CS is high, DOUT is high impedance.
CS
Serial-Clock Input. Clocks data in and out of the serial interface (duty cycle must
be 40% to 60%). See Table 3 for details on programming the clock mode.
13
14
15
13
14
15
SCLK
Serial-Data Input. DIN data is latched into the serial interface on the rising edge of
SCLK.
DIN
Serial-Data Output. Data is clocked out on the falling edge of SCLK. High
DOUT
impedance when CS is connected to V
.
DD
16
—
16
EOC
Active-Low End-of-Conversion Output. Data is valid after EOC pulls low.
1–6
AIN0–AIN5
Analog Inputs
External Differential Reference Negative Input/Analog Input 6. See Table 3 for
details on programming the setup register.
—
—
7
8
REF-/AIN6
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on
programming the setup register.
CNVST/AIN7
10 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
CS
t
CSH0
t
t
t
CSH1
t
CH
CP
CSS0
t
CSS1
t
CL
SCLK
DIN
t
DH
t
DS
t
t
DOT
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
EOC
OSCILLATOR
CONTROL
CNVST
AIN0
AIN1
12-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
T/H
AIN7
REF-
REF+
INTERNAL
REFERENCE
MAX11634–MAX11637
Figure 2. Functional Diagram
Microprocessor (µP) control is made easy through a 3-
wire SPI/QSPI/MICROWIRE-compatible serial interface.
Detailed Description
The MAX11634–MAX11637 are low-power, serial-out-
put, multichannel ADCs for temperature-control,
process-control, and monitoring applications. These
12-bit ADCs have internal track and hold (T/H) circuitry
that supports single-ended and fully differential inputs.
Data is converted from analog voltage sources in a
variety of channel and data-acquisition configurations.
Figure 2 shows a simplified functional diagram of the
MAX11634–MAX11637 internal architecture. The
MAX11636/MAX11637 have eight single-ended analog
input channels or four differential channels. The
MAX11634/MAX11635 have four single-ended analog
input channels or two differential channels.
______________________________________________________________________________________ 11
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
the subsequent data bytes are clocked from DIN into
Converter Operation
The MAX11634–MAX11637 ADCs use a fully differen-
tial, successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
temperature and voltage signals into a 12-bit digital
result. Both single-ended and differential configurations
are supported, with a unipolar signal range for single-
ended mode and bipolar or unipolar ranges for differ-
ential mode.
the serial interface on the rising edge of SCLK.
Tables 1–7 detail the register descriptions. Bits 5 and 4,
CKSEL1 and CKSEL0, respectively, control the clock
modes in the setup register (see Table 3). Choose
between four different clock modes for various ways to
start a conversion and determine whether the acquisi-
tions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN7 to act as a conver-
sion start and use it to request the programmed, inter-
nally timed conversions without tying up the serial bus.
In clock mode 01, use CNVST to request conversions
one channel at a time, controlling the sampling speed
without tying up the serial bus. Request and start inter-
nally timed conversions through the serial interface by
writing to the conversion register in the default clock
mode 10. Use clock mode 11 with SCLK up to 4.8MHz
for externally timed acquisitions to achieve sampling
rates up to 300ksps. Clock mode 11 disables scanning
and averaging. See Figures 4–7 for timing specifica-
tions and how to begin a conversion.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
Analog Input Protection
Internal ESD protection diodes clamp all pins to V
DD
and GND, allowing the inputs to swing from (GND -
0.3V) to (V + 0.3V) without damage. However, for
4–MAX1637
DD
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last-
requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). In clock mode
01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or CNVST
goes low. EOC is always high in clock mode 11.
accurate conversions near full scale, the inputs must
not exceed V by more than 50mV or be lower than
DD
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
3-Wire Serial Interface
The MAX11634–MAX11637 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices.
For SPI/QSPI, ensure the CPU serial interface runs in
master mode so it generates the serial clock signal.
Select the SCLK frequency of 10MHz or less, and set
clock polarity (CPOL) and phase (CPHA) in the µP con-
trol registers to the same value. The MAX11634–
MAX11637 operate with SCLK idling high or low, and
thus operate with CPOL = CPHA = 0 or CPOL = CPHA
= 1. Set CS low to latch input data at DIN on the rising
edge of SCLK. Output data at DOUT is updated on the
falling edge of SCLK. Bipolar true differential results are
available in two’s complement format, while all others
are in binary.
Single-Ended/Differential Input
The MAX11634–MAX11637 use a fully differential ADC
for all conversions. The analog inputs can be config-
ured for either differential or single-ended conversions
by writing to the setup register (see Table 3). Single-
ended conversions are internally referenced to GND
(see Figure 3).
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, and
AIN6/AIN7. AIN0–AIN7 are available on the MAX11636/
MAX11637. AIN0–AIN3 are available on the MAX11634/
MAX11635. See Tables 2–5 for more details on config-
uring the inputs. For the inputs that can be configured
as CNVST or an analog input, only one can be used at
a time. For the inputs that can be configured as REF- or
an analog input, the REF- configuration excludes the
analog input.
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. Use a second
byte, immediately following the setup byte, to write to
the unipolar mode or bipolar mode registers (see
Tables 1, 3, 4, and 5). A high-to-low transition on CS ini-
tiates the data input operation. The input data byte and
12 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
T/H enters hold mode, the difference between the sam-
pled positive and negative input voltages is converted.
REF
GND
AIN0–AIN7
(SINGLE-ENDED);
AIN0, AIN2,
AIN4, AIN6
(DIFFERENTIAL)
DAC
The time required for the T/H to acquire an input signal
is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
CIN+
COMPARATOR
the required acquisition time lengthens. The acquisition
+
time, t
, is the maximum time needed for a signal to
ACQ
HOLD
be acquired, plus the power-up time. It is calculated by
-
the following equation:
GND
(SINGLE-ENDED);
AIN1, AIN3,
AIN5, AIN7
(DIFFERENTIAL)
CIN-
t = 9 x (R + R ) x 24pF + t
ACQ S IN PWR
where R = 1.5kΩ, R is the source impedance of the
IN
S
PWR
HOLD
HOLD
input signal, and t
= 1µs, the power-up time of the
device. The varying power-up times are detailed in the
explanation of the clock mode conversions.
V
DD
/2
When the conversion is internally timed, t
is never
ACQ
Figure 3. Equivalent Input Circuit
less than 1.4µs, and any source impedance below
300Ω does not significantly affect the ADC’s AC perfor-
mance. A high-impedance source can be accommo-
Unipolar/Bipolar
Address the unipolar and bipolar registers through the
setup register (bits 1 and 0). Program a pair of analog
channels for differential operation by writing a 1 to the
appropriate bit of the bipolar or unipolar register.
Unipolar mode sets the differential input range from 0
dated either by lengthening t
or by placing a 1µF
ACQ
capacitor between the positive and negative analog
inputs.
Internal FIFO
The MAX11634–MAX11637 contain a FIFO buffer that
can hold up to 16 ADC results. This allows the ADC to
handle multiple internally clocked conversions without
tying up the serial bus.
to V
. A negative differential analog input in unipolar
REF
mode causes the digital output code to be zero.
Selecting bipolar mode sets the differential input range
to
V
REF
/2. The digital output code is binary in unipolar
mode and two’s complement in bipolar mode (Figures
8 and 9).
If the FIFO is filled and further conversions are requested
without reading from the FIFO, the oldest ADC results
are overwritten by the new ADC results. Each result
contains 2 bytes, with the MSB preceded by four lead-
ing zeros. After each falling edge of CS, the oldest
available byte of data is available at DOUT, MSB first.
When the FIFO is empty, DOUT is zero.
In single-ended mode, the MAX11634–MAX11637
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input
range from 0 to V
.
REF
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX11634–MAX11637s’ input architecture. In track
mode, a positive input capacitor is connected to
AIN0–AIN7 in single-ended mode (and AIN0, AIN2,
AIN4, AIN5, AIN6 in differential mode). A negative input
capacitor is connected to GND in single-ended mode
(or AIN1, AIN3, AIN5, AIN6, AIN7 in differential mode).
For external T/H timing, use clock mode 01. After the
Internal Clock
The MAX11634–MAX11637 operate from an internal
oscillator, which is accurate within 10% of the 4.4MHz
nominal clock rate. The internal oscillator is active in
clock modes 00, 01, and 10. Read out the data at clock
speeds up to 10MHz. See Figures 4–7 for details on
timing specifications and starting a conversion.
______________________________________________________________________________________ 13
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
In clock mode 01, the total conversion time depends on
Applications Information
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
Register Descriptions
The MAX11634–MAX11637 communicate between the
internal registers and the external circuitry through the
SPI/QSPI-compatible serial interface. Table 1 details
the registers and the bit names. Tables 2–7 show the
various functions within the conversion register, setup
register, averaging register, reset register, unipolar reg-
ister, and bipolar register.
Conversion Register
Select active analog input channels and scan modes
by writing to the conversion register. Table 2 details
channel selection, the four scan modes, and how to
request a temperature measurement. Request a scan
by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01.
Conversion Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, and if the external
reference is in use.
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
table as applicable):
A conversion is not performed if it is requested on a
channel that has been configured as CNVST or REF-.
Do not request conversions on channels 4–7 on the
MAX11634/MAX11635. Set CHSEL[2:0] to the lower
channel’s binary values. If the last two channels are
configured as a differential pair and one of them has
been reconfigured as CNVST or REF-, the pair is
ignored.
Total Conversion Time = t
x n
x n
+ t
CNV
AVG
RESULT RP
4–MAX1637
where:
t
= t
+ t
CONV
(MAX)
CNV
ACQ
(MAX)
n
n
= samples per result (amount of averaging)
AVG
Select scan mode 00 or 01 to return one result per
single-ended channel and one result per differential
pair within the requested range. Select scan mode 10
to scan a single input channel numerous times,
depending on NSCAN1 and NSCAN0 in the averag-
ing register (Table 6). Select scan mode 11 to return
only one result from a single channel.
= number of FIFO results requested; deter-
mined by number of channels being scanned or by
NSCAN1, NSCAN0
RESULT
t
= internal reference wake up; set to zero if internal
reference is already powered up or external reference
is being used
RP
Table 1. Input Data Byte (MSB First)
REGISTER NAME
Conversion
BIT 7
BIT 6
BIT 5
CHSEL2
CKSEL1
1
BIT 4
CHSEL1
CKSEL0
AVGON
1
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
X
BIT 2
SCAN1
REFSEL0
NAVG0
X
BIT 1
BIT 0
1
X
SCAN0
X
Setup
0
1
DIFFSEL1
DIFFSEL0
Averaging
0
0
NSCAN1
NSCAN0
Reset
0
0
0
X
X
X
X
X
X
Unipolar Mode (Setup)
Bipolar Mode (Setup)
X = Don’t care.
UCH0/1
BCH0/1
UCH2/3
BCH1/2
UCH4/5
BCH4/5
UCH6/7
BCH6/7
X
X
X
14 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the
unipolar mode and bipolar mode registers and configure
the analog input channels for differential operation.
Table 2. Conversion Register*
BIT
BIT
FUNCTION
NAME
Unipolar/Bipolar Mode Registers
The final 2 bits (LSBs) of the setup register control the
unipolar/bipolar mode address registers. Set bits 1 and
0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipo-
lar mode register. Set bits 1 and 0 to 11 to write to the
bipolar mode register. In both cases, the setup byte
must be followed immediately by 1 byte of data written
to the unipolar register or bipolar register. Hold CS low
and run 16 SCLK cycles before pulling CS high. If the
last 2 bits of the setup register are 00 or 01, neither the
unipolar mode register nor the bipolar mode register is
written. Any subsequent byte is recognized as a new
input data byte. See Tables 4 and 5 to program the
unipolar and bipolar mode registers.
—
7 (MSB) Set to 1 to select conversion register
X
6
5
4
3
2
1
Don’t care
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
X
Analog input channel select
Analog input channel select
Analog input channel select
Scan mode select
Scan mode select
0 (LSB) Don’t care
*See below for bit details.
SELECTED
CHANNEL (N)
CHSEL2
CHSEL1
CHSEL0
If a channel is configured as both unipolar and bipolar,
the unipolar setting takes precedence. In unipolar
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
mode, AIN+ can exceed AIN- by up to V
. The out-
REF
put format in unipolar mode is binary. In bipolar mode,
either input can exceed the other by up to V
output format in bipolar mode is two's complement.
/2. The
REF
Averaging Register
Write to the averaging register to configure the ADC to
average up to 32 samples for each requested result,
and to independently control the number of results
requested for single-channel scans.
Table 2 details the four scan modes available in the con-
version register. All four scan modes allow averaging as
long as the AVGON bit, bit 4 in the averaging register, is
set to 1. Select scan mode 10 to scan the same channel
multiple times. Clock mode 11 disables averaging.
SCAN MODE (CHANNEL N IS
SELECTED BY BITS CHSEL[2:0])
SCAN1 SCAN0
0
0
0
1
Scans channels 0 through N
Scans channels N through the highest
numbered channel
Reset Register
Write to the reset register (as shown in Table 7) to clear
the FIFO or to reset all registers to their default states.
Set the RESET bit to 1 to reset the FIFO. Set the RESET
bit to zero to return the MAX11634–MAX11637 to the
default power-up state.
Scans channel N repeatedly. The averaging
register sets the number of results.
1
1
0
1
No scan. Converts channel N once only.
Setup Register
Write a byte to the setup register to configure the clock,
reference, and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode, acquisition and sam-
pling, and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reference use.
Power-Up Default State
The MAX11634–MAX11637 power up with all blocks in
shutdown, including the reference. All registers power up
in state 00000000, except for the setup register, which
powers up in clock mode 10 (CKSEL1 = 1).
______________________________________________________________________________________ 15
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Table 3. Setup Register*
BIT NAME
—
BIT
FUNCTION
7 (MSB) Set to 0 to select setup register
—
6
Set to 1 to select setup register
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
5
Clock mode and CNVST configuration. Resets to 1 at power-up.
Clock mode and CNVST configuration
4
3
Reference mode configuration
2
1
Reference mode configuration
Unipolar/bipolar mode register configuration for differential mode
Unipolar/bipolar mode register configuration for differential mode
0 (LSB)
*See below for bit details.
CKSEL1
CKSEL0
CONVERSION CLOCK
Internal
ACQUISITION/SAMPLING
Internally timed
CNVST CONFIGURATION
0
0
1
1
0
1
0
1
CNVST
CNVST
AIN7*
AIN7*
Internal
Externally timed through CNVST
Internally timed
Internal
4–MAX1637
External (4.8MHz max)
Externally timed through SCLK
*The MAX11634/MAX11635 have a dedicated CNVST pin.
REFSEL1 REFSEL0
VOLTAGE REFERENCE
Internal
AutoShutdown
REF- CONFIGURATION
Reference off after scan; need
wake-up delay
0
0
1
1
0
1
0
1
AIN6
AIN6
AIN6
REF-*
External single-ended
Internal
Reference off; no wake-up delay
Reference always on; no wake-
up delay
External differential
Reference off; no wake-up delay
*The MAX11634/MAX11635 have a dedicated REF- pin.
DIFFSEL1 DIFFSEL0
FUNCTION
0
0
1
1
0
1
0
1
No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged.
1 byte of data follows the setup byte and is written to the unipolar mode register.
1 byte of data follows the setup byte and is written to the bipolar mode register.
16 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
edge of SCLK. Conversions in clock modes 00 and 01
are initiated by CNVST. Conversions in clock modes 10
and 11 are initiated by writing an input data byte to the
conversion register. Data is binary for unipolar mode and
two’s complement for bipolar mode.
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11634–MAX11637. The 12-bit conversion result is
output in MSB-first format with four leading zeros. DIN
data is latched into the serial interface on the rising
edge of SCLK. Data on DOUT transitions on the falling
Table 4. Unipolar Mode Register (Addressed Through Setup Register)
BIT NAME
BIT
FUNCTION
UCH0/1
7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion
UCH2/3
6
5
4
3
2
1
Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion
UCH4/5
Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion
UCH6/7
Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion
X
X
X
X
Don’t care
Don’t care
Don’t care
0 (LSB) Don’t care
Table 5. Bipolar Mode Register (Addressed Through Setup Register)
BIT NAME
BIT
FUNCTION
BCH0/1
7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion
BCH2/3
6
5
4
3
2
1
Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion
BCH4/5
Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion
BCH6/7
Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion
X
X
X
X
Don’t care
Don’t care
Don’t care
0 (LSB) Don’t care
______________________________________________________________________________________ 17
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Table 6. Averaging Register*
BIT NAME
—
BIT
FUNCTION
7 (MSB) Set to 0 to select averaging register
—
6
5
4
3
2
1
Set to 0 to select averaging register
Set to 1 to select averaging register
—
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
Set to 1 to turn averaging on. Set to 0 to turn averaging off.
Configures the number of conversions for single-channel scans
Configures the number of conversions for single-channel scans
Single-channel scan count (scan mode 10 only)
0 (LSB) Single-channel scan count (scan mode 10 only)
*See below for bit details.
AVGON
NAVG1
NAVG0
FUNCTION
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs 1 conversion for each requested result
Performs 4 conversions and returns the average for each requested result
Performs 8 conversions and returns the average for each requested result
Performs 16 conversions and returns the average for each requested result
Performs 32 conversions and returns the average for each requested result
4–MAX1637
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results
Scans channel N and returns 8 results
Scans channel N and returns 12 results
Scans channel N and returns 16 results
Table 7. Reset Register
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to 0 to select reset register
—
6
Set to 0 to select reset register
Set to 0 to select reset register
Set to 1 to select reset register
—
5
—
4
RESET
3
Set to 0 to reset all registers; set to 1 to clear the FIFO only
X
X
X
2
1
Don’t care
Don’t care
Don’t care
0 (LSB)
18 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
the internal oscillator. See Figure 5 for clock mode 01
timing.
Internally Timed Acquisitions and
Conversions Using CNVST
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If the internal
reference needs to wake up, an additional 65µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement are internally
timed. In this case, hold CNVST low for at least 40ns.
Performing Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11634–MAX11637
then wake up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
complete, EOC is pulled low and the results are avail-
able in the FIFO. Wait until EOC goes low before pulling
CS low to communicate with the serial interface. EOC
stays low until CS or CNVST is pulled low again.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next requested channel. The result is available on
DOUT once EOC has been pulled low.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
LSB1
MSB2
MSB1
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Figure 4. Clock Mode 00
______________________________________________________________________________________ 19
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
CNVST
(CONVERSION2)
(ACQUISITION1)
(ACQUISITION2)
CS
(CONVERSION1)
SCLK
DOUT
EOC
LSB1
MSB1
MSB2
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
Figure 5. Clock Mode 01
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DIN
4–MAX1637
CS
SCLK
DOUT
LSB1
MSB1
MSB2
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
Figure 6. Clock Mode 10
Internally Timed Acquisitions and
Conversions Using the Serial Interface
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This is
the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11634–MAX11637 then power up, scan all
requested channels, store the results in the FIFO, and
shut down. After the scan is complete, EOC is pulled
low and the results are available in the FIFO. EOC stays
low until CS is pulled low again.
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the eighth and ninth cycles, the pulse
width must be less than 100µs. To continuously convert
at 16 cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
20 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
(CONVERSION BYTE)
DIN
(ACQUISITION2)
(ACQUISITION1)
(CONVERSION1)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11
MAX11634–MAX11637 package. High-frequency noise
in the V power supply can affect performance.
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b[7:0]). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the four leading bits (nor-
mally zeros) are ignored. Internal registers that are
written partially through the SPI contain new values,
starting at the MSB up to the point that the partial write
is stopped. The part of the register that is not written
contains previously written values. If CS is pulled low
before EOC goes low, a conversion cannot be complet-
ed and the FIFO is corrupted.
DD
Bypass the V
close to the V
supply with a 0.1µF capacitor to GND,
pin. Minimize capacitor lead lengths for
DD
DD
best supply-noise rejection. If the power supply is very
noisy, connect a 10Ω resistor in series with the supply to
improve power-supply filtering.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX11634–MAX11637 is measured using the end-
point method.
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended or differential inputs. Figure 9 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Output coding is binary, with 1 LSB = V
/4096 for
REF
unipolar and bipolar operation, and 1 LSB = 0.125°C
for temperature measurements.
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Do not use wire-
wrap boards. Board layout should ensure that digital
and analog signal lines are separated from each other.
Do not run analog and digital (especially clock) signals
parallel to one another or run digital lines underneath the
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
______________________________________________________________________________________ 21
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
OUTPUT CODE
OUTPUT CODE
V
FULL-SCALE
TRANSITION
REF
2
FS
+ V
=
COM
011. . . 111
011. . .110
11. . .111
11. . .110
ZS = COM
-V
2
REF
11. . .101
+ V
REF
-FS =
COM
000. . . 010
000. . .001
000. . .000
V
4096
1 LSB =
FS = V + V
REF
COM
111 . . .111
111 . . . 110
111 . . . 101
ZS = V
COM
V
REF
1 LSB =
4096
00. . .011
00. . .010
100 . . . 001
100. . . 000
00. . . 001
00. . . 000
0
1
2
3
FS
COM*
- FS
+FS - 1 LSB
(COM)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
INPUT VOLTAGE (LSB)
*V
≥ V / 2
REF
COM
4–MAX1637
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
Figure 9. Bipolar Transfer Function, Full Scale ( FS) =
V
REF
/2
REF
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
⎡
⎤
2
2
2
2
THD = 20 xlog
V
+ V + V + V
V
1
(
)
2
3
4
5
⎢
⎣
⎥
⎦
where V is the fundamental amplitude, and V –V are
the amplitudes of the 2nd-order to 5th-order harmonics.
1
2
5
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
SINAD (dB) = 20 x log (Signal
/Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
22 ______________________________________________________________________________________
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
4–MAX1637
Package Information
Chip Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTꢀIꢁE
ꢁO.
ꢀAꢁD
PATTERꢁ ꢁO.
16 QSOP
E16+5
21-0055
90-0167
______________________________________________________________________________________ 23
12-Bit, 300ksps ADCs with Differential
Track/Hold, and Internal Reference
Revision History
REVISIOꢁ REVISIOꢁ
PAGES
CHAꢁGED
DESCRIPTIOꢁ
ꢁUMBER
DATE
0
1
6/11
9/11
Initial release
Released the MAX11636/MAX11637 and revised the Transfer Function section.
—
1, 21
4–MAX1637
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX11643EEG+
ADC, Successive Approximation, 8-Bit, 1 Func, 16 Channel, Serial Access, BICMOS, PDSO24, ROHS COMPLIANT, QSOP-24
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