MAX11638EEE+ [MAXIM]
ADC Single SAR 300ksps 8-bit Serial 16-Pin QSOP;
| 型号： | MAX11638EEE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC Single SAR 300ksps 8-bit Serial 16-Pin QSOP 信息通信管理 光电二极管 转换器 |
| 文件： | 总22页 (文件大小：1189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-6035; Rev 0; 9/11
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
General Description
Features
The MAX11638/MAX11639/MAX11642/MAX11643 are
serial 8-bit analog-to-digital converters (ADCs) with an
internal reference. These devices feature on-chip FIFO,
scan mode, internal clock mode, internal averaging,
and AutoShutdown™. The maximum sampling rate is
300ksps using an external clock. The MAX11642/
MAX11643 have 16 input channels and the MAX11638/
MAX11639 have 8 input channels. These four devices
operate from either a +3V supply or a +5V supply, and
o Analog Multiplexer with Track-and-Hold (T/H)
16 Channels (MAX11642/MAX11643)
8 Channels (MAX11638/MAX11639)
o Single Supply
2.7V to 3.6V (MAX11639/MAX11643)
4.75V to 5.25V (MAX11638/MAX11642)
o Internal Reference
2.5V (MAX11639/MAX11643)
4.096V (MAX11638/MAX11642)
®
contain a 10MHz SPI-/QSPI™-/MICROWIRE -compati-
ble serial port.
o External Reference: 1V to V
DD
The MAX11638/MAX11639 are available in 16-pin
QSOP packages. The MAX11642/MAX11643 are avail-
able in 24-pin QSOP packages. All four devices are
specified over the extended -40°C to +85°C tempera-
ture range.
o 16-Entry First-In/First-Out (FIFO)
o Scan Mode, Internal Averaging, and Internal Clock
o Accuracy: 1 LSB INL, 1 LSB DNL, No Missing
Codes Over Temperature
o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible
Applications
System Supervision
Interface
o Small Packages
Data-Acquisition Systems
Industrial Control Systems
Patient Monitoring
16-Pin QSOP (MAX11638/MAX11639)
24-Pin QSOP (MAX11642/MAX11643)
Data Logging
Pin Configurations
Instrumentation
TOP VIEW
+
Ordering Information
AIN0
1
2
3
4
5
6
7
8
16 EOC
15 DOUT
14 DIN
AIN1
AIN2
NUMBER
OF
INPUTS
SUPPLY
VOLTAGE
RANGE (V)
PIN
PACKAGE
PART
AIN3
MAX11638
MAX11639
13
12
11
SCLK
CS
MAX11638EEE+T
MAX11639EEE+T
MAX11642EEG+T
MAX11643EEG+T
8
8
4.75 to 5.25 16 QSOP
2.7 to 3.6 16 QSOP
4.75 to 5.25 24 QSOP
2.7 to 3.6 24 QSOP
AIN4
AIN5
V
DD
16
16
AIN6
10 GND
REF
CNVST/AIN7
9
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Pin Configurations continued at end of data sheet.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-60°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (V
AIN0–AIN13, CNVST/AIN_,
REF to GND...........................................-0.3V to (V
Maximum Current into Any Pin............................................50mA
+ 0.3V)
DD
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
24-Pin QSOP (derate 9.5mW/°C above +70°C)...........762mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
16 QSOP
24 QSOP
Junction-to-Ambient Thermal Resistance (θ )................88°C/W
Junction-to-Ambient Thermal Resistance (θ )...............105°C/W
Junction-to-Case Thermal Resistance (θ )......................37°C/W
JA
JA
Junction-to-Case Thermal Resistance (θ ).......................34°C/W
JC
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +3.6V (MAX11639/MAX11643), V
= +4.75V to +5.25V (MAX11638/MAX11642), f
= 300kHz, f
SCLK
=
DD
SAMPLE
DD
4.8MHz (external clock 50% duty cycle), V
= 2.5V (MAX11639/MAX11643), V
= 4.096V (MAX11638/MAX11642), T = T
to
REF
A
MIN
REF
T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 3)
Resolution
RES
INL
8
Bits
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
0.5
0.5
1
DNL
No missing codes over temperature
(Note 4)
0.5
0.5
Gain Error
1
Offset Error Temperature
Coefficient
ppm/°C
FSR
2
Gain Temperature Coefficient
0.8
0.1
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, f
= 4.8MHz)
SCLK
892/MAX1643
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
SINAD
THD
49
-70
-72
-67
1
dB
dBc
dBc
dBc
MHz
kHz
Up to the 5th harmonic
SFDR
IMD
f
= 29.9kHz, f
= 30.1kHz
IN2
IN1
-3dB point
S/(N + D) > 48dB
Full-Linear Bandwidth
100
2
_______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX11639/MAX11643), V
= +4.75V to +5.25V (MAX11638/MAX11642), f
= 300kHz, f
SCLK
=
DD
SAMPLE
DD
4.8MHz (external clock 50% duty cycle), V
= 2.5V (MAX11639/MAX11643), V
= 4.096V (MAX11638/MAX11642), T = T
to
REF
A
MIN
REF
T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
External reference
0.8
65
Power-Up Time
t
µs
µs
µs
PU
Internal reference (Note 5)
Acquisition Time
Conversion Time
t
0.6
ACQ
Internally clocked
3.5
t
CONV
Externally clocked (Note 6)
Externally clocked conversion
Data I/O
2.7
0.1
4.8
10
External Clock Frequency
f
MHz
SCLK
Aperture Delay
30
ns
ps
Aperture Jitter
< 50
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL REFERENCE
Unipolar
0
V
V
REF
V
= V
0.01
24
1
µA
pF
IN
DD
During acquisition time (Note 7)
MAX11638/MAX11642
MAX11639/MAX11643
MAX11638/MAX11642
MAX11639/MAX11643
4.024
2.48
4.096
2.50
20
4.168
2.52
REF Output Voltage
V
REF Temperature Coefficient
V
REF
ppm/°C
k
30
Output Resistance
6.5
REF Output Noise
200
-70
µV
RMS
REF Power-Supply Rejection
EXTERNAL REFERENCE
REF Input Voltage Range
PSRR
dB
V
REF
1.0
V
DD
+ 50mV
100
V
V
V
= 2.5V (MAX11639/MAX11643),
= 4.096V (MAX11638/MAX11642),
REF
40
REF
f
= 300ksps
SAMPLE
REF Input Current
I
µA
REF
V
V
= 2.5V (MAX11639/MAX11643),
= 4.096V (MAX11638/MAX11642),
REF
0.1
5
REF
f
= 0
SAMPLE
_______________________________________________________________________________________
3
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +3.6V (MAX11639/MAX11643), V
= +4.75V to +5.25V (MAX11638/MAX11642), f
= 300kHz, f
SCLK
=
DD
SAMPLE
DD
4.8MHz (external clock 50% duty cycle), V
= 2.5V (MAX11639/MAX11643), V
= 4.096V (MAX11638/MAX11642), T = T
to
REF
A
MIN
REF
T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS, CNVST) (Note 8)
MAX11638/MAX11642
0.8
Input Voltage Low
Input Voltage High
V
V
V
IL
MAX11639/MAX11643
MAX11638/MAX11642
MAX11639/MAX11643
V
DD
x 0.3
2.0
V
IH
V
x 0.7
DD
Input Hysteresis
V
200
mV
µA
pF
HYST
Input Leakage Current
Input Capacitance
I
V
= 0V or V
DD
0.01
15
1.0
IN
IN
C
IN
DIGITAL OUTPUTS (DOUT, EOC)
I
I
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Voltage Low
V
V
OL
SINK
Output Voltage High
V
= 1.5mA
V - 0.5
DD
V
OH
SOURCE
Three-State Leakage Current
Three-State Output
I
CS = V
0.05
15
1
µA
pF
L
DD
DD
C
CS = V
OUT
POWER REQUIREMENTS
MAX11638/MAX11642
MAX11639/MAX11643
4.75
2.7
5.25
3.6
2000
1200
5
Supply Voltage
V
V
DD
f
f
= 300ksps
= 0, REF on
1750
1000
0.2
SAMPLE
SAMPLE
Internal reference
External reference
Internal reference
External reference
MAX11639/MAX11643 Supply
Current (Note 9)
µA
Shutdown
= 300ksps
I
DD
f
1050
0.2
1200
5
SAMPLE
Shutdown
f
f
= 300ksps
= 0, REF on
2300
1000
0.2
2550
1350
5
SAMPLE
SAMPLE
MAX11638/MAX11642 Supply
Current (Note 9)
I
µA
Shutdown
= 300ksps
DD
f
1550
0.2
1700
5
SAMPLE
Shutdown
= 2.7V to 3.6V, full-scale input
V
V
0.2
1
DD
Power-Supply Rejection
PSR
mV
= 4.75V to 5.25V, full-scale input
0.2
1.4
DD
Note 2: Limits at T = -40°C are guaranteed by design and not production tested.
A
892/MAX1643
Note 3: The MAX11639/MAX11643 tested at V
Note 4: Offset nulled.
= +3V. The MAX11638/MAX11642 tested at V
= +5V.
DD
DD
Note 5: Time for reference to power up and settle to within 1 LSB.
Note 6: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 7: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating
Characteristics section.
Note 8: When CNVST is configured as a digital input, do not apply a voltage between V and V
.
IL
IH
Note 9: Supply current is specified on whether an internal or external reference is used for voltage conversions.
4
_______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
TIMING CHARACTERISTICS
(V
= +2.7V to +3.6V (MAX11639/MAX11643), V
= +4.75V to +5.25V (MAX11638/MAX11642), f
= 300kHz, f
SCLK
=
DD
SAMPLE
DD
4.8MHz (external clock 50% duty cycle), V
= 2.5V (MAX11639/MAX11643), V
= 4.096V (MAX11638/MAX11642), T = T
to
REF
A
MIN
REF
T
MAX
, unless otherwise noted. Typical values are at T = +25°C.) (Note 2) (Figure 1)
A
PARAMETER
SYMBOL
CONDITIONS
Externally clocked conversion
Data I/O
MIN
208
100
40
TYP
MAX
UNITS
SCLK Clock Period
t
ns
CP
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Fall to DOUT Transition
CS Rise to DOUT Disable
CS Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS Low to SCLK Setup
CS High to SCLK Setup
CS High After SCLK Hold
CS Low After SCLK Hold
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
CH
t
CL
40
t
C
LOAD
C
LOAD
C
LOAD
= 30pF
= 30pF
= 30pF
40
40
40
DOT
t
DOD
t
DOE
t
40
0
DS
DH
t
t
t
40
40
0
CSS0
CSS1
CSH1
CSH0
t
t
0
4
t
CKSEL = 00
40
1.4
CSPW
CNVST Pulse-Width Low
CKSEL = 01
Voltage conversion
Reference power-up
7
CS or CNVST Rise to EOC
Low (Note 10)
µs
65
Note 10: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
Typical Operating Characteristics
(V
= 3V and V
= 2.5V (MAX11639/MAX11643), V
= 5V and V
= 4.096V (MAX11638/MAX11642), f
= 4.8MHz,
SCLK
DD
REF
DD
REF
C
= 30pF, f = 300ksps, T = +25°C, unless otherwise noted.)
SAMPLE A
LOAD
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
0.2
0.1
0
0.2
0.1
0
0.2
0.1
0
MAX11638/MAX11642
MAX11639/MAX11643
MAX11638/MAX11642
-0.1
-0.2
-0.1
-0.2
-0.1
-0.2
0
64
128
192
256
0
64
128
192
256
0
64
128
192
256
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
OUTPUT CODE (DECIMAL)
_______________________________________________________________________________________
5
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Typical Operating Characteristics (continued)
(V
= 3V and V
= 2.5V (MAX11639/MAX11643), V
= 5V and V
= 4.096V (MAX11638/MAX11642), f
= 4.8MHz,
SCLK
DD
REF
DD
REF
C
= 30pF, f = 300ksps, T = +25°C, unless otherwise noted.)
SAMPLE A
LOAD
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
SINAD vs. FREQUENCY
SFDR vs. FREQUENCY
52.0
51.5
51.0
50.5
50.0
49.5
49.0
48.5
48.0
80
75
70
65
60
0.2
0.1
0
MAX11639/MAX11643
MAX11639/MAX11643
MAX11638/MAX11642
MAX11638/MAX11642
MAX11639/MAX11643
-0.1
-0.2
1
10
100
1000
1
10
100
1000
0
64
128
192
256
FREQUENCY (kHz)
FREQUENCY (kHz)
OUTPUT CODE (DECIMAL)
THD vs. FREQUENCY
SUPPLY CURRENT vs. SAMPLING RATE
-50
-60
3000
MAX11638/MAX11642
2500
2000
1500
1000
500
MAX11639/MAX11643
MAX11638/MAX11642
-70
INTERNAL
REFERENCE
-80
EXTERNAL
REFERENCE
-90
-100
0
1
10
100
1000
1
10
100
1000
FREQUENCY (kHz)
SAMPLING RATE (ksps)
SUPPLY CURRENT vs. SAMPLING RATE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1800
1600
1400
1200
1000
800
2600
2400
2200
2000
1800
1600
1400
1200
1000
MAX11639/MAX11643
INTERNAL
REFERENCE
892/MAX1643
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
EXTERNAL
REFERENCE
600
400
200
MAX11638/MAX11642
0
1
10
100
1000
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
SAMPLING RATE (ksps)
V
DD
(V)
6
_______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
Typical Operating Characteristics (continued)
(V
= 3V and V
= 2.5V (MAX11639/MAX11643), V
= 5V and V
= 4.096V (MAX11638/MAX11642), f
= 4.8MHz,
SCLK
DD
REF
DD
REF
C
= 30pF, f = 300ksps, T = +25°C, unless otherwise noted.)
SAMPLE A
LOAD
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.5
0.4
0.3
0.2
0.1
0
2000
1800
1600
1400
1200
1000
800
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
MAX11639/MAX11643
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
600
400
200
MAX11638/MAX11642
MAX11639/MAX11643
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5.15 5.20 5.25
V
(V)
V
(V)
V
(V)
DD
DD
DD
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
2500
2200
1900
1600
1300
1000
1800
1600
1400
1200
1000
800
INTERNAL
REFERENCE
INTERNAL
REFERENCE
EXTERNAL
REFERENCE
EXTERNAL
REFERENCE
MAX11638/MAX11642
MAX11639/MAX11643
600
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
2.5
2.0
1.5
1.0
0.5
0
MAX11639/MAX11643
MAX11638/MAX11642
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Typical Operating Characteristics (continued)
(V
= 3V and V
= 2.5V (MAX11639/MAX11643), V
= 5V and V
= 4.096V (MAX11638/MAX11642), f
= 4.8MHz,
SCLK
DD
REF
DD
REF
C
= 30pF, f = 300ksps, T = +25°C, unless otherwise noted.)
SAMPLE A
LOAD
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.502
2.501
2.500
2.499
2.498
2.497
4.099
4.098
4.097
4.096
4.095
4.094
MAX11639/MAX11643
MAX11638/MAX11642
2.7
3.0
3.3
3.6
4.75
4.85
4.95
5.05
(V)
5.15
5.25
V
(V)
V
DD
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
4.12
4.11
4.10
4.09
4.08
4.07
2.520
2.510
2.500
2.490
2.480
2.470
MAX11638/MAX11642
MAX11639/MAX11643
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
0.8
0.6
0.4
0.2
0
0.70
0.60
0.50
0.40
0.30
MAX11638/MAX11642
MAX11639/MAX11643
892/MAX1643
4.75
4.85
4.95
5.05
(V)
5.15
5.25
2.7
3.0
3.3
3.6
V
V
(V)
DD
DD
8
_______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
Typical Operating Characteristics (continued)
(V
= 3V and V
= 2.5V (MAX11639/MAX11643), V
= 5V and V
= 4.096V (MAX11638/MAX11642), f
= 4.8MHz,
SCLK
DD
REF
DD
REF
C
= 30pF, f = 300ksps, T = +25°C, unless otherwise noted.)
SAMPLE A
LOAD
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.8
0.4
0
MAX11639/MAX11643
MAX11638/MAX11642
MAX11638/MAX11642
-0.1
-40
-15
10
35
60
85
4.75
4.85
4.95
5.05
(V)
5.15
5.25
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
TEMPERATURE (°C)
DD
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.20
0.6
0.4
0.2
0
MAX11639/MAX11643
MAX11638/MAX11642
0.10
0
-0.2
-0.4
-0.6
-0.10
-0.20
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
DD
SAMPLING ERROR
vs. SOURCE IMPEDANCE
GAIN ERROR vs. TEMPERATURE
0.2
0.1
0
2
0
MAX11639/MAX11643
-2
-4
-6
-0.1
-0.2
-8
-10
-40
-15
10
35
60
85
0
2
4
6
8
10
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
_______________________________________________________________________________________
9
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Pin Description
MAX11638
MAX11639
MAX11642
MAX11643
NAME
FUNCTION
(8 CHANNELS)
(16 CHANNELS)
1–7
—
—
AIN0–AIN6
Analog Inputs
1–15
AIN0–AIN14 Analog Inputs
Active-Low Conversion Start Input/Analog Input 7. See Table 3 for
details on programming the setup register.
8
—
CNVST/AIN7
CNVST/AIN15
Active-Low Conversion Start Input/Analog Input 15. See Table 3 for details
on programming the setup register.
—
16
9
17
18
19
REF
Reference Input. Bypass to GND with a 0.1µF capacitor.
Ground
10
11
GND
V
DD
Power Input. Bypass to GND with a 0.1µF capacitor.
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
12
13
14
20
21
22
CS
SCLK
DIN
Serial Clock Input. Clocks data in and out of the serial interface (duty
cycle must be 40% to 60%). See Table 3 for details on programming the
clock mode.
Serial Data Input. DIN data is latched into the serial interface on the
rising edge of SCLK.
Serial Data Output. Data is clocked out on the falling edge of SCLK. High
15
16
23
24
DOUT
impedance when CS is connected to V
.
DD
EOC
End of Conversion Output. Data is valid after EOC pulls low.
892/MAX1643
10 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
CS
t
CSH0
t
t
t
CSH1
t
CH
CP
CSS0
t
CSS1
t
CL
SCLK
DIN
t
DH
t
DS
t
t
DOT
DOD
t
DOE
DOUT
Figure 1. Detailed Serial-Interface Timing Diagram
CS
DIN
SCLK
SERIAL
INTERFACE
DOUT
EOC
OSCILLATOR
CNVST
CONTROL
AIN0
AIN1
8-BIT
SAR
ADC
FIFO AND
ACCUMULATOR
T/H
AIN15
REF
INTERNAL
REFERENCE
MAX11638/MAX11639/
MAX11642/MAX11643
Figure 2. Functional Diagram
figurations. Microprocessor (µP) control is made easy
through a 3-wire SPI-/QSPI-/MICROWIRE-compatible
serial interface.
Detailed Description
The MAX11638/MAX11639/MAX11642/MAX11643 are
low-power, serial-output, multichannel ADCs with FIFO
capability for system monitoring, process-control, and
instrumentation applications. These 8-bit ADCs have
internal track-and-hold (T/H) circuitry supporting single-
ended inputs. Data is converted from analog voltage
sources in a variety of channel and data-acquisition con-
Figure 2 shows a simplified functional diagram of the
MAX11638/MAX11639/MAX11642/MAX11643 internal
architecture. The MAX11642/MAX11643 have 16 sin-
gle-ended analog input channels. The MAX11638/
MAX11639 have 8 single-ended analog input channels.
______________________________________________________________________________________ 11
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
to request conversions one channel at a time, control-
Converter Operation
The MAX11638/MAX11639/MAX11642/MAX11643 ADCs
use a successive-approximation register (SAR) conver-
sion technique and an on-chip T/H block to convert
voltage signals into an 8-bit digital result. This single-
ended configuration supports unipolar signal ranges.
ling the sampling speed without tying up the serial
bus. Request and start internally timed conversions
through the serial interface by writing to the conversion
register in the default clock mode 10. Use clock mode
11 with SCLK up to 4.8MHz for externally timed acqui-
sitions to achieve sampling rates up to 300ksps. Clock
mode 11 disables scanning and averaging. See
Figures 4–7 for timing specifications and how to begin
a conversion.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency
signals aliasing into the frequency band of interest.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next input
data byte (for clock modes 00 and 10). In clock mode
01, EOC goes low after the ADC completes each
requested operation. EOC goes high when CS or
CNVST goes low. EOC is always high in clock mode 11.
Analog Input Protection
Internal ESD protection diodes clamp all pins to V
DD
-
and GND, allowing the inputs to swing from (V
GND
Single-Ended Inputs
The single-ended analog input conversion modes can
be configured by writing to the setup register (see
Table 3). Single-ended conversions are internally refer-
enced to GND (see Figure 3).
0.3V) to (V
+ 0.3V) without damage. However, for
DD
accurate conversions near full scale, the inputs must
not exceed V by more than 50mV or be lower than
DD
GND by 50mV. If an off-channel analog input voltage
exceeds the supplies, limit the input current to 2mA.
AIN0–AIN7 are available on the MAX11638/MAX11639/
MAX11642/MAX11643. AIN12–AIN15 are only available
on the MAX11642/MAX11643. See Tables 2–5 for more
details on configuring the inputs. For the inputs that can
be configured as CNVST or an analog input, only one
can be used at a time.
3-Wire Serial Interface
The MAX11638/MAX11639/MAX11642/MAX11643 fea-
ture a serial interface compatible with SPI/QSPI and
MICROWIRE devices. For SPI/QSPI, ensure the CPU
serial interface runs in master mode so it generates the
serial clock signal. Select the SCLK frequency of 10MHz
or less, and set clock polarity (CPOL) and phase
(CPHA) in the µP control registers to the same value.
The MAX11638/MAX11639/MAX11642/MAX11643 oper-
ate with SCLK idling high or low, and thus operate with
CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to
latch input data at DIN on the rising edge of SCLK.
Output data at DOUT is updated on the falling edge of
SCLK. Results are output in binary format.
Unipolar
The MAX11638/MAX11639/MAX11642/MAX11643
always operate in unipolar mode. The analog inputs are
internally referenced to GND with a full-scale input
range from 0 to V
.
REF
REF
GND
DAC
Serial communication always begins with an 8-bit input
data byte (MSB first) loaded from DIN. A high-to-low
transition on CS initiates the data input operation. The
input data byte and the subsequent data bytes are
clocked from DIN into the serial interface on the rising
edge of SCLK. Tables 1–5 detail the register descrip-
tions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively,
control the clock modes in the setup register (see
Table 3). Choose between four different clock modes
for various ways to start a conversion and determine
whether the acquisitions are internally or externally
timed. Select clock mode 00 to configure CNVST/AIN_
to act as a conversion start and use it to request the
programmed, internally timed conversions without
tying up the serial bus. In clock mode 01, use CNVST
AIN0–AIN15
CIN+
COMPARATOR
+
892/MAX1643
HOLD
-
CIN-
GND
HOLD
HOLD
V
DD
/2
Figure 3. Equivalent Input Circuit
12 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
oscillator is active in clock modes 00, 01, and 10. Read
out the data at clock speeds up to 10MHz. See Figures
4–7 for details on timing specifications and starting a
conversion.
True Differential Analog Input T/H
The equivalent circuit of Figure 3 shows the
MAX11638/MAX11639/MAX11642/MAX11643’s input
architecture. In track mode, a positive input capacitor is
connected to AIN0–AIN15. A negative input capacitor is
connected to GND. For external T/H timing, use clock
mode 01. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The time required for the T/H to
acquire an input signal is determined by how quickly its
input capacitance is charged. If the input signal’s
source impedance is high, the required acquisition time
Applications Information
Register Descriptions
The MAX11638/MAX11639/MAX11642/MAX11643 com-
municate between the internal registers and the exter-
nal circuitry through the SPI-/QSPI-compatible serial
interface. Table 1 details the registers and the bit
names. Tables 2–5 show the various functions within
the conversion register, setup register, averaging regis-
ter, and reset register.
lengthens. The acquisition time, t
, is the maximum
ACQ
time needed for a signal to be acquired, plus the power-
up time. It is calculated by the following equation:
Conversion Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, and if the external
reference is in use.
t
= 9 x (R + R ) x 24pF + t
S IN PWR
ACQ
where R = 1.5kΩ, R is the source impedance of the
IN
S
input signal, and t
= 1µs, the power-up time of the
PWR
device. The varying power-up times are detailed in the
explanation of the clock mode conversions. When the
Use the following formula to calculate the total conver-
sion time for an internally timed conversion in clock
modes 00 and 10 (see the Electrical Characteristics
section as applicable):
conversion is internally timed, t
is never less than
ACQ
1.4µs, and any source impedance below 300Ω does not
significantly affect the ADC’s AC performance. A high-
impedance source can be accommodated either by
lengthening t
the positive and negative analog inputs.
or by placing a 1µF capacitor between
Total Conversion Time = t
where:
x n
x n
+ t
ACQ
CNV
AVG
RESULT RP
Internal FIFO
t
= t
(max) + t
(max)
CONV
CNV
ACQ
The MAX11638/MAX11639/MAX11642/MAX11643 con-
tain a FIFO buffer that can hold up to 16 ADC results.
This allows the ADC to handle multiple internally clocked
conversions, without tying up the serial bus. If the FIFO is
filled and further conversions are requested without
reading from the FIFO, the oldest ADC results are over-
written by the new ADC results. Each result contains 2
bytes, with the MSB preceded by four leading zeros.
After each falling edge of CS, the oldest available byte of
data is available at DOUT, MSB first. When the FIFO is
empty, DOUT is zero.
n
n
= samples per result (amount of averaging)
AVG
= number of FIFO results requested;
RESULT
determined by the number of channels being
scanned or by NSCAN1, NSCAN0
t
= internal reference wake-up; set to zero if inter-
RP
nal reference is already powered up or external ref-
erence is being used
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high, including any time
required to turn on the internal reference. Conversion
time in externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
Internal Clock
The MAX11638/MAX11639/MAX11642/MAX11643 oper-
ate from an internal oscillator, which is accurate within
10% of the 4.4MHz nominal clock rate. The internal
Table 1. Input Data Byte (MSB First)
REGISTER NAME
Conversion
Setup
BIT 7
BIT 6
BIT 5
CHSEL2
CKSEL1
1
BIT 4
CHSEL1
CKSEL0
AVGON
1
BIT 3
CHSEL0
REFSEL1
NAVG1
RESET
BIT 2
SCAN1
REFSEL0
NAVG0
X
BIT 1
SCAN0
X
BIT 0
1
0
0
0
CHSEL3
X
1
0
0
X
NSCAN0
X
Averaging
NSCAN1
X
Reset
0
X = Don’t care.
______________________________________________________________________________________ 13
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Conversion Register
Table 2. Conversion Register*
Select active analog input channels per scan and scan
modes by writing to the conversion register. Table 2
details channel selection and the four scan modes.
Request a scan by writing to the conversion register
when in clock mode 10 or 11, or by applying a low
pulse to the CNVST pin when in clock mode 00 or 01.
BIT
BIT
FUNCTION
NAME
—
7 (MSB) Set to 1 to select conversion register.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
—
6
5
4
3
2
1
Analog input channel select.
Analog input channel select.
Analog input channel select.
Analog input channel select.
Scan mode select.
A conversion is not performed if it is requested on a
channel that has been configured as CNVST. Do not
request conversions on channels 8–15 on the
MAX11638/MAX11639. Set CHSEL[3:0] to the lower
channel’s binary values.
Scan mode select.
Select scan mode 00 or 01 to return one result per sin-
gle-ended channel within the requested range. Select
scan mode 10 to scan a single input channel numerous
times, depending on NSCAN1 and NSCAN0 in the
averaging register (Table 4). Select scan mode 11 to
return only one result from a single channel.
0 (LSB) Don’t care.
*See below for bit details.
SELECTED
CHANNEL (N)
CHSEL3 CHSEL2 CHSEL1 CHSEL0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AIN0
AIN1
Setup Register
Write a byte to the setup register to configure the clock,
reference, and power-down modes. Table 3 details the
bits in the setup register. Bits 5 and 4 (CKSEL1 and
CKSEL0) control the clock mode, acquisition and sam-
pling, and the conversion start. Bits 3 and 2 (REFSEL1
and REFSEL0) control internal or external reference use.
AIN2
AIN3
AIN4
AIN5
AIN6
Averaging Register
Write to the averaging register to configure the ADC to
average up to 32 samples for each requested result,
and to independently control the number of results
requested for single-channel scans.
AIN7
AIN8
AIN9
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
Table 2 details the four scan modes available in the
conversion register. All four scan modes allow averag-
ing as long as the AVGON bit, bit 4 in the averaging
register, is set to 1. Select scan mode 10 to scan the
same channel multiple times. Clock mode 11 disables
averaging.
Reset Register
Write to the reset register (as shown in Table 5) to clear
the FIFO or to reset all registers to their default states.
Set the RESET bit to 1 to reset the FIFO. Set the RESET
bit to zero to return the MAX11638/MAX11639/
MAX11642/MAX11643 to the default power-up state.
SCAN MODE (CHANNEL N IS
SELECTED BY BITS CHSEL3–CHSEL0)
SCAN1 SCAN0
0
0
0
1
Scans channels 0 through N.
892/MAX1643
Scans channels N through the highest
numbered channel.
Scans channel N repeatedly. The averaging
register sets the number of results.
1
1
0
1
No scan. Converts channel N once only.
14 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
Table 3. Setup Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to zero to select setup register.
—
6
Set to 1 to select setup register.
Clock mode and CNVST configuration. Resets to 1 at power-up.
Clock mode and CNVST configuration.
Reference mode configuration.
Reference mode configuration.
Don’t care.
CKSEL1
CKSEL0
REFSEL1
REFSEL0
—
5
4
3
2
1
—
0 (LSB)
Don’t care.
*See below for bit details.
CKSEL1
CKSEL0
CONVERSION CLOCK
Internal
ACQUISITION/SAMPLING
Internally timed
CNVST CONFIGURATION
CNVST
0
0
1
1
0
1
0
1
Internal
Externally timed through CNVST
Internally timed
CNVST
Internal
AIN15/AIN7
AIN15/AIN7
External (4.8MHz max)
Externally timed through SCLK
REFSEL1 REFSEL0
VOLTAGE REFERENCE
Internal
AutoShutdown
Reference off after scan; need
wake-up delay.
0
0
1
0
1
0
External single ended
Internal
Reference off; no wake-up delay.
Reference always on; no wake-up
delay.
______________________________________________________________________________________ 15
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Table 4. Averaging Register*
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to zero to select averaging register.
—
6
Set to zero to select averaging register.
Set to 1 to select averaging register.
—
5
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
4
Set to 1 to turn averaging on. Set to zero to turn averaging off.
Configures the number of conversions for single-channel scans.
Configures the number of conversions for single-channel scans.
Single-channel scan count. (Scan mode 10 only.)
3
2
1
0 (LSB)
Single-channel scan count. (Scan mode 10 only.)
*See below for bit details.
AVGON
NAVG1
NAVG0
FUNCTION
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
Performs 1 conversion for each requested result.
Performs 4 conversions and returns the average for each requested result.
Performs 8 conversions and returns the average for each requested result.
Performs 16 conversions and returns the average for each requested result.
Performs 32 conversions and returns the average for each requested result.
NSCAN1
NSCAN0
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
0
1
1
0
1
0
1
Scans channel N and returns 4 results.
Scans channel N and returns 8 results.
Scans channel N and returns 12 results.
Scans channel N and returns 16 results.
Table 5. Reset Register
BIT NAME
BIT
FUNCTION
—
7 (MSB) Set to zero to select reset register.
—
6
Set to zero to select reset register.
Set to zero to select reset register.
Set to 1 to select reset register.
—
5
—
4
RESET
3
Set to zero to reset all registers. Set to 1 to clear the FIFO only.
Reserved. Don’t care.
X
X
X
2
1
892/MAX1643
Reserved. Don’t care.
0 (LSB)
Reserved. Don’t care.
16 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
Power-Up Default State
The MAX11638/MAX11639/MAX11642/MAX11643
power up with all blocks in shutdown, including the ref-
erence. All registers power up in state 00000000,
except for the setup register, which powers up in clock
mode 10 (CKSEL1 = 1).
and the results are available in the FIFO. Wait until EOC
goes low before pulling CS low to communicate with
the serial interface. EOC stays low until CS or CNVST is
pulled low again.
Do not initiate a second CNVST before EOC goes low;
otherwise, the FIFO can become corrupted.
Output Data Format
Figures 4–7 illustrate the conversion timing for the
MAX11638/MAX11639/MAX11642/MAX11643. The 8-bit
conversion result is output in MSB-first format with four
leading zeros followed by 10-bit data and four trailing
zeros. DIN data is latched into the serial interface on
the rising edge of SCLK. Data on DOUT transitions on
the falling edge of SCLK. Conversions in clock modes
00 and 01 are initiated by CNVST. Conversions in clock
modes 10 and 11 are initiated by writing an input data
byte to the conversion register. Data output is binary.
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
Performing Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If the internal
reference needs to wake up, an additional 65µs is
required for the internal reference to power up.
Internally Timed Acquisitions and
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
Conversions Using CNVST
Performing Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. The result is available on
DOUT once EOC has been pulled low.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX11638/MAX11639/
MAX11642/MAX11643 then wake up, scan all request-
ed channels, store the results in the FIFO, and shut
down. After the scan is complete, EOC is pulled low
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
EOC
LSB1
MSB2
MSB1
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Figure 4. Clock Mode 00
______________________________________________________________________________________ 17
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
CNVST
(CONVERSION2)
(ACQUISITION1)
(ACQUISITION2)
CS
(CONVERSION1)
SCLK
DOUT
EOC
LSB1
MSB1
MSB2
REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION.
Figure 5. Clock Mode 01
(CONVERSION BYTE)
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
DIN
CS
SCLK
DOUT
LSB1
MSB1
MSB2
EOC
THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED.
Figure 6. Clock Mode 10
Internally Timed Acquisitions and
complete, EOC is pulled low and the results are avail-
able in the FIFO. EOC stays low until CS is pulled low
again.
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
892/MAX1643
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing to the conversion register and are per-
formed one at a time using the SCLK as the conversion
clock. Scanning and averaging are disabled, and the
conversion result is available at DOUT during the con-
version. See Figure 7 for clock mode 11 timing.
Initiate a scan by writing a byte to the conversion regis-
ter. The MAX11638/MAX11639/MAX11642/MAX11643
then power up, scan all requested channels, store the
results in the FIFO, and shut down. After the scan is
18 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
(CONVERSION BYTE)
DIN
(ACQUISITION2)
(ACQUISITION1)
(CONVERSION1)
CS
SCLK
DOUT
EOC
MSB1
LSB1
MSB2
EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST.
Figure 7. Clock Mode 11
Initiate a conversion by writing a byte to the conversion
register followed by 16 SCLK cycles. If CS is pulsed
high between the 8th and 9th cycles, the pulse width
must be less than 100µs. To continuously convert at 16
cycles per conversion, alternate 1 byte of zeros
between each conversion byte.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
If reference mode 00 is requested, wait 65µs with CS
high after writing the conversion byte to extend the
acquisition and allow the internal reference to power up.
FS = V + V
REF
COM
ZS = V
COM
Partial Reads and Partial Writes
If the first byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the second byte of data that is read out contains the
next 8 bits (not b7–b0). The remaining bits are lost for
that entry. If the first byte of an entry in the FIFO is read
out fully, but the second byte is read out partially, the
rest of the entry is lost. The remaining data in the FIFO
is uncorrupted and can be read out normally after tak-
ing CS low again, as long as the 4 leading bits (normal-
ly zeros) are ignored. Internal registers that are written
partially through the SPI contain new values, starting at
the MSB up to the point that the partial write is stopped.
The part of the register that is not written contains previ-
ously written values. If CS is pulled low before EOC
goes low, a conversion cannot be completed and the
FIFO is corrupted.
V
REF
1 LSB =
256
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
0
1
2
3
FS
(COM)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
REF
Layout, Grounding, and Bypassing
Use PCBs for best performance. Do not use wire-
wrapped boards. Board layout should ensure that digi-
tal and analog signal lines are separated from each
other. Do not run analog and digital (especially clock)
signals parallel to one another or run digital lines under-
Transfer Function
Figure 8 shows the unipolar transfer function for single-
ended inputs. Code transitions occur halfway between
successive-integer LSB values. Output coding is binary,
neath the package. High-frequency noise in the V
power supply can affect performance. Bypass the V
supply with a 0.1µF capacitor to GND, close to the V
pin. Minimize capacitor lead lengths for best supply-
noise rejection. If the power supply is very noisy, con-
nect a 10Ω resistor in series with the supply to improve
power-supply filtering.
DD
DD
DD
with 1 LSB = V
/256.
REF
______________________________________________________________________________________ 19
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Signal-to-Noise Plus Distortion
Definitions
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL is
measured using the end-point method.
SINAD (dB) = 20 x log (Signal
/Noise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
Aperture Delay
Aperture delay (t ) is the time between the rising
AD
edge of the sampling clock and the instant when an
actual sample is taken.
⎛
⎞
2
2
2
2
THD = 20 x log
V2 + V3 + V4 + V5 /V1
⎜
(
)
⎟
⎝
⎠
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
where V1 is the fundamental amplitude, and V2–V5 are
the amplitudes of the 2nd through 5th order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
892/MAX1643
20 ______________________________________________________________________________________
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
892/MAX1643
Pin Configurations (continued)
Chip Information
PROCESS: BiCMOS
TOP VIEW
+
Package Information
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
1
2
3
4
5
6
7
8
9
24 EOC
23 DOUT
22 DIN
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
21
20
19
SCLK
CS
MAX11642
MAX11643
PACKAGE
TYPE
16 QSOP
PACKAGE
CODE
OUTLINE
NO.
21-0055
LAND
V
DD
PATTERN NO.
18 GND
E16+5
90-0167
17 REF
24 QSOP
E24+3
21-0055
90-0172
16 CNVST/AIN15
15 AIN14
14 AIN13
13 AIN12
AIN9 10
AIN10 11
AIN11 12
QSOP
______________________________________________________________________________________ 21
8-Bit, 16-/8-Channel, 300ksps ADCs
with FIFO and Internal Reference
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
9/11
Initial release
—
892/MAX1643
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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ADC, Successive Approximation, 12-Bit, 1 Func, 2 Channel, Serial Access, BICMOS, PDSO8, ROHS COMPLIANT, UMAX-8
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