MAX1185ECM+TD [MAXIM]
ADC, Flash Method, 10-Bit, 1 Func, 2 Channel, Parallel, Word Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, TQFP-48;
| 型号： | MAX1185ECM+TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Flash Method, 10-Bit, 1 Func, 2 Channel, Parallel, Word Access, CMOS, PQFP48, 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABC-HD, TQFP-48 |
| 文件： | 总21页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2175; Rev 3; 5/11
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
General Description
Features
o Single 3V Operation
The MAX1185 is a 3V, dual 10-bit analog-to-digital con-
verter (ADC) featuring fully-differential wideband track-
and-hold (T/H) inputs, driving two pipelined, nine-stage
ADCs. The MAX1185 is optimized for low-power, high
dynamic performance applications in imaging, instru-
mentation, and digital communication applications. This
ADC operates from a single 2.7V to 3.6V supply, con-
suming only 105mW while delivering a typical signal-to-
noise ratio (SNR) of 59.5dB at an input frequency of
7.5MHz and a sampling rate of 20Msps. Digital outputs
A and B are updated alternating on the rising (CHA)
and falling (CHB) edge of the clock. The T/H driven
input stages incorporate 400MHz (-3dB) input ampli-
fiers. The converters may also be operated with single-
ended inputs. In addition to low operating power, the
MAX1185 features a 2.8mA sleep mode as well as a
1µA power-down mode to conserve power during idle
periods.
o Excellent Dynamic Performance:
59.5dB SNR at f = 7.5MHz
IN
74dB SFDR at f = 7.5MHz
IN
o Low Power:
35mA (Normal Operation)
2.8mA (Sleep Mode)
1µA (Shutdown Mode)
o 0.02dB Gain and 0.25° Phase Matching
o Wide 1Vp-p Differential Analog Input Voltage
Range
o 400MHz, -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o Single 10-Bit Bus for Multiplexed, Digital Outputs
o User-Selectable Output Format—Two’s
Complement or Offset Binary
o 48-Pin TQFP Package with Exposed Pad for
Improved Thermal Dissipation
An internal 2.048V precision bandgap reference sets
the full-scale range of the ADC. A flexible reference
structure allows the use of this internal or an externally
derived reference, if desired for applications requiring
increased accuracy or a different input voltage range.
Ordering Information
TEMP
RANGE
PART
PIN-PACKAGE
MAX1185ECM
MAX1185ECM+
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
48 TQFP-EP*
48 TQFP-EP*
48 TQFP-EP*
The MAX1185 features parallel, multiplexed, CMOS-
compatible three-state outputs. The digital output for-
mat can be set to two’s complement or straight offset
binary through a single control pin. The device provides
for a separate output power supply of 1.7V to 3.6V for
flexible interfacing. The MAX1185 is available in a 7mm
x 7mm, 48-pin TQFP package, and is specified for the
extended industrial (-40°C to +85°C) temperature
range.
MAX1185ECM/V+
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive qualified part.
Pin-Compatible Versions table at end of data sheet.
Pin Configuration
Pin-compatible, nonmultiplexed. high-speed versions of
the MAX1185 are also available. Refer to the MAX1180
data sheet for 105Msps, the MAX1181 data sheet for
80Msps, the MAX1182 data sheet for 65Msps, the
MAX1183 data sheet for 40Msps, and the MAX1184
data sheet for 20Msps.
COM
1
2
36 D1A/B
35 D0A/B
34 OGND
V
DD
GND
INA+
INA-
3
4
33 OV
32 OV
DD
DD
5
V
6
31 OGND
30 A/B
DD
MAX1185
GND
INB-
INB+
GND
7
Applications
8
29 N.C.
28 N.C.
9
High Resolution Imaging
I/Q Channel Digitization
Multichannel IF Sampling
Instrumentation
N.C.
N.C.
N.C.
10
11
12
27
26
25
EP
V
DD
CLK
Video Application
Ultrasound
48 TQFP-EP
NOTE: THE PIN 1 INDICATOR FOR LEAD-FREE
PACKAGES IS REPLACED BY A "+" SIGN.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ABSOLUTE MAXIMUM RATINGS
V , OV
DD
to GND ...............................................-0.3V to +3.6V
DD
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow)
OGND to GND.......................................................-0.3V to +0.3V
INA+, INA-, INB+, INB- to GND ...............................-0.3V to V
REFIN, REFOUT, REFP, REFN, COM,
DD
CLK to GND............................................-0.3V to (V + 0.3V)
DD
OE, PD, SLEEP, T/B, D9A/B–D0A/B,
A/B to OGND .......................................-0.3V to (OV + 0.3V)
Lead(Pb)-free..............................................................+260°C
Containing lead(Pb)....................................................+240°C
DD
Continuous Power Dissipation (T = +70°C)
A
48-Pin TQFP-EP (derate 30.4mW/°C
MAX185
above +70°C)............................................................2430mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 1), f
= 20MHz, T = T
to T , unless
IN
L
CLK
A
MIN
MAX
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
DC ACCURACY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
f
f
= 7.5MHz
0.5
1.5
1.0
1.9
2
IN
IN
DNL
= 7.5MHz, no missing codes guaranteed
0.25
LSB
<
1
% FS
% FS
Gain Error
0
ANALOG INPUT
Differential Input Voltage
Range
V
Differential or single-ended inputs
Switched capacitor load
1.0
/2
V
V
DIFF
Common-Mode Input Voltage
Range
V
DD
V
CM
0.5
Input Resistance
R
100
5
kΩ
IN
IN
Input Capacitance
C
pF
CONVERSION RATE
Maximum Clock Frequency
f
20
MHz
CLK
CHA
CHB
5
Clock
cycles
Data Latency
5.5
DYNAMIC CHARACTERISTICS
f
f
f
f
f
f
= 7.5MHz, T = +25°C
A
57.3
57
59.5
59.4
59.4
59.2
74
INA or B
INA or B
INA or B
INA or B
INA or B
INA or B
Signal-to-Noise Ratio
(Note 3)
SNR
SINAD
SFDR
dB
dB
= 12MHz
= 7.5MHz, T = +25°C
A
Signal-to-Noise and Distortion
(Note 3)
= 12MHz
= 7.5MHz, T = +25°C
A
64
Spurious-Free Dynamic Range
(Note 3)
dBc
= 12MHz
72
2
_______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 1), f
= 20MHz, T = T
to T , unless
IN
L
CLK
A
MIN
MAX
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
-72
-71
-74
-72
MAX
UNITS
f
f
f
f
= 7.5MHz, T = +25°C
-64
INA or B
INA or B
INA or B
INA or B
A
Total Harmonic Distortion
(First 4 Harmonics) (Note 3)
THD
dBc
= 12MHz
= 7.5MHz
= 12MHz
Third-Harmonic Distortion
(Note 3)
HD3
IMD
dBc
dBc
f
f
= 11.9852MHz at -6.5dBFS,
= 12.8934MHz at -6.5dBFS (Note 4)
INA or B
Intermodulation Distortion
-76
INA or B
Small-Signal Bandwidth
Full-Power Bandwidth
Aperture Delay
Input at -20dBFS, differential inputs
Input at -0.5dBFS, differential inputs
500
400
1
MHz
MHz
ns
FPBW
t
AD
Aperture Jitter
t
2
ps
RMS
AJ
Overdrive Recovery Time
Differential Gain
For 1.5x full-scale input
2
ns
%
1
Differential Phase
Output Noise
0.25
0.2
Degrees
INA+ = INA- = INB+ = INB- = COM
LSB
RMS
INTERNAL REFERENCE
2.048
3%
Reference Output Voltage
REFOUT
V
Reference Temperature
Coefficient
TC
60
ppm/°C
mV/mA
REF
Load Regulation
1.25
BUFFERED EXTERNAL REFERENCE (V
= 2.048V)
REFIN
REFIN Input Voltage
V
V
2.048
2.012
V
V
REFIN
Positive Reference Output
Voltage
V
REFP
Negative Reference Output
Voltage
0.988
V
REFN
Differential Reference Output
Voltage Range
ΔVREF
ΔV
= V
- V
REFN
0.95
1.024
> 50
1.10
V
REF
REFP
REFIN Resistance
R
MΩ
REFIN
_______________________________________________________________________________________
3
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 1), f
= 20MHz, T = T
to T
, unless
IN
L
CLK
A
MIN
MAX
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Maximum REFP, COM Source
Current
I
5
mA
SOURCE
MAX185
Maximum REFP, COM Sink
Current
I
-250
µA
SINK
Maximum REFN Source Current
Maximum REFN Sink Current
I
250
-5
µA
SOURCE
I
mA
SINK
UNBUFFERED EXTERNAL REFERENCE (V
= AGND, reference voltage applied to REFP, REFN, and COM)
REFIN
R
R
,
Measured between REFP and COM, and
REFN and COM
REFP
REFP, REFN Input Resistance
4
kΩ
V
REFN
Differential Reference Input
Voltage
1.024
10%
ΔV
ΔV
= V
- V
REFP REFN
REF
REF
V
/2
10%
DD
COM Input Voltage
REFP Input Voltage
REFN Input Voltage
V
V
V
COM
REFP
REFN
V
+
COM
V
ΔV
/2
REF
V
-
COM
V
V
ΔV
/2
REF
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
0.8
x V
CLK
DD
Input High Threshold
Input Low Threshold
V
V
V
IH
0.8
x OV
PD, OE, SLEEP, T/B
CLK
DD
0.2
x V
DD
V
IL
0.2
x OV
PD, OE, SLEEP, T/B
DD
Input Hysteresis
Input Leakage
V
0.1
5
V
HYST
I
IH
V
V
= OV or V (CLK)
5
5
IH
IL
DD
DD
µA
pF
I
= 0
IL
Input Capacitance
C
IN
DIGITAL OUTPUTS (D0A/B–D9A/B, A/B)
Output-Voltage Low
V
I
I
= -200µA
0.2
10
V
V
OL
SINK
OV
- 0.2
DD
Output-Voltage High
V
= 200µA
SOURCE
OH
Three-State Leakage Current
I
OE = OV
OE = OV
µA
pF
LEAK
DD
Three-State Output Capacitance
C
5
OUT
DD
4
_______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 2.5V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
DD
DD
10kΩ resistor, V = 2Vp-p (differential w.r.t. COM), C = 10pF at digital outputs (Note 1), f
= 20MHz, T = T
to T , unless
IN
L
CLK
A
MIN
MAX
otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
V
2.7
1.7
3.0
2.5
35
2.8
1
3.6
3.6
50
V
V
DD
OV
DD
Operating, f
Sleep mode
= 7.5MHz at -0.5dBFS
INA or B
mA
µA
Analog Supply Current
Output Supply Current
Power Dissipation
I
VDD
Shutdown, clock idle, PD = OE = OV
15
DD
Operating, C = 15pF,
L
9
mA
f
= 7.5MHz at -0.5dBFS
INA or B
I
OVDD
Sleep mode
100
2
µA
Shutdown, clock idle, PD = OE = OV
10
DD
Operating, f
Sleep mode
= 7.5MHz at -0.5dBFS
105
8.4
3
150
INA or B
mW
PDISS
PSRR
Shutdown, clock idle, PD = OE = OV
45
µW
mV/V
%/V
DD
Offset
Gain
0.2
0.1
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
t
Figure 3 (Note 5)
Figure 3 (Note 5)
5
5
6
8
8
ns
ns
ns
DOA
DOB
DA/B
CLK Fall to CHB Output Data
Valid
Clock Rise/Fall to A/B Rise/Fall
Time
t
Output Enable Time
Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
t
Figure 4
10
ns
ns
ns
ns
ENABLE
t
Figure 4
1.5
DISABLE
25 7.5
25 7.5
t
Figure 3, clock period: 50ns
Figure 3, clock period: 50ns
Wake-up from sleep mode (Note 6)
Wake-up from shutdown (Note 6)
CH
t
CL
0.51
1.5
Wake-Up Time
t
µs
WAKE
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
f
f
f
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
= 7.5MHz at -0.5dBFS
-70
dB
dB
INA or B
INA or B
INA or B
Gain Matching
0.02
0.25
0.2
Phase Matching
Degrees
Note 1: Equivalent dynamic performance is obtainable over full OV
range with reduced C .
L
DD
Note 2: Specifications at ≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to V , V . Parameter guaranteed by design.
IH IL
Note 6: With REFIN driven externally, REFP, COM, and REFN are left unconnected while powered down.
_______________________________________________________________________________________
5
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics
(V = 3V, OV = 2.5V, V
= 2.048V, differential input at -0.5dBFS, f
= 20MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
DD
REFIN
CLK L A
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
FFT PLOT CHA (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
f
= 20.0005678MHz
= 5.9742906MHz
= 7.5343935MHz
= -0.525dBFS
f
f
f
= 20.0005678MHz
= 5.9742906MHz
= 7.5243935MHz
= -0.462dBFS
f
f
f
= 20.0005678MHz
= 7.5343935MHz
= 11.9852035MHz
= -0.489dBFS
CHB
CHA
CHA
CLK
INA
INB
CLK
INA
INB
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
MAX185
A
A
A
INA
INA
INA
HD3
HD3
HD3
HD2
HD2
4
HD2
7
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
8
9
10
0
1
2
3
5
6
7
8
9
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
TWO-TONE IMD PLOT (DIFFERENTIAL INPUT,
FFT PLOT CHB (DIFFERENTIAL INPUT,
8192-POINT DATA RECORD)
8192-POINT DATA RECORD)
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
61
60
59
58
57
56
55
f
f
f
= 20.0005678MHz
= 11.9852035MHz
= 12.8934324MHz
= -6.5dBFS
f
f
f
= 20.0005678MHz
= 7.5343935MHz
= 11.9852035MHz
= -0.471dBFS
CHB
CLK
IN1
IN2
CLK
INA
INB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
IN1
A
A
IN
CHB
INA
f
IN2
CHA
HD3
HD2
IM3
IM3
IM2
2
0
5
10 15 20 25 30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
0
1
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
-60
-64
-68
-72
62
60
58
56
54
80
76
72
68
64
60
CHA
CHB
CHB
CHB
CHA
CHA
-76
-80
0
5
10 15 20 25 30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
Typical Operating Characteristics (continued)
(V = 3V, OV = 2.5V, V
= 2.048V, differential input at -0.5dBFS, f
= 20MHz, C ≈ 10pF, T = +25°C, unless otherwise noted
DD
DD
REFIN
CLK L A
FULL-POWER INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
SMALL-SIGNAL INPUT BANDWIDTH
vs. ANALOG INPUT FREQUENCY, SINGLE-ENDED
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER (f = 7.53MHz)
IN
6
6
65
60
55
50
45
40
35
V
IN
= 100mV
P-P
4
2
4
2
0
0
-2
-4
-6
-8
-2
-4
-6
-8
-20
-16
-12
-8
-4
0
1
10
100
1000
1
10
100
1000
ANALOG INPUT POWER (dBFS)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE PLUS DISTORTION
vs. ANALOG INPUT POWER (f = 7.53MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER (f = 7.53MHz)
IN
vs. ANALOG INPUT POWER (f = 7.53MHz)
IN
IN
65
60
55
50
45
40
35
-55
-60
90
85
80
75
-65
-70
-75
-80
-85
70
65
60
55
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
-20
-16
-12
-8
-4
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
INTEGRAL NONLINEARITY
(BEST END-POINT FIT)
DIFFERENTIAL NONLINEARITY
GAIN ERROR vs. TEMPERATURE
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
CHB
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-0.1
-0.2
CHA
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Typical Operating Characteristics (continued)
(V = 3V, OV = 2.5V, V
= 2.048V, differential input at -0.5dBFS, f
= 20MHz, C ≈ 10pF, T = +25°C, unless otherwise noted.)
DD
DD
REFIN
CLK
L
A
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.2
38
36
34
32
30
28
38
37
36
35
34
33
0.1
0
MAX185
-0.1
-0.2
-0.3
-0.4
CHB
CHA
-40
-15
10
35
60
85
2.70 2.85 3.00 3.15 3.30 3.45 3.60
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
DD
SNR/SINAD, -THD/SFDR
vs. CLOCK DUTY CYCLE
ANALOG POWER-DOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
80
74
68
62
56
50
0.25
0.20
0.15
0.10
0.05
0
2.0100
2.0080
2.0060
2.0040
2.0020
2.0000
f
= 7.53MHz
INA/B
OE = PD = OV
DD
SFDR
THD
SNR
SINAD
35
40
45
50
55
60
65
70
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
(V)
CLOCK DUTY CYCLE (%)
V
V
DD
DD
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OUTPUT NOISE HISTOGRAM (DC INPUT)
70,000
63,000
56,000
49,000
42,000
35,000
28,000
21,000
14,000
7,000
2.014
2.010
2.006
64,515
2.002
1.998
1.994
869
N-1
152
N+1
0
0
0
-40
-15
10
35
60
85
N-2
N
N+2
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
8
_______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
Pin Description
PIN
NAME
FUNCTION
1
COM
Common-Mode Voltage Input/Output. Bypass to GND with a ≥ 0.1µF capacitor.
Analog Supply Voltage. Bypass each supply pin to GND with a 0.1µF capacitor. Analog
supply accepts a 2.7V to 3.6V input range.
2, 6, 11, 14, 15
V
DD
3, 7, 10, 13, 16
GND
INA+
INA-
INB-
INB+
CLK
Analog Ground
4
5
Channel A Positive Analog Input. For single-ended operation, connect signal source to INA+.
Channel A Negative Analog Input. For single-ended operation, connect INA- to COM.
Channel B Negative Analog Input. For single-ended operation, connect INB- to COM.
Channel B Positive Analog Input. For single-ended operation, connect signal source to INB+.
Converter Clock Input
8
9
12
T/B selects the ADC digital output format.
High: Two’s complement.
Low: Straight offset binary.
17
18
19
20
T/B
SLEEP
PD
Sleep Mode Input.
High: Deactivates the two ADCs, but leaves the reference bias circuit active.
Low: Normal operation.
Power-Down Input.
High: Power-down mode.
Low: Normal operation.
Output Enable Input.
High: Digital outputs disabled.
Low: Digital outputs enabled.
OE
21–29
30
N.C.
A/B
Do not connect.
A/B Data Indicator. This digital output indicates CHA data (A/B = 1) or CHB data (A/B = 0)
to be present on the output. A/B follows the external clock signal with typically 6ns delay.
31, 34
32, 33
OGND
Output Driver Ground
Output Driver Supply Voltage. Bypass each supply pin to OGND with a 0.1µF capacitor. Output
driver supply accepts a 1.7V to 3.6V input range.
OV
DD
Three-State Digital Output, Bit 0 (LSB). Depending on status of A/B, output data reflects
channel A or channel B data.
35
36
37
38
39
40
D0A/B
D1A/B
D2A/B
D3A/B
D4A/B
D5A/B
Three-State Digital Output, Bit 1. Depending on status of A/B, output data reflects channel A
or channel B data.
Three-State Digital Output, Bit 2. Depending on status of A/B, output data reflects channel A
or channel B data.
Three-State Digital Output, Bit 3. Depending on status of A/B, output data reflects channel A
or channel B data.
Three-State Digital Output, Bit 4. Depending on status of A/B, output data reflects channel A
or channel B data.
Three-State Digital Output, Bit 5. Depending on status of A/B, output data reflects channel A
or channel B data.
_______________________________________________________________________________________
9
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
Three-State Digital Output, Bit 6. Depending on status of A/B, output data reflects channel A
or channel B data.
41
D6A/B
Three-State Digital Output, Bit 7. Depending on status of A/B, output data reflects channel A
or channel B data.
42
43
44
D7A/B
D8A/B
D9A/B
Three-State Digital Output, Bit 8. Depending on status of A/B, output data reflects channel A
or channel B data.
MAX185
Three-State Digital Output, Bit 9 (MSB). Depending on status of A/B, output data reflects
channel A or channel B data.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
45
46
47
REFOUT
REFIN
REFP
Reference Input. V
= 2 x (V
- V
). Bypass to GND with a > 1nF capacitor.
REFIN
REFP
REFN
Positive Reference Input/Output. Conversion range is (V
a > 0.1µF capacitor.
- V
). Bypass to GND with
REFP
REFN
Negative Reference Input/Output. Conversion range is (V
a > 0.1µF capacitor.
- V
). Bypass to GND with
REFP
REFN
48
—
REFN
EP
Exposed Pad. Connect to analog ground.
Input Track-and-Hold (T/H) Circuits
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuits in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuits
sample the input signals onto the two capacitors (C2a
and C2b) through switches S4a and S4b. S2a and S2b
set the common mode for the amplifier input, and open
simultaneously with S1, sampling the input waveform.
Switches S4a and S4b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the out-
put of the amplifier and switch S4c is closed. The result-
ing differential voltages are held on capacitors C2a and
C2b. The amplifiers are used to charge capacitors C1a
and C1b to the same values originally held on C2a and
C2b. These values are then presented to the first stage
quantizers and isolate the pipelines from the fast-chang-
ing inputs. The wide input bandwidth T/H amplifiers allow
the MAX1185 to track and sample/hold analog inputs of
high frequencies (> Nyquist). Both ADC inputs (INA+,
INB+, INA-, and INB-) can be driven either differentially or
single-ended. Match the impedance of INA+ and INA- as
well as INB+ and INB- and set the common-mode volt-
Detailed Description
The MAX1185 uses a nine-stage, fully-differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consumption.
Samples taken at the inputs move progressively through
the pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held input
voltages into a digital code. The digital-to-analog con-
verters (DACs) convert the digitized results back into
analog voltages, which are then subtracted from the
original held input signals. The resulting error signals
are then multiplied by two and the residues are passed
along to the next pipeline stages, where the process is
repeated until the signals have been processed by all
nine stages. Digital error correction compensates for
ADC comparator offsets in each of these pipeline
stages and ensures no missing codes.
Both input channels are sampled on the rising edge of
the clock and the resulting data is multiplexed at the
output. CHA data is updated on the rising edge (five
clock cycles later) and CHB data is updated on the
falling edge (5.5 clock cycles later) of the clock signal.
The A/B indicator follows the clock signal with a typical
delay time of 6ns and remains high when CHA data is
updated and low when CHB data is updated.
age to midsupply (V /2) for optimum performance.
DD
10 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
V
V
IN
V
V
OUT
IN
OUT
x2
x2
Σ
Σ
T/H
T/H
FLASH
ADC
FLASH
ADC
DAC
DAC
1.5 BITS
1.5 BITS
2-BIT FLASH
ADC
2-BIT FLASH
ADC
STAGE 1
STAGE 2
STAGE 8
STAGE 9
STAGE 1
STAGE 2
STAGE 8
STAGE 9
DIGITAL CORRECTION LOGIC
10
DIGITAL CORRECTION LOGIC
10
T/H
T/H
V
INB
V
INA
OUTPUT
MULTIPLEXER
10
D0A/B–D9A/B
Figure 1. Pipelined Architecture—Stage Blocks
INTERNAL BIAS
S2a
COM
S5a
C1a
S3a
S4a
INA+
OUT
C2a
S4c
S1
OUT
INA-
S4b
C2b
S3b
C1b
C1a
S5b
S2b
CLK
HOLD
HOLD
INTERNAL BIAS
INTERNAL BIAS
S2a
COM
COM
S5a
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
TRACK
S3a
S4a
INB+
OUT
OUT
C2a
MAX1185
S4c
S1
INB-
S4b
C2b
S3b
C1b
S5b
COM
S2b
INTERNAL BIAS
Figure 2. MAX1185 T/H Amplifiers
______________________________________________________________________________________ 11
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
The MAX1185 clock input operates with a voltage thresh-
Analog Inputs and Reference
Configurations
old set to V /2. Clock inputs with a duty cycle other
DD
than 50%, must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
The full-scale range of the MAX1185 is determined by the
internally generated voltage difference between REFP
(V /2 + V
/4) and REFN (V /2 - V
/4). The
REFIN
DD
REFIN
DD
System Timing Requirements
Figure 3 shows the relationship between clock and
analog input, A/B indicator, and the resulting CHA/CHB
data output. CHA and CHB data are sampled on the
rising edge of the clock signal. Following the rising
edge of the 5th clock cycles, the digitized value of the
original CHA sample is presented at the output, fol-
lowed one half-clock cycle later by the digitized value
of the original CHB sample.
full-scale range for both on-chip ADCs is adjustable
through the REFIN pin, which is provided for this purpose.
REFOUT, REFP, COM (V /2), and REFN are internally
DD
buffered low-impedance outputs.
MAX185
The MAX1185 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
A channel selection signal (A/B indicator) allows the user
to determine which output data represents which input
channel. With A/B = 1, digitized data from CHA is present
at the output and with A/B = 0 digitized data from CHB is
present.
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a > 10nF capacitor to
GND. In internal reference mode, REFOUT, COM, REFP,
and REFN become low-impedance outputs.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE), Channel
Selection (A/B)
In buffered external reference mode, adjust the reference
voltage levels externally by applying a stable and accu-
rate voltage at REFIN. In this mode, COM, REFP, and
REFN become outputs. REFOUT may be left open or con-
nected to REFIN through a > 10kΩ resistor.
All digital outputs, D0A/B–D9A/B (CHA or CHB data) and
A/B are TTL/CMOS logic-compatible. The output coding
can be chosen to be either offset binary or two’s comple-
ment (Table 1) controlled by a single pin (T/B). Pull T/B
low to select offset binary and high to activate two’s com-
plement output coding. The capacitive load on the digital
outputs D0A/B–D9A/B should be kept as low as possible
(< 15pF), to avoid large digital currents that could feed
back into the analog portion of the MAX1185, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1185,
small-series resistors (e.g., 100Ω) may be added to the
digital output paths close to the MAX1185.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high impedance and may be driven
through separate, external reference sources.
Clock Input (CLK)
The MAX1185’s CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low jit-
ter and fast rise and fall times (< 2ns). In particular, sam-
pling occurs on the rising edge of the clock signal,
requiring this edge to provide lowest possible jitter. Any
significant aperture jitter would limit the SNR performance
of the on-chip ADCs as follows:
Figure 4 displays the timing relationship between output
enable and data output valid as well as power-
down/wake-up and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1185 offers two power-save modes—sleep
and full power-down mode. In sleep mode (SLEEP = 1),
only the reference bias circuit is active (both ADCs are
disabled), and current consumption is reduced to
2.8mA.
SNR = 20 x log (1/[2π x f x t ])
dB
10
IN AJ
where f represents the analog input frequency and t
IN
AJ
is the time of the aperture jitter.
Clock jitter is especially critical for undersampling appli-
cations. The clock input should always be considered as
an analog input and routed away from any analog input
or other digital signal lines.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power-down. Pulling OE high forces
the digital outputs into a high-impedance state.
12 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
CHA
CHB
t
CLK
t
t
CH
CL
CLK
t
t
DOA
DOB
A/B
CHB
D0B
CHA
D1A
CHB
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
t
DA/B
D0A/B-D9A/B
D1B
Figure 3. Timing Diagram for Multiplexed Outputs
the amplifiers. The user may select the R
and C
IN
ISO
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
R
of 50Ω is placed before the capacitive load to
ISO
OE
prevent ringing and oscillation. The 22pF C capacitor
IN
acts as a small bypassing capacitor.
t
t
DISABLE
ENABLE
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1185 for
optimum performance. Connecting the center tap of the
HIGH
IMPEDANCE
OUTPUT
D0A/B–D9A/B
HIGH IMPEDANCE
VALID DATA
transformer to COM provides a V
/2 DC level shift to
DDS
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
Figure 4. Output Timing Diagram
In general, the MAX1185 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
/2 output voltage for level
DDS
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
______________________________________________________________________________________ 13
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Table 1. MAX1185 Output Codes For Differential Inputs
STRAIGHT OFFSET
DIFFERENTIAL INPUT
VOLTAGE*
DIFFERENTIAL
INPUT
TWO’S COMPLEMENT
T/B = 1
BINARY
T/B = 0
V
x 511/512
+FULL SCALE - 1LSB
+ 1 LSB
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
REF
V
x 1/512
0
REF
Bipolar Zero
MAX185
- V
x 1/512
- 1 LSB
REF
-V
x 511/512
- FULL SCALE + 1 LSB
- FULL SCALE
REF
REF
-V
= V
x 512/512
- V
REFN
*V
REF
REFP
Single-Ended AC-Coupled Input Signal
Grounding, Bypassing, and
Board Layout
Figure 7 shows an AC-coupled, single-ended applica-
tion. Amplifiers like the MAX4108 provide high speed,
high bandwidth, low noise, and low distortion to maintain
the integrity of the input signal.
The MAX1185 requires high-speed board layout design
techniques. Locate all bypass capacitors as close as
possible to the device, preferably on the same side as
the ADC, using surface-mount devices for minimum
Typical QAM Demodulation Application
The most frequently used modulation technique for digital
communications applications is probably the Quadrature
Amplitude Modulation (QAM). Typically found in spread-
spectrum based systems, a QAM signal represents a
carrier frequency modulated in both amplitude and
phase. At the transmitter, modulating the baseband sig-
nal with quadrature outputs, a local oscillator followed by
subsequent up-conversion can generate the QAM signal.
The result is an in-phase (I) and a quadrature (Q) carrier
component, where the Q component is 90 degree phase-
shifted with respect to the in-phase component. At the
receiver, the QAM signal is divided down into it’s I and Q
components, essentially representing the modulation
process reversed. Figure 8 displays the demodulation
process performed in the analog domain, using the dual
matched 3.3V, 10-bit ADC MAX1185 and the MAX2451
quadrature demodulator to recover and digitize the I and
Q baseband signals. Before being digitized by the
MAX1185, the mixed down-signal components may be fil-
tered by matched analog filters, such as Nyquist or
Pulse-Shaping filters. These remove any unwanted
images from the mixing process, thereby enhancing the
overall signal-to-noise (SNR) performance and minimizing
intersymbol interference.
inductance. Bypass V , REFP, REFN, and COM with
DD
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV ) to OGND. Multilayer
DD
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
(1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively,
all ground pins could share the same ground plane, if
the ground plane is sufficiently isolated from any noisy
digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from the sensitive analog traces of
either channel. Make sure to isolate the analog input
lines to each respective converter to minimize channel-
to-channel crosstalk. Keep all signal lines short and
free of 90 degree turns.
14 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
+5V
0.1μF
LOWPASS FILTER
INA+
MAX4108
R
50Ω
IS0
0.1μF
300Ω
C
IN
22pF
0.1μF
-5V
600Ω
600Ω
300Ω
COM
0.1μF
+5V
+5V
0.1μF
0.1μF
600Ω
INPUT
0.1μF
0.1μF
LOWPASS FILTER
MAX4108
300Ω
300Ω
INA-
MAX4108
R
IS0
C
IN
22pF
50Ω
-5V
-5V
+5V
300Ω
300Ω
600Ω
MAX1185
0.1μF
LOWPASS FILTER
INB+
MAX4108
R
50Ω
IS0
0.1μF
300Ω
C
IN
22pF
0.1μF
-5V
600Ω
600Ω
300Ω
0.1μF
+5V
+5V
0.1μF
0.1μF
600Ω
INPUT
0.1μF
0.1μF
LOWPASS FILTER
MAX4108
300Ω
300Ω
INB-
MAX4108
R
IS0
50Ω
C
IN
22pF
-5V
-5V
300Ω
300Ω
600Ω
Figure 5. Typical Application for Single-Ended-to-Differential Conversion
______________________________________________________________________________________ 15
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
25Ω
INA+
22pF
0.1μF
6
5
4
1
2
T1
V
IN
N.C.
COM
MAX185
2.2μF
0.1μF
3
MINICIRCUITS
TT1–6
25Ω
INA-
INB+
22pF
22pF
MAX1185
25Ω
0.1μF
6
5
4
1
2
3
T1
V
IN
N.C.
2.2μF
0.1μF
MINICIRCUITS
TT1–6
25Ω
INB-
22pF
Figure 6. Transformer-Coupled Input Drive
Static Parameter Definitions
Dynamic Parameter
Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the MAX1185 are measured using
the best straight-line fit method.
Aperture Jitter
Figure 9 depicts the aperture jitter (t ), which is the
AJ
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 9).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes and a monotonic transfer function.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
16 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
REFP
1kΩ
1kΩ
R
50Ω
ISO
V
IN
0.1μF
INA+
COM
INA-
MAX4108
C
22pF
IN
100Ω
100Ω
REFN
0.1μF
R
50Ω
ISO
C
IN
22pF
REFP
MAX1185
R
50Ω
1kΩ
ISO
V
IN
0.1μF
INB+
MAX4108
C
IN
100Ω
100Ω
1kΩ
22pF
REFN
0.1μF
R
50Ω
ISO
INB-
C
IN
22pF
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N-Bits):
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components minus the fundamental
and the DC offset.
SNR
= 6.02 x N + 1.76
dB[max]
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
______________________________________________________________________________________ 17
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX2451
INA+
INA-
A/B
0°
DSP
POST
PROCESSING
90°
MAX1185
MAX185
INB+
INB-
CHA AND CHB DATA
ALTERNATINGLY
AVAILABLE ON 10-BIT,
MULTIPLEXED
DOWNCONVERTER
÷
8
OUTPUT BUS
Figure 8. Typical QAM Application, Using the MAX1185
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first four
harmonics of the input signal to the fundamental itself.
This is expressed as:
CLK
⎛
⎞
2
2
2
2
V
+ V + V + V
3 4 5
2
⎜
⎜
⎝
⎟
⎟
⎠
THD = 20 ×log
ANALOG
INPUT
10
V
1
t
AD
where V is the fundamental amplitude, and V through
5
harmonics.
1
2
t
AJ
V
are the amplitudes of the 2nd- through 5th-order
SAMPLED
DATA (T/H)
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
HOLD
TRACK
TRACK
T/H
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) inter-
modulation products. The individual input tone levels
are backed off by 6.5dB from full scale.
Figure 9. T/H Aperture Timing
18 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
Functional Diagram
V
OGND
OV
DD
GND
DD
INA+
PIPELINE
ADC
A/B
DEC
MUX
T/H
INA-
CLK
10
CONTROL
INB+
INB-
10
PIPELINE
ADC
OUTPUT
DRIVERS
DEC
T/H
D0A/B–D9A/B
OE
T/B
REFERENCE
PD
SLEEP
MAX1185
REFOUT
REFN COM REFP
REFIN
Pin-Compatible Versions
RESOLUTION
(Bits)
SPEED GRADE
PART
OUTPUT BUS
(Msps)
MAX1190
MAX1180
MAX1181
MAX1182
MAX1183
MAX1186
MAX1184
MAX1185
MAX1198
MAX1197
MAX1196
MAX1195
10
10
10
10
10
10
10
10
8
120
105
80
Full duplex
Full duplex
Full duplex
Full duplex
Full duplex
Half duplex
Full duplex
Half duplex
Full duplex
Full duplex
Half duplex
Full duplex
65
40
40
20
20
100
60
8
8
40
8
40
______________________________________________________________________________________ 19
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
21-0065
LAND PATTERN NO.
90-0137
48 TQFP-EP
C48E+7
MAX185
20 ______________________________________________________________________________________
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
MAX185
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
2
3
4/10
5/11
Added automotive qualified part to Ordering Information
Corrected pin 13 label in Pin Configuration
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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