MAX1202BC/D [MAXIM]
5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE; 5V，8通道，串行， 12位ADC， 3V数字接口
| 型号： | MAX1202BC/D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 5v, 8-cHANNEL, sERIAL, 12-bIT adcS WITH 3v dIGITAL iNTERFACE |
| 文件： | 总24页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1173; Rev 2; 5/98
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1202/MAX1203 are 12-bit data-acquisition
systems specifically designed for use in applications
with mixed +5V (analog) and +3V (digital) supply volt-
ages. They operate with a single +5V analog supply or
dual ±5V analog supplies, and combine an 8-channel
multiplexer, high-bandwidth track/hold, and serial inter-
face with high conversion speed and low power con-
sumption.
♦ 8-Channel Single-Ended or 4-Channel
Differential Inputs
♦ Operates from Single +5V or Dual ±5V Supplies
♦ User-Adjustable Output Logic Levels
(2.7V to 5.25V)
♦ Low Power: 1.5mA (operating mode)
2µA (power-down mode)
A 4-wire s e ria l inte rfa c e c onne c ts d ire c tly to
SPI™/MICROWIRE™ devices without external logic,
and a serial strobe output allows direct connection to
TMS320-fa mily d ig ita l s ig na l p roc e s s ors . The
MAX1202/MAX1203 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions. The serial
interface operates at up to 2MHz.
♦ Internal Track/Hold, 133kHz Sampling Rate
♦ Internal 4.096V Reference (MAX1202)
♦ SPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦ Software-Configurable Unipolar/Bipolar Inputs
♦ 20-Pin DIP/SSOP
The MAX1202 features an internal 4.096V reference,
while the MAX1203 requires an external reference. Both
parts have a reference-buffer amplifier that simplifies
gain trim. They also have a VL pin that is the power
supply for the digital outputs. Output logic levels (3V,
3.3V, or 5V) are determined by the value of the voltage
applied to this pin.
Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX1202ACPP 0°C to +70°C 20 Plastic DIP
MAX1202BCPP 0°C to +70°C 20 Plastic DIP
MAX1202ACAP 0°C to +70°C 20 SSOP
MAX1202BCAP 0°C to +70°C 20 SSOP
MAX1202BC/D 0°C to +70°C Dice*
±1/2
±1
These devices provide a hard-wired SHDN pin and two
software-selectable power-down modes. Accessing the
serial interface automatically powers up the devices. A
quick turn-on time enables the MAX1202/MAX1203 to
be shut down between conversions, allowing the user
to optimize supply currents. By customizing power-
down between conversions, supply current can drop
below 10µA at reduced sampling rates.
±1/2
±1
±1
Ordering Information continued at end of data sheet.
*Dice are specified at T = +25°C, DC parameters only.
A
P in Co n fig u ra t io n
The MAX1202/MAX1203 are available in 20-pin SSOP
and DIP packages, and are specified for the commer-
cial, extended, and military temperature ranges.
TOP VIEW
20
V
DD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
1
2
Ap p lic a t io n s
5V/3V Mixed-Supply Systems
Data Acquisition
19 SCLK
18 CS
3
MAX1202
MAX1203
4
17 DIN
5
SSTRB
16
High-Accuracy Process Control
Battery-Powered Instruments
Medical Instruments
6
15 DOUT
14 VL
7
8
13 GND
V
9
12 REFADJ
11 REF
SS
Typical Operating Circuit appears at end of data sheet.
SPI is a registered trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
SHDN
10
DIP/SSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ................................................................-0.3V to 6V
Continuous Power Dissipation (T = +70°C)
A
VL ...............................................................-0.3V to (V + 0.3V)
Plastic DIP (derate 11.11mW/°C above +70°C) ...........889mW
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
CERDIP (derate 11.11mW°C above +70°C).................889mW
Operating Temperature Ranges
DD
V
SS
to GND.................................................................0.3V to -6V
V
DD
to V ................................................................-0.3V to 12V
SS
CH0–CH7 to GND............................(V - 0.3V) to (V + 0.3V)
SS
DD
CH0–CH7 Total Input Current...........................................±20mA
REF to GND................................................-0.3V to (V + 0.3V)
MAX1202_C_P/MAX1203_C_P ............................0°C to +70°C
MAX1202_E_P/MAX1203_E_P..........................-40°C to +85°C
MAX1202BMJP/MAX1203BMJP .....................-55°C to +125°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
REFADJ to GND .........................................-0.3V to (V + 0.3V)
DD
Digital Inputs to GND .................................-0.3V to (V + 0.3V)
DD
Digital Outputs to GND.................................-0.3V to (VL + 0.3V)
Digital Output Sink Current .................................................25mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V ±5%, VL = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
SS
SCLK
/MAX1203
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin;
REF
T
A
= T
to T ; unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY (Note 1)
Resolution
12
Bits
MAX1202A/MAX1203A
±0.5
±1.0
±1.0
±3.0
±3
Relative Accuracy (Note 2)
INL
LSB
MAX1202B/MAX1203B
Differential Nonlinearity
Offset Error
DNL
No missing codes over temperature
LSB
LSB
MAX1202 (all grades)
Gain Error (Note 3)
MAX1203A
±1.5
±3
LSB
External reference, 4.096V
External reference, 4.096V
MAX1203B
Gain Temperature Coefficient
±0.8
±0.1
ppm/°C
LSB
Channel-to-Channel
Offset Matching
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 4.096Vp-p, 133ksps, 2.0MHz external clock, bipolar-input mode)
Signal-to-Noise + Distortion Ratio
SINAD
70
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-80
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Small-Signal Bandwidth
SFDR
80
dB
dB
V
= 4.096Vp-p, 65kHz (Note 4)
-85
4.5
IN
-3dB rolloff
MHz
kHz
Full-Power Bandwidth
800
2
_______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%, VL = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
SS
SCLK
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin;
REF
T
A
= T
to T ; unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CONVERSION RATE
Internal clock
5.5
6
10
Conversion Time (Note 5)
t
µs
CONV
External clock, 2MHz, 12 clocks/conversion
Track/Hold Acquisition Time
Aperture Delay
t
1.5
µs
ns
ACQ
10
<50
1.7
Aperture Jitter
ps
Internal Clock Frequency
MHz
External compensation mode, 4.7µF
Internal compensation mode (Note 6)
Used for data transfer only
0.1
0.1
0
2.0
0.4
2.0
External Clock Frequency Range
MHz
ANALOG INPUT
Unipolar, V = 0V
V
REF
SS
Input Voltage Range, Single-
Ended and Differential (Note 7)
V
Bipolar, V = -5V
±V
/ 2
SS
REF
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= ±5V
±0.01
16
±1
µA
pF
CH_
(Note 6)
INTERNAL REFERENCE (MAX1202 only, reference-buffer enabled)
REF Output Voltage
T
A
= +25°C
4.076
4.096
4.116
30
V
REF Short-Circuit Current
mA
MAX1202AC
±30
±30
±30
2.5
±50
±60
V
REF
Temperature Coefficient
MAX1202AE
ppm/°C
MAX1202B
Load Regulation (Note 8)
Capacitive Bypass at REF
0mA to 0.5mA output load
Internal compensation mode
External compensation mode
mV
µF
0
4.7
Capacitive Bypass at REFADJ
REFADJ Adjustment Range
0.01
µF
%
±1.5
EXTERNAL REFERENCE AT REF (Reference buffer disabled, V
= 4.096V)
REF
2.50
12
V
50mV
+
DD
Input Voltage Range
V
Input Current
200
20
350
µA
kΩ
µA
Input Resistance
REF Input Current in Shutdown
1.5
10
SHDN = 0V
V
50mV
-
DD
REFADJ Buffer Disable Threshold
V
_______________________________________________________________________________________
3
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%, VL = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
SS
SCLK
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin;
REF
T
A
= T
to T ; unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EXTERNAL REFERENCE AT REFADJ
Internal compensation mode
External compensation mode
MAX1202
0
Capacitive Bypass at REF
µF
V/V
µA
4.7
1.68
1.64
Reference-Buffer Gain
MAX1203
MAX1202
±50
±5
REFADJ Input Current
MAX1203
POWER REQUIREMENTS
V
Positive Supply Voltage
Negative Supply Voltage
V
5 ±5%
DD
V
SS
0 or -5 ±5%
V
Operating mode
1.5
30
2
2.5
70
mA
/MAX1203
Positive Supply Current
I
DD
Fast power-down (Note 9)
Full power-down (Note 9)
Operating mode and fast power-down
Full power-down
µA
10
50
Negative Supply Current
I
SS
µA
10
Logic Supply Voltage
VL
2.70
5.25
10
V
Logic Supply Current (Notes 6, 10)
I
VL
VL = V = 5V
µA
DD
Positive Supply Rejection
(Note 11)
V
= 5V ±5%; external reference, 4.096V;
DD
PSR
PSR
PSR
±0.06
±0.01
±0.06
±0.5
±0.5
±0.5
mV
mV
mV
full-scale input
Negative Supply Rejection
(Note 11)
V
SS
= -5V ±5%; external reference, 4.096V;
full-scale input
Logic Supply Rejection
(Note 12)
External reference, 4.096V; full-scale input
4
_______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±5%, VL = 2.7V to 3.6V; V = 0V or -5V ±5%; f = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion
DD
SS
SCLK
cycle (133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin;
REF
T
= T
to T
; unless otherwise noted.)
PARAMETER SYMBOL
DIGITAL INPUTS: DIN, SCLK, CS, SHDN
A
MIN MAX
CONDITIONS
MIN
TYP
MAX
UNITS
V
2.0
V
V
DIN, SCLK, CS Input High Voltage
DIN, SCLK, CS Input Low Voltage
DIN, SCLK, CS Input Hysteresis
DIN, SCLK, CS Input Leakage
DIN, SCLK, CS Input Capacitance
SHDN Input High Voltage
IH
V
IL
0.8
V
HYST
0.15
V
I
IN
V
= 0V or V
DD
±1
15
µA
pF
V
IN
C
(Note 6)
IN
V
SH
V
- 0.5
DD
V
SM
1.5
V
DD
- 1.5
V
SHDN Input Mid-Voltage
V
FLT
2.75
V
SHDN Voltage, Floating
SHDN = open
V
0.5
4.0
V
SHDN Input Low Voltage
SL
I
SH
µA
µA
SHDN Input Current, High
SHDN Input Current, Low
SHDN = V
DD
I
SL
-4.0
SHDN = 0V
SHDN Maximum Allowed
Leakage, Mid-Input
-100
100
0.4
nA
SHDN = open
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 2.7V to 3.6V)
I
= 3mA
= 6mA
SINK
Output Voltage Low
V
OL
V
I
0.3
SINK
Output Voltage High
V
OH
I
= 1mA
VL - 0.5
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
±10
15
µA
pF
CS = VL
CS = VL (Note 6)
L
C
OUT
DIGITAL OUTPUTS: DOUT, SSTRB (VL = 4.75V to 5.25V)
I
= 5mA
= 8mA
0.4
SINK
Output Voltage Low
V
OL
V
I
0.3
SINK
Output Voltage High
V
OH
I
= 1mA
4
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
I
±10
15
µA
pF
CS = 5V
CS = 5V (Note 6)
L
C
OUT
_______________________________________________________________________________________
5
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
TIMING CHARACTERISTICS
(V = +5V ±5%, VL = 2.7V to 3.6V, V = 0V or -5V ±5%, T = T
to T , unless otherwise noted.)
MAX
DD
SS
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
1.5
TYP
MAX
UNITS
µs
Acquisition Time
t
ACQ
DIN to SCLK Setup
t
100
ns
DS
DH
DO
DIN to SCLK Hold
t
0
ns
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
t
C
C
C
= 100pF
= 100pF
= 100pF
20
240
240
240
ns
LOAD
LOAD
LOAD
t
ns
DV
t
ns
TR
t
100
0
ns
CSS
CSH
t
ns
t
200
200
ns
CH
t
ns
CL
t
C
= 100pF
240
240
ns
SSTRB
LOAD
CS Fall to SSTRB Output Enable
(Note 6)
/MAX1203
t
External-clock mode only, C
External-clock mode only, C
Internal-clock mode only
= 100pF
= 100pF
ns
ns
ns
SDV
LOAD
LOAD
CS Rise to SSTRB Output
Disable (Note 6)
t
240
STR
SSTRB Rise to SCLK Rise
(Note 6)
t
0
SCK
Note 1: Tested at V = 5.0V; V = 0V; unipolar-input mode.
DD
SS
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 3: MAX1202—internal reference, offset nulled; MAX1203—external reference (V = 4.096V), offset nulled.
REF
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V to V
.
SS
DD
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND;
REFADJ = GND. Shutdown supply current is also dependent on V (Figure 12c).
IH
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on f , and on the static and capacitive load at DOUT and SSTRB.
SCLK
Note 11: Measured at V
+ 5% and V
- 5% only.
SUPPLY
SUPPLY
Note 12: Measured at VL = 2.7V and VL = 3.6V.
6
_______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V
DD
= 5V ±5%; VL = 2.7V to 3.6V; V = 0V; f
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
SS
SCLK
(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = +25°C;
A
REF
unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
6
2.0
REFADJ = GND
FULL POWER-DOWN
5
1.8
1.6
4
3
MAX1202
MAX1202
1.4
1.2
1.0
MAX1203
2
1
0.5
0
MAX1203
0
-60
-20
20
60
100
140
-60
-20
20
60
100
140
4.5
4.7
4.9
5.1
5.3
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
OFFSET ERROR
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
5
4
0.8
0.7
0.6
2.0
1.5
1.0
3
2
DIFFERENTIAL
0.5
0.4
0.3
0.2
0.1
0
0.5
0
1
0
SINGLE-ENDED
-1
-2
-3
-0.5
-1.0
-1.5
-2.0
-4
-5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CHANNEL-TO-CHANNEL GAIN-ERROR
MATCHING vs. TEMPERATURE
CHANNEL-TO-CHANNEL OFFSET-ERROR
MATCHING vs. TEMPERATURE
5
4
3
2
3
2
1
0
1
0
-1
-2
-3
-1
-2
-3
-4
-5
-60
-20
20
60
100
140
-60
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V
DD
= 5V ±5%; VL = 2.7V to 3.6V; V = 0V; f
= 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle
SS
SCLK
(133ksps); MAX1202—4.7µF capacitor at REF pin; MAX1203—external reference, V
= 4.096V applied to REF pin; T = +25°C;
A
REF
unless otherwise noted.)
INTEGRAL NONLINEARITY
vs. DIGITAL
FFT PLOT
1.0
0.8
20
0
V
SS
= -5V
0.6
-20
-40
-60
-80
-100
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-120
/MAX1203
0
750 1500 2250 3000 3750 4500
DIGITAL CODE
0
33.25
66.50
FREQUENCY (kHz)
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
1–8
9
CH0–CH7
Sampling Analog Inputs
V
SS
Negative Supply Voltage. Tie V to -5V ±5% or to GND.
SS
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1202/MAX1203 down to 10µA (max)
supply current; otherwise, the MAX1202/MAX1203 are fully operational. Pulling SHDN to V puts the
reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-
DD
10
SHDN
buffer amplifier in external compensation mode.
Reference-Buffer Output/ADC Reference Input. In internal reference mode (MAX1202 only), the refer-
ence buffer provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference
11
REF
mode, disable the internal buffer by pulling REFADJ to V
DD.
12
13
REFADJ
GND
Input to the Reference-Buffer Amplifier. Tie REFADJ to V to disable the reference-buffer amplifier.
DD
Ground; IN- Input for Single-Ended Conversions
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB). 2.7V ≤ VL ≤ 5.25V.
14
15
VL
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1202/MAX1203 begin
the analog-to-digital conversion, and goes high when the conversion is finished. In external clock
mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS
is high (external clock mode).
16
SSTRB
17
18
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
CS
Serial-Clock Input. SCLK clocks data in and out of the serial interface. In external clock mode, SCLK
also sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
19
20
SCLK
V
DD
Positive Supply Voltage, +5V ±5%
8
_______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
+3.3V
18
19
3k
CS
DOUT
DOUT
SCLK
INPUT
SHIFT
INT
17
10
3k
DIN
C
C
LOAD
LOAD
CLOCK
REGISTER
CONTROL
LOGIC
SHDN
GND
a. High-Z to V and V to V
OH
GND
1
2
3
4
5
6
7
8
CH0
CH1
CH2
CH3
15
16
OUTPUT
SHIFT
REGISTER
DOUT
b. High-Z to V and V to V
OL
OH
OL
OL
OH
SSTRB
ANALOG
INPUT
MUX
Figure 1. Load Circuits for Enable Time
T/H
CH4
CH5
CH6
CH7
CLOCK
IN
12-BIT
SAR
ADC
+3.3V
OUT
MAX1202
MAX1203
20
14
9
13
REF
3k
V
DD
GND
DOUT
DOUT
A ≈ 1.68
+2.44V
REFERENCE
(MAX1202)
VL
20k
V
SS
3k
C
LOAD
12
11
C
LOAD
REFADJ
REF
+4.096V
GND
GND
a. V to High-Z
OH
b. V to High-Z
OL
Figure 2. Load Circuits for Disable Time
Figure 3. Block Diagram
with respect to GND during a conversion. To do this,
connect a 0.1µF capacitor from IN- (of the selected
analog input) to GND.
_______________De t a ile d De s c rip t io n
The MAX1202/MAX1203 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 12-bit digital output. A flexible ser-
ial interface provides easy interface to 3V microproces-
sors (µPs). Figure 3 is the MAX1202/MAX1203 block
diagram.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the input control word’s
last bit is entered. The T/H switch opens at the end of
the acquisition interval, retaining charge on C
sample of the signal at IN+.
as a
HOLD
P s e u d o -Diffe re n t ia l In p u t
Figure 4 shows the ADC’s analog comparator’s sam-
pling architecture. In single-ended mode, IN+ is inter-
na lly s witc he d to CH0–CH7 a nd IN- is s witc he d to
GND. In differential mode, IN+ and IN- are selected
from p a irs of CH0/CH1, CH2/CH3, CH4/CH5, a nd
CH6/CH7. Config ure the c ha nne ls us ing Ta b le s 3
and 4.
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
HOLD
negative input (IN-). In single-ended mode, IN- is sim-
ply GND. This unbalances node ZERO at the compara-
tor’s inp ut. The c a p a c itive DAC a d jus ts d uring the
re ma ind e r of the c onve rs ion c yc le to re s tore nod e
ZERO to 0V within the limits of 12-b it re s olution.
This action is equivalent to transferring a charge of
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential such that only the signal at IN+ is
sampled. The return side (IN-) must remain stable (typi-
cally within ±0.5LSB, within ±0.1LSB for best results)
16p F x [(V +) - (V -)] from C to the b ina ry-
IN
IN
HOLD
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
_______________________________________________________________________________________
9
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
be used if an input capacitor is connected to the analog
Tra c k /Ho ld
The T/H enters tracking mode on the falling clock edge
after the fifth bit of the 8-bit control word is shifted in. The
T/H enters hold mode on the falling clock edge after the
eighth bit of the control word is shifted in. IN- is con-
nected to GND if the converter is set up for single-ended
inputs, and the converter samples the “+” input. IN- con-
nects to the “-” input if the converter is set up for differen-
tial inputs, and the difference of |N+ - IN- is sampled.
The positive input connects back to IN+, at the end of
inputs, as shown in Figure 5. Note that the input capaci-
tor forms an RC filter with the input source impedance,
limiting the ADC’s signal bandwidth.
12-BIT CAPACITIVE DAC
REF
COMPARATOR
INPUT
MUX
C
HOLD
ZERO
the conversion, and C
charges to the input signal.
–
+
HOLD
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
a c q uis ition time inc re a s e s a nd more time mus t b e
allowed between conversions. The acquisition time,
16pF
9k
R
IN
C
SWITCH
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
t
, is the maximum time the device takes to acquire
ACQ
T/H
SWITCH
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following:
/MAX1203
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = GND.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, CH6/CH7.
t
= 9 x (R + R ) x 16pF
S IN
ACQ
where RIN = 9kΩ, RS = the source impedance of the
input signal, and t is never less than 1.5µs. Source
impedances below 1kΩ do not significantly affect the
ACQ
Figure 4. Equivalent Input Circuit
ADC’s AC performance. Higher source impedances can
+3V
VL
V
DD
+5V
OSCILLOSCOPE
0.1µF
0.1µF
4.7µF
GND
SCLK
V
SS
MAX1202
MAX1203
SSTRB
DOUT*
0V TO
4.096V
ANALOG
INPUT
CH7
CS
0.01µF
SCLK
CH4
2MHz
OSCILLATOR
CH3
CH1
CH2
+3V
DIN
SSTRB
DOUT
REFADJ
REF
SHDN
N.C.
C1
4.7µF
C2
0.01µF
+2.5V
**
+2.5V
REFERENCE
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX).
**REQUIRED FOR MAX1203 ONLY.
Figure 5. Quick-Look Circuit
10 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
Table 1a. Unipolar Full Scale and Zero
Scale
Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
ZERO
SCALE
NEGATIVE
FULL SCALE SCALE
ZERO
REFERENCE
FULL SCALE
REFERENCE
Internal
External
FULL SCALE
Internal
0V
0V
0V
+4.096V
-4.096V / 2
-1/2 V
0V
0V
0V
+4.096V / 2
at REFADJ
at REF
V
x A*
REFADJ
at
+1/2 V
REFADJ
REFADJ
External
REFADJ
x A*
x A*
V
REF
at REF
-1/2 V
+1/2 V
REF
REF
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
*A = 1.68 for the MAX1202, 1.64 for the MAX1203.
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result shifts out of DOUT. Varying the ana-
log inp ut to CH7 a lte rs the s e q ue nc e of b its from
DOUT. A total of 15 clock cycles per conversion is
required. All SSTRB and DOUT output transitions occur
on SCLK’s falling edge.
In p u t Ba n d w id t h
The ADC’s inp ut tra c king c irc uitry ha s a 4.5MHz
small-signal bandwidth. Therefore it is possible to digi-
tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
ra te b y us ing und e rs a mp ling te c hniq ue s . To a void
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Ho w t o S t a rt a Co n ve rs io n
Clocking a control byte into DIN starts conversion on
the MAX1202/MAX1203. With CS low, each rising edge
on SCLK c loc ks a b it from DIN into the MAX1202/
MAX1203’s internal shift register. After CS falls, the first
logic “1” bit defines the control byte’s MSB. Until this
first “start” bit arrives, any number of logic “0” bits can
be clocked into DIN with no effect. Table 2 shows the
control-byte format.
An a lo g In p u t Ra n g e a n d In p u t P ro t e c t io n
Internal protection diodes, which clamp the analog
inputs to V
and V , allow the analog input pins to
DD
SS
swing from (V - 0.3V) to (V
+ 0.3V) without dam-
SS
DD
age. However, for accurate conversions near full scale,
the inputs must not exceed V by more than 50mV, or
DD
be lower than V by 50mV.
SS
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels more than 2mA.
The MAX1202/MAX1203 a re fully c omp a tib le with
SPI/MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE and
SPI both transmit and receive a byte at the same time.
Using the Typical Operating Circuit, the simplest soft-
ware interface requires only three 8-bit transfers to per-
form a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the
12-bit conversion result).
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Qu ic k Lo o k
Us e the c irc uit of Fig ure 5 to q uic kly e va lua te the
MAX1202/MAX1203’s a na log p e rforma nc e . The
MAX1202/MAX1203 require a control byte to be written
to DIN before each conversion. Tying DIN to +3V feeds
in control byte $FF hex, which triggers single -ended
unipolar conversions on CH7 in external clock mode
______________________________________________________________________________________ 11
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
Table 2. Control-Byte Format
Bit 7
(MSB)
Bit 0
(LSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
START
SEL 2
SEL 1
SEL 0
PD1
PD0
UNI/BIP
SGL/DIF
Bit
Name
Description
7 (MSB)
START
The first logic 1 bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels is used for the conversion
(Tables 3 and 4).
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to V can be converted; in bipolar mode, the signal can range
3
2
UNI/BIP
SGL/DIF
REF
from -V
/ 2 to +V
/ 2.
REF
REF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to GND. In differential mode, the voltage dif-
ference between two channels is measured. (Tables 3 and 4.)
Selects clock and power-down modes.
/MAX1203
PD1
0
0
PD0
0
1
Mode
Full power-down (I = 2µA, internal reference)
Fast power-down (I = 30µA, internal reference)
DD
1
PD1
PD0
DD
0 (LSB)
1
1
0
1
Internal clock mode
External clock mode
DIF
Table 3. Channel Selection in Single-Ended Mode (SGL/
= 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
GND
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+
–
–
–
–
–
–
–
–
+
+
+
+
+
+
+
DIF
Table 4. Channel Selection in Differential Mode (SGL/
= 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
–
+
–
–
–
+
–
+
+
+
12 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Digital Output
In unipolar-input mode, the output is straight binary
(Fig ure 15); for b ip ola r inp uts , the outp ut is two’s -
complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the VL pin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1202/MAX1203’s digital inputs are
designed to be compatible with 5V CMOS logic as well
as 3V logic.
1) Set up the control byte for external clock mode and
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS on the MAX1202/MAX1203 low.
In t e rn a l a n d Ex t e rn a l Clo c k Mo d e s
The MAX1202/MAX1203 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1202/
MAX1203. The T/H acquires the input signal as the last
three bits of the control byte are clocked into DIN. Bits
PD1 and PD0 of the control byte program the clock
mode. Figures 7–10 show the timing characteristics
common to both modes.
3) Transmit TB1 and simultaneously receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and simulta-
neously receive byte RB3.
6) Pull CS on the MAX1202/MAX1203 high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded with
one leading zero and three trailing zeros. The total conver-
sion time is a function of the serial-clock frequency and
the amount of idle time between 8-bit transfers. To avoid
excessive T/H droop, make sure that the total conversion
time does not exceed 120µs.
External Clock
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows SSTRB timing in external clock
mode.
CS
t
ACQ
SCLK
1
4
8
12
16
20
24
UNI/ SGL/
BIP DIF
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
PD1 PD0
START
RB2
B8
RB3
B0
LSB
RB1
FILLED WITH
ZEROS
B11
MSB
B10 B9
B7
B6
B5
B4
B3
B2
B1
ACQUISITION
1.5µs
CONVERSION
IDLE
ADC STATE
IDLE
(SCLK = 2MHz)
Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)
______________________________________________________________________________________ 13
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
• • •
CS
t
t
CH
t
CSH
CSS
t
t
CL
CSH
SCLK
• • •
t
DS
t
DH
DIN
• • •
t
DV
t
DO
t
TR
DOUT
• • •
/MAX1203
Figure 7. Detailed Serial-Interface Timing
CS
• • •
• • •
t
t
STR
SDV
SSTRB
SCLK
• • •
• • •
t
t
SSTRB
SSTRB
• • •
• • •
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
The conversion must complete in some minimum time or
droop on the sample-and-hold capacitors might degrade
conversion results. Use internal clock mode if the clock
period exceeds 10µs or if serial-clock interruptions could
cause the conversion interval to exceed 120µs.
convenience, at any clock rate from zero to 2MHz.
SSTRB goes low at the start of the conversion, then goes
high when the conversion is complete. SSTRB is low for
a maximum of 10µs, during which time SCLK should
remain low for best noise performance. An internal regis-
ter stores data while the conversion is in progress. SCLK
clocks the data out at this register at any time after the
conversion is complete. After SSTRB goes high, the next
falling clock edge produces the MSB of the conversion
at DOUT, followed by the remaining bits in MSB-first for-
mat (Figure 9). CS does not need to be held low once a
Internal Clock
In internal clock mode, the MAX1202/MAX1203 generate
their own conversion clock. This frees the µP from run-
ning the SAR conversion clock, and allows the con-
ve rs ion re s ults to b e re a d b a c k a t the p roc e s s or’s
14 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
CS
SCLK
DIN
1
4
8
18
24
2
3
5
6
7
9
10
11
12
19
20
21
22
23
UNI/ SGL/
BIP DIF
SEL2 SEL1 SEL0
PD1 PD0
START
SSTRB
t
CONV
FILLED WITH
ZEROS
B11
MSB
B0
LSB
DOUT
B10 B9
B2
B1
ACQUISITION
1.5µs
(SCLK = 2MHz)
CONVERSION
10µs MAX
ADC STATE
IDLE
IDLE
Figure 9. Internal Clock Mode Timing
CS • • •
t
t
CONV
CSS
t
t
SCK
CSH
SSTRB • • •
t
SSTRB
SCLK • • •
PD0 CLOCK IN
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
after the eighth bit of the control byte (the PD0 bit) is
clocked into DIN. The start bit is defined as one of the
following:
conversion is started. Pulling CS high prevents data from
being clocked into the MAX1202/MAX1203 and three-
states DOUT, but it does not adversely affect an internal
c loc k mod e c onve rs ion a lre a d y in p rog re s s . Whe n
internal clock mode is selected, SSTRB does not go into
a high-impedance state when CS goes high.
The first high bit clocked into DIN with CS low any-
time the converter is idle (e.g., after V is applied).
DD
or
Figure 10 shows SSTRB timing in internal clock mode.
Data can be shifted in and out of the MAX1202/MAX1203
The first high bit clocked into DIN after bit 5 (B5) of a
conversion in progress appears at DOUT.
at clock rates up to 2.0MHz, if t
is kept above 1.5µs.
ACQ
Da t a Fra m in g
If a falling edge on CS forces a start bit before B5
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1202/MAX1203 can run is 15 clocks/conversion.
CS’s falling edge does not start a conversion on the
MAX1202/MAX1203. The first logic high clocked into DIN
is interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on SCLK’s falling edge
______________________________________________________________________________________ 15
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
Figure 11a shows the serial-interface timing necessary
to perform a conversion every 15 SCLK cycles in exter-
nal clock mode. If CS is low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
For the MAX1202, fast power-down mode turns off all
c irc uitry e xc e p t the b a nd g a p re fe re nc e . With fa s t
power-down mode, the supply current is 30µA. Power-up
time can be shortened to 5µs in internal compensation
mode.
Most microcontrollers (µCs) require that data transfers
occur in multiples of eight clock cycles; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1202/MAX1203. Fig ure 11b s hows the
serial-interface timing necessary to perform a conver-
sion every 16 SCLK cycles in external clock mode.
Since the MAX1203 does not have an internal reference,
power-up times coming out of full or fast power-down are
identical.
I
DD
shutdown current can increase if any digital input
(DIN, SCLK, CS) is held high in either power-down
mode. The actual shutdown current depends on the
state of the digital inputs, the voltage applied to the digi-
tal inputs (V ), the supply voltage (V ), and the operat-
__________ Ap p lic a t io n s In fo rm a t io n
P o w e r-On Re s e t
When power is first applied and if SHDN is not pulled
low, inte rna l p owe r-on re s e t c irc uitry a c tiva te s the
MAX1202/MAX1203 in internal clock mode, ready to
convert with SSTRB = high. After the power supplies
are stabilized, the internal reset time is 100µs. No con-
ve rs ions s hould b e p e rforme d d uring this p ha s e .
SSTRB is high on power-up, and if CS is low, the first
logical 1 on DIN is interpreted as a start bit. Until a con-
version takes place, DOUT shifts out zeros.
IH
DD
ing temperature. Figure 12c shows the maximum I
DD
increase for each digital input held high in power-down
mode for different operating conditions. This current is
cumulative, so if all three digital inputs are held high, the
additional shutdown current is three times the value
shown in Figure 12c.
/MAX1203
In both software power-down modes, the serial interface
remains operational, but the ADC does not convert.
Table 5 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor (200ms with a 33µF capacitor) when the
c a p a c itor is initia lly fully d is c ha rg e d . From fa s t
power-down, start-up time can be eliminated by using
low-leakage capacitors that do not discharge more than
1/2LSB while shut down. In power-down, the capacitor
has to supply the current into the reference (typically
1.5µA) and the transient currents at power-up.
Re fe re n c e -Bu ffe r Co m p e n s a t io n
In addition to its shutdown function, SHDN also selects
internal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. Compensated or not, the minimum clock rate is
100kHz due to droop on the sample-and-hold.
Floa t SHDN to s e le c t e xte rna l c omp e ns a tion. The
Typical Operating Circuit uses a 4.7µF capacitor at REF.
A value of 4.7µF or greater ensures stability and allows
c onve rte r op e ra tion a t the 2MHz full c loc k s p e e d .
External compensation increases power-up time (see
the section Choosing Power-Down Mode, and Table 5).
Figures 12a and 12b show the various power-down
sequences in both external and internal clock modes.
Internal compensation requires no external capacitor at
REF, and is selected by pulling SHDN high. Internal
compensation allows for the shortest power-up times,
but the external clock must be limited to 400kHz during
the conversion.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 6, PD1 and
PD0 a ls o s p e c ify the c loc k mod e . Whe n s oftwa re
power-down is asserted, the ADC continues to operate
in the last specified clock mode until the conversion is
complete. The ADC then powers down into a low quies-
cent-current state. In internal clock mode, the interface
remains active and conversion results can be clocked
out even though the MAX1202/MAX1203 have already
entered software power-down.
P o w e r-Do w n
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down or fast power-down mode via bits 1 and 0
of the DIN c ontrol b yte with SHDN hig h or floa ting
(Tables 2 and 6). Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
The first logical 1 on DIN is interpreted as a start bit and
powers up the MAX1202/MAX1203. Following the start
b it, the c ontrol b yte a ls o d e te rmine s c loc k a nd
power-down modes. For example, if the DIN word con-
tains PD1 = 1, the chip remains powered up. If PD1 = 0,
power-down resumes after one conversion.
Full power-down mode turns off all chip functions that draw
quiescent current, reducing I and I typically to 2µA.
DD
SS
16 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
CS
1
8
1
8
1
SCLK
DIN
S
CONTROL BYTE 2
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DOUT
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
• • •
• • •
• • •
• • •
CS
SCLK
S
CONTROL BYTE 0
S
CONTROL BYTE 1
DIN
DOUT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Hardware Power-Down
The SHDN pin places the converter into full power-down
mode. Unlike the software power-down modes, conver-
sion is not completed; it stops coincidentally with SHDN
being brought low. There is no power-up delay if an
external reference, which is not shut down, is used.
SHDN also selects internal or external reference com-
pensation (Table 7).
bypass capacitor at REFADJ forms an RC filter with the
internal 20kΩ reference resistor, with a 0.2ms time con-
stant. To achieve full 12-bit accuracy, 10 time constants
(or 2ms in this example) are required for the reference
buffer to settle. When exiting FULLPD, waiting this 2ms in
FASTPD mode (instead of just exiting FULLPD mode and
returning to normal operating mode) reduces power con-
sumption by a factor of 10 or more (Figure 13).
P o w e r-Do w n S e q u e n c in g
The MAX1202/MAX1203’s a utoma tic p owe r-d own
modes can save considerable power when operating
at less than maximum sample rates. The following sec-
tions discuss the various power-down sequences.
Lowest Power at Higher Throughputs
Figure 14b shows power consumption with external-
reference compensation in fast power-down, with one
and eight channels converted. The external 4.7µF com-
pensation requires a 50µs wait after power-up. This cir-
cuit combines fast multichannel conversion with the
lowest power consumption possible. Full power-down
mode can increase power savings in applications where
the MAX1202/MAX1203 are inactive for long periods of
time, but where intermittent bursts of high-speed conver-
sion are required.
Lowest Power at up to
500 Conversions per Channel per Second
Figure 14a depicts MAX1202 power consumption for one
or eight channel conversions using full power-down
mode and internal reference compensation. A 0.01µF
______________________________________________________________________________________ 17
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
CLOCK
MODE
INTERNAL
EXTERNAL
EXTERNAL
SHDN
SETS FAST
POWER-DOWN
MODE
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
DIN
S X X X X X 1 1
S X X X X X 0 1
S X X X X X 1 1
DOUT
DATA VALID
(12 DATA BITS)
DATA VALID
(12 DATA BITS)
DATA
INVALID
POWERED
UP
FULL
POWER-
DOWN
POWERED UP
POWERED UP
MODE
FAST
POWER-DOWN
Figure 12a. Timing Diagram for Power-Down Modes, External Clock
/MAX1203
Table 5. Typical Power-Up Delay Times
REF
CAPACITOR
(µF)
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION MODE
POWER-DOWN
MODE
Enabled
Enabled
Enabled
Disabled
Disabled
Internal
Internal
External
Fast
Full
5
26
26
300
4.7
Fast/Full
Fast
See Figure 14c
133
133
133
2
2
Full
Table 7. Hard-Wired Shutdown
and Compensation Mode
Table 6. Software Shutdown
and Clock Mode
SHDN
STATE
DEVICE
MODE
REFERENCE-BUFFER
COMPENSATION
PD1
PD0
DEVICE MODE
0
0
1
1
0
1
0
1
Full power-down mode
Fast power-down mode
Internal clock mode
External clock mode
V
Enabled
Internal compensation
External compensation
DD
Floating
Enabled
Full
Power-Down
GND
N/A
18 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
CLOCK
MODE
INTERNAL CLOCK MODE
SETS FULL
POWER-DOWN
SETS INTERNAL
CLOCK MODE
DIN
S X X X X X 1 0
S X X X X X 0 0
S
DOUT
DATA VALID
DATA VALID
SSTRB
MODE
CONVERSION
CONVERSION
FULL
POWER-DOWN
POWERED UP
POWERED
UP
Figure 12b. Timing Diagram for Power-Down Modes, Internal Clock
40
35
Ex t e rn a l a n d In t e rn a l Re fe re n c e s
The MAX1202 can be used with an internal or external
reference, whereas an external reference is required for
the MAX1203. An external reference can be connected
directly at the REF terminal, or at the REFADJ pin.
(V - V ) = 2.55V
DD IH
30
25
20
15
10
5
An internal buffer is designed to provide 4.096V at
REF for both the MAX1202 a nd the MAX1203. The
MAX1202’s inte rna lly trimme d 2.44V re fe re nc e is
buffered with a gain of 1.68. The MAX1203’s REFADJ
pin is buffered with a gain of 1.64, to scale an external
2.5V reference at REFADJ to 4.096V at REF.
(V - V ) = 2.25V
DD IH
(V - V ) = 1.95V
DD IH
0
MAX1202 Internal Reference
The MAX1202’s full-s c a le ra ng e us ing the inte rna l
reference is 4.096V with unipolar inputs and ±2.048V
with bipolar inputs. The internal reference voltage is
adjustable to ±1.5% with the circuit of Figure 17.
-60
-20
20
60
100
140
TEMPERATURE (°C)
Figure 12c. Additional I
for Each Digital Input at a Logic 1
Shutdown Supply Current vs. V
IH
DD
COMPLETE CONVERSION SEQUENCE
2ms WAIT
(ZEROS)
CH1
CH7
(ZEROS)
DIN
1
0 0
FULLPD
2.5V
1
0 1
FASTPD
1
1 1
1
0 0
FULLPD
1
0 1
FASTPD
NOPD
REFADJ
REF
0V
4V
0V
τ = RC = 20kΩ x C
REFADJ
t
≈ 15µs
BUFFEN
Figure 13. MAX1202 FULLPD/FASTPD Power-Up Sequence
______________________________________________________________________________________ 19
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
MAX1202/MAX1203
FAST POWER-DOWN
FULL POWER-DOWN
1000
10,000
2ms FASTPD WAIT
400kHz EXTERNAL CLOCK
INTERNAL COMPENSATION
8 CHANNELS
1 CHANNEL
8 CHANNELS
100
10
1000
100
1 CHANNEL
2MHz EXTERNAL CLOCK
EXTERNAL COMPENSATION
50µs WAIT
1
10
0
50 100 150 200 250 300 350 400 450 500
CONVERSIONS PER CHANNEL PER SECOND
0
2k
4k
6k
8k 10k 12k 14k 16k 18k
CONVERSIONS PER CHANNEL PER SECOND
Figure 14b. MAX1202/MAX1203 Supply Current vs. Sample
Rate/Second, FASTPD, 2MHz Clock
Figure 14a. MAX1202 Supply Current vs. Sample Rate/Second,
FULLPD, 400kHz Clock
/MAX1203
External Reference
With both the MAX1202 and MAX1203, an external refer-
ence can be placed at either the input (REFADJ) or the
output (REF) of the internal reference-buffer amplifier. The
REFADJ inp ut imp e d a nc e is typ ic a lly 20kΩ for the
MAX1202, and higher than 100kΩ for the MAX1203,
where the internal reference is omitted. At REF, the DC
input resistance is a minimum of 12kΩ. During conversion,
an external reference at REF must deliver up to 350µA DC
load current and have an output impedance of 10Ω or
less. If the reference has higher output impedance or is
noisy, bypass it close to the REF pin with a 4.7µF capacitor.
3.0
2.5
2.0
1.5
1.0
0.5
0
Using the buffered REFADJ input makes buffering of the
external reference unnecessary. When connecting an
external reference directly at REF, disable the internal
0.0001 0.001
0.01
0.1
1
10
buffer by tying REFADJ to V . In power-down, the input
DD
TIME IN SHUTDOWN (sec)
bias current to REFADJ can be as much as 25µA with
REFADJ tied to V
(MAX1202 only). Pull REFADJ to
DD
GND to minimize the input bias current in power-down.
Figure 14c. Typical Power-Up Delay vs. Time in Shutdown
Tra n s fe r Fu n c t io n a n d Ga in Ad ju s t
Figure 15 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 16 shows the bipolar
I/O transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary with 1LSB = 1.00mV (4.096V/4096) for unipo-
lar operation, and 1LSB = 1.00mV [(4.096V/2 - -4.096V/
2)/4096] for bipolar operation.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For b e s t p e rforma nc e , us e p rinte d c irc uit b oa rd s .
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 17 shows how to adjust the ADC gain in applica-
tions that use the internal reference. The circuit provides
±1.5% (±65LSBs) of gain adjustment range.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
20 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
OUTPUT CODE
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
011 . . . 111
011 . . . 110
FS = +2.048V
+4.096V
11 . . . 110
11 . . . 101
1LSB =
4096
000 . . . 010
000 . . . 001
000 . . . 000
FS = +4.096V
4.096V
4096
1LSB = +
111 . . . 111
111 . . . 110
111 . . . 101
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
1
2
3
FS
0V
-FS
+FS - 1LSB
INPUT VOLTAGE (LSBs)
FS - 3/2LSB
INPUT VOLTAGE (LSBs)
Figure 15. Unipolar Transfer Function, 4.096V = Full Scale
Figure 16. Bipolar Transfer Function, ±4.096V/2 = Full Scale
(“star” ground point) at GND. Connect all other analog
grounds to this ground. No other digital system ground
s hould b e c onne c te d to this s ing le -p oint a na log
ground. The ground return to the power supply for this
ground should be low impedance and as short as pos-
sible for noise-free operation.
+5V
MAX1202
510k
100k
REFADJ
12
High-frequency noise in the power supplies can affect
the ADC’s high-speed comparator. Bypass these sup-
plies to the single-point analog ground with 0.1µF and
0.01µF
24k
4.7µF
b yp a s s
c a p a c itors
c los e
to
the
MAX1202/MAX1203. Minimize capacitor lead lengths
for best supply-noise rejection. If the +5V power supply
is very noisy, a 10Ω resistor can be connected as a
lowpass filter, as shown in Figure 18.
Figure 17. MAX1202 Reference-Adjust Circuit
______________________________________________________________________________________ 21
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
3) Write an 8-bit word (1XXXXX11) to the MAX1202/
TMS 3 2 0 CL3 x t o MAX1 2 0 2 /
MAX1 2 0 3 In t e rfa c e
Figure 19 shows an application circuit to interface the
MAX1202/MAX1203 to the TMS320 in external clock mode.
Figure 20 shows the timing diagram for this interface circuit.
MAX1203 to initia te a c onve rs ion a nd p la c e the
device into external clock mode. Refer to Table 2 to
select the proper XXXXX bit values for your specific
application.
4) The MAX1202/MAX1203’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1202/MAX1203.
Use the following steps to initiate a conversion in the
MAX1202/MAX1203 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and CLKR
(TMS320 receive clock) as an active-high input clock.
The TMS320’s CLKX and CLKR are tied together with
the MAX1202/MAX1203’s SCLK input.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
2) The MAX1202/MAX1203’s CS is driven low by the
TMS320’s XF_ I/O port to enable data to be clocked
into the MAX1202/MAX1203’s DIN.
6) Pull CS high to disable the MAX1202/MAX1203 until
the next conversion is initiated.
/MAX1203
SUPPLIES
XF
CLKX
CLKR
DX
CS
+5V
-5V
+3V
GND
SCLK
TMS320LC3x
R* = 10Ω
MAX1202
MAX1203
DIN
V
DD
GND
V
SS
VL
+3V DGND
DR
DOUT
DIGITAL
CIRCUITRY
FSR
SSTRB
MAX1202
MAX1203
*OPTIONAL
Figure 18. Power-Supply Grounding Connection
Figure 19. MAX1202/MAX1203-to-TMS320 Serial Interface
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0
HIGH
IMPEDANCE
SSTRB
HIGH
IMPEDANCE
DOUT
MSB
B10
B1
LSB
Figure 20. TMS320 Serial-Interface Timing Diagram
22 ______________________________________________________________________________________
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
/MAX1203
_Ord e rin g In fo rm a t io n (c o n t in u e d )
__________Typ ic a l Op e ra t in g Circ u it
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
+5V
+3V
MAX1202AEPP
MAX1202BEPP
MAX1202AEAP
MAX1202BEAP
MAX1202BMJP
MAX1203ACPP
MAX1203BCPP
MAX1203ACAP
MAX1203BCAP
MAX1203BC/D
MAX1203AEPP
MAX1203BEPP
MAX1203AEAP
MAX1203BEAP
MAX1203BMJP
-40°C to +85°C 20 Plastic DIP
-40°C to +85°C 20 Plastic DIP
-40°C to +85°C 20 SSOP
-40°C to +85°C 20 SSOP
-55°C to +125°C 20 CERDIP**
0°C to +70°C 20 Plastic DIP
0°C to +70°C 20 Plastic DIP
0°C to +70°C 20 SSOP
±1/2
±1
V
CH0
DD
V
DD
VL
0V to
4.096V
±1/2
±1
C3
0.1µF
C4
4.7µF
C5
0.1µF
ANALOG
INPUTS
MAX1202
±1
GND
V
SS
CPU
±1/2
±1
CH7
I/O
CS
±1/2
±1
SCLK
SCK (SK)
MOSI (SO)
MISO (SI)
0°C to +70°C 20 SSOP
REF
DIN
C1
4.7µF
0°C to +70°C Dice*
±1
DOUT
-40°C to +85°C 20 Plastic DIP
-40°C to +85°C 20 Plastic DIP
-40°C to +85°C 20 SSOP
-40°C to +85°C 20 SSOP
-55°C to +125°C 20 CERDIP**
±1/2
±1
SSTRB
SHDN
REFADJ
C2
0.01µF
V
SS
±1/2
±1
±1
*Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability.
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 2503
SUBSTRATE CONNECTED TO V
SS
______________________________________________________________________________________ 23
5 V, 8 -Ch a n n e l, S e ria l, 1 2 -Bit ADCs
w it h 3 V Dig it a l In t e rfa c e
________________________________________________________P a c k a g e In fo rm a t io n
/MAX1203
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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