MAX1213EGK [MAXIM]
1.8V, 12-Bit, 170Msps ADC for Broadband Applications; 1.8V ， 12位，170Msps ADC，用于宽带应用
| 型号： | MAX1213EGK |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.8V, 12-Bit, 170Msps ADC for Broadband Applications |
| 文件： | 总20页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1003; Rev 2; 6/05
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
General Description
Features
The MAX1213 is a monolithic, 12-bit, 170Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies up to
300MHz. The product operates with conversion rates
up to 170Msps while consuming only 788mW.
ꢀ 170Msps Conversion Rate
ꢀ Low Noise Floor of -68dBFS
ꢀ Excellent Low-Noise Characteristics
SNR = 65.8dB at f = 65MHz
IN
SNR = 64.5dB at f = 250MHz
IN
At 170Msps and an input frequency up to 250MHz, the
MAX1213 achieves a spurious-free dynamic range
(SFDR) of 72.9dBc. Its excellent signal-to-noise ratio
(SNR) of 65.8dB at 10MHz remains flat (within 2dB) for
input tones up to 250MHz. This ADC yields an excellent
low-noise floor of -68dBFS, which makes it ideal for
wideband applications such as cable head-end
receivers and power-amplifier predistortion in cellular
base-station transceivers.
ꢀ Excellent Dynamic Range
SFDR = 76.5dBc at f = 65MHz
IN
SFDR = 72.9dBc at f = 250MHz
IN
ꢀ 59.5dB NPR for f
= 28.8MHz and a Noise
NOTCH
Bandwidth of 50MHz
ꢀ Single 1.8V Supply
ꢀ 788mW Power Dissipation at f
= 170MHz
SAMPLE
The MAX1213 requires a single 1.8V supply. The analog
input is designed for either differential or single-ended
operation and can be AC- or DC-coupled. The ADC also
features a selectable on-chip divide-by-2 clock circuit,
which allows the user to apply clock frequencies as high
as 340MHz. This helps to reduce the phase noise of the
input clock source. A low-voltage differential signal
(LVDS) sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible and the data format can be selected to be either
two’s complement or offset binary.
and f = 65MHz
IN
ꢀ On-Chip Track-and-Hold Amplifier
ꢀ Internal 1.23V-Bandgap Reference
ꢀ On-Chip Selectable Divide-by-2 Clock Input
ꢀ LVDS Digital Outputs with Data Clock Output
ꢀ MAX1213 EV Kit Available
The MAX1213 is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX1213EGK
-40°C to +85°C
68 QFN-EP*
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family.
*EP = Exposed paddle.
Pin-Compatible Versions
Applications
Base-Station Power-Amplifier Linearization
RESOLUTION
SPEED GRADE
(Msps)
PART
(BITS)
Cable Head-End Receivers
MAX1121
MAX1122
MAX1123
MAX1124
MAX1213
MAX1214
MAX1215
8
250
170
210
250
170
210
250
Wireless and Wired Broadband Communication
Communications Test Equipment
10
10
10
12
12
12
Radar and Satellite Subsystems
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
ABSOLUTE MAXIMUM RATINGS
AV
to AGND ..................................................... -0.3V to +2.1V
to OGND .................................................... -0.3V to +2.1V
Thermal Resistance (multilayer board)
CC
OV
θjc................................................................................0.8°C/W
θja.................................................................................24°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-60°C to +150°C
Maximum Current into Any Pin............................................50mA
Lead Temperature (soldering,10s) ..................................+300°C
CC
CC
AV
to OV ...................................................... -0.3V to +2.1V
CC
AGND to OGND ................................................... -0.3V to +0.3V
INP, INN to AGND....................................-0.3V to (AV + 0.3V)
REFIO, REFADJ to AGND........................-0.3V to (AV + 0.3V)
All Digital Inputs to AGND........................-0.3V to (AV + 0.3V)
All Digital Outputs to OGND....................-0.3V to (OV + 0.3V)
CC
CC
CC
CC
ESD on All Pins (Human Body Model) ............................. 2000V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
SAMPLE
CC
CC
internal reference, digital output pins differential R = 100Ω 1%, T = T
to T
, unless otherwise noted. Typical values are at
L
A
MIN
MAX
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
12
-2
Bits
Integral Nonlinearity
(Note 2)
INL
f
= 10MHz, T = +25°C
0.75
0.3
+2
LSB
IN
A
Differential Nonlinearity (Note 2)
Transfer Curve Offset
DNL
T
T
= +25°C, No missing codes
= +25°C (Note 2)
-0.8
-3.3
+0.8
+3.3
LSB
mV
A
V
OS
A
Offset Temperature Drift
40
µV/°C
ANALOG INPUTS (INP, INN)
Full-Scale Input Voltage Range
V
T
A
= +25°C (Note 2)
1320
1454
130
1590
mV
P-P
FS
Full-Scale Range Temperature
Drift
ppm/°C
Common-Mode Input Range
Input Capacitance
V
Internally self-biased
1.365 0.15
V
pF
CM
C
2.5
4.2
700
IN
Differential Input Resistance
Full-Power Analog Bandwidth
REFERENCE (REFIO, REFADJ)
Reference Output Voltage
Reference Temperature Drift
REFADJ Input High Voltage
SAMPLING CHARACTERISTICS
Maximum Sampling Rate
Minimum Sampling Rate
Clock Duty Cycle
R
3.00
1.18
6.25
1.30
kΩ
IN
FPBW
MHz
V
T
A
= +25°C, REFADJ = AGND
1.23
90
V
ppm/°C
V
REFIO
V
Used to disable the internal reference
AV - 0.1
CC
REFADJ
f
f
170
MHz
MHz
%
SAMPLE
SAMPLE
20
Set by clock-management circuit
Figures 4, 11
40 to 60
620
Aperture Delay
t
ps
AD
Aperture Jitter
t
Figure 11
0.2
ps
RMS
AJ
2
_______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
SAMPLE
CC
CC
internal reference, digital output pins differential R = 100Ω 1%, T = T
to T
, unless otherwise noted. Typical values are at
L
A
MIN
MAX
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUTS (CLKP, CLKN)
Differential Clock Input Amplitude
(Note 3)
200
500
mV
P-P
Clock Input Common-Mode
Voltage Range
Internally self-biased
1.15 0.25
V
Clock Differential Input
Resistance
11
25%
R
C
kΩ
CLK
Clock Differential Input
Capacitance
5
pF
CLK
DYNAMIC CHARACTERISTICS (at -1dBFS)
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
f
IN
= 10MHz, T ≥ +25°C
64.5
64.5
66.2
65.8
65
A
= 65MHz, T ≥ +25°C
A
Signal-to-Noise
SNR
dB
dB
Ratio
= 200MHz
= 250MHz
64.5
65.9
65.2
63.9
63.5
83
= 10MHz, T ≥ +25°C
64
A
= 65MHz, T ≥ +25°C
63.5
A
Signal-to-Noise
SINAD
and Distortion
= 200MHz
= 250MHz
= 10MHz, T ≥ +25°C
73
69
A
= 65MHz, T ≥ +25°C
76.5
70.7
72.9
-85
Spurious-Free
SFDR
A
dBc
dBc
Dynamic Range
= 200MHz
= 250MHz
= 10MHz, T ≥ +25°C
-73
-69
A
= 65MHz, T ≥ +25°C
-76.5
-70.7
-72.9
A
Worst Harmonics
(HD2 or HD3)
= 200MHz
= 250MHz
Two-Tone Intermodulation
TTIMD
f
f
= 99MHz at -7dBFS,
= 101MHz at -7dBFS
IN1
IN2
-78
dBc
dB
Distortion
f
= 28.8MHz 1MHz,
NOTCH
Noise Power Ratio
NPR
59.5
noise BW = 50MHz, A = -9.1dBFS
IN
LVDS DIGITAL OUTPUTS (D0P/N–D11P/N, ORP/N)
Differential Output Voltage
Output Offset Voltage
|V
|
R = 100Ω 1%
250
400
mV
V
OD
L
OV
R = 100Ω 1%
L
1.125
1.310
OS
_______________________________________________________________________________________
3
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
= OV
= 1.8V, AGND = OGND = 0, f
= 170MHz, differential sine-wave clock input drive, 0.1µF capacitor on REFIO,
SAMPLE
CC
CC
internal reference, digital output pins differential R = 100Ω 1%, T = T
to T
, unless otherwise noted. Typical values are at
L
A
MIN
MAX
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVCMOS DIGITAL INPUTS (CLKDIV, T/B)
Digital Input Voltage Low
V
0.2 x AV
V
V
IL
CC
Digital Input Voltage High
TIMING CHARACTERISTICS
CLK-to-Data Propagation Delay
CLK-to-DCLK Propagation Delay
DCLK-to-Data Propagation Delay
LVDS Output Rise Time
V
0.8 x AV
IH
CC
t
Figure 4
Figure 4
1.75
4.95
3.2
ns
ns
ns
ps
ps
PDL
t
CPDL
t
- t
Figure 4 (Note 3)
2.8
3.6
PDL CPDL
t
20% to 80%, C = 5pF
460
460
RISE
FALL
L
LVDS Output Fall Time
t
20% to 80%, C = 5pF
L
Clock
cycles
Output Data Pipeline Delay
t
Figure 4
11
LATENCY
POWER REQUIREMENTS
Analog Supply Voltage Range
Digital Supply Voltage Range
Analog Supply Current
AV
1.70
1.70
1.80
1.80
375
63
1.90
1.90
425
75
V
V
CC
OV
CC
I
f
f
f
= 65MHz
= 65MHz
= 65MHz
mA
AVCC
IN
IN
IN
Digital Supply Current
I
mA
OVCC
Analog Power Dissipation
P
788
1.8
900
mW
mV/V
%FS/V
DISS
Offset
Gain
Power-Supply Rejection Ratio
(Note 4)
PSRR
1.5
Note 1: ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: Static linearity and offset parameters are computed from a best-fit straight line through the code transition points. The full-
scale range (FSR) is defined as 4095 x slope of the line.
Note 3: Parameter guaranteed by design and characterization: T = T
to T
.
MAX
A
MIN
Note 4: PSRR is measured with both analog and digital supplies connected to the same potential.
4
_______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Typical Operating Characteristics
(AV = OV = 1.8V, AGND = OGND = 0, f
= 170MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
f
= 170MHz
SAMPLE
f
f
= 170MHz
f
f
= 170MHz
SAMPLE
SAMPLE
f
= 200.11108MHz
= 12.47192MHz
= 65.09888MHz
IN
IN
IN
A
IN
A
A
= -1.025dBFS
= -1.001dBFS
= -1.099dBFS
IN
IN
SNR = 65dB
SNR = 66.7dB
SINAD = 66.4dB
SFDR = 83.8dBc
HD2 = -83.8dBc
HD3 = -84dBc
SNR = 66.5dB
SINAD = 65.7dB
SFDR = 76dBc
HD2 = -77.7dBc
HD3 = -76dBc
SINAD = 63.9dB
SFDR = 70.7dBc
HD2 = -74.8dBc
HD3 = -70.7dBc
HD3
HD2
HD3
HD2
HD3
HD2
0
10 20 30
0
10 20 30
0
10 20 30
ANALOG INPUT FREQUENCY (MHz)
50
80
50
80
50
80
40
60 70
40
60 70
40
60 70
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(8192-POINT DATA RECORD)
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(f
= 170MHz, A = -1dBFS)
SAMPLE
IN
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
70
65
60
55
50
45
f
f
= 170MHz
SAMPLE
f
f
f
= 170MHz
SAMPLE
SNR
= 250.04038MHz
IN
A
= 99.25659MHz
= 101.08276MHz
IN1
IN2
A
= -1.040dBFS
IN
f
SNR = 64.5dB
IN2
= A = -6.974dBFS
IN1
IN2
SINAD = 63.5dB
SFDR = 72.9dBc
HD2 = -77.4dBc
HD3 = -72.9dBc
IMD = -78dBc
f
IN1
SINAD
HD3
2f
- f
HD2
f
- f
IN1
IN2
IN1 IN2
f
+ f
IN1 IN2
3f - 2f
IN2
IN1
0
10 20 30
0
10 20 30
50
80
50
80
0
50
100
150
200
250
300
40
60 70
40
60 70
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
f
(MHz)
IN
SFDR vs. ANALOG INPUT FREQUENCY
HD2/HD3 vs. ANALOG INPUT FREQUENCY
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(f
= 170MHz, A = -1dBFS
(f
= 170MHz, A = -1dBFS)
(f
= 170MHz, f = 65.098877MHz)
SAMPLE
IN
SAMPLE
IN
SAMPLE
IN
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
95
90
85
80
75
70
65
60
55
50
45
40
70
60
50
40
30
20
10
SNR
HD3
SINAD
HD2
0
50
100
150
200
250
300
0
50
100
150
200
250
300
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
f
(MHz)
f
(MHz)
IN
IN
_______________________________________________________________________________________
5
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Typical Operating Characteristics (continued)
(AV = OV = 1.8V, AGND = OGND = 0, f
= 170MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
SFDR vs. ANALOG INPUT AMPLITUDE
= 170MHz, f = 65.098877MHz)
SNR/SINAD vs. SAMPLE FREQUENCY
(f = 65MHz, A = -1dBFS)
HD2/HD3 vs. ANALOG INPUT AMPLITUDE
(f
(f
= 170MHz, f = 65.098877MHz)
SAMPLE
IN
IN
IN
SAMPLE
IN
90
80
70
60
50
40
30
-30
-40
-50
-60
-70
-80
-90
-100
75
70
65
60
55
50
45
40
SNR
SINAD
HD2
HD3
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT AMPLITUDE (dBFS)
0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
0
0
20 40 60 80 100 120 140 160 180
(MHz)
ANALOG INPUT AMPLITUDE (dBFS)
f
SAMPLE
HD2/HD3 vs. SAMPLE FREQUENCY
(f = 65MHz,A = -1dBFS)
SFDR vs. SAMPLE FREQUENCY
(f = 65MHz, A = -1dBFS)
TOTAL POWER DISSIPATION vs. SAMPLE
FREQUENCY (f = 65MHz, A = -1dBFS)
IN
IN
IN
IN
IN
IN
-60
-65
85
80
75
70
65
60
55
830
810
790
770
750
730
710
-70
HD3
-75
-80
HD2
-85
-90
-95
-100
-105
-110
0
20 40 60 80 100 120 140 160 180
(MHz)
0
20 40 60 80 100 120 140 160 180
(MHz)
20 40 60 80 100 120 140 160 180
(MHz)
f
f
SAMPLE
f
SAMPLE
SAMPLE
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
GAIN BANDWIDTH PLOT
= 170MHz, A = -1dBFS)
(f
SAMPLE
IN
2.0
1.6
1.0
0.8
1
0
f
= 12.5MHz
f = 12.5MHz
IN
IN
1.2
0.6
-1
-2
-3
-4
-5
-6
-7
0.8
0.4
0.4
0.2
0
0
-0.4
-0.8
-1.2
-1.6
-2.0
-0.2
-0.4
-0.6
-0.8
-1.0
DIFFERENTIAL TRANSFORMER COUPLING
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL OUTPUT CODE
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Typical Operating Characteristics (continued)
(AV = OV = 1.8V, AGND = OGND = 0, f
= 170MHz, A = -1dBFS; see each TOC for detailed information on test condi-
IN
CC
CC
SAMPLE
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential R = 100Ω, T = +25°C.)
L
A
SNR/SINAD vs. TEMPERATURE
SFDR vs. TEMPERATURE
HD2/HD3 vs. TEMPERATURE
(f = 65MHz, A = -1dBFS)
(f = 65MHz, A = -1dBFS)
(f = 65MHz, A = -1dBFS)
IN
IN
IN
IN
IN
IN
70
69
68
67
66
65
64
63
62
61
60
-60
-64
-68
-72
-76
-80
-84
-88
-92
-96
-100
80
78
76
74
72
70
68
66
64
HD3
SNR
HD2
SINAD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SNR/SINAD, SFDR vs. SUPPLY VOLTAGE
(f = 65.098877MHz, A = -1dBFS)
INTERNAL REFERENCE
vs. SUPPLY VOLTAGE
PROPAGATION DELAY TIMES
vs. TEMPERATURE
IN
IN
80
76
72
68
64
60
1.2550
1.2530
1.2510
1.2490
1.2470
1.2450
6
5
4
3
2
1
0
AV = OV
MEASURED AT THE REFIO PIN
CC
CC
SFDR
REFADJ = AV = OV
CC
CC
t
CPDL
SNR
t
PDL
35
SINAD
1.70
1.75
1.80
1.85
1.90
1.70
1.75
1.80
1.85
1.90
-40
-15
10
60
85
VOLTAGE SUPPLY (V)
VOLTAGE SUPPLY (V)
TEMPERATURE (°C)
NOISE-POWER RATIO PLOT
(WIDE NOISE BANDWIDTH: 50MHz)
NOISE-POWER RATIO vs. ANALOG INPUT
POWER (f = 28.2MHz 1MHz)
NOTCH
0
70
65
60
55
50
45
40
35
30
25
20
f
= 28.8MHz
NOTCH
NPR = 59.5dB
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
5
10 15 20 25 30 35 40 45 50
ANALOG INPUT FREQUENCY (MHz)
-40 -35 -30 -25 -20 -15 -10 -5
ANALOG INPUT POWER (dBFS)
0
_______________________________________________________________________________________
7
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Pin Description
PIN
NAME
AV
FUNCTION
1, 6, 11–14, 20,
25, 62, 63, 65
Analog Supply Voltage. Bypass each pin with a parallel combination of 0.1µF and 0.22µF
capacitors for best decoupling results.
CC
2, 5, 7, 10, 15, 16,
18, 19, 21, 24,
64, 66, 67
AGND
REFIO
Analog Converter Ground
Reference Input/Output. With REFADJ pulled high, this I/O port allows an external reference
source to be connected to the MAX1213. With REFADJ pulled low, the internal 1.23V bandgap
reference is active.
3
4
Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim
potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases
FSR). If REFADJ is connected to AV , the internal reference can be overdriven with an
CC
REFADJ
external source connected to REFIO. If REFADJ is connected to AGND, the internal reference is
used to determine the FSR of the data converter.
8
9
INP
INN
Positive Analog Input Terminal. Internally self-biased to 1.365V.
Negative Analog Input Terminal. Internally self-biased to 1.365V.
Clock Divider Input. This LVCMOS-compatible input controls which speed the converter’s
digital outputs are updated with. CLKDIV has an internal pulldown resistor.
CLKDIV = 0: ADC updates digital outputs at one-half the input clock rate.
CLKDIV = 1: ADC updates digital outputs at input clock rate.
17
CLKDIV
CLKP
True Clock Input. This input ideally requires an LVPECL-compatible input level to maintain the
converter’s excellent performance. Internally self-biased to 1.15V.
22
23
Complementary Clock Input. This input ideally requires an LVPECL-compatible input level to
maintain the converter’s excellent performance. Internally self-biased to 1.15V.
CLKN
26, 45, 61
OGND
Digital Converter Ground. Ground connection for digital circuitry and output drivers.
27, 28, 41, 44, 60
OV
Digital Supply Voltage. Bypass with a 0.1µF capacitor for best decoupling results.
Complementary Output Bit 0 (LSB)
True Output Bit 0 (LSB)
CC
29
30
31
32
33
34
35
36
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
Complementary Output Bit 1
True Output Bit 1
Complementary Output Bit 2
True Output Bit 2
Complementary Output Bit 3
True Output Bit 3
8
_______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Pin Description (continued)
PIN
37
NAME
D4N
D4P
FUNCTION
Complementary Output Bit 4
38
True Output Bit 4
39
D5N
D5P
Complementary Output Bit 5
True Output Bit 5
40
Complementary Clock Output. This output provides an LVDS-compatible output level and can
be used to synchronize external devices to the converter clock.
42
43
DCLKN
DCLKP
True Clock Output. This output provides an LVDS-compatible output level and can be used to
synchronize external devices to the converter clock.
46
47
48
49
50
51
52
53
54
55
56
57
D6N
D6P
Complementary Output Bit 6
True Output Bit 6
D7N
D7P
Complementary Output Bit 7
True Output Bit 7
D8N
D8P
Complementary Output Bit 8
True Output Bit 8
D9N
D9P
Complementary Output Bit 9
True Output Bit 9
D10N
D10P
D11N
D11P
Complementary Output Bit 10
True Output Bit 10
Complementary Output Bit 11 (MSB)
True Output Bit 11 (MSB)
Complementary Output for Out-of-Range Control Bit. If an out-of-range condition is detected,
bit ORN flags this condition by transitioning low.
58
59
ORN
ORP
True Output for Out-of-Range Control Bit. If an out-of-range condition is detected, bit ORP flags
this condition by transitioning high.
Two’s Complement or Binary Output Format Selection. This LVCMOS-compatible input controls
the digital output format of the MAX1213. T/B has an internal pulldown resistor.
T/B = 0: Two’s complement output format.
68
T/B
T/B = 1: Binary output format.
Exposed Paddle. The exposed paddle is located on the backside of the chip and must be
connected to analog group for optimum performance.
—
EP
_______________________________________________________________________________________
9
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
CLKDIV
DCLKP
DCLKN
CLKP
CLOCK-
DIVIDER
CONTROL
CLOCK
MANAGEMENT
CLKN
INP
INPUT
BUFFER
12-BIT PIPELINE
QUANTIZER
CORE
LVDS
DATA PORT
T/H
D0P/N–D11P/N
INN
12
2.2kΩ
2.2kΩ
ORP
ORN
COMMON-MODE
BUFFER
REFERENCE
MAX1213
REFIO REFADJ
Figure 1. Simplified MAX1213 Block Diagram
Detailed Description—
Theory of Operation
AV
CC
The MAX1213 uses a fully differential pipelined archi-
tecture that allows for high-speed conversion, opti-
mized accuracy, and linearity while minimizing power
consumption and die size.
INP
INN
2.2kΩ
2.2kΩ
Both positive (INP) and negative/complementary ana-
log input terminals (INN) are centered around a com-
mon-mode voltage of 1.365V, and accept a differential
TO COMMON MODE
TO COMMON MODE
AGND
analog input voltage swing of V / 4 each, resulting in
FS
a typical differential full-scale signal swing of 1.454V
.
P-P
Inputs INP and INN are buffered prior to entering each
T/H stage and are sampled when the differential sam-
pling clock signal transitions high.
COMMON-MODE
VOLTAGE (1.365V)
INP
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. The result is a 12-bit parallel
digital output word in user-selectable two’s complement
or offset binary output formats with LVDS-compatible
output levels. See Figure 1 for a more detailed view of
the MAX1213 architecture.
COMMON-MODE
VOLTAGE (1.365V)
INN
Figure 2. Simplified Analog Input Architecture and Allowable
Input Voltage Range
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1213. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for
enhanced AC performance as the signals are progress-
ing through the analog stages. The MAX1213 analog
inputs are self-biased at a common-mode voltage of
1.365V and allow a differential input voltage swing of
through 2kΩ resistors, resulting in a typical differential
input resistance of 4kΩ. It is recommended to drive the
analog inputs of the MAX1213 in AC-coupled configu-
ration to achieve best dynamic performance. See the
Transformer-Coupled, Differential Analog Input Drive
section for a detailed discussion of this configuration.
1.454V
(Figure 2). Both inputs are self-biased
P-P
10 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
The MAX1213 also features an internal clock-manage-
ment circuit (duty-cycle equalizer) that ensures that the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of >20MHz to work appropriately and accord-
ing to data sheet specifications.
On-Chip Reference Circuit
The MAX1213 features an internal 1.23V bandgap refer-
ence circuit (Figure 3), which in combination with an inter-
nal reference-scaling amplifier determines the FSR of the
MAX1213. Bypass REFIO with a 0.1µF capacitor to
AGND. To compensate for gain errors or increase the
ADC’s FSR, the voltage of this bandgap reference can be
indirectly adjusted by adding an external resistor (e.g.,
100kΩ trim potentiometer) between REFADJ and AGND
or REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1213 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
4.95ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
To disable the internal reference, connect REFADJ to
AV . In this configuration, an external, stable refer-
CC
ence must be applied to REFIO to set the converter’s
full scale. To enable the internal reference, connect
REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1213
with an LVDS- or LVPECL-compatible clock to achieve
the best dynamic performance. The clock signal source
must be a high-quality, low-phase noise with fast edge
rates to avoid any degradation in the noise performance
of the ADC. The clock inputs (CLKP, CLKN) are internal-
ly biased to 1.15V, accept a typical differential signal
Divide-by-2 Clock Control (CLKDIV)
The MAX1213 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
swing of 0.5V , and are usually driven in AC-coupled
P-P
configuration. See the Differential, AC-Coupled PECL-
Compatible Clock Input section for more circuit details
on how to drive CLKP and CLKN appropriately. Although
not recommended, the clock inputs also accept a single-
ended input signal.
to OV
disables the divide-by-2 mode.
CC
REFERENCE
SCALING AMPLIFIER
REFT
ADC FULL SCALE = REFT-REFB
G
REFB
REFERENCE
BUFFER
REFIO
1V
0.1µF
REFADJ
CONTROL LINE TO
DISABLE REFERENCE BUFFER
100Ω*
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY
MAX1213
AV
CC
AV /2
CC
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Figure 3. Simplified Reference Architecture
______________________________________________________________________________________ 11
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
mat. All LVDS outputs provide a typical voltage swing
System Timing Requirements
Figure 4 depicts the relationship between the clock
input and output, analog input, sampling event, and
data output. The MAX1213 samples on the rising
(falling) edge of CLKP (CLKN). Output data is valid on
the next rising (falling) edge of the DCLKP (DCLKN)
clock, but has an internal latency of 11 clock cycles.
of 0.325V around a common-mode voltage of roughly
1.15V, and must be differentially terminated at the far
end of each transmission line pair (true and comple-
mentary) with 100Ω. The LVDS outputs are powered
from a separate power supply, which can be operated
between 1.7V and 1.9V.
The MAX1213 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out-of-range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Digital Outputs (D0P/N–D11P/N, DCLKP/N,
ORP/N) and Control Input T/B
Digital outputs D0P/N–D11P/N, DCLKP/N, and ORP/N
are LVDS compatible, and data on D0P/N–D11P/N is
presented in either binary or two’s-complement format
(Table 1). The T/B control line is an LVCMOS-compati-
ble input, which allows the user to select the desired
output format. Pulling T/B low outputs data in two’s
complement and pulling it high presents data in offset
binary format on the 12-bit parallel bus. T/B has an
internal pulldown resistor and may be left unconnected
in applications using only two’s complement output for-
Note: Although a differential LVDS output architecture
reduces single-ended transients to the supply and
ground planes, capacitive loading on the digital out-
puts should still be kept as low as possible. Using
LVDS buffers on the digital outputs of the ADC when
driving larger loads may improve overall performance
and reduce system-timing constraints.
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
SAMPLING EVENT
INN
INP
t
t
CL
CH
t
AD
CLKN
CLKP
N + 9
N
N + 8
N + 1
t
CPDL
t
LATENCY
DCLKP
DCLKN
N + 1
N - 8
N
N - 7
t
- t
CPDL PDL
t
PDL
D0P/N–
D11P/N
ORP/N
N - 8
N
N - 7
N - 1
N + 1
t
- t ~ 0.4 x t
WITH t
= 1/f
PDL PDL
SAMPLE
SAMPLE SAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
12 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Table 1. MAX1213 Digital Output Coding
INP ANALOG
INPUT VOLTAGE
LEVEL
INN ANALOG
INPUT VOLTAGE
LEVEL
OUT-OF-RANGE
ORP (ORN)
BINARY DIGITAL OUTPUT
CODE (D11P/N–D0P/N)
TWO’S COMPLEMENT DIGITAL
OUTPUT CODE (D11P/N–D0P/N)
1111 1111 1111
(exceeds +FS, OR set)
0111 1111 1111
(exceeds +FS, OR set)
> V
+ V / 4
< V
- V / 4
1 (0)
0 (1)
0 (1)
0 (1)
1 (0)
CM
FS
CM
FS
V
+ V / 4
V
- V / 4
1111 1111 1111 (+FS)
0111 1111 1111 (+FS)
CM
FS
CM
CM
FS
CM
1000 0000 0000 or
0111 1111 1111 (FS/2)
0000 0000 0000 or
1111 1111 1111 (FS/2)
V
V
V
- V / 4
V
+ V / 4
0000 0000 0000 (-FS)
1000 0000 0000 (-FS)
CM
FS
CM
FS
00 0000 0000
(exceeds -FS, OR set)
10 0000 0000
(exceeds -FS, OR set)
< V
+ V / 4
> V
- V / 4
CM FS
CM
FS
OV
CC
REFERENCE
SCALING
AMPLIFIER
REFT
ADC FULL SCALE = REFT-REFB
G
REFB
REFERENCE
BUFFER
1V
V
V
ON
OP
REFIO
0.1µF
13kΩ TO
1MΩ
REFADJ
2.2kΩ
2.2kΩ
CONTROL LINE
TO DISABLE
REFERENCE BUFFER
13kΩ TO
1MΩ
MAX1213
OGND
AV /2
CC
AV
CC
Figure 5. Simplified LVDS Output Architecture
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
Applications Information
FSR Adjustments Using the Internal
Bandgap Reference
Figure 6a: Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
FS VOLTAGE vs. FS ADJUST RESISTOR
The MAX1213 supports a full-scale adjustment range of
10% ( 5%). To decrease the full-scale signal range, an
external resistor value ranging from 13kΩ to 1MΩ may
be added between REFADJ and AGND. A similar
approach can be taken to increase the ADC’s full-scale
range (FSR). Adding a variable resistor, potentiometer,
or predetermined resistor value between REFADJ and
REFIO increases the FSR of the data converter. Figure
6a shows the two possible configurations and their
impact on the overall full-scale range adjustment of the
MAX1213. Do not use resistor values of less than 13kΩ
to avoid instability of the internal gain regulation loop
for the bandgap reference. See Figure 6b for the
results of the adjustment range for a selection of resis-
tors used to trim the full-scale range of the MAX1213.
1.57
1.55
1.53
RESISTOR VALUE APPLIED BETWEEN
1.51
1.49
1.47
1.45
1.43
1.41
1.39
1.37
REFADJ AND REFIO INCREASES V
FS
RESISTOR VALUE APPLIED BETWEEN
REFADJ AND AGND DECREASES V
FS
0
125 250 375 500 625 750 875 1000
FS ADJUST RESISTOR (kΩ)
Figure 6b: FS Adjustment Range vs. FS Adjustment Resistor
______________________________________________________________________________________ 13
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
commended to drive the ADC inputs in single-ended
Differential, AC-Coupled,
LVPECL-Compatible Clock Input
configuration. In differential input mode, even-order
harmonics are usually lower since INP and INN are bal-
anced, and each of the ADC inputs only requires half
the signal swing compared to a single-ended configu-
ration. Wideband RF transformers provide an excellent
solution to convert a single-ended signal to a fully dif-
ferential signal, required by the MAX1213 to reach its
optimum dynamic performance.
The MAX1213 dynamic performance depends on the
use of a very clean clock source. The phase noise floor
of the clock source has a negative impact on the SNR
performance. Spurious signals on the clock signal
source also affect the ADC’s dynamic range. The pre-
ferred method of clocking the MAX1213 is differentially
with LVDS- or LVPECL-compatible input levels. The fast
data transition rates of these logic families minimize the
clock-input circuitry’s transition uncertainty, thereby
improving the SNR performance. To accomplish this, a
50Ω reverse-terminated clock signal source with low
phase noise is AC-coupled into a fast differential
receiver such as the MC100LVEL16D (Figure 7). The
receiver produces the necessary LVPECL output levels
to drive the clock inputs of the data converter.
A secondary-side termination of a 1:1 transformer (e.g.,
Mini-Circuit’s ADT1-1WT) into two separate 24.9Ω 1%
resistors (use tight resistor tolerances to minimize
effects of imbalance; 0.5% would be an ideal choice)
placed between top/bottom and center tap of the trans-
former is recommended to maximize the ADC’s dynam-
ic range. This configuration optimizes THD and SFDR
performance of the ADC by reducing the effects of
transformer parasitics. However, the source imped-
ance combined with the shunt capacitance provided
by a PC board and the ADC’s parasitic capacitance
limit the ADC’s full-power input bandwidth to approxi-
mately 600MHz.
Transformer-Coupled, Differential Analog
Input Drive
In general, the MAX1213 provides the best SFDR and
THD with fully differential input signals and it is not re-
V
CLK
0.1µF
SINGLE-ENDED
INPUT TERMINAL
8
0.1µF
0.1µF
2
7
6
150Ω
0.1µF
50Ω
MC100LVEL16D
3
150Ω
510Ω
510Ω
AV
CC
OV
CC
4
5
0.01µF
CLKN CLKP
INP
INN
D0P/N–D11P/N
VGND
MAX1213
12
AGND
OGND
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
14 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
To further enhance THD and SFDR performance at
Grounding, Bypassing, and
Board Layout Considerations
high-input frequencies (>100MHz), a second trans-
former (Figure 8) should be placed in series with the
single-ended-to-differential conversion transformer.
This transformer reduces the increase of even-order
harmonics at high frequencies.
The MAX1213 requires board layout design techniques
suitable for high-speed data converters. This ADC pro-
vides separate analog and digital power supplies. The
analog and digital supply voltage pins accept input
voltage ranges of 1.7V to 1.9V. Although both supply
types can be combined and supplied from one source,
it is recommended to use separate sources to cut down
on performance degradation caused by digital switch-
ing currents, which can couple into the analog supply
Single-Ended, AC-Coupled Analog Inputs
Although not recommended, the MAX1213 can be used
in single-ended mode (Figure 9). Analog signals can be
AC-coupled to the positive input INP through a 0.1µF
capacitor and terminated with a 49.9Ω resistor to AGND.
The negative input should be reverse terminated with
24.9Ω resistors and AC-grounded with a 0.1µF capacitor.
network. Isolate analog and digital supplies (AV
and
CC
OV ) where they enter the PC board with separate
CC
networks of ferrite beads and capacitors to their corre-
sponding grounds (AGND, OGND).
AV
CC
OV
CC
10Ω
SINGLE-ENDED
INPUT TERMINAL
INP
INN
0.1µF
ADT1-1WT
ADT1-1WT
D0P/N–D11P/N
25Ω
MAX1213
25Ω
12
10Ω
0.1µF
AGND
OGND
Figure 8. Analog Input Configuration with Back-to-Back Transformers and Secondary-Side Termination
AV
CC
OV
CC
SINGLE-ENDED
INPUT TERMINAL
0.1µF
0.1µF
INP
INN
D0P/N–D11P/N
50Ω
MAX1213
12
25Ω
AGND
OGND
Figure 9. Single-Ended AC-Coupled Analog Input Configuration
______________________________________________________________________________________ 15
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
To achieve optimum performance, provide each supply
with a separate network of a 47µF tantalum capacitor
and parallel combinations of 10µF and 1µF ceramic
capacitors. Additionally, the ADC requires each supply
pin to be bypassed with separate 0.1µF ceramic
capacitors (Figure 10). Locate these capacitors directly
at the ADC supply pins or as close as possible to the
MAX1213. Choose surface-mount capacitors, whose
preferred location should be on the same side as the
converter to save space and minimize the inductance.
If close placement on the same side is not possible,
these bypassing capacitors may be routed through
vias to the bottom side of the PC board.
input, segregate the digital output bus carefully from the
analog input circuitry. To further minimize the effects of
digital noise coupling, ground return vias can be posi-
tioned throughout the layout to divert digital switching
currents away from the sensitive analog sections of the
ADC. This approach does not require split ground
planes, but can be accomplished by placing substantial
ground connections between the analog front end and
the digital outputs.
The MAX1213 is packaged in a 68-pin QFN-EP pack-
age (package code: G6800-4), providing greater
design flexibility, increased thermal dissipation, and
optimized AC performance of the ADC. The exposed
paddle (EP) must be soldered down to AGND.
Multilayer boards with separated ground and power
planes produce the highest level of signal integrity.
Consider the use of a split ground plane arranged to
match the physical location of analog and digital
ground on the ADC’s package. The two ground planes
should be joined at a single point such that the noisy
digital ground currents do not interfere with the analog
ground plane. The dynamic currents that may need to
travel long distances before they are recombined at a
common-source ground, resulting in large and undesir-
able ground loops, are a major concern with this
approach. Ground loops can degrade the input noise
by coupling back to the analog front end of the convert-
er, resulting in increased spurious activity, leading to
decreased noise performance.
In this package, the data converter die is attached to
an EP lead frame with the back of this frame exposed
at the package bottom surface, facing the PC board
side of the package. This allows a solid attachment of
the package to the board with standard infrared (IR)
flow soldering techniques.
Thermal efficiency is one of the factors for selecting a
package with an exposed pad for the MAX1213. The
exposed pad improves thermal and ensures a solid
ground connection between the DAC and the PC
board’s analog ground layer.
Considerable care must be taken when routing the digi-
tal output traces for a high-speed, high-resolution data
converter. It is recommended running the LVDS output
traces as differential lines with 100Ω matched imped-
ance from the ADC to the LVDS load device.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy, digital systems ground. To minimize the
coupling of the digital output signals from the analog
BYPASSING-ADC LEVEL
BYPASSING-BOARD LEVEL
AV
CC
OV
AV
CC
CC
0.1µF
0.1µF
ANALOG POWER-
SUPPLY SOURCE
10µF
47µF
1µF
AGND
OGND
D0P/N–D11P/N
OV
CC
MAX1213
12
DIGITAL/OUTPUT
DRIVER POWER-
SUPPLY SOURCE
10µF
47µF
1µF
NOTE: EACH POWER-SUPPLY PIN (ANALOG
AND DIGITAL) SHOULD BE DECOUPLED WITH
AN INDIVIDUAL 0.1µF CAPACITOR AS CLOSE
AS POSSIBLE TO THE ADC.
AGND
OGND
Figure 10. Grounding, Bypassing, and Decoupling Recommendations for MAX1213
16 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
tion error only and results directly from the ADC’s reso-
lution (N bits):
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. However, the
static linearity parameters for the MAX1213 are mea-
sured using the histogram method with an input fre-
quency of 10MHz.
SNR
= 6.02 x N + 1.76
[max]
In reality, other noise sources such as thermal noise,
clock jitter, signal phase noise, and transfer function
nonlinearities are also contributing to the SNR calcula-
tion and should be considered when determining the
signal-to-noise ratio in ADC.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to all spectral components excluding the fundamen-
tal and the DC offset. In the case of the MAX1213,
SINAD is computed from a curve fit.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1LSB. A DNL
error specification of less than 1LSB guarantees no
missing codes and a monotonic transfer function. The
MAX1213’s DNL specification is measured with the his-
togram method based on a 10MHz input tone.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of RMS amplitude of the carrier fre-
quency (maximum signal component) to the RMS value
of the next-largest noise or harmonic distortion compo-
nent. SFDR is usually measured in dBc with respect to
the carrier frequency amplitude or in dBFS with respect
to the ADC’s full-scale range.
Dynamic Parameter Definitions
Aperture Jitter
Figure 11 depicts the aperture jitter (t ), which is the
AJ
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation
products to the RMS sum of the two fundamental input
tones. This is expressed as:
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 11).
2
2
2
2
V
+ V
+......+ V
+ V
IM1
IM2
IM3 IMn
IMD = 20 × log
2
2
V
+ V
2
1
CLKN
CLKP
The fundamental input tone amplitudes (V and V ) are at
1
2
-7dBFS. The intermodulation products are the amplitudes
of the output spectrum at the following frequencies:
ANALOG
INPUT
• Second-order intermodulation products: f
+ f
,
,
,
,
IN1
IN2
t
AD
f
- f
IN2 IN1
t
AJ
• Third-order intermodulation products: 2 x f
- f
IN1
IN2
SAMPLED
DATA (T/H)
2 x f
- f , 2 x f
IN2 IN1
+ f , 2 x f
+ f
IN2 IN1
IN1
IN2
• Fourth-order intermodulation products: 3 x f
- f
IN1 IN2
3 x f
- f , 3 x f
IN2 IN1
+ f , 3 x f
+ f
IN2 IN1
IN1
IN2
HOLD
TRACK
TRACK
T/H
• Fifth-order intermodulation products: 3 x f
- 2 x f
IN1 IN2
+ 2 x f
IN1
3 x f -2 x f , 3 x f +2 x f , 3 x f
IN2
IN2
IN1
IN1
IN2
Figure11. Aperture Jitter/Delay Specifications
Full-Power Bandwidth
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
A large -1dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. The -3dB-point is defined as
full-power input bandwidth frequency of the ADC.
______________________________________________________________________________________ 17
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Noise Power Ratio (NPR)
NPR is commonly used to characterize the return path of
cable systems where the signals are typically individual
Pin Configuration
TOP VIEW
quadrature amplitude-modulated (QAM) carriers with a
frequency spectrum similar to noise. Numerous such
carriers are operated in a continuous spectrum, generat-
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
ing a noise-like signal, which covers a relatively broad
bandwidth. To test the MAX1213 for NPR, a “noise-like”
signal is passed through a high-order bandpass filter to
produce an approximately square spectral pedestal of
noise with about the same bandwidth as the signals
being simulated. Following the bandpass filter, the signal
is passed through a narrow band-reject filter to produce
a deep notch at the center of the noise pedestal. Finally,
this signal is applied to the MAX1213 and its digitized
results analyzed. The RMS noise power of the signal
inside the notch is compared with the RMS noise level
outside the notch using an FFT. Note that the NPR test
requires sufficiently long data records to guarantee a
suitable number of samples inside the notch. NPR for the
MAX1213 was determined for 50MHz noise bandwidth
signals, simulating a typical cable signal environment
(see the Typical Operating Characteristics for test details
and results) with a notch frequency of 28.8MHz.
AV
1
2
3
4
5
6
7
8
9
51 D8P
50 D8N
49 D7P
48 D7N
47 D6P
46 D6N
45 OGND
CC
AGND
REFIO
EP
REFADJ
AGND
AV
CC
AGND
INP
44 OV
CC
INN
43 DCLKP
42 DCLKN
MAX1213
AGND 10
AV
CC
AV
CC
AV
CC
AV
CC
11
12
13
14
41 OV
CC
40 D5P
39 D5N
38 D4P
37 D4N
36 D3P
35 D3N
AGND 15
AGND 16
CLKDIV 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Pin-Compatible Lower
Speed/Resolution Versions
QFN
Applications that require lower resolution and/or higher
speed can refer to other family members of the
MAX1213. Adjusting an application to a lower resolution
has been simplified by maintaining an identical pinout
for all members of this high-speed family. See the
Pin-Compatible Versions table for a selection of different
resolution and speed grades.
18 ______________________________________________________________________________________
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
For the MAX1213, the package code is G6800-4.
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
______________________________________________________________________________________ 19
1.8V, 12-Bit, 170Msps ADC for
Broadband Applications
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
21-0122
C
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 20
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX1213EGK-TD
ADC, Proprietary Method, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, 10 X 10 MM, 0.90 MM HEIGHT, MO-220, QFN-68
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MAX1214EGK
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