MAX12528EVKIT [MAXIM]
Low-Voltage and Low-Power Operation;
| 型号： | MAX12528EVKIT |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Voltage and Low-Power Operation |
| 文件： | 总21页 (文件大小：753K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Evaluate: MAX12527/28/29/57/58/59
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
General Description
Features
The
MAX12527/MAX12528/MAX12529/MAX12557/
● Low-Voltage and Low-Power Operation
● On-Board Clock-Shaping Circuitry Option
● On-Board Output Drivers
MAX12558/MAX12559 evaluation kits (EV kits) are fully
assembled and tested circuit boards that contain all the
components necessary to evaluate the performance of
this family of 12-bit and 14-bit, dual analog-to-digital con-
verters (ADCs). These ADCs accept differential analog
input signals. The EV kits generate these signals from
user-provided single-ended input sources. The digital
outputs produced by the ADCs can be easily sampled
with a user-provided high-speed logic analyzer or data-
acquisition system. The EV kits operate from 2.0V and
3.3V power supplies.
● Fully Assembled and Tested
Ordering Information
PART
TEMP RANGE*
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
IC PACKAGE
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
68 TQFN-EP**
MAX12527EVKIT#
MAX12528EVKIT
MAX12529EVKIT
MAX12557EVKIT
MAX12558EVKIT
MAX12559EVKIT
Part Selection Table
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
PART
MAX12559ETK
MAX12558ETK
MAX12557ETK
MAX12529ETK
MAX12528ETK
MAX12527ETK
96
80
65
96
80
65
14
14
14
12
12
12
#Denotes ROHS compliant with exemption.
*EV kit PC board temperature range only.
**EP = Exposed paddle.
Component List
DESIGNATION QTY
DESCRIPTION
Not installed (0603)
DESIGNATION QTY
DESCRIPTION
C1–C4
0
220μF ±20%, 6.3V tantalum
capacitors (C case)
AVX TPSC227M006R0250
C33–C38,
8
C47, C53
C5, C6, C11,
C13, C14, C16,
C17, C28–C32,
C45, C46,
0.1μF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
10μF ±20%, 6.3V X5R ceramic
capacitors (0805)
TDK C2012X5R0J106M
C39, C40, C41,
6
22
C55, C61, C66
C57–C60,
C62–C65
1.0μF ±20%, 10V X5R ceramic
capacitors (0603)
TDK C1608X5R1A105M
C42, C43,
4
5.6pF ±0.5pF, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H5R6D
C44, C56
C7–C10
4
8
4
0.01μF ±5%, 25V C0G ceramic
capacitors (0603)
TDK C1608C0G1E103J
C51, C52
C67
2
1
4.7μF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J475M
C12,
C21–C27
1.0μF ±20%, 6.3V X5R ceramic
capacitor (0402)
TDK C1005X5R0J105M
0.1μF ±20%, 6.3V X5R ceramic
capacitors (0201)
TDK C0603X5R0J104M
C15, C18,
C19, C20
19-3920; Rev 2; 3/21
Evaluate: MAX12527/28/29/57/58/59
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
Component List (continued)
DESIGNATION QTY
DESCRIPTION
DESIGNATION QTY
DESCRIPTION
220Ω ±5% resistor arrays
Panasonic EXB-2HV-221J
Dual Schottky diode (SOT23)
Central Semiconductor
CMPD6263S
Vishay BAS70-04
Diodes Inc. BAS70-04
RA1–RA8
8
4
D1
1
1:1 RF transformers
Mini-Circuits ADT1-1WT
T1–T4
1:2 RF transformer
Coilcraft TTWB-2-B
T5
TP1–TP6
U1
1
6
1
J1, J2, J7
J3, J4, J8
J5, J6
3
3
2
6
SMA PC mount connectors
2-pin headers
Test points
Dual-row, 40-pin headers (2 x 20)
3-pin headers
See the EV Kit Specific
Component List
JU1–JU6
Low-voltage 16-bit registers
(48-pin TSSOP)
Pericom PI74ALVTC16374 or Texas
Instruments SN74ALVCH16374DGGR
EMI filters
Murata NFM41PC155B1E3
L1–L4
4
U2, U3
U4
2
1
R1–R8,
R13–R16,
R21–R32,
0
Not installed (0603)
TinyLogic ULP-A buffer (SC70-5)
Fairchild NC7SV125P5
R37, R40–R45
TinyLogic ULP-A inverter (SC70-6)
Fairchild NC7WV04P6
R9–R12
R17–R20
R33–R36
R38, R39
R46, R47
R48
4
4
0
2
2
1
4
75Ω ±0.5% resistors (0603)
110Ω ±0.5% resistors (0603)
Not installed (0402)
U5
1
6
None
Shunts
MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
PC board
49.9Ω ±1% resistors (0603)
100Ω ±1% resistors (0603)
10kΩ potentiometer
None
1
R49–R52
24.9Ω ±0.5% resistors (0402)
EV Kit Specific Component List
REFERENCE
EV KIT PART NUMBER
DESCRIPTION
DESIGNATOR
MAX12527EVKIT#
MAX12528EVKIT
Maxim MAX12527ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12528ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm
Maxim MAX12529ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12557ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12558ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
Maxim MAX12559ETK (68-pin thin QFN, 10mm x 10mm x 0.8mm)
MAX12529EVKIT
U1
MAX12557EVKIT
MAX12558EVKIT
MAX12559EVKIT
Maxim Integrated
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
Component Suppliers
SUPPLIER
PHONE
FAX
WEBSITE
www.avxcorp.com
www.centralsemi.com
www.coilcraft.com
www.diodes.com
AVX
843-946-0238
631-435-1110
847-639-6400
805-446-4800
888-522-5372
770-436-1300
714-373-7366
800-435-2336
847-803-6100
972-644-5580
843-626-3123
631-435-1824
847-639-1469
805-446-4850
—
Central Semiconductor
Coilcraft
Diodes Inc.
Fairchild
www.fairchildsemi.com
www.murata.com
Murata
770-436-3030
714-737-7323
408-435-1100
847-390-4405
214-480-7800
Panasonic
Pericom
www.panasonic.com
www.pericom.com
www.component.tdk.com
www.ti.com
TDK
Texas Instruments
Note: Indicate that you are using the MAX12527, MAX12528, MAX12529, MAX12557, MAX12558, and MAX12559 when contacting
these component suppliers.
2) Connect the clock signal generator to the input of the
clock bandpass filter.
3) Connect the output of the clock bandpass filter to the
Quick Start
Recommended Equipment
● DC power supplies:
SMA connector labeled J7.
Analog (VDD)
3.3V, 500mA
2.0V, 50mA
2.0V, 100mA
4) Connect the analog input signal generators to the
inputs of the desired analog bandpass filters. For best
results, connect the bandpass filter directly to the
SMA connector and forego any cables in between.
5) Connect the output of the analog bandpass filters to
the SMA connectors labeled J1 and J2. The analog
input signals can be monitored at J3 and J4. Elimi-
nate cables between bandpass filter outputs and
SMA connectors. If cables must be used, they should
be as short as possible. Add a 3dB to 6dB attenua-
tor between bandpass filter and SMA connectors to
control undesired distortion components induced by
the signal generator.
Digital (OVDD)
Buffers (VLOGIC)
● Signal generator with low phase noise and low jitter for
clock input signal (e.g., HP/Agilent 8644B)
● Two signal generators with low phase noise for
analog signal inputs (e.g., HP/Agilent 8644B)
● Logic analyzer or data-acquisition system (e.g., HP/
Agilent 16500C)
● Narrow-band analog bandpass filters (e.g., Allen
Avionics, K&L Microwave) for input signals and clock
signal
6) Connect the logic analyzer to headers J5 and J6 to
collect digitized data from channels A and B. See
the Output Bit Locations section in this document for
header connections.
7) Connect a 3.3V, 500mA power supply to VDD and
connect its ground terminal to the GND pad.
8) Connect a 2.0V, 50mA power supply to OVDD and
● Digital multimeter
Procedure
The EV kit is a fully assembled and tested printed circuit
(PC) board. Follow the steps below to verify board opera-
tion. Do not turn on power supplies or enable signal
generators until all connections are completed.
connect its ground terminal to the GND pad.
9) Connect a 2.0V, 100mA power supply to VLOGIC and
1) Verify that shunts are installed in the following locations:
JU1 (2-3) Independent reference mode
JU2 (2-3) ADC active (not in power-down mode)
JU3 (2-3) Outputs in two’s-complement format
JU4 (1-2) Differential clock input
connect its ground terminal to the GND pad.
10) Short the VCLK pad to the corresponding GND pad.
Note: The VCLK supply is only required when the
data converter is operating in single-ended clock
mode. See the Configuring the EV Kit for Single-
Ended Clock Operation section in this document for
further details.
JU5 (2-3) No clock division
JU6 (2-3) No clock division
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
11) Turn on all the power supplies.
12) Enable the signal generators.
Power Supplies
For best performance, the EV kits require separate
analog, digital, clock, and buffer power-supply sources.
Individual 3.3V and 2.0V power supplies are recommend-
ed to power the analog (VDD) and digital (OVDD) portions
of the converter. A separate 2.0V power supply (VLOGIC)
is used to power the output buffers (U2, U3) of the EV kit.
The on-board clock circuitry (VCLK) is powered by a 3.3V
power supply. The VCLK supply is only required when the
ADC is operating in single-ended clock mode. See the
Configuring the EV Kit for Single-Ended Clock Operation
section for further details.
13) Set the clock signal generator to the desired clock
frequency. See the Part Selection Table for the appro-
priate frequency settings for each EV kit. The ampli-
tude of the generator should be sufficient to produce
a 16dBm signal at the SMA input of the EV kit. Inser-
tion losses due to the series-connected filter (step 2)
and the interconnecting cables decrease the amount
of power seen at the EV kit input. Account for these
losses when setting the signal generator amplitude.
14) Set the analog input signal generators to output the
desired test frequency. The amplitude of the gen-
erator should produce a signal that is no larger than
7.5dBm as measured at the SMA input of the EV kit.
Insertion losses due to the series-connected filter
(step 5) and the interconnecting cables decrease the
amount of power seen at the EV kit input. Account for
these losses when setting the signal generator ampli-
tude. Also account for the attenuation from the 3dB to
6dB attenuator.
Converter Power-Down
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 each feature an active-high
global device power-down pin. Jumper JU2 controls this
feature. See Table 1 for shunt positions.
Table 1. Power-Down Shunt Settings (JU2)
SHUNT
POSITION
PD PIN
DESCRIPTION
15) All signal generators should be phase-locked to each
other.
1-2
OVDD
ADC powered down
ADC active (normal operation)
2-3*
GND
16) Enable the logic analyzer.
*Default configuration: JU2 (2-3).
17) Collect data using the logic analyzer.
Clock
Detailed Description
Additionally, the data converter allows for either differ-
ential or single-ended signals to drive the clock inputs.
The EV kit is a fully assembled and tested circuit board
that contains all the components necessary to evalu-
ate the performance of the MAX12527, MAX12528,
MAX12529, MAX12557, MAX12558, or MAX12559.
The
MAX12527/MAX12528/MAX12529/MAX12557/
MAX12558/MAX12559 EV kits support both methods.
In single-ended operation, the clock signal is applied to
the ADC through a buffer (U5). In differential mode, an on-
board transformer converts a user-provided single-ended
analog input and generates a differential analog signal,
which is then applied to the ADC’s input pins.
The ADCs accept differential input signals; however, on-
board transformers (T1–T4) convert a readily available
single-ended source output to the required differential sig-
nal. The input signals of the ADC can be measured using
a differential oscilloscope probe at headers J3 and J4.
Output drivers (U2 and U3) buffer the output signals of
the data converter. The digital outputs of the EV kit are
accessible at headers J5 and J6.
Jumper JU4 controls the ADC clock input. See Table 2 for
jumper configuration.
Table 2. Clock Selection Shunt Settings (JU4)
The EV kits are designed as a four-layer PC board to
optimize the performance of this family of ADCs. Separate
analog, digital, clock, and buffer power planes minimize
noise coupling between analog and digital signals. 100Ω
differential microstrip transmission lines are used for
analog and clock inputs. 50Ω microstrip transmission
lines are used for all digital outputs. The trace lengths of
the 100Ω differential input lines are matched to within a
few thousandths of an inch to minimize layout-dependent
input-signal skew.
SHUNT
POSITION SECLK PIN
DIFFCLK/
DESCRIPTION
1-2*
2-3
OVDD
Differential clock mode.
Single-ended clock mode.
See the Configuring the EV Kit
for Single-Ended Clock Operation
section for further details.
GND
*Default configuration: JU4 (1-2).
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
Configuring the EV Kits for
Single-Ended Clock Operation
Optimizing the Analog Input Network for
Different Input Frequencies
To configure the MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559 EV kits for single-
ended clock operation, the following modifications must
be made to the clock circuit:
The EV kits are designed for excellent AC performance
across a broad 3MHz to 400MHz input frequency range.
The design can be further optimized by adjusting com-
ponents C7–C10 and R49–R52. See Table 4 for the
appropriate component values for specific input frequency
ranges.
1) Cut the trace at locations R41, R43, and R44.
2) Install 0Ω resistors at locations R40, R42, and R45.
3) Install a 49.9Ω ±1% resistor at location R37.
Table 4. Component Selection for
Optimized AC Performance
4) Connect a 3.3V power supply to VCLK (needs to
be capable of sourcing up to 10mA output current).
Connect the ground terminal of this supply to GND.
INPUT
FREQUENCY
RANGE (MHz)
C7–C10
COMPONENT
VALUES (pF)
R49–R52
COMPONENT
VALUES (Ω)
In single-ended clock configuration, potentiometer R48
can be utilized to control the duty cycle of the clock input
signal. Measure the clock input at J8 and adjust R48 until
the desired duty cycle is achieved.
3 to 400*
< 10
5.6
12 to 22
12
25
0
25 to 50
0
Clock-Divider Control
10 to 125
> 125
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 each feature internal divide-
by-2/divide-by-4 clock-divider circuitry (DIV2, DIV4).
Jumpers JU5 and JU6 control this circuitry. Refer to
the individual ADC data sheets for a detailed explana-
tion of the internal clock divider. See Table 3 for jumper
configuration.
5.6 to 12
*Default EV kit configuration.
Reference
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 feature numerous refer-
ence operation modes. The default EV kit configuration
connects the ADC’s internal 2.048V reference output to
the reference input. In this case, the converter generates
the REFN, REFP, and COM voltages from this input (refer
to the individual ADC’s data sheet for a more detailed
explanation).
Table 3. Clock-Divider Shunt Settings
(JU5, JU6)
SHUNT
PD PIN
POSITION
DESCRIPTION
JU5 JU6 DIV2
DIV4
To apply a user-supplied reference, cut the trace at
location R33 and connect the desired external reference
to the REFIN pad. Alternatively, the EV kit can be con-
figured to use a divided internal reference value. If the
desired reference voltage is less than 2.048V, cut the
trace at location R33 and install resistors in locations R33
and R34. Calculate the resistor values from the equations
below:
2-3* 2-3* GND
GND Normal clock mode
1-2
2-3
1-2
2-3 OVDD GND Divide-by-2 clock mode (DIV2)
1-2 GND OVDD Divide-by-4 clock mode (DIV4)
1-2 OVDD OVDD INVALID
*Default configuration: JU5 (2-3), JU6 (2-3).
Input Signal
V
Although this family of ADCs accepts differential analog
input signals, the EV kit only requires single-ended analog
input signals, with amplitudes less than 7.5dBm. Insertion
losses due to a series-connected filter and the intercon-
necting cables decrease the amount of power seen at
the EV kit input. Account for these losses when setting
the signal generator amplitude. On-board transformers
(T1–T4) convert the single-ended analog input signals
and generate the recommended differential analog sig-
nals at the ADCs’ differential input pins.
REF
R34 =
×R
T
V
REFOUT
R33 = R − R34
T
where:
V
V
= desired reference voltage
REF
= ADC’s internal reference voltage of 2.048V
REFOUT
R = ADC’s minimum reference resistance ≈ 10kΩ
T
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
Shared Reference Mode
Table 6. Reference Test Point Connections
To maximize isolation between the two input channels,
the MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 feature two independent
references. To improve channel matching this family of
ADCs provides a mode where both input channels share
the same reference. Jumper JU1 controls this shared
reference feature. See Table 5 for the desired jumper
configuration.
TEST POINT CONNECTION
DESCRIPTION
Common-mode voltage for
channel A.
TP1
TP2
TP3
TP4
TP5
TP6
COMA
COMB
REFPA
REFNA
REFPB
REFNB
Common-mode voltage for
channel B.
Positive voltage reference
terminal for channel A.
Negative voltage reference
terminal for channel A.
Table 5. Shared Reference Shunt
Settings (JU1)
Positive voltage reference
terminal for channel B.
SHUNT
POSITION
SHREF
PIN
DESCRIPTION
Negative voltage reference
terminal for channel B.
Shared reference mode.
Install 0Ω resistors at locations
R35 and R36.
1-2
OVDD
Note: Refer to the respective ADC data sheet for REFP, REFN,
and COM voltage ranges.
Independent reference mode.
Remove any component at
locations R35 and R36.
Output Signal
2-3*
GND
The MAX12527, MAX12528, and MAX12529 feature two
12-bit, parallel, CMOS-compatible digital outputs that
transmit the converted analog input signals. The higher-
resolution MAX12557, MAX12558, and MAX12559 fea-
ture two 14-bit, parallel, CMOS-compatible digital outputs
that transmit the converted analog input signals. Each
set of 12-bit or 14-bit digital outputs also includes a clock
(CLK) bit and overrange (DORA/B) bit to accommodate
data synchronization and error detection. See the Output
Bit Locations section for more details on how to configure
these 12-bit and 14-bit converter outputs.
*Default configuration: JU1 (2-3).
Alternative Reference Mode
The MAX12527, MAX12528, MAX12529, MAX12557,
MAX12558, and MAX12559 derive their REFP, REFN,
and COM voltages from the REFIN input. To override
these derived voltages, follow the board modifications
given below.
1) Cut the trace at location R33.
Output Format
2) Remove resistor R34 (not installed by default).
3) Connect the REFIN pad to GND.
Set the digital output coding to either two’s-complement
or Gray code, by configuring jumper JU3. See Table 7 for
the jumper configuration.
4) Apply the desired voltages to test points TP1–TP6.
See Table 6 for a detailed description of test point connections.
Table 7. Output Format Shunt Settings (JU3)
SHUNT
POSITION
G/T Pin
DESCRIPTION
Gray code selected.
Digital output format is Gray code.
1-2
OVDD
Two’s complement selected.
Digital output format is two’s
complement.
2-3*
GND
*Default configuration: JU3 (2-3).
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
Note: Silkscreen markings on the EV kit PC board indi-
cate pin markings for the MAX12557, MAX12558, and
MAX12559. These pin markings are not valid for the
MAX12527, MAX12528, or MAX12529. Use the connec-
tions outlined in Table 9.
Output Bit Locations
Two drivers (U2 and U3) buffer the digital outputs of the
individual ADCs. These drivers can drive large capacitive
loads, which may be present at the logic analyzer connec-
tion. The outputs of the buffers are connected to 40-pin
headers J5 and J6. See Table 8 (14-bit ADCs) and Table
9 (12-bit ADCs) for bit locations of headers J5 and J6.
Table 8. Output Bit Locations (MAX12557,
MAX12558, MAX12559—14-Bit, Dual ADCs)
Table 9. Output Bit Locations (MAX12527,
MAX12528, MAX12529—12-Bit, Dual ADCs)
CHANNEL
CHANNEL
SIGNAL
DESCRIPTION
SIGNAL
DESCRIPTION
A
B
A
B
D0
D1
J5-37
J5-35
J5-33
J5-31
J5-29
J5-27
J5-25
J5-23
J5-21
J5-19
J5-17
J5-15
J5-13
J5-11
J5-9
J6-37
J6-35
J6-33
J6-31
J6-29
J6-27
J6-25
J6-23
J6-21
J6-19
J6-17
J6-15
J6-13
J6-11
J6-9
Data Bit 0 (LSB)
Data Bit 1
N.C.
N.C.
D0
J5-37
J5-35
J5-33
J5-31
J5-29
J5-27
J5-25
J5-23
J5-21
J5-19
J5-17
J5-15
J5-13
J5-11
J5-9
J6-37
J6-35
J6-33
J6-31
J6-29
J6-27
J6-25
J6-23
J6-21
J6-19
J6-17
J6-15
J6-13
J6-11
J6-9
N.C.
N.C.
D2
Data Bit 2
Data Bit 0 (LSB)
Data Bit 1
D3
Data Bit 3
D1
D4
Data Bit 4
D2
Data Bit 2
D5
Data Bit 5
D3
Data Bit 3
D6
Data Bit 6
D4
Data Bit 4
D7
Data Bit 7
D5
Data Bit 5
D8
Data Bit 8
D6
Data Bit 6
D9
Data Bit 9
D7
Data Bit 7
D10
D11
D12
D13
DOR
CLK
Data Bit 10
Data Bit 11
Data Bit 12
Data Bit 13 (MSB)
Over Range Bit
Clock Bit
D8
Data Bit 8
D9
Data Bit 9
D10
D11
DOR
CLK
Data Bit 10
Data Bit 11 (MSB)
Over Range Bit
Clock Bit
J5-3
J6-3
J5-3
J6-3
Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39,
and 40 of J6 are open. All other pins that are not listed in Table
8 are connected to GND.
Note: Pins 1, 2, 5, 6, 39, and 40 of J5 and pins 1, 2, 5, 6, 7, 39,
and 40 of J6 are open. All other pins that are not listed in Table
9 are connected to GND.
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MAX12527/MAX12528/MAX12529/
MAX12557/MAX12558/MAX12559
Evaluation Kits
D D
O V
D D
O V
G N D
G N D
G N D
G N D
D D
O V
D D
V
D D
V
D D
V
D D
V
G N D
G N D
G N D
D D
V
D D
V
D D
V
Figure 1. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 1 of 4)
Maxim Integrated
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G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
V C C
V C C
V C C
V C C
Figure 2. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 2 of 4)
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G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
V C C
V C C
V C C
V C C
Figure 3. MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 3 of 4)
Maxim Integrated
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MAX12557/MAX12558/MAX12559
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D D
O V
D D
O V
G N D
G N D
G N D
G N D
D D
O V
D D
V
D D
V
D D
V
G N D
G N D
G N D
D D
V
D D
V
D D
V
D D
V
Figure 4. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 1 of 4)
Maxim Integrated
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G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
V C C
V C C
V C C
V C C
Figure 5. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 2 of 4)
Maxim Integrated
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G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
V C C
V C C
V C C
V C C
Figure 6. MAX12527/MAX12528/MAX12529 EV Kit Schematic (Sheet 3 of 4)
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R43
SHORT
(PC TRACE)
C51
0.01µF
R41
SHORT
(PC TRACE)
C45
0.1µF
CLKN
J7
T5
R38
49.9Ω
1%
1
2
3
6
5
4
R45
OPEN
2
D1
3
1
R37
OPEN
J8
R39
49.9Ω
1%
CLKP
VCLK
R44
SHORT
(PC TRACE)
C52
0.01µF
R46
100Ω
1%
VCLK
R48
10kΩ
C46
R47
100Ω
1%
0.01µF
5
2
U5–A
6
U5–B
1
3
4
R40
OPEN
R42
OPEN
VCLK
L4
VCLK
GND
1
3
C53
220µF
6.3V
C47
220µF
6.3V
C55
10µF
C56
1µF
2
Figure 7. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Schematic (Sheet 4 of 4)
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1.0”
Figure 8. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit Component Placement Guide—Component Side
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1.0”
Figure 9. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout—Component Side
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1.0”
Figure 10. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 2)—Ground Planes
Maxim Integrated
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1.0”
Figure 11. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout (Inner Layer 3)—Power Planes
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1.0”
Figure 12. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Layout—Solder Side
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1.0”
Figure 13. MAX12527/MAX12528/MAX12529/MAX12557/MAX12558/MAX12559 EV Kit PC Board Component Placement Guide—Solder Side
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Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
12/05
Initial Release
—
Updated Ordering Information, Component List, and EV Kit Specific Component
List
1
2
1/21
3/21
1–19
1, 2
Updated Ordering Information and Component List
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2021 Maxim Integrated Products, Inc.
│ 21
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