MAX1263BCEG-T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 8 Channel, Parallel, Word Access, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24;
| 型号： | MAX1263BCEG-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 8 Channel, Parallel, Word Access, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137, QSOP-24 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2719; Rev 0; 04/03
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
Features
The MAX1261/MAX1263 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed, byte-wide parallel interface. They operate
ꢀ 12-Bit Resolution, ±±0. ꢀLB ꢀineꢁaitꢂ
ꢀ +3V Lingle Opeaꢁtion
ꢀ Usea-Adjustꢁble ꢀogic ꢀevel (+108V to +306V)
ꢀ Inteanꢁl +20.V Refeaence
with a single +3V analog supply and feature a V
LOGIC
ꢀ Loftwꢁae-Configuaꢁble, Anꢁlog Input Multiplexea
8-Chꢁnnel Lingle Ended/
pin that allows them to interface directly with a +1.8V to
+5.5V digital supply.
4-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1261)
4-Chꢁnnel Lingle Ended/
2-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1263)
Power consumption is only 5.7mW (V
= V
) at
LOGIC
DD
the maximum sampling rate of 250ksps. Two software-
selectable power-down modes enable the MAX1261/
MAX1263 to be shut down between conversions;
accessing the parallel interface returns them to normal
operation. Powering down between conversions can
cut supply current to under 10µA at reduced sampling
rates.
ꢀ Loftwꢁae-Configuaꢁble, Unipolꢁa/Bipolꢁa Inputs
ꢀ ꢀow Powea
109mA (2.±ksps)
10±mA (1±±ksps)
4±±µA (1±ksps)
2µA (Lhutdown)
Both devices offer software-configurable analog inputs
for unipolar/bipolar and single-ended/pseudo-differen-
tial operation. In single-ended mode, the MAX1261 has
eight input channels and the MAX1263 has four input
channels (four and two input channels, respectively,
when in pseudo-differential mode).
ꢀ Inteanꢁl 3MHz Full-Powea Bꢁndwidth Taꢁck/Hold
ꢀ Bꢂte-Wide Pꢁaꢁllel (8 + 4) Inteafꢁce
ꢀ Lmꢁll Footpaint
28-Pin QLOP (MAX1261)
24-Pin QLOP (MAX1263)
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power consumption and space requirements.
Pin Configurations
TOP VIEW
The MAX1261 is available in a 28-pin QSOP package,
while the MAX1263 is available in a 24-pin QSOP. For
pin-compatible +5V, 12-bit versions, refer to the
MAX1262/MAX1264 data sheet.
HBEN
D7
1
2
3
4
5
6
7
8
9
28
27
V
V
LOGIC
DD
D6
26 REF
25 REFADJ
24 GND
23 COM
22 CH0
21 CH1
20 CH2
19 CH3
18 CH4
17 CH5
16 CH6
15 CH7
D5
Applications
D4
MAX1261
Industrial Control Systems
Energy Management
Data Logging
D3/D11
D2/D10
D1/D9
D0/D8
Patient Monitoring
Touch Screens
Data-Acquisition Systems
INT 10
RD 11
WR 12
CLK 13
CS 14
Ordering Information
INꢀ
PART
PIN-PACKAGE
TEMP RANGE
(ꢀLB)
0.5
1
0°C to +70°C
0°C to +70°C
MAX1261ACEI
MAX1261BCEI
MAX1261AEEI
MAX1261BEEI
28 QSOP
28 QSOP
28 QSOP
28 QSOP
QLOP
-40°C to +85°C
-40°C to +85°C
0.5
1
Pin Configurations continued at end of data sheet.
Ordering Information continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABLOꢀUTE MAXIMUM RATINGL
V
V
to GND..............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
LOGIC
to GND.........................................................-0.3V to +6V
24-Pin QSOP (derate 9.5mW/°C above +70°C) ..........762mW
28-Pin QSOP (derate 8.0mW/°C above +70°C) ..........667mW
Operating Temperature Ranges
CH0–CH7, COM to GND............................-0.3V to (V
REF, REFADJ to GND ................................-0.3V to (V
+ 0.3V)
+ 0.3V)
DD
DD
Digital Inputs to GND ...............................................-0.3V to +6V
Digital Outputs (D0–D11, INT) to GND...-0.3V to (V + 0.3V)
MAX1261_C_ _/MAX1263_C_ _..........................0°C to +70°C
MAX1261_E_ _/MAX1263_E_ _ .......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
LOGIC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECTRICAꢀ CHARACTERILTICL
(V
= V
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty
DD
LOGIC
DD REF
CLK
cycle); T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
LYMBOꢀ
CONDITIONL
MIN
TYP
MAX
UNITL
RES
INL
12
Bits
MAX126_A
MAX126_B
0.5
1
Relative Accuracy (Note 2)
LSB
Differential Nonlinearity
Offset Error
DNL
No missing codes overtemperature
1
LSB
LSB
4
Gain Error
(Note 3)
4
LSB
Gain Temperature Coefficient
2.0
0.2
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC LPECIFICATIONL (f
= 50kHz, V = 2.5V , 250ksps, external f
= 4.8MHz, bipolar input mode)
IN(sine wave)
SINAD
IN
CLK
P-P
Signal-to-Noise Plus Distortion
67
80
70
dB
dB
Total Harmonic Distortion
(Including 5th-Order Harmonic)
THD
-78
Spurious-Free Dynamic Range
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
SFDR
IMD
dB
dB
f
f
= 49kHz, f
= 52kHz
2
IN
76
-78
250
3
IN1
= 125kHz, V = 2.5V (Note 4)
P-P
dB
IN
IN
SINAD > 68dB
-3dB rolloff
kHz
MHz
Full-Power Bandwidth
CONVERLION RATE
External clock mode
3.3
2.5
3.2
Conversion Time (Note 5)
t
External acquisition/internal clock mode
Internal acquisition/internal clock mode
3.0
3.6
3.5
4.1
625
µs
CONV
Track/Hold Acquisition Time
Aperture Delay
t
ns
ns
ACQ
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
50
<50
<200
Aperture Jitter
ps
External Clock Frequency
Duty Cycle
f
0.1
30
4.8
70
MHz
%
CLK
2
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
EꢀECTRICAꢀ CHARACTERILTICL (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty
DD
LOGIC
DD REF
CLK
cycle); T = T
to T
unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
ANAꢀOG INPUTL
LYMBOꢀ
CONDITIONL
MIN
TYP
MAX
UNITL
Analog Input Voltage Range,
Single Ended and Differential
(Note 6)
Unipolar, V
= 0
0
V
REF
COM
V
IN
V
Bipolar, V
= V
/ 2
-V
/2
+V
/2
REF
COM
REF
REF
Multiplexer Leakage Current
On-/off-leakage current, V = 0 or V
0.01
12
1
µA
pF
IN
DD
Input Capacitance
C
IN
INTERNAꢀ REFERENCE
REF Output Voltage
2.49
2.5
15
2.51
V
mA
REF Short-Circuit Current
REF Temperature Coefficient
REFADJ Input Range
TC
T
= 0°C to +70°C
20
ppm/°C
mV
REF
A
For small adjustments
100
REFADJ High Threshold
Load Regulation
To power down the internal reference
0 to 0.5mA output load (Note 7)
V
DD
- 1.0
V
0.2
mV/mA
µF
Capacitive Bypass at REFADJ
Capacitive Bypass at REF
EXTERNAꢀ REFERENCE AT REF
0.01
1
4.7
1.0
10
µF
V
+
DD
50mV
REF Input Voltage Range
V
REF
V
V
= 2.5V, f
= 250ksps
SAMPLE
200
300
2
REF
REF Input Current
I
µA
REF
Shutdown mode
DIGITAꢀ INPUTL AND OUTPUTL
Input High Voltage
V
V
V
V
= 2.7V
= 1.8V
= 2.7V
= 1.8V
2.0
1.5
LOGIC
LOGIC
LOGIC
LOGIC
V
V
V
IH
0.8
0.5
Input Low Voltage
V
IL
Input Hysteresis
V
200
0.1
15
mV
µA
pF
V
HYS
Input Leakage Current
Input Capacitance
Output Low Voltage
Output High Voltage
I
V
= 0 or V
1
0.4
1
IN
DD
IN
C
IN
OL
OH
V
I = 1.6mA
SINK
V
I
= 1mA
V
- 0.5
V
SOURCE
LOGIC
Tri-State Leakage Current
I
0.1
15
µA
pF
CS = V
CS = V
LEAKAGE
DD
DD
Tri-State Output Capacitance
C
OUT
_______________________________________________________________________________________
3
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
EꢀECTRICAꢀ CHARACTERILTICL (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty
DD
LOGIC
DD REF
CLK
cycle); T = T
to T
unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
POWER REQUIREMENTL
Analog Supply Voltage
LYMBOꢀ
CONDITIONL
MIN
TYP
MAX
UNITL
V
DD
2.7
1.8
3.6
V
V
V
+
DD
Digital Supply Voltage
V
LOGIC
0.3
Internal reference
2.3
1.9
0.9
0.5
2.6
2.3
1.2
0.8
Operating mode,
= 250ksps
f
External reference
Internal reference
External reference
SAMPLE
mA
Positive Supply Current
I
DD
Standby mode
Shutdown mode
2
10
150
10
µA
µA
mV
f
= 250ksps
SAMPLE
V
Current
I
C = 20pF
L
LOGIC
LOGIC
Not converting
= 3V 10%, full-scale input
2
Power-Supply Rejection
PSR
V
DD
0.4
0.9
TIMING CHARACTERILTICL
(V
= V
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty
DD
LOGIC
DD REF
CLK
cycle); T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
CLK Period
LYMBOꢀ
CONDITIONL
MIN
208
40
40
40
0
TYP
MAX
UNITL
ns
t
CP
CH
CLK Pulse Width High
t
ns
CLK Pulse Width Low
t
ns
CL
DS
t
t
ns
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
ns
DH
t
t
40
40
ns
CWS
ns
CWH
CS to CLK or WR
Setup Time
t
60
0
ns
ns
CSWS
CLK or WR to CS
Hold Time
t
CSWH
t
100
60
ns
ns
ns
CS Pulse Width
CS
t
(Note 8)
= 20pF (Figure 1)
WR Pulse Width
WR
t
C
20
100
CS Rise to Output Disable
TC
LOAD
4
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERILTICL (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, REFADJ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 4.8MHz (50% duty
DD
LOGIC
DD REF
CLK
cycle); T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
LYMBOꢀ
CONDITIONL
= 20pF, Figure 1
MIN
20
TYP
MAX
70
UNITL
ns
t
TR
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
RD Rise to Output Disable
RD Fall to Output Data Valid
HBEN to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
t
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
20
70
ns
DO
t
t
20
110
100
110
ns
DO1
ns
INT1
t
ns
DO2
Note 1: Tested at V
= +3V, COM = GND, unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note .: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to V
Note 7: External load should not change during conversion for specified accuracy.
.
DD
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
V
LOGIC
3kΩ
DOUT
DOUT
C
LOAD
20pF
C
LOAD
20pF
3kΩ
a) HIGH-Z TO V AND V TO V
OH
b) HIGH-Z TO V AND V TO V
OL
OH
OL
OL
OH
Figure 1. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
.
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(V
= V
= +3V, V
= +2.500V, f
= 4.8MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
LOGIC
REF
CLK L A
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.5
0.4
0.5
0.4
10,000
1000
100
10
0.3
0.3
WITH INTERNAL
REFERENCE
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
WITH EXTERNAL
REFERENCE
1
0.1
1
10 100
f
1k 10k 100k 1M
(Hz)
0
1000
2000
3000
4000
5000
0
1000
2000
3000
4000
5000
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
SAMPLE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
STANDBY CURRENT vs. SUPPLY VOLTAGE
2.10
2.05
2.00
1.95
1.90
1.85
1.80
2.2
2.1
2.0
1.9
1.8
1.7
1.6
930
920
910
900
890
880
R = ∞
R = ∞
L
L
CODE = 101010100000
CODE = 101010100000
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
V
(V)
TEMPERATURE (°C)
V
(V)
DD
DD
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE
1.2
1.1
1.0
0.9
0.8
1.50
1.25
1.00
930
920
910
900
890
880
0.75
0.50
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
DD
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(V
= V
= +3V, V
= +2.500V, f
= 4.8MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
LOGIC
REF
CLK L A
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
2.53
2.53
2.52
2.51
2.50
2.49
2.48
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
2.52
2.51
2.50
2.49
2.48
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
V
(V)
TEMPERATURE (°C)
V
DD
(V)
DD
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
0.5
0.0
1
0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-0.5
-1.0
-1.5
-2.0
-1
-2
-3
-40
-15
10
35
60
85
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
DD
LOGIC SUPPLY CURRENT
vs. TEMPERATURE
LOGIC SUPPLY CURRENT
vs. SUPPLY VOLTAGE
FFT PLOT
250
200
150
100
50
250
200
20
0
V
= 3V
DD
= 50kHz
f
f
IN
SAMPLE
= 250ksps
-20
-40
-60
-80
-100
-120
-140
150
100
50
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
0
200
400
600
800 1000 1200
V
(V)
TEMPERATURE (°C)
FREQUENCY (kHz)
DD
_______________________________________________________________________________________
7
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
NAME
FUNCTION
MAX1261
MAX1263
High Byte Enable. Used to multiplex the 12-bit conversion result:
1: Four MSBs are multiplexed on the data bus.
1
1
HBEN
0: Eight LSBs are available on the data bus.
2
3
2
3
D7
D6
Tri-State Digital I/O Line (D7)
Tri-State Digital I/O Line (D6)
4
4
D5
Tri-State Digital I/O Line (D5)
5
5
D4
Tri-State Digital I/O Line (D4)
6
6
D3/D11
D2/D10
D1/D9
D0/D8
INT
Tri-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1)
Tri-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1)
Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1)
Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1)
INT goes low when the conversion is complete and the output data is ready.
7
7
8
8
9
9
10
10
Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on
the data bus.
11
12
13
11
12
13
RD
Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR
latches in configuration data and starts an acquisition plus a conversion cycle. When CS is
low in external acquisition mode, the first rising edge on WR ends acquisition and starts a
conversion.
WR
Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In
CLK
internal clock mode, connect this pin to either V
or GND.
DD
14
15
16
17
18
19
20
21
22
14
—
—
—
—
15
16
17
18
CS
Active-Low Chip Select. When CS is high, digital outputs (D7–D0) are high impedance.
Analog Input Channel 7
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Analog Input Channel 6
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and
must be stable to 0.5 LSB during conversion.
23
24
19
20
COM
GND
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a
25
21
REFADJ
REF
0.01µF capacitor. When using an external reference, connect REFADJ to V
the internal bandgap reference.
to disable
DD
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor to
GND when using the internal reference.
26
27
28
22
23
24
V
DD
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GND.
Digital Power Supply. V
powers the digital outputs of the data converter and can
LOGIC
V
LOGIC
range from +1.8V to (V + 300mV).
DD
8
_______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
either of the analog inputs. This configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
Detailed Description
Converter Operation
The MAX1261/MAX1263 ADCs use a successive-
approximation (SAR) conversion technique and an
input track/hold (T/H) stage to convert an analog input
signal to a 12-bit digital output. Their parallel (8 + 4)
output format provides an easy interface to standard
microprocessors (µPs). Figure 2 shows the simplified
internal architecture of the MAX1261/MAX1263.
return side (IN-) must remain stable within 0.5 LSB
( 0.1 LSB for best performance) with respect to GND
during a conversion. To accomplish this, connect a
0.1µF capacitor from IN- (the selected input) to GND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor C
. At
HOLD
the end of the acquisition interval, the T/H switch
opens, retaining charge on C
signal at IN+.
as a sample of the
HOLD
Single-Ended and
Pseudo-Differential Operation
The conversion interval begins with the input multiplex-
er switching C from the positive input (IN+) to the
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit in
Figure 3. In single-ended mode, IN+ is internally
switched to channels CH0–CH7 for the MAX1261
(Figure 3a) and to CH0–CH3 for the MAX1263 (Figure
3b), while IN- is switched to COM (Table 3).
HOLD
negative input (IN-). This unbalances node zero at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node 0 to 0V within the
limits of 12-bit resolution. This action is equivalent to
transferring a 12pF[(V ) - (V )] charge from C
HOLD
IN+
IN-
In differential mode, IN+ and IN- are selected from ana-
log input pairs (Table 4) and are internally switched to
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
REF
REFADJ
17kΩ
1.22V
REFERENCE
A =
V
2.05
(CH7)
(CH6)
(CH5)
(CH4)
CH3
CH2
CH1
CH0
ANALOG
INPUT
MULTIPLEXER
T/H
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
12
SUCCESSIVE-
COM
APPROXIMATION
REGISTER
CLK
CLOCK
4
8
MAX1261
MAX1263
CS
WR
RD
4
8
CONTROL LOGIC
AND
LATCHES
MUX
8
HBEN
INT
V
DD
8
V
LOGIC
TRI-STATE, BIDIRECTIONAL
I/O INTERFACE
GND
D0–D7
8-BIT DATA BUS
( ) ARE FOR MAX1261 ONLY.
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1261/MAX1263
_______________________________________________________________________________________
9
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Track/Hold
The MAX1261/MAX1263 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next rising
edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. Note that, in internal clock
mode, this occurs approximately 1µs after writing the
control byte. In single-ended operation, IN- is connect-
ed to COM and the converter samples the positive (+)
input. In pseudo-differential operation, IN- connects to
the negative (-) input, and the difference of (IN+) - (IN-) is
sampled. At the beginning of the next conversion, the
12-BIT CAPACITIVE DAC
REF
COMPARATOR
INPUT
MUX
C
HOLD
ZERO
–
+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
12pF
R
IN
800Ω
C
SWITCH
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
positive input connects back to IN+ and C
HOLD
charges to the input signal.
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
Figure 3a. MAX1261 Simplified Input Structure
t
, is the maximum time the device takes to acquire
ACQ
the signal and is also the minimum time required for the
signal to be acquired. Calculate this with the following
equation:
12-BIT CAPACITIVE DAC
REF
COMPARATOR
INPUT
MUX
C
HOLD
t
= 9(R + R )C
S IN IN
ACQ
ZERO
–
+
CH0
CH1
where R is the source impedance of the input signal,
S
12pF
R
(800Ω) is the input resistance, and C (12pF) is
IN
IN
R
IN
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1261/
MAX1263s’ AC performance.
800Ω
C
SWITCH
CH2
CH3
HOLD
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
T/H
SWITCH
COM
SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS
CH0/CH1 AND CH2/CH3
Input Bandwidth
The MAX1261/MAX1263 T/H stage offers a 250kHz full-
linear and a 3MHz full-power bandwidth, enabling
these parts to use undersampling techniques to digitize
high-speed transients and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate.
To avoid high-frequency signals being aliased into the
frequency band of interest, anti-alias filtering is recom-
mended.
Figure 3b. MAX1263 Simplified Input Structure
Analog Input Protection
Internal protection diodes, which clamp the analog
input to V and GND, allow each input channel to
DD
swing within (GND - 300mV) to (V
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V
less than (GND - 50mV).
+ 300mV) without
DD
Starting a Conversion
Initiate a conversion by writing a control byte that
selects the multiplexer channel and configures the
MAX1261/MAX1263 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
+ 50mV) or be
DD
If an off-channel analog input voltage exceeds the sup-
plies by more than 50mV, limit the forward-bias input
current to 4mA.
1± ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0, terminates
acquisition and starts conversion on WR’s rising edge
(Figure 5).
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval ends (three external
cycles or approximately 1µs in internal clock mode)
(Figure 4). Note that, when the internal acquisition is
combined with the internal clock, the aperture jitter can
be as high as 200ps. Internal clock users wishing to
achieve the 50ps jitter specification should always use
external acquisition mode.
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see the Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the
MAX1261/MAX1263 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Tꢁble 10 Contaol Bꢂte Functionꢁl Descaiption
BIT
NAME
FUNCTION
PD1 and PD± select the various clock and power-down modes.
±
±
1
1
±
1
±
1
Full power-down mode. Clock mode is unaffected.
D7, D6
PD1, PD0
Standby power-down mode. Clock mode is unaffected.
Normal operation mode. Internal clock mode selected.
Normal operation mode. External clock mode selected.
ACQMOD = 0: Internal acquisition mode
ACQMOD = 1: External acquisition mode
D5
D4
ACQMOD
SGL/DIF = 0: Pseudo-differential analog input mode
SGL/DIF = 1: Single-ended analog input mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
SGL/DIF
UNI/BIP = 0: Bipolar mode
UNI/BIP = 1: Unipolar mode
In unipolar mode, an analog input signal from 0 to V
D3
UNI/BIP
can be converted; in bipolar mode, the sig-
REF
nal can range from -V /2 to +V
REF
/2.
REF
Address bits A2, A1, A0 select which of the 8/4 (MAX1261/MAX1263) channels are to be converted
(Tables 3 and 4).
D2, D1, D0
A2, A1, A0
______________________________________________________________________________________ 11
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
t
CS
CS
t
ACQ
t
CONV
t
t
CSWH
CSWS
t
WR
WR
t
DH
t
DS
CONTROL
BYTE
D7–D0
ACQMOD = 0
t
INT1
INT
RD
HBEN
DOUT
t
t
t
TR
D0
D01
HIGH-Z
HIGH-Z
HIGH/LOW
HIGH/LOW
BYTE VALID
BYTE VALID
Figure 4. Conversion Timing Using Internal Acquisition Mode
t
CS
CS
t
t
t
CONV
CSWS
ACQ
t
WR
t
t
CSHW
WR
DH
t
DS
CONTROL
BYTE
ACQMOD = 1
CONTROL
BYTE
ACQMOD = 0
D7–D0
INT
t
INT1
RD
HBEN
t
D01
t
D0
t
TR
HIGH-Z
HIGH-Z
HIGH/LOW
HIGH/LOW
BYTE VALID
BYTE VALID
DOUT
Figure 5. Conversion Timing Using External Acquisition Mode
12 ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
mended, because it causes a voltage droop across the
hold capacitor in the T/H stage that results in degraded
performance.
Selecting Clock Mode
The MAX1261/MAX1263 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The parts retain
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition can
be used. At power-up, the MAX1261/MAX1263 enter
the default external clock mode.
Digital Interface
Input (control byte) and output data are multiplexed on
a tri-state parallel interface. This parallel interface (I/O)
can easily be interfaced with standard µPs. Signals CS,
WR, and RD control the write and read operations. CS
represents the chip-select signal, which enables a µP
to address the MAX1261/MAX1263 as an I/O port.
When high, CS disables the CLK, WR, and RD inputs
and forces the interface into a high-impedance (high-Z)
state.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. To select
this mode, bit D7 of the control byte must be set to 1
and bit D6 must be set to zero. The internal clock fre-
quency is then selected, resulting in a conversion time
of 3.6µs. When using the internal clock mode, tie the
CLK pin either high or low to prevent the pin from float-
ing.
Input Format
The control byte is latched into the device on pins
D7–D0 during a write command. Table 2 shows the
control byte format.
Output Format
The output format for both the MAX1261/MAX1263 is
binary in unipolar mode and two’s complement in bipo-
lar mode. When reading the output data, CS and RD
must be low. When HBEN = 0, the lower 8 bits are read.
With HBEN = 1, the upper 4 bits are available and the
output data bits D7–D4 are set either low in unipolar
mode or set to the value of the MSB in bipolar mode
(Table 5).
External Clock Mode
To select the external clock mode, bits D6 and D7 of
the control byte must be set to 1. Figure 6 shows the
clock and WR timing relationship for internal (Figure 6a)
and external (Figure 6b) acquisition modes with an
external clock. For proper operation, a 100kHz to
4.8MHz clock frequency with 30% to 70% duty cycle is
recommended. Operating the MAX1261/MAX1263 with
clock frequencies lower than 100kHz is not recom-
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
t
CP
CLK
WR
t
t
CL
CH
t
CWS
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = 0
ACQUISITION STARTS
t
CWH
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
ACQMOD = 0
WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
______________________________________________________________________________________ 13
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
t
CWS
t
DH
ACQMOD = 0
WR GOES HIGH WHEN CLK IS HIGH.
ACQMOD = 1
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
t
CWH
t
DH
ACQMOD = 1
WR GOES HIGH WHEN CLK IS LOW.
ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
Tꢁble 20 Contaol Bꢂte Foamꢁt
D7 (MLB)
D6
D.
D4
D3
D2
D1
D± (ꢀLB)
PD1
PD0
ACQMOD
A2
A1
A0
SGL/DIF
UNI/BIP
Tꢁble 30 Chꢁnnel Lelection foa Lingle-Ended Opeaꢁtion (LGꢀ/DIF = 1)
A2
0
A1
0
A±
0
CH±
CH1
CH2
CH3
CH4*
CH.*
CH6*
CH7*
COM
+
-
-
-
-
-
-
-
-
0
0
1
+
0
1
0
+
0
1
1
+
1
0
0
+
1
0
1
+
1
1
0
+
1
1
1
+
*Channels CH4–CH7 apply to MAX1261 only.
14 ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble 40 Chꢁnnel Lelection foa Pseudo-Diffeaentiꢁl Opeaꢁtion (LGꢀ/DIF = ±)
A2
0
A1
0
A±
0
CH±
CH1
CH2
CH3
CH4*
CH.*
CH6*
CH7*
+
-
-
0
0
1
+
0
1
0
+
-
-
0
1
1
+
1
0
0
+
-
-
1
0
1
+
1
1
0
+
-
-
1
1
1
+
*Channels CH4–CH7 apply to MAX1261 only.
Internal Reference
Applications Information
With the internal reference, the full-scale range is +2.5V
with unipolar inputs and 1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
( 100mV) in the reference voltage (Figure 7).
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1261/MAX1263 in external
clock mode and sets INT high. After the power supplies
stabilize, the internal reset time is 10µs, and no conver-
sions should be attempted during this phase. When
Note that the reference buffer must be compensated
with an external capacitor (4.7µF min) connected
between REF and GND to reduce reference noise and
switching spikes from the ADC. To further minimize
noise on the reference, connect a 0.01µF capacitor
between REFADJ and GND.
using the internal reference, 500µs is required for V
to stabilize.
REF
Internal and External Reference
The MAX1261/MAX1263 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADJ.
External Reference
With both the MAX1261 and MAX1263, an external ref-
erence can be placed at either the input (REFADJ) or
the output (REF) of the internal reference buffer amplifier.
An internal buffer is designed to provide +2.5V at REF for
both the MAX1261 and the MAX1263. The internally
trimmed +1.22V reference is buffered with a +2.05V/V
gain.
Using the REFADJ input makes buffering the external
reference unnecessary. The REFADJ input impedance
is typically 17kΩ.
Tꢁble .0 Dꢁtꢁ-Bus Output (8 + 4 Pꢁaꢁllel
Inteafꢁce)
+3V
PIN
D0
D1
D2
D3
HBEN = ±
BIT 0 (LSB)
BIT 1
HBEN = 1
BIT 8
50kΩ
MAX1261
MAX1263
330kΩ
BIT 9
50kΩ
REFADJ
REF
BIT 2
BIT 10
BIT 3
BIT 11 (MSB)
4.7µF
GND
0.01µF
BIPOꢀAR
UNIPOꢀAR
(UNI/BIP = ±)
(UNI/BIP = 1)
D4
BIT 4
GND
BIT 11
BIT 11
BIT 11
BIT 11
0
0
0
0
D5
D6
D7
BIT 5
BIT 6
BIT 7
Figure 7. Reference Voltage Adjustment with External
Potentiometer
______________________________________________________________________________________ 1.
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
When applying an external reference to REF, disable
the internal reference buffer by connecting REFADJ to
DD
Therefore, an external reference at REF must deliver up
to 200µA DC load current during a conversion and
have an output impedance less than 10Ω. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the REF pin with a 4.7µF capacitor.
rising edge on WR causes the MAX1261/MAX1263 to
exit shutdown mode and return to normal operation. To
achieve full 12-bit accuracy with a 4.7µF reference
bypass capacitor, 500µs is required after power-up.
Waiting 500µs in standby mode, instead of in full-power
mode, can reduce power consumption by a factor of 3 or
more. When using an external reference, only 50µs is
required after power-up. Enter standby mode by per-
forming a dummy conversion with the control byte speci-
fying standby mode.
V
. The DC input resistance at REF is 25kΩ.
Power-Down Modes
Save power by placing the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 2). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Note: Bypassing capacitors larger than 4.7µF between
REF and GND results in longer power-up delays.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes.
Standby Mode
While in standby mode, the supply current is 850µA
(typ). The part powers up on the next rising edge on
WR and is ready to perform conversions. This quick
turn-on time allows the user to realize significantly
reduced power consumption for conversion rates
below 250ksps.
Figure 8 depicts the nominal, unipolar input/output (I/O)
transfer function and Figure 9 shows the bipolar I/O
transfer function. Code transitions occur halfway
between successive-integer LSB values. Output coding
is binary, with 1 LSB = (V
/ 4096).
REF
Maximum Sampling Rate/
Achieving 300ksps
When running at the maximum clock frequency of
4.8MHz, the specified throughput of 250ksps is
achieved by completing a conversion every 19 clock
cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
Shutdown Mode
Shutdown mode turns off all chip functions that draw qui-
escent current, reducing the typical supply current to 2µA
immediately after the current conversion is completed. A
OUTPUT CODE
FULL-SCALE
OUTPUT CODE
REF
TRANSITION
FS
=
+ COM
+ COM
111 . . . 111
111 . . . 110
011 . . . 111
011 . . . 110
FS = REF + COM
ZS = COM
2
ZS = COM
REF
4096
-REF
2
1 LSB =
-FS =
100 . . . 010
100 . . . 001
100 . . . 000
000 . . . 010
000 . . . 001
000 . . . 000
REF
4096
1 LSB =
011 . . . 111
011 . . . 110
011 . . . 101
111 . . . 111
111 . . . 110
111 . . . 101
000 . . . 001
000 . . . 000
100 . . . 001
100 . . . 000
COM*
0
1
2
2048
FS
- FS
+FS - 1 LSB
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
INPUT VOLTAGE (LSB)
(COM)
*COM ≥ V / 2
REF
Figure 8. Unipolar Transfer Function
Figure 9. Bipolar Transfer Function
16 ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble 60 Full Lcꢁle ꢁnd Zeao Lcꢁle foa Unipolꢁa ꢁnd Bipolꢁa Opeaꢁtion
UNIPOꢀAR MODE
BIPOꢀAR MODE
Full scale
Zero scale
—
V
REF
+ COM
Positive full scale
Zero scale
V
/2 + COM
COM
REF
COM
—
Negative full scale
-V
/2 + COM
REF
sion cycles, and 2 read cycles. This assumes that the
results of the last conversion are read before the next
control byte is written. Throughputs up to 300ksps can
be achieved by first writing a control word to begin the
acquisition cycle of the next conversion, then reading
the results of the previous conversion from the bus
(Figure 10). This technique allows a conversion to be
completed every 16 clock cycles. Note that the switch-
ing of the data bus during acquisition or conversion can
cause additional supply noise, which can make it diffi-
cult to achieve true 12-bit performance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The sta-
tic linearity parameters for the MAX1261/MAX1263 are
measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
one star point (Figure 11) connecting the two ground
systems (analog and digital). For lowest noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
Aperture Definitions
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples. Aperture delay (t ) is
AD
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
error only and results directly from the ADC’s resolution
(N bits):
High-frequency noise in the power supply (VDD) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
to the star ground with a network
DD
of two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1261/MAX1263s’ power-
supply pin. Minimize capacitor lead length for best sup-
ply-noise rejection; add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. Therefore, SNR is computed by taking the ratio of
the RMS signal to the RMS noise, which includes all
spectral components minus the fundamental, the first
five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD (dB) = 20 x log (Signal
/ Noise
)
RMS
RMS
______________________________________________________________________________________ 17
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
WR
RD
HBEN
CONTROL
BYTE
D11–D8
D7–D0 D11–D8
D7–D0
CONTROL BYTE
CONVERSION
D7–D0
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
ACQUISITION
STATE
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
SUPPLIES
+3V
V
= +2V/+3V
GND
LOGIC
ENOB = (SINAD - 1.76) / 6.02
4.7µF
0.1µF
R* = 5Ω
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
GND
V
DD
COM
+2V/+3V DGND
2
2
2
2
DIGITAL
CIRCUITRY
THD = 20 x log
V
+ V + V + V
/ V
1
2
3
4
5
MAX1261
MAX1263
where V is the fundamental amplitude, and V through
5
monics.
1
2
*OPTIONAL
V are the amplitudes of the 2nd- through 5th-order har-
Figure 11. Power-Supply and Grounding Connections
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next-largest distor-
tion component.
Chip Information
TRANSISTOR COUNT: 5781
SUBSTRATE CONNECTED TO GND
18 ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Circuits
+1.8V TO +3.6V
+3V
+1.8V TO +3.6V
+3V
CLK
CLK
V
V
LOGIC
LOGIC
MAX1261
V
MAX1263
V
DD
DD
+2.5V
+2.5V
CS
REF
CS
REF
µP
CONTROL
INPUTS
µP
CONTROL
INPUTS
WR
REFADJ
WR
REFADJ
4.7µF
4.7µF
0.1µF
0.1µF
RD
RD
HBEN
HBEN
INT
OUTPUT STATUS
INT
OUTPUT STATUS
CH7
CH6
CH5
D7
D6
D7
D6
CH4
D5
D5
ANALOG
INPUTS
CH3
CH2
CH1
CH3
CH2
CH1
D4
D4
ANALOG
INPUTS
D3/D11
D3/D11
D2/D10
D2/D10
CH0
CH0
D1/D9
D0/D8
D1/D9
D0/D8
COM
COM
GND
GND
µP DATA BUS
µP DATA BUS
Pin Configurations (continued)
Ordering Information (continued)
INꢀ
(ꢀLB)
PART
TEMP RANGE
PIN-PACKAGE
TOP VIEW
HBEN
D7
1
2
3
4
5
6
24
23
V
V
LOGIC
DD
*
MAX1263ACEG
0°C to +70°C
0°C to +70°C
24 QSOP
24 QSOP
24 QSOP
24 QSOP
0.5
1
MAX1263BCEG*
MAX1263AEEG -40°C to +85°C
0.5
1
*
*
D6
22 REF
MAX1263BEEG -40°C to +85°C
D5
21 REFADJ
20 GND
19 COM
* Future product—contact factory for availability.
D4
MAX1263
D3/D11
D2/D10
D1/D9
7
8
18 CH0
17 CH1
D0/D8
9
16 CH2
15 CH3
14 CS
INT 10
RD 11
WR 12
13 CLK
QLOP
______________________________________________________________________________________ 19
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www0mꢁxim-ic0com/pꢁckꢁges.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
2± ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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