MAX1281BEUP+ [MAXIM]
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference;
| 型号： | MAX1281BEUP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 400ksps/300ksps, Single-Supply, Low-Power, 8-Channel, Serial 12-Bit ADCs with Internal Reference 信息通信管理 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1684; Rev 2; 10/10
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
General Description
Features
♦ 8-Channel Single-Ended or 4-Channel
The MAX1280/MAX1281 12-bit ADCs combine an 8-chan-
nel analog-input multiplexer, high-bandwidth track/hold,
and serial interface with high conversion speed and low
power consumption. The MAX1280 operates from a single
+4.5V to +5.5V supply; the MAX1281 operates from a sin-
gle +2.7V to +3.6V supply. Both devices’ analog inputs
are software configurable for unipolar/bipolar and single-
ended/pseudo-differential operation.
Pseudo-Differential Inputs
♦ Internal Multiplexer and Track/Hold
♦ Single-Supply Operation
+4.5V to +5.5V (MAX1280)
+2.7V to +3.6V (MAX1281)
♦ Internal +2.5V Reference
The 4-wire serial interface connects directly to
SPI™/QSPI™/MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1280/
MAX1281 use an external serial-interface clock to per-
form successive-approximation analog-to-digital con-
versions. Both parts feature an internal +2.5V reference
and a reference-buffer amplifier with a 1.5ꢀ voltage-
adjustment range. An external reference with a 1V to
♦ 400ksps Sampling Rate (MAX1280)
♦ Low Power 2.5mA (400ksps)
1.3mA (Reduced-Power Mode)
0.9mA (Fast Power-Down Mode)
2µA (Full Power-Down)
♦ SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
V
range may also be used.
DD1
♦ Software-Configurable Unipolar or Bipolar Inputs
♦ 20-Pin TSSOP Package
The MAX1280/MAX1281 provide a hard-wired SHDN
pin and four software-selectable power modes (normal
operation, reduced power, fast power-down, and full
power-down). These devices can be programmed to
automatically shut down at the end of a conversion or to
operate with reduced power. When using the power-
down modes, accessing the serial interface automatical-
ly powers up the devices, and the quick turn-on time
allows them to be powered down between all conver-
sions. This technique can cut supply current to under
100µA at reduced sampling rates.
Ordering Information
TEMP
RANGE
PIN-
PACKAGE
INL
(LSB)
PART
MAX1280BCUP+
MAX1280BEUP+
MAX1281BCUP+
MAX1281BEUP+
0°C to +70°C
-40°C to +85°C
0°C to +70°C
20 TSSOP
20 TSSOP
20 TSSOP
20 TSSOP
1
1
1
1
-40°C to +85°C
The MAX1280/MAX1281 are available in 20-pin TSSOP
packages. These devices are higher-speed versions of
the MAX146/MAX147 (for more information, see the
respective data sheet).
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration
Applications
TOP VIEW
+
Portable Data Logging
Data Acquisition
CH0
CH1
1
2
V
DD1
20
19
18
17
V
DD2
Medical Instruments
Battery-Powered Instruments
Pen Digitizers
SCLK
CS
CH2
3
MAX1280
MAX1281
CH3
4
5
CH4
16 DIN
CH5
6
15 SSTRB
Process Control
CH6
14
13
12
11
DOUT
7
8
CH7
GND
REFADJ
9
COM
SHDN
REF
10
SPI and QSPI are trademarks of Motorola, Inc.
TSSOP
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ABSOLUTE MAXIMUM RATINGS
V
V
to GND............................................................ -0.3V to +6V
20-Pin TSSOP (derate 7.0mW/°C above +70°C) .........559mW
Operating Temperature Ranges
DD_
to V
........................................................ -0.3V to +0.3V
DD1
DD2
CH0–CH7, COM to GND.......................... -0.3V to (V
REF, REFADJ to GND .............................. -0.3V to (V
Digital Inputs to GND .............................................. -0.3V to +6V
Digital Outputs to GND ............................ -0.3V to (V + 0.3V)
+ 0.3V)
+ 0.3V)
MAX128_BCUP.................................................. 0°C to +70°C
MAX128_BEUP............................................... -40°C to +85°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
Soldering Temperature (reflow) ...................................... +260°C
DD1
DD1
DD2
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (T = +70°C)
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX1280
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
LSB
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
1.0
1.0
6.0
7.0
DNL
No missing codes over temperature
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
0.8
0.1
ppm/°C
LSB
Channel-to-Channel Offset-Error
Matching
DYNAMIC SPECIFICATIONS (100kHz sine-wave input, 2.5Vp-p, 400ksps, 6.4MHz clock, bipolar input mode)
Signal-to-Noise plus Distortion
Ratio
SINAD
70
dB
Total Harmonic Distortion
Spurious-Free Dynamic Range
Intermodulation Distortion
THD
SFDR
IMD
Up to the 5th harmonic
-81
80
76
dB
dB
dB
f
f
= 99kHz, f
= 102kHz
2
IN
1
IN
Channel-to-Channel Crosstalk
(Note 4)
= 200kHz, V = 2.5Vp-p
-78
dB
IN
IN
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
-3dB point
6
MHz
kHz
SINAD > 68dB
350
t
2.5
µs
ns
CONV
t
468
ACQ
10
ns
Aperture Jitter
<50
ps
Serial Clock Frequency
Duty Cycle
f
0.5
40
6.4
60
MHz
ꢀ
SCLK
2
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1280 (continued)
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUTS (CH7–CH0, COM)
Unipolar, V
= 0
V
REF
COM
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
CH_
V
Bipolar, V
or V
= V
/2,
REF
COM
CH_
V /2
REF
referenced to COM or CH_
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0 or V
µA
pF
0.001
18
1
CH_
DD1
INTERNAL REFERENCE
REF Output Voltage
V
REF
T
A
= +25°C
2.480
2.500 2.520
30
V
REF Short-Circuit Current
mA
REF Output Temperature
Coefficient
TC V
15
ppm/°C
REF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
0 to 1mA output load
0.1
2.0
10
10
mV/mA
µF
4.7
0.01
µF
1.22
50
V
For small adjustments, from 1.22V
To power down the internal reference
mV
REFADJ Buffer Disable
Threshold
1.33
1.0
V
V
DD1
Buffer Voltage Gain
2.05
200
V/V
EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF)
V
+
DD1
50mV
REF Input Voltage Range
(Note 8)
V
V
V
= 2.500V, f
= 2.500V, f
= 6.4MHz
= 0
350
320
5
REF
SCLK
REF Input Current
µA
REF
SCLK
In power-down, f
= 0
SCLK
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
V
3.0
V
V
INH
V
0.8
1
INL
V
HYST
0.2
15
V
I
V
IN
= 0 or V
DD2
µA
pF
IN
Input Capacitance
C
IN
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
V
I
I
= 5mA
0.4
10
V
V
OL
SINK
Output Voltage High
V
OH
= 1mA
SOURCE
4
Three-State Leakage Current
I
µA
pF
CS = 5V
CS = 5V
L
Three-State Output Capacitance
C
15
OUT
_______________________________________________________________________________________
3
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1280 (continued)
(V
= V
= +4.5V to +5.5V, COM = GND, f
= 6.4MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (400ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLY
Positive Supply Voltage
(Note 9)
V
DD1
,
4.5
5.5
V
DD2
Operating mode (Note 10)
Reduced-power mode (Note 11)
Fast power-down (Note 11)
Full power-down (Note 11)
= 5V 10ꢀ, midscale input
DD2
2.5
1.3
0.9
2
4.0
2.0
1.5
10
mA
I
V
V
=
VDD1 +
DD1
DD2
Supply Current
I
= 5.5V
VDD2
µA
Power-Supply Rejection
PSR
V
DD1
= V
0.5
2.0
mV
ELECTRICAL CHARACTERISTICS—MAX1281
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
LSB
LSB
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
1.0
1.0
6.0
7.0
DNL
No missing codes over temperature
Gain Error (Note 3)
Gain-Error Temperature
Coefficient
1.6
0.2
ppm/°C
LSB
Channel-to-Channel Offset-
Error Matching
DYNAMIC SPECIFICATIONS (75kHz sine-wave input, 2.5Vp-p, 300ksps, 4.8MHz clock, bipolar input mode)
Signal-to-Noise plus
Distortion Ratio
SINAD
THD
70
-81
80
dB
dB
dB
dB
dB
Total Harmonic Distortion
Up to the 5th harmonic
Spurious-Free Dynamic
Range
SFDR
IMD
Intermodulation Distortion
f
f
= 73kHz, f
= 77kHz
76
IN2
IN1
Channel-to-Channel Crosstalk
(Note 4)
= 150kHz, V = 2.5Vp-p
-78
IN
IN
Full-Power Bandwidth
Full-Linear Bandwidth
-3dB point
3
MHz
kHz
SINAD > 68dB
250
4
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1281 (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
CONVERSION RATE
Conversion Time (Note 5)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
Normal operating mode
3.3
µs
ns
CONV
Track/Hold Acquisition Time
Aperture Delay
t
Normal operating mode
625
ACQ
10
ns
Aperture Jitter
< 50
ps
Serial Clock Frequency
Duty Cycle
f
Normal operating mode
0.5
40
4.8
60
MHz
ꢀ
SCLK
ANALOG INPUTS (CH7–CH0, COM)
Unipolar, V
= 0
V
REF
COM
Input Voltage Range, Single-
Ended and Differential (Note 6)
V
CH_
V
Bipolar, V
or V
= V
/2,
REF
COM
CH_
V /2
REF
referenced to COM or CH_
Multiplexer Leakage Current
Input Capacitance
On/off leakage current, V
= 0 or V
µA
pF
0.001
18
1
CH_
DD1
INTERNAL REFERENCE
REF Output Voltage
V
REF
T
A
= +25°C
2.480
2.500 2.520
15
V
REF Short-Circuit Current
mA
REF Output Temperature
Coefficient
TC V
15
ppm/°C
REF
Load Regulation (Note 7)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Input Range
0 to 0.75mA output load
0.1
2.0
10
10
mV/mA
µF
4.7
0.01
µF
1.22
50
V
For small adjustments, from 1.22V
To power down the internal reference
mV
REFADJ Buffer Disable
Threshold
1.33
1.0
V
- 1
+
V
DD1
Buffer Voltage Gain
2.05
200
V/V
EXTERNAL REFERENCE (Reference buffer disabled, reference applied to REF)
V
DD1
50mV
REF Input Voltage Range
(Note 8)
V
V
V
= 2.500V, f
= 2.500V, f
= 4.8MHz
= 0
350
320
5
REF
SCLK
REF Input Current
µA
REF
SCLK
In power-down, f
= 0
SCLK
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage
V
2.0
V
V
INH
V
0.8
1
INL
V
HYST
0.2
15
V
I
V
IN
= 0 or V
DD2
µA
pF
IN
Input Capacitance
C
IN
_______________________________________________________________________________________
5
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
ELECTRICAL CHARACTERISTICS—MAX1281 (continued)
(V
= V
= +2.7V to +3.6V, COM = GND, f
= 4.8MHz, 50ꢀ duty cycle, 16 clocks/conversion cycle (300ksps), external
DD1
DD2
SCLK
+2.5V at REF, REFADJ = V
, T = T
DD1
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX
A
MIN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.4
UNITS
DIGITAL OUTPUTS (DOUT, SSTRB)
Output Voltage Low
V
OL
I
I
= 5mA
= 0.5mA
V
V
SINK
Output Voltage High
V
OH
V
- 0.5V
SOURCE
DD2
Three-State Leakage Current
I
L
10
µA
CS = 3V
Three-State Output
Capacitance
C
OUT
15
pF
CS = 3V
POWER SUPPLY
Positive Supply Voltage
(Note 9)
V
V
,
DD1
2.7
3.6
V
DD2
Operating mode
2.5
1.3
0.9
2
3.5
2.0
1.5
10
Reduced-power mode (Note 11)
Fast power-down (Note 11)
Full power-down (Note 11)
= 2.7V to 3.6V, midscale input
DD2
mA
I
+
VDD2
V
V
=
VDD1
I
DD1
DD2
Supply Current (Note 10)
Power-Supply Rejection
= 3.6V
µA
mV
PSR
V
DD1
= V
0.5
2.0
TIMING CHARACTERISTICS—MAX1280
(Figures 1, 2, 6, 7; V
= V
= +4.5V to +5.5V; T = T
to T
; unless otherwise noted.)
MAX
DD1
DD2
A
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
156
62
62
35
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
t
CH
t
CL
DS
DH
t
t
t
35
0
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall Ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CS Rise to DOUT Disable
CS Rise to SSTRB Disable
CS Fall to DOUT Enable
CS Fall to SSTRB Enable
CS Pulse Width High
CSS
t
CSH
CSO
t
35
35
10
10
t
CS1
t
t
t
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
20
20
DOH
t
STH
80
80
65
65
65
65
DOV
t
STV
10
10
DOD
t
STD
t
DOE
t
STE
t
100
CSW
6
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
TIMING CHARACTERISTICS—MAX1281
(Figures 1, 2, 6, 7; V
= V
= +2.7V to +3.6V; T = T
to T
; unless otherwise noted.)
MAX
DD1
DD2
A
MIN
PARAMETER
SCLK Period
SYMBOL
CONDITIONS
MIN
208
83
83
45
0
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
DIN to SCLK Setup
DIN to SCLK Hold
t
CH
t
CL
DS
DH
t
t
t
45
0
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Rise to CS Fall ignore
CS Rise to SCLK Rise Ignore
SCLK Rise to DOUT Hold
SCLK Rise to SSTRB Hold
SCLK Rise to DOUT Valid
SCLK Rise to SSTRB Valid
CS Rise to DOUT Disable
CS Rise to SSTRB Disable
CS Fall to DOUT Enable
CS Fall to SSTRB Enable
CS Pulse Width High
CSS
t
CSH
CSO
t
45
45
13
1
t
CS1
t
t
t
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
= 20pF
20
20
DOH
t
STH
100
100
85
DOV
t
STV
13
13
DOD
t
85
STD
t
85
DOE
t
85
STE
t
100
CSW
Note 1: MAX1280 tested at V
= V
= +5V, MAX1281 tested at V
= V
= +3V; COM = GND; unipolar single-ended
DD2
DD1
DD2
DD1
input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nulled.
Note 3: Offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50ꢀ duty cycle.
Note 6: The absolute voltage range for the analog inputs (CH7–CH0, and COM) is from GND to V
.
DD1
Note 7: External load should not change during conversion for specified accuracy. Guaranteed specification of 2mV/mA is a result
of production test limitations.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Electrical characteristics are guaranteed from V
= V
to V
= V
. For operations beyond
DD2(MAX)
DD1(MIN)
DD2(MIN)
DD1(MAX)
this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory.
Note 10: A = midscale. Unipolar mode MAX1280 tested with 20pF on DOUT, 20pF on SSTRB, and f = 6.4MHz, 0 to 5V.
IN
.
SCLK
MAX1281 tested with same loads, f
= 4.8MHz, 0 to 3V. DOUT = FFF hex.
SCLK
Note 11:
PD1
PD0
MODE
0
0
1
1
0
1
0
1
Full power-down.
Fast power-down.
Reduced power mode.
Normal operation (operating mode).
_______________________________________________________________________________________
7
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics
(MAX1280: V
= V
= 5.0V, f
= 6.4MHz; MAX1281: V
= V
= 3.0V, f
= 4.8MHz; C
= 20pF, 4.7µF capacitor
DD1
DD2
SCLK
DD1
DD2
SCLK
LOAD
at REF, 0.01µF capacitor at REFADJ, T = +25°C, unless otherwise noted.)
A
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (CONVERTING)
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
0
0.6
0.4
0.2
0
3.5
3.0
2.5
2.0
-0.2
-0.4
-0.6
-0.1
-0.2
-0.3
1.5
2.5
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500
DIGITAL OUTPUT CODE
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
(STATIC)
SUPPLY CURRENT vs. SUPPLY
VOLTAGE (STATIC)
SUPPLY CURRENT vs. TEMPERATURE
2.5
2.0
1.5
1.0
0.5
0
3.2
3.0
2.8
2.6
2.4
2.2
2.0
2.5
2.0
1.5
1.0
0.5
0
MAX1280 (PD1 = 1, PD0 = 1)
MAX1281 (PD1 = 1, PD0 = 1)
MAX1280 (PD1 = 1, PD0 = 0)
MAX1281 (PD1 = 1, PD0 = 0)
NORMAL OPERATION (PD1 = PD0 = 1)
REDP (PD1 = 1, PD0 = 0)
MAX1280
FASTDP (PD1 = 0, PD0 = 1)
MAX1281
MAX1280 (PD1 = 0, PD0 = 1)
MAX1281 (PD1 = 0, PD0 = 1)
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
5
4
3
2
1
0
2.5
2.0
1.5
1.0
0.5
0
2.5005
2.5003
2.5001
2.4999
2.4997
2.4995
(PD1 = PD0 = 0)
(PD1 = PD0 = 0)
MAX1280
MAX1281
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40 -20
0
20
40
60
80 100
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Typical Operating Characteristics (continued)
(MAX1280: V
= V
= 5.0V, f
= 6.4MHz; MAX1281: V
= V
= 3.0V, f
= 4.8MHz; C
= 20pF, 4.7µF capacitor
DD1
DD2
SCLK
DD1
DD2
SCLK
LOAD
at REF, 0.01µF capacitor at REFADJ, T = +25°C, unless otherwise noted.)
A
REFERENCE VOLTAGE
vs. TEMPERATURE
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
2.5002
2.5000
2.4998
2.4996
2.4994
2.4992
2.4990
2.4988
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-2.5
MAX1280
MAX1281
-0.5
-1.0
-1.5
-2.0
-2.5
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
-40 -20
0
20
40
60
80 100
V
DD
(V)
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
1
0
0.5
0
MAX1281
-0.5
-1.0
-1.5
-2.0
-1
-2
-3
2.7
3.0
3.3
3.6
-40
-15
10
35
60
85
V
(V)
TEMPERATURE (°C)
DD
_______________________________________________________________________________________
9
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to 0.5LSB.
9
COM
Active-Low Shutdown Input. Pulling SHDN low shuts down the device, reducing supply current to 2µA
(typ).
10
SHDN
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode, the reference buffer provides a +2.500V nominal output, externally
adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to
11
REF
V
.
DD1
12
13
14
REFADJ
GND
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to V
.
DD1
Analog and Digital Ground
DOUT
Serial Data Output. Data is clocked out at SCLK’s rising edge. High impedance when CS is high.
Serial Strobe Output. SSTRB pulses high for one clock period before the MSB decision. High imped-
ance when CS is high.
15
16
17
SSTRB
DIN
Serial Data Input. Data is clocked in at SCLK’s rising edge.
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
and SSTRB are high impedance.
CS
Serial Clock Input. Clocks data in and out of the serial interface and sets the conversion speed. (Duty
cycle must be 40ꢀ to 60ꢀ.)
18
SCLK
19
20
V
V
Positive Supply Voltage
Positive Supply Voltage
DD2
DD1
V
DD2
V
DD2
6k
6k
DOUT
DOUT
DOUT
DOUT
C
20pF
C
LOAD
20pF
LOAD
C
20pF
C
LOAD
20pF
LOAD
6k
6k
GND
GND
GND
a) High-Z to V and V to V
GND
b) High-Z to V and V to V
OL
OL
OH
OH
OL
OH
a) V to High-Z
b) V to High-Z
OL
OH
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
10 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
in order to maintain 0.5LSB accuracy. Assuming a sinu-
soidal signal at IN-, the input voltage is determined by:
Detailed Description
The MAX1280/MAX1281 analog-to-digital converters
(ADCs) use a successive-approximation conversion tech-
nique and input track/hold (T/H) circuitry to convert an
analog signal to a 12-bit digital output. A flexible serial
interface provides easy interface to microprocessors
(µPs). Figure 3 shows a functional diagram of the
MAX1280/MAX1281.
ν
= V
sin(2πft)
(
)
IN-
IN-
The maximum voltage variation is determined by:
dν
IN-
1LSB
t
CONV
V
REF
max
= V
2πf ≤
=
(
)
IN-
12
d
t
2
t
CONV
A 650mVp-p 60Hz signal at IN- will generate 0.5LSB
of error when using a +2.5V reference voltage and a
Pseudo-Differential Input
The equivalent input circuit of Figure 4 shows the
MAX1280/MAX1281’s input architecture, which is com-
posed of a T/H, input multiplexer, input comparator,
switched-capacitor DAC, and reference.
2.5µs conversion time (15/f
). When a DC reference
SCLK
voltage is used at IN-, connect a 0.1µF capacitor to
GND to minimize noise at the input.
During the acquisition interval, the channel selected as
In single-ended mode, the positive input (IN+) is con-
nected to the selected input channel and the negative
input (IN-) is set to COM. In differential mode, IN+ and
IN- are selected from the following pairs: CH0/CH1,
CH2/CH3, CH4/CH5, and CH6/CH7. Configure the
channels according to Tables 2 and 3.
the positive input (IN+) charges capacitor C
. The
HOLD
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on C
as a sample of the signal at IN+. The conver-
HOLD
The MAX1280/MAX1281 input configuration is pseudo-
differential in that only the signal at IN+ is sampled. The
return side (IN-) is connected to the sampling capacitor
while converting and must remain stable within 0.5LSB
( 0.1LSB for best results) with respect to GND during a
conversion.
sion interval begins with the input multiplexer switching
from IN+ to IN-. This unbalances node ZERO at
C
HOLD
the comparator’s input. The capacitive DAC adjusts
during the remainder of the conversion cycle to restore
node ZERO to V
/2 within the limits of 12-bit
DD1
resolution. This action is equivalent to transferring a
12pF x (V + - V -) charge from C to the binary-
If a varying signal is applied to the selected IN-, its ampli-
tude and frequency must be limited to maintain accuracy.
The following equations determine the relationship
between the maximum signal amplitude and its frequency
IN
IN
HOLD
weighted capacitive DAC, which in turn forms a digital
representation of the analog input signal.
GND
17
18
CS
CAPACITATIVE
SCLK
DAC
REF
INPUT
MUX
INPUT
SHIFT
REGISTER
INT
CLOCK
16
10
DIN
C
12pF
CONTROL
LOGIC
HOLD
CH0
CH1
SHDN
COMPARATOR
ZERO
1
2
3
4
5
6
7
8
14
15
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
OUTPUT
SHIFT
DOUT
C
*
SWITCH
6pF
R
IN
REGISTER
SSTRB
800Ω
ANALOG
INPUT
MUX
HOLD
TRACK
T/H
CLOCK
CH6
CH7
IN
12-BIT
SAR
ADC
AT THE SAMPLING INSTANT,
CH6
CH7
THE MUX INPUT SWITCHES FROM
THE SELECTED IN+ CHANNEL TO
THE SELECTED IN- CHANNEL.
OUT
20
19
REF
V
V
DD1
DD2
9
COM
A ≈ 2.05*
17kΩ
+1.22V
REFERENCE
V
DD1
/2
13
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM
PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
GND
12
11
REFADJ
REF
MAX1280
MAX1281
+2.500V
*INCLUDES ALL INPUT PARASITICS
Figure 3. Functional Diagram
Figure 4. Equivalent Input Circuit
______________________________________________________________________________________ 11
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM and the converter con-
verts the “+” input. If the converter is set up for differen-
tial inputs, the difference of [(IN+) - (IN-)] is converted.
At the end of the conversion, the positive input con-
Input Bandwidth
The ADC’s input tracking circuitry has a 6MHz
(MAX1280) or 3MHz (MAX1281) small-signal band-
width, so it is possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. To avoid high-frequency signals
being aliased into the frequency band of interest, anti-
alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
nects back to IN+ and C
nal.
charges to the input sig-
HOLD
input to V
and GND, allow the channel input pins to
DD1
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
swing from GND - 0.3V to V
+ 0.3V without dam-
DD1
age. However, for accurate conversions near full scale,
the inputs must not exceed V
be lower than GND by 50mV.
by more than 50mV or
DD1
If the analog input exceeds 50mV beyond the sup-
plies, do not allow the input current to exceed 2mA.
t
, is the maximum time the device takes to acquire
ACQ
the signal and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
Quick Look
To quickly evaluate the MAX1280/MAX1281’s analog
performance, use the circuit of Figure 5. The MAX1280/
MAX1281 require a control byte to be written to DIN
✕
✕
t
= 9 (R + R ) 12pF
S IN
ACQ
where R = 800Ω, R = the source impedance of the
IN
S
before each conversion. Connecting DIN to V
feeds
DD2
input signal; t
is never less than 468ns (MAX1280)
ACQ
in control bytes of $FF (HEX), which trigger single-
ended unipolar conversions on CH7 without powering
down between conversions. The SSTRB output pulses
or 625ns (MAX1281). Note that source impedances
below 2kΩ do not significantly affect the ADC’s AC per-
formance.
OSCILLOSCOPE
V
+3V or +5V
DD1
MAX1280
MAX1281
SCLK
0.1µF
10µF
V
DD2
0V TO
2.500V
ANALOG
INPUT
GND
COM
CH7
0.01µF
0.01µF
SSTRB
DOUT*
CS
SCLK
DIN
REFADJ
REF
TO V
DD2
EXTERNAL CLOCK
DOUT
SSTRB
2.5V
CH1
CH2
CH3
CH4
SHDN
TO V
4.7µF
DD2
*FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit
12 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
t
ACQ
SCLK
1
4
8
9
12
16
20
24
SGL/
DIF
SEL SEL SEL UNI/
DIN
PD1 PD0
2
1
0
BIP
START
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
SSTRB
RB1
RB2
RB3
DOUT
B11 B10 B9 B8 B7
B6
B5 B4 B3 B2 B1 B0
ACQUISITION
IDLE
CONVERSION
IDLE
Figure 6. Single-Conversion Timing
high for one clock period before the MSB of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 16 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
typically occur 20ns after the rising edge of SCLK.
clock frequency from 500kHz to 6.4MHz (MAX1280) or
4.8MHz (MAX1281).
1) Set up the control byte and call it TB1. TB1 should
be of the format 1XXXXXXX binary, where the Xs
denote the particular channel, selected conversion
mode, and power mode.
2) Use a general-purpose I/O line on the CPU to pull
Starting a Conversion
Start a conversion by clocking a control byte into DIN.
With CS low, each rising edge on SCLK clocks a bit from
DIN into the MAX1280/MAX1281’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with no
effect. Table 1 shows the control-byte format.
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simultane-
ously, receive byte RB3.
The MAX1280/MAX1281 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the Typical Operating Circuit, the
simplest software interface requires only three 8-bit
transfers to perform a conversion (one 8-bit transfer to
configure the ADC, and two more 8-bit transfers to
clock out the 12-bit conversion result). See Figure 17
for MAX1280/MAX1281 QSPI connections.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion, padded
with three leading zeros and one trailing zero. The total
conversion time is a function of the serial-clock fre-
quency and the amount of idle time between 8-bit
transfers. To avoid excessive T/H droop, make sure the
total conversion time does not exceed 120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar input mode, the output is two’s
complement (Figure 15). Data is clocked out on the ris-
ing edge of SCLK in MSB-first format.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode, so the CPU generates the serial clock. Choose a
______________________________________________________________________________________ 13
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 1. Control-Byte Format
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
BIT
NAME
DESCRIPTION
7 (MSB)
START
The first logic “1” bit after CS goes low defines the beginning of the control byte.
6
5
4
SEL2
SEL1
SEL0
These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
3
UNI/BIP
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0 to V
can be converted; in bipolar mode, the differential signal can
REF
range from -V
/2 to +V
REF
/2.
REF
2
SGL/DIF
1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1
PD1
PD0
Select operating mode.
0 (LSB)
PD1
PD0
Mode
0
0
1
1
0
1
0
1
Full power-down
Fast power-down
Reduced Power
Normal Operation
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
0
0
+
–
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
+
–
–
–
–
–
–
–
+
+
+
+
+
+
Table 3. Channel Selection in Psuedo-Differential Mode (SGL/DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+
–
+
–
+
–
+
–
–
–
+
–
+
–
+
+
14 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
t
CSW
t
CSS
t
CH
t
CP
t
CSH
t
t
t
CL
CSO
CS1
SCLK
t
DS
t
DH
t
DOH
DIN
t
t
DOV
DOD
t
DOE
DOUT
t
STH
t
t
STD
STV
t
STE
SSTRB
Figure 7. Detailed Serial-Interface Timing
Serial Clock
The fastest the MAX1280/MAX1281 can run with CS
held low between conversions is 16 clocks per conver-
sion. Figure 8 shows the serial-interface timing neces-
sary to perform a conversion every 16 SCLK cycles. If
CS is tied low and SCLK is continuous, guarantee a
start bit by first clocking in 16 zeros.
The external serial clock not only shifts data in and out,
but also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the next
12 SCLK falling edges (Figure 6). SSTRB and DOUT go
into a high-impedance state when CS goes high; after
the next CS rising edge, SSTRB outputs a logic low.
Figure 7 shows the detailed serial-interface timing.
Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1280/MAX1281 in normal operating mode, ready to
convert with SSTRB = low. The MAX1280/MAX1281
require 10µs to reset after the power supplies stabilize;
no conversions should be initiated during this time. If
CS is low, the first logic 1 on DIN is interpreted as a
start bit. Until a conversion takes place, DOUT shifts out
zeros. Additionally, wait for the reference to stabilize
when using the internal reference.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on SCLK’s falling edge after the eighth bit of
the control byte (the PD0 bit) is clocked into DIN. The
start bit is defined as follows:
Power Modes
You can save power by placing the converter in one of
the two low-current operating modes or in full power-
down between conversions. Select the power mode
through bit 1 and bit 0 of the DIN control byte (Tables 1
and 4), or force the converter into hardware shutdown
by driving SHDN to GND.
The first high bit clocked into DIN with CS low any
time the converter is idle, e.g., after V
are applied.
and V
DD2
DD1
OR
The first high bit clocked into DIN after bit 6 of a con-
version in progress is clocked onto the DOUT pin.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
Once a start bit has been recognized, the current con-
version may only be terminated by pulling SHDN low.
______________________________________________________________________________________ 15
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
S
CONTROL BYTE 2
S
ETC
1
8
12
16 1
5
8
12
16
1
5
8
12
16
1
5
SCLK
HIGH-Z
HIGH-Z
B11
B6
CONVERSION RESULT 0
B0
B11
B6
CONVERSION RESULT 1
B0
B11
B6
DOUT
SSTRB
Figure 8. Continuous 16-Clock/Conversion Timing
Table 4. Software-Controlled Power Modes
TOTAL SUPPLY CURRENT
CIRCUIT SECTIONS*
PD1/PD0
MODE
AFTER
CONVERSION
CONVERTING
INPUT COMPARATOR
REFERENCE
Full Power-Down
(FULLPD)
00
01
2.5mA
2.5mA
2µA
Off
Off
Fast Power-Down
(FASTPD)
0.9mA
Reduced Power
On
Reduced-Power
Mode (REDPD)
10
11
2.5mA
2.5mA
1.3mA
2.0mA
Reduced Power
Full Power
On
On
Operating Mode
*Circuit operation between conversions; during conversion, all circuits are fully powered up.
progress. In software power-down mode, the serial
interface remains active, waiting for a new control byte
to start conversion and switch to full-power mode.
Once the conversion is completed, the device goes
into the programmed power mode until a new control
byte is written.
up delay from a full power-down (software or hard-
ware), as shown in Figure 9.
Software Power-Down
Software power-down is activated using bits PD1 and
PD0 of the control byte. When software shutdown is
asserted, the ADC completes the conversion in
progress and powers down into the specified low-
quiescent-current state (2µA, 0.9mA, or 1.3mA).
The power-up delay is dependent on the power-down
state. Software low-power modes will be able to start
conversion immediately when running at decreased
clock rates (see Power-Down Sequencing). During
power-on reset, when exiting software full power-down
mode or exiting hardware shutdown, the device goes
immediately into full-power mode and is ready to con-
vert after 2µs when using an external reference. When
using the internal reference, wait for the typical power-
The first logic 1 on DIN is interpreted as a start bit and
puts the MAX1280/MAX1281 into their full-power mode.
Following the start bit, the data input word or control
byte also determines the next power-down state. For
example, if the DIN word contains PD1 = 0 and PD0 =
1, a 0.9mA power-down starts after the conversion.
16 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 4 details the four power modes with the corre-
sponding supply current and operating sections. For
data rates achievable in software power-down modes,
see Power-Down Sequencing section.
less than maximum sample rates. Figures 10 and 11
show the average supply current as a function of the
sampling rate.
Using Full Power-Down Mode
Full power-down mode (FULLPD) achieves the lowest
power consumption at up to 1000 conversions per
channel per second. Figure 10a shows the MAX1281’s
power consumption for 1- or 8-channel conversions
using full power-down mode (PD1 = PD0 = 0), with the
internal reference and the maximum clock speed. A
0.01µF bypass capacitor plus the internal 17kΩ refer-
ence resistor at REFADJ forms an RC filter with a 200µs
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up if the
bypass capacitor is fully discharged between conver-
sions. Waiting this 2ms in FASTPD mode or reduced-
power mode (REDP) instead of full power-down mode
can further reduce power consumption. This is
achieved by using the sequence shown in Figure 12a.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike software power-down mode, the
conversion is terminated immediately. When returning
to normal operation from SHDN with an external refer-
ence, the MAX1280/MAX1281 can be considered fully
powered-up within 2µs of actively pulling SHDN high.
When using the internal reference, the conversion
should be initiated only after the reference has settled;
its recovery time depends on the external bypass
capacitors and shutdown duration.
Power-Down Sequencing
The MAX1280/MAX1281’s automatic power-down
modes can save considerable power when operating at
Figure 10b shows the MAX1281’s power consumption
for 1- or 8-channel conversions using FULLPD mode
(PD1 = PD0 = 0), an external reference, and the maxi-
mum clock speed. One dummy conversion to power-up
the device is needed, but no wait-time is necessary to
start the second conversion, thereby achieving lower
power consumption at up to the full sampling rate.
1.50
1.25
1.00
0.75
0.50
0.25
0
Using Fast Power-Down and
Reduced-Power Modes
FASTPD and REDP modes achieve the lowest power
consumption at speeds close to the maximum sample
rate. Figure 11 shows the MAX1281’s power consump-
tion in FASTPD mode (PD1 = 0, PD0 = 1), REDP mode
(PD1 = 1, PD0 = 0), and (for comparison) normal
operating mode (PD1 = 1, PD0 = 1). The figure shows
0.0001 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 9. Reference Power-Up Delay vs. Time in Shutdown
10,000
1000
MAX1281
MAX1281
V
= V = 3.0V
DD2
V
= V
= 3.0V
= 20pF
DD1
DD1 DD2
C
= 20pF
C
LOAD
LOAD
1000
100
10
CODE = 101010000000
CODE = 101010000000
100
8 CHANNELS
8 CHANNELS
10
1
1 CHANNEL
1 CHANNEL
1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
SAMPLING RATE (sps)
SAMPLING RATE (sps)
Figure 10a. Average Supply Current vs. Sample Rate (Using
FULLPD and Internal Reference)
Figure 10b. Average Supply Current vs. Sampling Rate (Using
FULLPD and External Reference)
______________________________________________________________________________________ 17
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
power consumption using the specified power-down
mode, with the internal reference and the maximum
clock speed. The clock speed in FASTPD or REDP
should be limited to 4.8MHz for the MAX1280/
MAX1281. FULLPD mode may provide increased power
savings in applications where the MAX1280/
MAX1281 are inactive for long periods of time, but
where intermittent bursts of high-speed conversions are
required.
Internal and External References
The MAX1280/MAX1281 can be used with an internal
or external reference. An external reference can be
connected directly at REF or at the REFADJ pin.
2.5
NORMAL OPERATION
An internal buffer is designed to provide 2.5V at REF for
both the MAX1280/MAX1281. The internally trimmed
1.22V reference is buffered with a gain of +2.05V/V.
2.0
REDP
FASTPD
1.5
1.0
Internal Reference
The MAX1280/MAX1281’s full-scale range with the inter-
nal reference is 2.5V for unipolar inputs and 1.25V for
bipolar inputs. The internal reference voltage is
adjustable to 100mV with the circuit of Figure 13.
MAX1281, V = V = 3.0V
DD1
DD2
C
LOAD
= 20pF
CODE = 101010000000
0.5
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the internal reference-
buffer amplifier. The REFADJ input impedance is typical-
ly 17kΩ. At REF, the DC input resistance is a minimum of
50
200
SAMPLING RATE (sps)
150
250
0
100
300 350
Figure 11. Average Supply Current vs. Sampling Rate (Using
REPD, FASTPD, and Normal Operation and Internal Reference)
WAIT 2ms (10 x RC)
0
0
1
0
0
0
1
1
1
1
DIN
FULLPD
REDP
FULLPD
1.22V
DUMMY CONVERSION
1.22V
2.5V
RE FADJ
0V
0V
γ = RC = 17kΩx 0.01µF
2.5V
REF
2.5mA
2.5mA
2.5mA
I
+ I
VDD1 VDD2
1.3mA OR 0.9mA
0mA
0mA
Figure 12a. Full Power-Down Timing
1
0
1
0
0
1
1
1
1
DIN
REDPD
REDP
FASTPD
2.5mA
2.5V (ALWAYS ON)
2.5mA
REF
2.5mA
0.9mA
1.3mA
1.3mA
I
+ I
VDD1 VDD2
Figure 12b. Reduced-Power/Fast Power-Down Timing
18 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
+3.3V
OUTPUT CODE
24kΩ
V
REF
2
FS
=
+ V
COM
MAX1281
REFADJ
011 . . . 111
011 . . . 110
510kΩ
ZS = COM
100kΩ
12
-V
2
REF
-FS =
+ V
COM
000 . . . 010
000 . . . 001
000 . . . 000
0.01µF
V
REF
1 LSB =
4096
111 . . . 111
111 . . . 110
111 . . . 101
Figure 13. MAX1281 Reference-Adjust Circuit
100 . . . 001
100 . . . 000
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
COM*
INPUT VOLTAGE (LSB)
- FS
+FS - 1LSB
11 . . . 110
11 . . . 101
≤
V
*V
/ 2
REF
COM
Figure 15. Bipolar Transfer Function, Full Scale (FS) =
/ 2 + V , Zero Scale (ZS) = V
FS = V + V
REF
COM
V
REF
COM
COM
ZS = V
COM
tions occur halfway between successive-integer LSB
values. Output coding is binary, with 1LSB = 610µV
for unipolar and bipolar operation.
V
4096
REF
1 LSB =
00 . . . 011
00 . . . 010
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards; wire-
wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
00 . . . 001
00 . . . 000
0
1
2
3
FS
(COM)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
Figure 14. Unipolar Transfer Function, Full Scale (FS) = V
REF
+ V
, Zero Scale (ZS) = V
COM
COM
Figure 16 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at GND. Connect all analog grounds
to the star ground. Connect the digital system ground
to star ground at this point only. For lowest-noise opera-
tion, the ground return to the star ground’s power sup-
ply should be low impedance and as short as possible.
18kΩ. During conversion, an external reference at REF
must deliver up to 350µA DC load current and have 10Ω
or less output impedance. If the reference has a higher
output impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct REF input,
disable the internal buffer by connecting REFADJ to
High-frequency noise in the V
power supply may
DD1
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 10µF
capacitors, located close to pin 20 of the MAX1280/
MAX1281. Minimize capacitor lead lengths for best
supply-noise rejection. If the power supply is very
noisy, a 10Ω resistor can be connected as a lowpass
filter (Figure 16).
V
.
DD1
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figure 14 depicts the nominal,
unipolar input/output (I/O) transfer function, and Figure
15 shows the bipolar I/O transfer function. Code transi-
______________________________________________________________________________________ 19
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Table 5. Full Scale and Zero Scale
UNIPOLAR MODE
BIPOLAR MODE
Positive
Full Scale
Zero
Scale
Negative
Full Scale
Full Scale
+ V
Zero Scale
COM
V
REF
/ 2
-V
/ 2
REF
V
COM
V
REF
COM
+ V
+ V
COM
COM
connected with the MAX1280/MAX1281’s SCLK
input.
2) The MAX1280/MAX1281’s CS pin is driven low by
the TMS320’s XF_ I/O port to enable data to be
clocked into the MAX1280/MAX1281’s DIN pin.
SUPPLIES
V
DD1
V
DD2
GND
3) An 8-bit word (1XXXXX11) should be written to the
MAX1280/MAX1281 to initiate a conversion and
place the device into normal operating mode. See
Table 1 to select the proper XXXXX bit values for
your specific application.
R* = 10Ω
4) The MAX1280/MAX1281’s SSTRB output is moni-
tored through the TMS320’s FSR input. A falling
edge on the SSTRB output indicates that the conver-
sion is in progress and data is ready to be received
from the MAX1280/MAX1281.
V
GND
COM
V
DD2
V
DD
DGND
DD1
DIGITAL
CIRCUITRY
MAX1280
MAX1281
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits repre-
sent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
*OPTIONAL
6) Pull CS high to disable the MAX1280/MAX1281 until
Figure 16. Power-Supply Grounding Connection
the next conversion is initiated.
High-Speed Digital Interfacing with QSPI
Definitions
The MAX1280/MAX1281 can interface with QSPI using
the circuit in Figure 17 (f
= 4.0MHz, CPOL = 0,
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1280/MAX1281
are measured using the endpoint method.
SCLK
CPHA = 0). This QSPI circuit can be programmed to do
a conversion on each of the eight channels. The result
is stored in memory without taxing the CPU, since QSPI
incorporates its own microsequencer.
TMS320LC3x Interface
Figure 18 shows an application circuit that interfaces
the MAX1280/MAX1281 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 19.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
Use the following steps to initiate a conversion in the
MAX1280/MAX1281 and to read the results:
1) The TMS320 should be configured with CLKX (trans-
mit clock) as an active-high output clock and with
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
AJ
the time between the samples.
20 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
+3V OR +5V +3V OR +5V
V
V
DD1
1
2
20
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
0.1µF
10µF
(POWER SUPPLIES)
DD2 19
SCLK
CS
SCK
18
17
16
15
14
13
3
4
PCS0
ANALOG
INPUTS
MAX1280
MAX1281
DIN
MC683XX
5
6
MOSI
SSTRB
DOUT
7
MISO
8
GND
9
REFADJ 12
V
10
11
REF
DD1
4.7µF
0.01µF
(GND)
Figure 17. QSPI Connections
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, Signal-to-noise ratio (SNR) is the ratio of full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal theoretical minimum
analog-to-digital noise is caused by quantization error
only and results directly from the ADC’s resolution (N
bits):
XF
CS
CLKX
SCLK
TMS320LC3x
MAX1280
MAX1281
CLKR
✕
SNR = (6.02 N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
DX
DR
DIN
DOUT
SSTRB
FSR
Signal-to-Noise Plus Distortion
Signal-to-noise ratio plus distortion (SINAD) is the ratio
of the fundamental input frequency’s RMS amplitude to
RMS equivalent of all other ADC output signals.
Figure 18. MAX1280/MAX1281-to-TMS320 Serial Interface
✕
SINAD (dB) = 20 log (Signal
/ Noise
)
RMS
RMS
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
falling edge of the sampling clock and the instant when
an actual sample is taken.
______________________________________________________________________________________ 21
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
CS
SCLK
START
SEL2
SEL1
SEL0 UNI/BIP SGI/DIF PD1
PD0
DIN
SSTRB
HIGH IMPEDANCE
HIGH IMPEDANCE
DOUT
B10
B1
MSB
B0
Figure 19. MAX1280/MAX1281-to-TMS320 Serial Interface
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
Typical Operating Circuit
ENOB = (SINAD - 1.76) / 6.02
+5V OR
+3V
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
V
V
V
CH0
DD
DD1
0.1µF
0 TO
+2.5V
DD2
ANALOG
INPUTS
MAX1280
MAX1281
CH8
GND
CPU
COM
CS
⎛
⎞
2
2
2
2
2
V
+ V + V + V + V
3 4 4 5
2
⎜
⎟
I/O
REF
⎝
⎠
4.7µF
THD = 20 × log
SCLK
DIN
SCK (SK)
MOSI (SO)
MISO (SI)
V
1
DOUT
SSTRB
SHDN
REFADJ
where V is the fundamental amplitude, and V through
1
2
0.01µF
V5 are the amplitudes of the 2nd- through 5th-order har-
monics, respectively.
V
SS
22 ______________________________________________________________________________________
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 TSSOP
U20+2
21-0066
______________________________________________________________________________________ 23
400ksps/300ksps, Single-Supply, Low-Power, 8-Channel,
Serial 12-Bit ADCs with Internal Reference
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
5/00
Initial release
—
Changed specifications due to single pass flow qualifications and added lead-
free information
1
2
4/10
1–5
Changed multiplexer leakage current condition, added note to supply current
condition, changed Note 11, changed Figures 4 and 12b
10/10
5, 6, 7, 11, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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