MAX1294ACEI+T [MAXIM]
ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, 0.025 INCH PITCH, QSOP-28;
| 型号： | MAX1294ACEI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | ADC, Successive Approximation, 12-Bit, 1 Func, 6 Channel, Parallel, Word Access, PDSO28, 0.150 INCH, 0.025 INCH PITCH, QSOP-28 光电二极管 转换器 |
| 文件： | 总19页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1533; Rev 2; 12/02
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
General Description
Features
The MAX1294/MAX1296 low-power, 12-bit analog-to-
digital converters (ADCs) feature a successive-approxi-
mation ADC, automatic power-down, fast wake-up
(2µs), an on-chip clock, +2.5V internal reference, and a
high-speed 12-bit parallel interface. They operate with
a single +5V analog supply.
ꢀ 12-Bit Resolution, ±±0. ꢀLB ꢀineꢁaitꢂ
ꢀ Lingle +.V Opeaꢁtion
ꢀ Inteanꢁl +20.V Refeaence
ꢀ Loftwꢁae-Configuaꢁble Anꢁlog Input Multiplexea
6-Chꢁnnel Lingle-Ended/
Power consumption is only 10mW at the maximum sam-
pling rate of 420ksps. Two software-selectable power-
down modes enable the MAX1294/MAX1296 to be shut
down between conversions; accessing the parallel
interface returns them to normal operation. Powering
down between conversions can reduce supply below
10µA at lower sampling rates.
3-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1294)
2-Chꢁnnel Lingle-Ended/
1-Chꢁnnel Pseudo-Diffeaentiꢁl (MAX1296)
ꢀ Loftwꢁae-Configuaꢁble Unipolꢁa/Bipolꢁa
Anꢁlog Inputs
ꢀ ꢀow Cuaaent
208mA (42±ksps)
10±mA (1±±ksps)
4±±µA (1±ksps)
2µA (Lhutdown)
Both devices offer software-configurable analog inputs for
unipolar/bipolar and single-ended/pseudo-differential
operation. In single-ended mode, the MAX1294 has six
input channels and the MAX1296 has two (three input
channels and one input channel, respectively, when in
pseudo-differential mode).
ꢀ Inteanꢁl 6MHz Full-Powea Bꢁndwidth Taꢁck/Hold
ꢀ Pꢁaꢁllel 12-Bit Inteafꢁce
Excellent dynamic performance and low power, com-
bined with ease of use and small package size, make
these converters ideal for battery-powered and data-
acquisition applications or for other circuits with demand-
ing power-consumption and space requirements.
ꢀ Lmꢁll Footpaint
28-Pin QLOP (MAX1294)
24-Pin QLOP (MAX1296)
The MAX1294/MAX1296 tri-states INT when CS goes
high. Refer to MAX1266/MAX1268 if tri-stating INT is not
desired.
Pin Configurations
TOP VIEW
The MAX1294 is offered in a 28-pin QSOP package, while
the MAX1296 is available in a 24-pin QSOP. For pin-com-
patible +3V, 12-bit versions, see the MAX1295/MAX1297.
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
24 D10
23 D11
Applications
Data Logging
22
V
DD
Industrial Control Systems
Energy Management
21 REF
20 REFADJ
19 GND
18 COM
17 CH0
16 CH1
15 CS
Patient Monitoring
Touchscreens
Data-Acquisition Systems
MAX1296
Ordering Information
INꢀ
TEMP RANGE PIN-PACKAGE
(ꢀLB)
PART
MAX1294ACEI
0°C to +70°C
0°C to +70°C
28 QSOP
28 QSOP
28 QSOP
28 QSOP
24 QSOP
24 QSOP
24 QSOP
24 QSOP
0.5
1
D0 10
INT 11
RD 12
MAX1294BCEI
MAX1294AEEI -40°C to +85°C
MAX1294BEEI -40°C to +85°C
0.5
1
14 CLK
13 WR
MAX1296ACEG
0°C to +70°C
0°C to +70°C
0.5
1
QLOP
MAX1296BCEG
MAX1296AEEG -40°C to +85°C
MAX1296BEEG -40°C to +85°C
0.5
1
Pin Configurations continued at end of data sheet.
Typical Operating Circuits appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
ABLOꢀUTE MAXIMUM RATINGL
DD
V
to GꢁD..............................................................-0.3V to +6V
Operating Temperature Ranges
CH0–CH5, COM to GꢁD............................-0.3V to (V
REF, REFADꢂ to GꢁD.................................-0.3V to (V
Digital Inputs to GꢁD ...............................................-0.3V to +6V
+ 0.3V)
+ 0.3V)
MAX1294_C_ _/MAX1296_C_ _.........................0°C to +70°C
MAX1294_E_ _/MAX1296_E_ _ ......................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
Digital Outputs (D0–D11, INT) to GꢁD.......-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
28-Pin QSOP (derate 8.00mW/°C above +70°C)........667mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECTRICAꢀ CHARACTERILTICL
(V
T
= +5V 10ꢀ, COM = GꢁD, REFADꢂ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 7.6MHz (50ꢀ duty cycle),
CLK
DD
DD
REF
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MAX
A
MIꢁ
PARAMETER
LYMBOꢀ
CONDITIONL
MIN
12
TYP
MAX
UNITL
DC ACCURACY (ꢁote 1)
Resolution
RES
IꢁL
Bits
MAX129_A
MAX129_B
0.5
1
Relative Accuracy (ꢁote 2)
LSB
Differential ꢁonlinearity
Offset Error
DꢁL
ꢁo missing codes over temperature
1
LSB
LSB
4
Gain Error (ꢁote 3)
Gain Temperature Coefficient
4
LSB
2.0
0.2
ppm/°C
Channel-to-Channel Offset
Matching
LSB
DYNAMIC LPECIFICATIONL (f
= 50kHz, V = 2.5V , 420ksps, external f
= 7.6MHz, bipolar input mode)
P-P
Iꢁ(sine wave)
SIꢁAD
Iꢁ
CLK
Signal-to-ꢁoise Plus Distortion
67
70
dB
dB
Total Harmonic Distortion
(including 5th-order harmonic)
THD
-80
Spurious-Free Dynamic Range
Intermodulation Distortion
Channel-to-Channel Crosstalk
Full-Linear Bandwidth
SFDR
IMD
-80
dB
dB
f
f
= 49kHz, f
= 52kHz
76
-78
350
6
Iꢁ1
Iꢁ2
= 175kHz (ꢁote 4)
dB
Iꢁ
SIꢁAD > 68dB
-3dB rolloff
kHz
MHz
Full-Power Bandwidth
CONVERLION RATE
External clock mode
2.1
2.5
3.2
Conversion Time (ꢁote 5)
t
External acquisition/internal clock mode
Internal acquisition/internal clock mode
3.0
3.6
3.5
4
µs
COꢁV
T/H Acquisition Time
Aperture Delay
t
400
ns
ns
ACQ
External acquisition or external clock mode
External acquisition or external clock mode
Internal acquisition/internal clock mode
25
<50
<200
Aperture ꢂitter
ps
External Clock Frequency
Duty Cycle
f
0.1
30
7.6
70
MHz
ꢀ
CLK
2
_______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
EꢀECTRICAꢀ CHARACTERILTICL (continued)
(V
T
= +5V 10ꢀ, COM = GꢁD, REFADꢂ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 7.6MHz (50ꢀ duty cycle),
CLK
DD
DD
REF
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MAX
A
MIꢁ
PARAMETER
LYMBOꢀ
CONDITIONL
MIN
TYP
MAX
UNITL
ANAꢀOG INPUTL
Unipolar, V
= 0
0
V
REF
COM
Analog Input Voltage Range
Single-Ended and Differential
(ꢁote 6)
V
Iꢁ
V
Bipolar, V
= V
/ 2
-V
/2
+V /2
REF
COM
REF
REF
Multiplexer Leakage Current
Input Capacitance
On/off-leakage current, V = 0 or V
Iꢁ
0.01
12
1
µA
pF
DD
C
Iꢁ
INTERNAꢀ REFERENCE
REF Output Voltage
2.49
2.5
15
2.51
V
mA
REF Short-Circuit Current
REF Temperature Coefficient
REFADꢂ Input Range
TC
20
ppm/°C
mV
REF
For small adjustments
100
REFADꢂ High Threshold
Load Regulation (ꢁote 7)
Capacitive Bypass at REFADꢂ
Capacitive Bypass at REF
EXTERNAꢀ REFERENCE AT REF
To power down the internal reference
0 to 0.5mA output load
V
- 1
V
DD
0.2
mV/mA
µF
0.01
1
4.7
10
µF
V
+
DD
1.0
REF Input Voltage Range
REF Input Current
V
V
REF
50mV
V
= 2.5V, f
= 420ksps
SAMPLE
200
300
2
µA
µA
REF
I
REF
Shutdown mode
DIGITAꢀ INPUTL AND OUTPUTL
Input Voltage High
V
4.0
V
V
IH
Input Voltage Low
V
0.8
1
IL
Input Hysteresis
V
HYS
200
0.1
15
mV
µA
pF
V
Input Leakage Current
Input Capacitance
I
Iꢁ
V
= 0 or V
DD
Iꢁ
C
Iꢁ
OL
OH
Output Voltage Low
Output Voltage High
V
I
I
= 1.6mA
0.4
1
SIꢁK
V
= 1mA
V
- 0.5
V
SOURCE
DD
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTL
Analog Supply Voltage
I
0.1
15
µA
pF
CS = V
CS = V
LEAKAGE
DD
DD
C
OUT
V
DD
4.5
5.5
3.6
3.1
1.2
0.8
10
V
Internal reference
External reference
Internal reference
External reference
3.3
2.8
1.0
0.5
2
Operating mode,
= 420ksps
f
SAMPLE
mA
DD
Positive Supply Current
Power-Supply Rejection
I
Standby mode
Shutdown mode
µA
PSR
V
DD
= 5V 10ꢀ, full-scale input
0.3
0.9
mV
_______________________________________________________________________________________
3
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
TIMING CHARACTERILTICL
(V
T
= +5V 10ꢀ, COM = GꢁD, REFADꢂ = V , V
= +2.5V, 4.7µF capacitor at REF pin, f
= 7.6MHz (50ꢀ duty cycle),
CLK
DD
DD
REF
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MAX
A
MIꢁ
PARAMETER
LYMBOꢀ
CONDITIONL
MIN
TYP
MAX
UNITL
ns
CLK Period
t
132
40
40
40
0
CP
CH
CLK Pulse Width High
t
ns
CLK Pulse Width Low
t
ns
CL
DS
t
t
ns
Data Valid to WR Rise Time
WR Rise to Data Valid Hold Time
WR to CLK Fall Setup Time
CLK Fall to WR Hold Time
CS to CLK or WR Setup Time
CLK or WR to CS Hold Time
CS Pulse Width
ns
DH
t
t
60
40
40
0
ns
CWS
ns
CWH
t
ns
CSWS
t
ns
CSWH
t
100
60
10
10
10
ns
CS
t
ns
WR Pulse Width (ꢁote 8)
CS Rise to Output Disable
RD Rise to Output Disable
RD Fall to Output Data Valid
RD Fall to INT High Delay
CS Fall to Output Data Valid
WR
t
TC
C
LOAD
C
LOAD
C
LOAD
C
LOAD
C
LOAD
= 20pF, Figure 1
60
40
ns
t
TR
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
= 20pF, Figure 1
ns
t
50
ns
DO
t
50
ns
IꢁT1
t
100
ns
DO2
Note 1: Tested at V
= +5V, COM = GꢁD, unipolar single-ended input mode.
DD
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have
been removed.
Note 3: Offset nulled.
Note 4: On channel is grounded; sine wave applied to off channels.
Note .: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50ꢀ duty cycle.
Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GꢁD to V
Note 7: External load should not change during conversion for specified accuracy.
.
DD
Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
V
DD
3kΩ
DOUT
DOUT
C
LOAD
20pF
C
LOAD
20pF
3kΩ
a) High-Z to V and V to V
OH
b) High-Z to V and V to V
OL
OH
OL
OL
OH
Figure 1. Load Circuits for Enable/Disable Times
4
_______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(V
= +5V, V
= +2.500V, f
= 7.6MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
REF
CLK
L
A
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
SUPPLY CURRENT
vs. SAMPLE FREQUENCY
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
0.5
0.5
0.4
10,000
1000
100
10
0.4
0.3
WITH INTERNAL REFERENCE
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
WITH EXTERNAL REFERENCE
0
1k
0
1000
2000
3000
4000
5000
1
10k 100k
0
1000
2000
3000
4000
5000
0.1
10
100
1M
DIGITAL OUTPUT CODE
DIGITAL OUTPUT CODE
f
(Hz)
SAMPLE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
STANDBY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
2.2
2.1
2.0
990
980
970
960
950
940
930
2.3
2.2
2.1
2.0
1.9
1.8
1.7
R = ∞
R = ∞
L
L
CODE = 101010100000
CODE = 101010100000
1.9
1.8
4.50
4.75
5.00
(V)
5.25
5.50
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
V
V
TEMPERATURE (°C)
DD
DD
POWER-DOWN CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs. TEMPERATURE
STANDBY CURRENT vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
990
980
970
960
950
940
930
2.2
2.1
2.0
1.9
1.8
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
_______________________________________________________________________________________
.
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(V
= +5V, V
= +2.500V, f
= 7.6MHz, C = 20pF, T = +25°C, unless otherwise noted.)
DD
REF
CLK L A
REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
OFFSET ERROR vs. SUPPLY VOLTAGE
2.53
2.53
1.0
0.5
0
2.52
2.51
2.50
2.49
2.48
2.52
2.51
2.50
2.49
2.48
-0.5
-1.0
-40
-15
10
35
60
85
4.50
4.75
5.00
(V)
5.25
5.50
4.50
4.75
5.00
(V)
5.25
5.50
TEMPERATURE (°C)
V
V
DD
DD
GAIN ERROR vs. SUPPLY VOLTAGE
GAIN ERROR vs. TEMPERATURE
OFFSET ERROR vs. TEMPERATURE
2
1
0
2.0
1.5
1.0
0.5
0
2
1
0
-1
-2
-1
-2
4.50
4.75
5.00
(V)
5.25
5.50
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE (°C)
DD
TEMPERATURE (°C)
FFT PLOT
20
0
V
f
= 5V
DD
= 50kHz
IN
f
= 400ksps
SAMPLE
-20
-40
-60
-80
-100
-120
-140
0
200
400
600
800
1000
FREQUENCY (kHz)
6
_______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description
PIN
NAME
FUNCTION
MAX1294
MAX1296
1
2
1
2
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
INT
Three-State Digital Output (D9)
Three-State Digital Output (D8)
Three-State Digital I/O Line (D7)
Three-State Digital I/O Line (D6)
Three-State Digital I/O Line (D5)
Three-State Digital I/O Line (D4)
Three-State Digital I/O Line (D3)
Three-State Digital I/O Line (D2)
Three-State Digital I/O Line (D1)
Three-State Digital I/O Line (D0)
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
10
11
INT goes low when the conversion is complete and output data is ready.
Active-Low Read Select. If CS is low, a falling edge on RD enables the read
operation on the data bus.
12
12
RD
Active-Low Write Select. When CS is low in the internal acquisition mode, a rising
edge on WR latches in configuration data and starts an acquisition plus a conver-
sion cycle. When CS is low in external acquisition mode, the first rising edge on WR
ends acquisition and starts a conversion.
13
13
WR
Clock Input. In external clock mode, drive CLK with a TTL/CMOS-compatible clock.
14
15
14
15
CLK
In internal clock mode, connect this pin to either V
or GꢁD.
DD
Active-Low Chip Select. When CS is high, digital outputs (INT, D11–D0) are high
impedance.
CS
16
17
18
19
20
21
—
—
—
—
16
17
CH5
CH4
CH3
CH2
CH1
CH0
Analog Input Channel 5
Analog Input Channel 4
Analog Input Channel 3
Analog Input Channel 2
Analog Input Channel 1
Analog Input Channel 0
Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode
and must be stable to 0.5 LSB during conversion.
22
23
18
19
COM
GꢁD
Analog and Digital Ground
Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GꢁD with
24
20
REFADꢂ
a 0.01µF capacitor. When using an external reference, connect REFADꢂ to V
to
DD
disable the internal bandgap reference.
_______________________________________________________________________________________
7
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Pin Description (continued)
PIN
NAME
FUNCTION
MAX1294
MAX1296
Bandgap Reference Buffer Output/External Reference Input. Add a 4.7µF capacitor
to GꢁD when using the internal reference.
25
21
REF
26
27
28
22
23
24
V
Analog +5V Power Supply. Bypass with a 0.1µF capacitor to GꢁD.
Three-State Digital Output (D11)
DD
D11
D10
Three-State Digital Output (D10)
REF
T/H
REFADJ
17kΩ
1.22V
REFERENCE
A =
V
2.05
(CH5)
(CH4)
(CH3)
(CH2)
CH1
ANALOG
INPUT
MULTIPLEXER
CHARGE REDISTRIBUTION
12-BIT DAC
COMP
CH0
12
SUCCESSIVE-
APPROXIMATION
REGISTER
COM
CLK
CLOCK
CS
WR
RD
CONTROL LOGIC
&
MAX1294
MAX1296
LATCHES
INT
V
DD
12
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
GND
D0–D11
12-BIT DATA BUS
( ) ARE FOR MAX1294 ONLY.
Figure 2. Simplified Functional Diagram
track/hold (T/H) stage to convert an analog input signal to
a 12-bit digital output. This output format provides easy
interface to standard microprocessors (µPs). Figure 2
shows the simplified internal architecture of the MAX1294/
MAX1296.
_______________Detailed Description
Converter Operation
The MAX1294/MAX1296 ADCs use a successive-approx-
imation (SAR) conversion technique and an input
8
_______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
tial mode, Iꢁ+ and Iꢁ- are selected from analog input
pairs (Table 3) and are internally switched to either of
the analog inputs. This configuration is pseudo-differen-
tial to the effect that only the signal at Iꢁ+ is sampled.
The return side (Iꢁ-) must remain stable within 0.5
LSB ( 0.1 LSB for best performance) with respect to
GꢁD during a conversion. To accomplish this, connect
a 0.1µF capacitor from Iꢁ- (the selected input) to GꢁD.
Single-Ended and
Pseudo-Differential Operation
The sampling architecture of the ADCs’ analog com-
parator is illustrated in the equivalent input circuits of
Figure 3. In single-ended mode, Iꢁ+ is internally
switched to channels CH0–CH5 for the MAX1294
(Figure 3a) and to CH0–CH1 for the MAX1296 (Figure
3b), while Iꢁ- is switched to COM (Table 2). In differen-
12-BIT CAPACITIVE DAC
12-BIT CAPACITIVE DAC
V
V
REF
REF
COMPARATOR
COMPARATOR
INPUT
MUX
INPUT
MUX
C
C
HOLD
HOLD
ZERO
ZERO
–
–
+
+
CH0
CH1
CH0
CH1
12pF
12pF
R
R
IN
IN
800Ω
800Ω
CH2
CH3
CH4
CH5
C
C
SWITCH
SWITCH
HOLD
HOLD
TRACK
TRACK
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
T/H
SWITCH
T/H
SWITCH
COM
COM
SINGLE-ENDED MODE: IN+ = CH0–CH5, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3, AND CH4/CH5
SINGLE-ENDED MODE: IN+ = CH0–CH1, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR
CH0/CH1.
Figure 3a. MAX1294 Simplified Input Structure
Figure 3b. MAX1296 Simplified Input Structure
Tꢁble 10 Contaol-Bꢂte Functionꢁl Descaiption
BIT
NAME
FUNCTIONAꢀ DELCRIPTION
PD1 and PD± select the various clock and power-down modes.
±
±
1
1
±
1
±
1
Full Power-Down Mode. Clock mode is unaffected.
D7, D6
PD1, PD0
Standby Power-Down Mode. Clock mode is unaffected.
ꢁormal Operation Mode. Internal clock mode selected.
ꢁormal Operation Mode. External clock mode selected.
ACQMOD = 0: Internal Acquisition Mode
ACQMOD = 1: External Acquisition Mode
D5
D4
ACQMOD
SGL/DIF = 0: Pseudo-Differential Analog Input Mode
SGL/DIF = 1: Single-Ended Analog Input Mode
In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage
difference between two channels is measured (see Tables 2, 4).
SGL/DIF
UꢁI/BIP = 0: Bipolar Mode
UꢁI/BIP = 1: Unipolar Mode
In unipolar mode, an analog input signal from 0V to V
D3
UꢁI/BIP
can be converted; in bipolar mode, the
REF
signal can range from -V /2 to +V
REF
/2.
REF
Address bits A2, A1, A0 select which of the 6/2 (MAX1294/MAX1296) channels is to be converted
(see Tables 2, 3).
D2, D1, D0
A2, A1, A0
_______________________________________________________________________________________
9
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble 20 Chꢁnnel Lelection foa Lingle-Ended Opeaꢁtion (LGꢀ/DIF = 1)
A2
A1
A±
CH±
CH1
CH2*
CH3*
CH4*
CH.*
COM
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
+
-
-
-
-
-
-
+
+
+
+
+
*Channels CH2–CH5 apply to MAX1294 only.
Tꢁble 30 Chꢁnnel Lelection foa Pseudo-Diffeaentiꢁl Opeaꢁtion (LGꢀ/DIF = ±)
A2
0
A1
0
A±
0
CH±
CH1
CH2*
CH3*
CH4*
CH.*
+
0
0
1
+
0
1
0
+
-
0
1
1
+
1
0
0
+
-
-
1
0
1
+
*Channels CH2–CH5 apply to MAX1294 only.
During the acquisition interval, the channel selected as
the positive input (Iꢁ+) charges capacitor C . At
If an analog input voltage exceeds the supplies by
more than 50mV, limit the forward-bias input current to
4mA.
HOLD
the end of the acquisition interval, the T/H switch
opens, retaining charge on C
signal at Iꢁ+.
as a sample of the
HOLD
Track/Hold
The MAX1294/MAX1296 T/H stage enters its tracking
mode on the rising edge of WR. In external acquisition
mode, the part enters its hold mode on the next on ris-
ing edge of WR. In internal acquisition mode, the part
enters its hold mode on the fourth falling edge of clock
after writing the control byte. ꢁote that, in internal clock
mode, this is approximately 1µs after writing the control
byte.
The conversion interval begins with the input multiplex-
er switching C from the positive input (Iꢁ+) to the
HOLD
negative input (Iꢁ-). This unbalances node ZERO at the
comparator’s positive input. The capacitive digital-to-
analog converter (DAC) adjusts during the remainder of
the conversion cycle to restore node ZERO to 0V within
the limits of 12-bit resolution. This action is equivalent to
transferring a 12pF [(V + - V -)] charge from C
HOLD
Iꢁ
Iꢁ
In single-ended operation, Iꢁ- is connected to COM
and the converter samples the positive “+” input. In
pseudo-differential operation, Iꢁ- connects to the nega-
to the binary-weighted capacitive DAC, which in turn
forms a digital representation of the analog input signal.
Analog Input Protection
Internal protection diodes, which clamp the analog
tive input “-”, and the difference of (Iꢁ+) - (Iꢁ-) is sam-
|
|
pled. At the beginning of the next conversion, the
input to V
and GꢁD, allow each input channel to
positive input connects back to Iꢁ+ and C
charges to the input signal.
DD
HOLD
swing within (GꢁD - 300mV) to (V
+ 300mV) without
DD
damage. However, for accurate conversions near full
scale, both inputs must not exceed (V
less than (GꢁD - 50mV).
The time required for the T/H stage to acquire an input
signal depends on how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
+ 50mV) or be
DD
1± ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time,
ACQ
the signal, and is also the minimum time required for
the signal to be acquired. Calculate this with the follow-
ing equation:
ends (Figure 4). ꢁote that, when the internal acquisition
is combined with the internal clock, the aperture jitter
can be as high as 200ps. Internal clock users wishing
to achieve the 50ps jitter specification should always
use external acquisition mode.
t
, is the maximum time the device takes to acquire
External Acquisition
Use external acquisition mode for precise control of the
sampling aperture and/or dependent control of acquisi-
tion and conversion times. The user controls acquisition
and start-of-conversion with two separate write pulses.
The first pulse, written with ACQMOD = 1, starts an
acquisition interval of indeterminate length. The second
write pulse, written with ACQMOD = 0 (all other bits in
control byte unchanged), terminates acquisition and
starts conversion on WR rising edge (Figure 5).
t
= 9 (R + R ) C
S Iꢁ Iꢁ
ACQ
where R is the source impedance of the input signal,
S
R
(800Ω) is the input resistance, and C (12pF) is
Iꢁ
Iꢁ
the ADC’s input capacitance. Source impedances
below 3kΩ have no significant impact on the MAX1294/
MAX1296’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Together with the input impedance, this capacitor
forms an RC filter, limiting the ADC’s signal bandwidth.
The address bits for the input multiplexer must have the
same values on the first and second write pulse.
Power-down mode bits (PD0, PD1) can assume new
values on the second write pulse (see Power-Down
Modes section). Changing other bits in the control byte
corrupts the conversion.
Input Bandwidth
The MAX1294/MAX1296 T/H stage offers a 350kHz full-
linear and a 6MHz full-power bandwidth. This makes it
possible to digitize high-speed transients and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended.
Reading a Conversion
A standard interrupt signal INT is provided to allow the
MAX1294/MAX1296 to flag the µP when the conversion
has ended and a valid result is available. INT goes low
when the conversion is complete and the output data is
ready (Figures 4 and 5). It returns high on the first read
cycle or if a new control byte is written.
Starting a Conversion
Initiate a conversion by writing a control byte, which
selects the multiplexer channel and configures the
MAX1294/MAX1296 for either unipolar or bipolar opera-
tion. A write pulse (WR + CS) can either start an acqui-
sition interval or initiate a combined acquisition plus
conversion. The sampling interval occurs at the end of
the acquisition interval. The ACQMOD (acquisition
mode) bit in the input control byte (Table 1) offers two
options for acquiring the signal: an internal and an
external acquisition. The conversion period lasts for 13
clock cycles in either the internal or external clock or
acquisition mode. Writing a new control byte during a
conversion cycle aborts the conversion and starts a
new acquisition interval.
Selecting Clock Mode
The MAX1294/MAX1296 operate with either an internal
or an external clock. Control bits D6 and D7 select
either internal or external clock mode. The part retains
the last-requested clock mode if a power-down mode is
selected in the current input word. For both internal and
external clock mode, internal or external acquisition
can be used. At power-up, the MAX1294/MAX1296
enter the default external clock mode.
Internal Clock Mode
Select internal clock mode to release the µP from the
burden of running the SAR conversion clock. Bit D7 of
the control byte must be set to 1 and bit D6 must be set
to 0. The internal clock frequency is then selected,
resulting in a conversion time of 3.6µs. When using the
internal clock mode, tie the CLK pin either high or low
to prevent the pin from floating.
Internal Acquisition
Select internal acquisition by writing the control byte
with the ACQMOD bit cleared (ACQMOD = 0). This
causes the write pulse to initiate an acquisition interval
whose duration is internally timed. Conversion starts
when this acquisition interval (three external clock
cycles or approximately 1µs in internal clock mode)
______________________________________________________________________________________ 11
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
t
CS
CS
t
t
t
CSWS
ACQ
CONV
t
t
CSWH
WR
WR
t
DH
t
DS
CONTROL
BYTE
D7–D0
ACQMOD = "0"
HIGH-Z
HIGH-Z
HIGH-Z
INT
RD
t
INT1
t
t
D0
TR
HIGH-Z
DOUT
VALID DATA
Figure 4. Conversion Timing Using Internal Acquisition Mode
t
CS
CS
t
CSWS
t
t
CONV
ACQ
t
CSHW
t
WR
WR
t
DH
t
t
OH
DS
CONTROL
BYTE
ACQMOD = "1"
CONTROL
BYTE
ACQMOD = "0"
D7–D0
INT
HIGH-Z
HIGH-Z
t
INT1
RD
t
t
TR
D0
HIGH-Z
HIGH-Z
VALID DATA
DOUT
Figure 5. Conversion Timing Using External Acquisition Mode
12 ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
External Clock Mode
To select external clock mode, bits D6 and D7 of the
control byte must be set to 1. Figure 6 shows the clock
and WR timing relationship for internal (Figure 6a) and
external (Figure 6b) acquisition modes with an external
clock. For proper operation, a 100kHz to 7.6MHz clock
frequency with 30ꢀ to 70ꢀ duty cycle is recommended.
Operating the MAX1294/MAX1296 with clock frequen-
cies lower than 100kHz is not recommended because
the resulting voltage droop across the hold capacitor in
the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a three-
state parallel interface (I/O) that can easily be inter-
faced with standard µPs. The signals CS, WR, and RD
control the write and read operations. CS represents
the chip-select signal, which enables a µP to address
the MAX1294/MAX1296 as an I/O port. When high, CS
disables the CLK, WR, and RD inputs and forces the
interface into a high-impedance (high-Z) state.
ACQUISITION STARTS
CONVERSION STARTS
ACQUISITION ENDS
t
CP
CLK
WR
t
t
CL
CH
t
CWS
WR GOES HIGH WHEN CLK IS HIGH
ACQMOD = "0"
ACQUISITION STARTS
t
CWH
ACQUISITION ENDS
CONVERSION STARTS
CLK
WR
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS LOW
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS
ACQUISITION ENDS
CONVERSION STARTS
CLK
t
CWS
t
DH
WR
ACQMOD = "1"
ACQMOD = "0"
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
ACQUISITION STARTS
CONVERSION STARTS
CLK
WR
t
CWH
t
DH
ACQMOD = "1"
WR GOES HIGH WHEN CLK IS LOW
ACQMOD = "0"
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
______________________________________________________________________________________ 13
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble 40 Contaol-Bꢂte Foamꢁt
D7
(MLB)
D±
(ꢀLB)
D6
D.
D4
D3
D2
D1
PD1
PD0
ACQMOD
A2
A1
A0
SGL/DIF
UꢁI/BIP
Input Format
The control bit sequence is latched into the device on
pins D7–D0 during a write command. Table 4 shows
the control-byte format.
V
= +5V
DD
50kΩ
50kΩ
MAX1294
MAX1296
Output Data Format
The 12-bit-wide output format for both the MAX1294/
MAX1296 is binary in unipolar mode and two’s comple-
ment in bipolar mode. CS, RD, WR, INT, and the 12 bits
of output data can interface directly to a 16-bit data bus.
When reading the output data, CS and RD must be low.
330kΩ
REFADJ
REF
4.7µF
0.01µF
Applications Information
Power-On Reset
When power is first applied, internal power-on reset cir-
cuitry activates the MAX1294/MAX1296 in external clock
mode and sets INT high. After the power supplies stabi-
lize, the internal reset time is 10µs; no conversions
should be attempted during this phase. When using the
Figure 7. Reference Adjustment with External Potentiometer
Using the REFADꢂ input makes buffering the external
reference unnecessary. The REFADꢂ input impedance
is typically 17kΩ.
When applying an external reference to REF, disable the
internal reference buffer by connecting REFADꢂ to V
internal reference, 500µs is required for V
to stabilize.
REF
.
DD
Internal and External Reference
The MAX1294/MAX1296 can be used with an internal
or external reference voltage. An external reference
can be connected directly to REF or REFADꢂ.
The DC input resistance at REF is 25kΩ. Therefore, an
external reference at REF must deliver up to 200µA DC
load current during a conversion and have an output
impedance less than 10Ω. If the reference has higher
output impedance or is noisy, bypass it close to the REF
pin with a 4.7µF capacitor.
An internal buffer is designed to provide +2.5V at REF for
both devices. The internally trimmed +1.22V reference is
buffered with a +2.05V/V gain.
Power-Down Modes
To save power, place the converter in a low-current
shutdown state between conversions. Select standby
mode or shutdown mode using bits D6 and D7 of the
control byte (Tables 1 and 4). In both software power-
down modes, the parallel interface remains active, but
the ADC does not convert.
Internal Reference
The full-scale range with the internal reference is +2.5V
with unipolar inputs and 1.25V with bipolar inputs. The
internal reference buffer allows for small adjustments
( 100mV) in the reference voltage (Figure 7).
Note: The reference buffer must be compensated with
an external capacitor (4.7µF min) connected between
REF and GꢁD to reduce reference noise and switching
spikes from the ADC. To further minimize reference
noise, connect a 0.01µF capacitor between REFADꢂ
and GꢁD.
Standby Mode
While in standby mode, the supply current is typically
1mA. The part powers up on the next rising edge of WR
and is ready to perform conversions. This quick turn-on
time allows the user to realize significantly reduced
power consumption for conversion rates below
420ksps.
External Reference
With the MAX1294/MAX1296, an external reference can
be placed at either the input (REFADꢂ) or the output
(REF) of the internal-reference buffer amplifier.
14 ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Tꢁble .0 Full Lcꢁle ꢁnd Zeao Lcꢁle foa Unipolꢁa ꢁnd Bipolꢁa Opeaꢁtion
UNIPOꢀAR MODE
BIPOꢀAR MODE
Positive Full Scale
Full Scale
Zero Scale
—
V
REF
+ COM
V
/2 + COM
COM
REF
COM
Zero Scale
—
ꢁegative Full Scale
-V
/2 + COM
REF
OUTPUT CODE
REF
OUTPUT CODE
FULL-SCALE
TRANSITION
FS
FS = REF + COM
ZS = COM
=
+ COM
+ COM
011 . . . 111
011 . . . 110
111 . . . 111
2
111 . . . 110
ZS = COM
-REF
2
-FS =
000 . . . 010
000 . . . 001
000 . . . 000
100 . . . 010
100 . . . 001
100 . . . 000
REF
4096
REF
4096
1 LSB =
1 LSB =
111 . . . 111
111 . . . 110
111 . . . 101
011 . . . 111
011 . . . 110
011 . . . 101
100 . . . 001
100 . . . 000
000 . . . 001
000 . . . 000
COM*
INPUT VOLTAGE (LSB)
0
1
2
FS
- FS
+FS - 1 LSB
2048
INPUT VOLTAGE (LSB)
(COM)
FS - 3/2 LSB
*COM ≥ V / 2
REF
Figure 9. Bipolar Transfer Functions
Figure 8. Unipolar Transfer Functions
Shutdown Mode
unipolar input/output (I/O) transfer function, and Figure 9
shows the bipolar I/O transfer function. Code transitions
occur halfway between successive-integer LSB values.
Shutdown mode turns off all chip functions that draw
quiescent current, reducing the typical supply current
to 2µA immediately after the current conversion is com-
pleted. A rising edge on WR causes the MAX1294/
MAX1296 to exit shutdown mode and return to normal
operation. To achieve full 12-bit accuracy with a 4.7µF
reference bypass capacitor, 500µs is required after
power-up. Waiting 500µs in standby mode, instead of
in full-power mode, can reduce power consumption by
a factor of three or more. When using an external refer-
ence, only 50µs is required after power-up. Enter
standby mode by performing a dummy conversion with
the control byte specifying standby mode.
Output coding is binary, with 1 LSB = (V
/ 4096).
REF
Maximum Sampling Rate/
Achieving 475ksps
When running at the maximum clock frequency of
7.6MHz, the specified throughput of 420ksps is
achieved by completing a conversion every 18 clock
cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
sion cycles, and 1 read cycle. This assumes that the
results of the last conversion are read before the next
control byte is written. It is possible to achieve higher
throughputs, up to 475ksps, by first writing a control
byte to begin the acquisition cycle of the next conver-
sion, and then reading the results of the previous con-
version from the bus. This technique (Figure 10) allows
a conversion to be completed every 16 clock cycles.
ꢁote that the switching of the data bus during acquisi-
Note: Bypass capacitors larger than 4.7µF between
REF and GꢁD result in longer power-up delays.
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar
and bipolar modes. Figures 8 depicts the nominal
______________________________________________________________________________________ 1.
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
WR
RD
CONTROL
WORD
D11–
D0
D11–D0
CONTROL WORD
CONVERSION
D7–D0
STATE
ACQUISITION
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
tion or conversion can cause additional supplynoise,
which can make it difficult to achieve true 12-bit perfor-
mance.
SUPPLIES
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-
wrap configurations are not recommended, since the
layout should ensure proper separation of analog and
digital traces. Do not run analog and digital lines paral-
lel to each other, and don’t lay out digital signal paths
underneath the ADC package. Use separate analog
and digital PC board ground sections with only one star
point (Figure 11) connecting the two ground systems
(analog and digital). For lowest noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
+5V
+5V
GND
4.7µF
0.1µF
R* = 5Ω
V
GND
COM
+5V
DGND
DD
DIGITAL
CIRCUITRY
MAX1294
MAX1296
High-frequency noise in the power supply, V , could
DD
*OPTIONAL
impair operation of the ADC’s fast comparator. Bypass
Figure 11. Power-Supply and Grounding Connections
V
to the star ground with a network of two parallel
DD
capacitors, 0.1µF and 4.7µF, located as close to the
MAX1294/MAX1296’s power-supply pin as possible.
Minimize capacitor lead length for best supply-noise
rejection and add an attenuation resistor (5Ω) if the
power supply is extremely noisy.
16 ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SIꢁAD) is the ratio of the
Definitions
Integral Nonlinearity
Integral nonlinearity (IꢁL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. IꢁL for
the MAX1294/MAX1296 is measured using the end-
point method.
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SIꢁAD (dB) = 20 x log (Signal
/ ꢁoise
)
RMS
RMS
Effective Number of Bits
Effective number of bits (EꢁOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Differential Nonlinearity
Differential nonlinearity (DꢁL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DꢁL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
EꢁOB = (SIꢁAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
Aperture Jitter
Aperture jitter (t ) is the sample-to-sample variation in
Aꢂ
the time between the samples.
Aperture Delay
2
2
2
2
Aperture delay (t ) is the time between the rising
AD
THD = 20 × log
V
+ V + V + V
/ V
1
2
3
4
5
edge of the sampling clock and the instant when an
actual sample is taken.
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SꢁR) is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (ꢁ bits):
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
SꢁR = (6.02 x ꢁ + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SꢁR is calculated by taking
the ratio of the RMS signal to the RMS noise, which
includes all spectral components minus the fundamen-
tal, the first five harmonics, and the DC offset.
Chip Information
TRAꢁSISTOR COUꢁT: 5781
SUBSTRATE COꢁꢁECTED TO GꢁD
______________________________________________________________________________________ 17
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Typical Operating Circuits
CLK
CLK
+5V
+5V
MAX1294
V
DD
MAX1296
V
DD
+2.5V
+2.5V
CS
WR
RD
REF
CS
WR
RD
REF
µP
CONTROL
INPUTS
µP
CONTROL
INPUTS
0.1µF
0.1µF
REFADJ
INT
REFADJ
4.7µF
4.7µF
OUTPUT STATUS
INT
D11
D10
D9
OUTPUT STATUS
D11
D10
D9
D8
D8
D7
D6
D7
D6
CH5
CH4
D5
D4
D3
D5
D4
D3
CH3
CH2
CH1
ANALOG
INPUTS
CH1
D2
D2
ANALOG
INPUTS
CH0
CH0
D1
D0
D1
D0
COM
COM
GND
GND
µP DATA BUS
µP DATA BUS
Pin Configurations (continued)
TOP VIEW
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
28 D10
27 D11
26
V
DD
25 REF
24 REFADJ
23 GND
22 COM
21 CH0
20 CH1
19 CH2
18 CH3
17 CH4
16 CH5
15 CS
MAX1294
D0 10
INT 11
RD 12
WR 13
CLK 14
QLOP
18 ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs
with +2.5V Reference and Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www0mꢁxim-ic0com/pꢁckꢁges.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600_____________________19
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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