MAX1323_技术文档

19-3592; Rev 0; 2/05

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

General Description

Features

The MAX1319/MAX1323/MAX1327 are single-channel,

14-bit, 526ksps analog-to-digital converters (ADCs) with

2 ꢀLS ꢁIꢀ and 1 ꢀLS DIꢀ with no ꢂissing codesꢃ The

MAX1323 has a 5ꢄ inpꢅt range with 16ꢃ5ꢄ Vaꢅlt-toler-

ant inpꢅtsꢃ The MAX1327 has a 1ꢆꢄ inpꢅt range with

16ꢃ5ꢄ Vaꢅlt-tolerant inpꢅts and the MAX1319 has a ꢆ to

+5ꢄ inpꢅt range with 6ꢃꢆꢄ Vaꢅlt-tolerant inpꢅtsꢃ ꢇther

Veatꢅres inclꢅde a 1ꢆMHz track/hold (T/H) inpꢅt band-

width, internal clock, internal (+2ꢃ5ꢄ) or external (+2ꢃꢆꢄ

to +3ꢃꢆꢄ) reVerence, and shꢅtdown ꢂodeꢃ

♦ 14-Bit ADCs

526ksps

2 ꢀLB ꢁIꢀꢂ 1 ꢀLB DIꢀꢂ Iꢃ oissiꢄꢅ Cꢃꢆꢇs

90ꢆBc LFDRꢂ -86ꢆBc THDꢂ 76.5ꢆB LꢁIADꢂ 77ꢆB

LIR at 100kHz ꢁꢄput

♦ Fast 1.6µs Cꢃꢄvꢇrsiꢃꢄ Timꢇ

♦ Flꢇxiblꢇ ꢁꢄput Raꢄꢅꢇs

0 tꢃ +5V (oAX1319)

5V (oAX1323)

10V (oAX1327)

A 16ꢃ6MHz, 14-bit, parallel interVace provides the con-

version resꢅlts and accepts digital conVigꢅration inpꢅtsꢃ

♦ Iꢃ Calibratiꢃꢄ Iꢇꢇꢆꢇꢆ

These devices operate Vroꢂ a +4ꢃ75ꢄ to +5ꢃ25ꢄ analog

sꢅpply and a separate +2ꢃ7ꢄ to +5ꢃ25ꢄ digital sꢅpply,

and consꢅꢂe less than 35ꢂA total sꢅpply cꢅrrentꢃ For

ꢂꢅltichannel applications, reVer to the MAX1316–

MAX1318/MAX132ꢆ–MAX1322/MAX1324–MAX1326

data sheetꢃ

♦ 14-Bit Hiꢅh-Lpꢇꢇꢆ Parallꢇl ꢁꢄtꢇrfacꢇ

♦ ꢁꢄtꢇrꢄal ꢃr Extꢇrꢄal Clꢃck

♦ +2.5V ꢁꢄtꢇrꢄal Rꢇfꢇrꢇꢄcꢇ ꢃr +2.0V tꢃ +3.0V

Extꢇrꢄal Rꢇfꢇrꢇꢄcꢇ

♦ +5V Aꢄalꢃꢅ Lupplyꢂ +3V tꢃ +5V Diꢅital Lupply

32mA Aꢄalꢃꢅ Lupply Currꢇꢄt (typ)

These devices coꢂe in a 48-pin TQFP package and

operate over the extended -4ꢆ°C to +85°C teꢂpera-

tꢅre rangeꢃ

550µA Diꢅital Lupply Currꢇꢄt (typ)

Lhutꢆꢃwꢄ aꢄꢆ Pꢃwꢇr-Laviꢄꢅ oꢃꢆꢇs

♦ 48-Piꢄ TQFP Packaꢅꢇ (7mm x 7mm Fꢃꢃtpriꢄt)

Applications

ꢄibration and WaveVorꢂ Analysis

Pin Configuration

Data-Acqꢅisition Lysteꢂs

TOP VIEW

ꢁndꢅstrial Process Control and Aꢅtoꢂation

AV

1

2

36 D12

35 D11

34 D10

33 D9

32 D8

31 D7

30 D6

29 D5

DD

Ordering Information/

Selector Guide

AGND

3

A

4

IN

ꢁIPUT

PKG

I.C.

MSV

I.C.

5

PART

PꢁI-PACKAGE

RAIGE (V)

CODE

6

MAX1319

MAX1323

MAX1327

ꢆ to +5

7

oAX1319ECM 48 TQFP

oAX1323ECM 48 TQFP

oAX1327ECM 48 TQFP

C48-6

I.C.

8

5

I.C.

D4

D3

D2

D1

9

28

27

26

25

1ꢆ

I.C.

10

11

12

Iꢃtꢇ: All devices operate over the -4ꢆ°C to +85°C teꢂperatꢅre

I.C.

rangeꢃ

I.C.

TQFP

Typical Operating Circuits appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

ABLOꢀUTE oAXꢁoUo RATꢁIGL

Aꢄ to AGID ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to +6ꢄ

REF+, CꢇM, REF- to AGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Aꢄ + ꢆꢃ3ꢄ)

DD

Dꢄ

to DGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to +6ꢄ

Dꢆ–D13 to DGID ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Dꢄ

+ ꢆꢃ3ꢄ)

DD

AGID to DGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to +ꢆꢃ3ꢄ

CHꢆ, ꢁꢃCꢃ to AGID (MAX1319)ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ 6ꢃꢆꢄ

CHꢆ, ꢁꢃCꢃ to AGID (MAX1323/MAX1327)ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ 16ꢃ5ꢄ

ꢁITCꢀK/EXTCLK to AGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Aꢄ + ꢆꢃ3ꢄ)

EOC, EOLC, WR, ꢁꢃCꢃ2, RD,

CS to DGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Dꢄ + ꢆꢃ3ꢄ)

CꢇIꢄLT, CꢀK, LHDI,

AꢀꢀꢇI to DGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Dꢄ + ꢆꢃ3ꢄ)

MLꢄ, REF , REF to AGIDꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-ꢆꢃ3ꢄ to (Aꢄ + ꢆꢃ3ꢄ)

Maxiꢂꢅꢂ Cꢅrrent into Any Pin Except Aꢄ , Dꢄ

,

DD

AGID, DGID ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ 5ꢆꢂA

Continꢅoꢅs Power Dissipation (T = +7ꢆ°C)

A

TQFP (derate 22ꢃ7ꢂW/°C above +7ꢆ°C)ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ1818ꢂW

ꢇperating Teꢂperatꢅre Range ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-4ꢆ°C to +85°C

Jꢅnction Teꢂperatꢅreꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ+15ꢆ°C

Ltorage Teꢂperatꢅre Rangeꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ-65°C to +15ꢆ°C

ꢀead Teꢂperatꢅre (soldering, 1ꢆs) ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃ+3ꢆꢆ°C

DD

ML

DD

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

EꢀECTRꢁCAꢀ CHARACTERꢁLTꢁCL

(Aꢄ

= +5ꢄ, Dꢄ

= ꢆꢃ1µF, C

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), C

= C

= ꢆꢃ1µF, C

=

DD

REF-

DD

REF

REFML

REF

REFML

REF+

C

= 2ꢃ2µF || ꢆꢃ1µF, C

= 2ꢃ2µF || ꢆꢃ1µF (MAX1319; ꢅnipolar device), MLꢄ =

REF+-to-REF-

CꢇM

MLꢄ

AGID (MAX1323/MAX1327; bipolar devices), V

= 1ꢆMHz 5ꢆ% dꢅty, t

, ꢅnless otherwise notedꢃ Typical valꢅes are at T = +25°Cꢃ)

= 2ꢆꢆns, t

= 1ꢆns, ꢁITCꢀK/EXTCLK = AGID

QUꢁET

CꢀK

ACQ

(external clock), LHDI = DGID, T = T

to T

A

MꢁI

MAX A

PARAoETER

LTATꢁC PERFORoAICE (Iꢃtꢇ 1)

Resolꢅtion

LYoBOꢀ

COIDꢁTꢁOIL

oꢁI

TYP

oAX

UIꢁTL

I

14

Sits

ꢀLS

ꢁntegral Ionlinearity

ꢁIꢀ

DIꢀ

(Iote 2)

ꢆꢃ8

ꢆꢃ5

2

1

DiVVerential Ionlinearity

Io ꢂissing codes

Unipolar device

Sipolar devices

Unipolar device

Sipolar devices

(Iote 3)

33

ꢇVVset Error

ꢇVVset DriVt

ꢀLS

4

ppꢂ/°C

4

Gain Error

1ꢆ

3

49

ꢀLS

Gain Teꢂperatꢅre CoeVVicient

ppꢂ/°C

DYIAoꢁC PERFORoAICE (at f = 100kHzꢂ -0.4ꢆBFL)

ꢁI

Unipolar

74ꢃ5

75

76

76ꢃ5

76ꢃꢆ

76ꢃ5

93

Lignal-to-Ioise Ratio

LIR

dS

Sipolar

Unipolar

Sipolar

74ꢃ5

75

Lignal-to-Ioise and Distortion

Ratio

LꢁIAD

Lpꢅrioꢅs Free Dynaꢂic Range

Total Harꢂonic Distortion

LFDR

THD

83

dSc

-9ꢆ

-83

AIAꢀOG ꢁIPUTL (CH0–CH7)

MAX1319

MAX1323

MAX1327

ꢆ

+5

ꢁnpꢅt ꢄoltage Range

ꢄ

-5

-1ꢆ

+1ꢆ

2

_______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

EꢀECTRꢁCAꢀ CHARACTERꢁLTꢁCL (cꢃꢄtiꢄuꢇꢆ)

(Aꢄ

= +5ꢄ, Dꢄ

= ꢆꢃ1µF, C

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), C

= C

= ꢆꢃ1µF, C

=

DD

REF

REFML

REF

REFML

REF+

C

= 2ꢃ2µF || ꢆꢃ1µF, C

= 2ꢃ2µF || ꢆꢃ1µF (MAX1319; ꢅnipolar device), MLꢄ =

REF-

REF+-to-REF-

CꢇM

MLꢄ

AGID (MAX1323/MAX1327; bipolar devices), V

= 1ꢆMHz 5ꢆ% dꢅty, t

, ꢅnless otherwise notedꢃ Typical valꢅes are at T = +25°Cꢃ)

= 2ꢆꢆns, t

= 1ꢆns, ꢁITCꢀK/EXTCLK = AGID

QUꢁET

CꢀK

ACQ

(external clock), LHDI = DGID, T = T

to T

A

MꢁI

MAX A

PARAoETER

LYoBOꢀ

COIDꢁTꢁOIL

oꢁI

-ꢆꢃ157

-1ꢃ16

-1ꢃ13

TYP

ꢆꢃ54

-ꢆꢃ12

ꢆꢃ29

-ꢆꢃ87

ꢆꢃ56

-ꢆꢃ85

7ꢃ58

8ꢃ66

14ꢃ26

15

oAX

UIꢁTL

ꢄ

= +5ꢄ

= ꢆꢄ

ꢆꢃ72

ꢁI

MAX1319

= +5ꢄ

= -5ꢄ

ꢆꢃ39

ꢆꢃ74

ꢁnpꢅt Cꢅrrent

MAX1323

MAX1327

ꢂA

= +1ꢆꢄ

= -1ꢆꢄ

MAX1319

MAX1323

MAX1327

ꢁnpꢅt Resistance

kΩ

ꢁnpꢅt Capacitance

pF

TRACK/HOꢀD

External Clock Throꢅghpꢅt Rate

ꢁnternal Clock Throꢅghpꢅt Rate

Lꢂall-Lignal Sandwidth

Fꢅll-Power Sandwidth

Apertꢅre Delay

526

1ꢆ

ksps

MHz

ns

1ꢆ

16

Apertꢅre Jitter

5ꢆ

ps

RML

ꢁITERIAꢀ REFEREICE

REF

ML

ꢄoltage

ꢄ

2ꢃ475

2ꢃ5ꢆꢆ

3ꢆ

2ꢃ525

ꢄ

REFML

REF ꢄoltage

ꢄ

REF

REF Teꢂperatꢅre CoeVVicient

EXTERIAꢀ REFEREICE (REF

ꢁnpꢅt Cꢅrrent

ppꢂ/°C

aꢄꢆ REF ꢇxtꢇrꢄally ꢆrivꢇꢄ)

oL

-25ꢆ

2ꢃꢆ

+25ꢆ

3ꢃꢆ

µA

ꢄ

REF

ML

ꢁnpꢅt ꢄoltage Range

ꢄ

Unipolar device

2ꢃ5

15

REFML

REF ꢁnpꢅt ꢄoltage Range

REF ꢁnpꢅt Capacitance

ꢄ

2ꢃꢆ

3ꢃꢆ

ꢄ

REF

pF

REF

ML

ꢁnpꢅt Capacitance

15

_______________________________________________________________________________________

3

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

EꢀECTRꢁCAꢀ CHARACTERꢁLTꢁCL (cꢃꢄtiꢄuꢇꢆ)

(Aꢄ

= +5ꢄ, Dꢄ

= ꢆꢃ1µF, C

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), C

= C

= ꢆꢃ1µF, C

=

DD

REF

REFML

REF

REFML

REF+

C

= 2ꢃ2µF || ꢆꢃ1µF, C

= 2ꢃ2µF || ꢆꢃ1µF (MAX1319; ꢅnipolar device), MLꢄ =

REF-

REF+-to-REF-

CꢇM

MLꢄ

AGID (MAX1323/MAX1327; bipolar devices), V

= 1ꢆMHz 5ꢆ% dꢅty, t

, ꢅnless otherwise notedꢃ Typical valꢅes are at T = +25°Cꢃ)

= 2ꢆꢆns, t

= 1ꢆns, ꢁITCꢀK/EXTCLK = AGID

QUꢁET

CꢀK

ACQ

(external clock), LHDI = DGID, T = T

to T

A

MꢁI

MAX A

PARAoETER

LYoBOꢀ

COIDꢁTꢁOIL

oꢁI

TYP

oAX

UIꢁTL

DꢁGꢁTAꢀ ꢁIPUTL (D0–D7ꢂ RDꢂ CSꢂ CꢀKꢂ LHDIꢂ COIVLT)

ꢆꢃ7 x

ꢁnpꢅt-ꢄoltage High

ꢁnpꢅt-ꢄoltage ꢀow

ꢄ

ꢁH

Dꢄ

DD

ꢆꢃ3 x

ꢄ

ꢁꢀ

Dꢄ

DD

ꢁnpꢅt Hysteresis

ꢁnpꢅt Capacitance

ꢁnpꢅt Cꢅrrent

15

ꢂꢄ

pF

µA

C

ꢁI

ꢁ

ꢄ

= ꢆꢄ or Dꢄ

ꢁI DD

1

ꢁI

CꢀOCK-LEꢀECT ꢁIPUT (ꢁITCꢀK/EXTCLK)

ꢆꢃ7 x

ꢁnpꢅt-ꢄoltage High

ꢄ

Aꢄ

DD

ꢆꢃ3 x

Aꢄ

ꢁnpꢅt-ꢄoltage ꢀow

DD

DꢁGꢁTAꢀ OUTPUTL (D0–D13ꢂ EOCꢂ EOLC)

Dꢄ

ꢆꢃ6

-

DD

ꢇꢅtpꢅt-ꢄoltage High

ꢄ

ꢁ

= ꢆꢃ8ꢂA

ꢄ

ꢇH

LꢇURCE

= 1ꢃ6ꢂA

LꢁIK

ꢇꢅtpꢅt-ꢄoltage ꢀow

ꢄ

ꢆꢃ4

ꢄ

ꢇꢀ

Tri-Ltate ꢀeakage Cꢅrrent

Tri-Ltate ꢇꢅtpꢅt Capacitance

POWER LUPPꢀꢁEL

RD ≥ ꢄ or CS ≥ ꢄ

ꢆꢃꢆ6

15

1

µA

pF

ꢁH

RD ≥ ꢄ or CS ≥ ꢄ

ꢁH

Analog Lꢅpply ꢄoltage

Digital Lꢅpply ꢄoltage

Aꢄ

Dꢄ

4ꢃ75

2ꢃ7ꢆ

5ꢃ25

36

ꢄ

DD

MAX1319

32

28

Analog Lꢅpply Cꢅrrent

ꢁ

ꢂA

AꢄDD

MAX1323/MAX1327

32

Digital Lꢅpply Cꢅrrent

Lhꢅtdown Cꢅrrent

ꢁ

7ꢆꢆ

1ꢆ

2

µA

dS

DꢄDD

ꢄ

= Dꢄ

DD

LHDI

= Dꢄ , ꢄ

= Dꢄ

DD

ꢆꢃ1

5ꢆ

RD

DD LHDI

Power-Lꢅpply Rejection Ratio

PLRR

Aꢄ

= +4ꢃ75ꢄ to +5ꢃ75ꢄ (Iote 5)

DD

4

_______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

TꢁoꢁIG CHARACTERꢁLTꢁCL (Fiꢅurꢇs 3ꢂ 4ꢂ 5ꢂ aꢄꢆ 6) (Tablꢇs 1ꢂ 2)

PARAoETER

LYoBOꢀ

COIDꢁTꢁOIL

oꢁI

TYP

oAX

UIꢁTL

ꢁnternal clock

1ꢃ6

1ꢃ8

ns

Conversion Tiꢂe

t

CꢇIꢄ

Clock

cycles

External clock (Figꢅre 4)

(Iote 4)

16

CꢇIꢄLT Pꢅlse-Width ꢀow

(Acqꢅisition Tiꢂe)

t

ꢆꢃ16

1ꢆꢆ

µs

ACQ

CS Pꢅlse Width

t

2

t

3

t

8

t

9

3ꢆ

ꢆ

ns

RD Pꢅlse-Width ꢀow

CS to RD Letꢅp Tiꢂe

RD to CS Hold Tiꢂe

ꢆ

Data Access Tiꢂe

(RD ꢀow to ꢄalid Data)

t

3ꢆ

ns

1ꢆ

11

Sꢅs Relinqꢅish Tiꢂe (RD High)

EOC Pꢅlse Width

t

ns

ꢁnternal clock

8ꢆ

12

Clock

cycle

External clock (Figꢅre 4)

1

External CꢀK Period

t

9ꢆ

2ꢆ

ꢆꢃ1

ns

16

17

18

External CꢀK High Period

External CꢀK ꢀow Period

External Clock Freqꢅency

ꢁnternal Clock Freqꢅency

CꢇIꢄLT High to CꢀK Edge

EOC ꢀow to RD

ꢀogic sensitive to rising edges

(Iote 6)

ns

12ꢃ5

MHz

ns

1ꢆ

t

(Iote 7)

2ꢆ

ꢆ

19

ns

2ꢆ

Iꢃtꢇ 1: For the MAX1319, ꢄ = ꢆ to +5ꢄꢃ For the MAX1323, ꢄ = -5ꢄ to +5ꢄꢃ For the MAX1327, ꢄ = -1ꢆꢄ to +1ꢆꢄꢃ

ꢁI

Iꢃtꢇ 2: ꢁIꢀ is deVined as the deviation oV the analog valꢅe at any code Vroꢂ its theoretical valꢅe aVter oVVset and gain errors have

been reꢂovedꢃ

Iꢃtꢇ 3: ꢇVVset nꢅlledꢃ

Iꢃtꢇ 4: CꢇIꢄLT ꢂꢅst reꢂain low Vor at least the acqꢅisition periodꢃ

Iꢃtꢇ 5: DeVined as the change in positive Vꢅll scale caꢅsed by a 5% variation in the noꢂinal sꢅpply voltageꢃ

Iꢃtꢇ 6: Miniꢂꢅꢂ clock Vreqꢅency is liꢂited only by the internal T/H droop rateꢃ ꢀiꢂit the tiꢂe between the Valling edge oV CꢇIꢄLT

to the Valling edge oV EꢇꢀC to a ꢂaxiꢂꢅꢂ oV ꢆꢃ25ꢂsꢃ

Iꢃtꢇ 7: To avoid T/H droop degrading the saꢂpled analog inpꢅt signals, the Virst clock pꢅlse shoꢅld occꢅr within 1ꢆµs oV the rising

edge oV CꢇIꢄLT and have a ꢂiniꢂꢅꢂ clock Vreqꢅency oV 1ꢆꢆkHzꢃ

_______________________________________________________________________________________

5

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Typical Operating Characteristics

(Aꢄ

= +5ꢄ, Dꢄ

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), see the Typical Operating Circuits,

REFML

DD

REF

V

= 1ꢆMHz 5ꢆ% dꢅty, ꢁITCꢀK/EXTCLK = AGID (external clock), LHDI = DGID, T = +25°Cꢃ)

A

CꢀK

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

1.00

0.75

0.50

0.25

0

50

45

40

35

30

0.75

0.50

0.25

0

-0.25

-0.50

-0.75

-1.00

-0.25

-0.50

-0.75

-1.00

f

= 250ksps

4.87

SAMPLE

0

4096

8192

12,288

16,384

0

4096

8192

12,288

16,384

4.75

5.00

5.12

5.25

DIGITAL OUTPUT CODE

SUPPLY VOLTAGE (V)

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

SHUTDOWN CURRENT

vs. TEMPERATURE

50

45

40

35

30

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

ANALOG

SHUTDOWN

CURRENT

ANALOG

SHUTDOWN

CURRENT

DIGITAL

SHUTDOWN

CURRENT

DIGITAL

SHUTDOWN

CURRENT

f

= 250ksps

SAMPLE

-40

-15

10

35

60

85

2.5

3.5

4.5

5.5

-40

-15

10

35

60

85

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

TEMPERATURE (°C)

INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

OFFSET ERROR vs. SUPPLY VOLTAGE

2.5004

2.5003

2.5002

2.5001

2.5000

2.4999

2.4998

2.4997

2.4996

1.5

1.0

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

0.5

0

-0.5

-1.0

-1.5

-2.0

NORMALIZED AT T = +25°C

A

4.7

4.8

4.9

5.0

5.1

5.2

5.3

4.75

4.85

4.95

5.05

5.15

5.25

-40

-15

10

35

60

85

AV (V)

DD

AV (V)

DD

TEMPERATURE (°C)

6

_______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Typical Operating Characteristics (continued)

(Aꢄ

= +5ꢄ, Dꢄ

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), see the Typical Operating Circuits,

REFML

DD

REF

V

= 1ꢆMHz 5ꢆ% dꢅty, ꢁITCꢀK/EXTCLK = AGID (external clock), LHDI = DGID, T = +25°Cꢃ)

A

CꢀK

OFFSET ERROR vs. TEMPERATURE

GAIN ERROR vs. SUPPLY VOLTAGE

GAIN ERROR vs. TEMPERATURE

0.04

16

15

14

13

12

11

10

9

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0.03

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

NORMALIZED AT T = +25°C

A

-40

-15

10

35

60

85

4.75

4.85

4.95

5.05

5.15

5.25

-40

-15

10

35

60

85

TEMPERATURE (°C)

AV (V)

DD

TEMPERATURE (°C)

SIGNAL-TO-NOISE RATIO

vs. CLOCK FREQUENCY

SIGNAL-TO-NOISE PLUS DISTORTION

vs. CLOCK FREQUENCY

FFT

80

79

78

77

76

75

74

73

72

71

70

0

-20

80

79

78

77

76

75

74

73

72

71

70

f

= 103kHz

= 490kHz

= 10MHz

ANALOG_IN

SAMPLE

CLK

f

= 100kHz

IN

f = 100kHz

IN

SINAD = 76.7dB

SNR = 77.0dB

THD = -88.3dB

SFDR = 91.0dB

-40

-60

-80

-100

-120

-140

8

10

12

14

16

18

20

0

0.05

0.10

0.15

0.20

0.25

8

10

12

14

16

18

20

f

(MHz)

FREQUENCY (MHz)

CLK

f

(MHz)

CLK

EFFECTIVE NUMBER OF BITS

vs. CLOCK FREQUENCY

TOTAL HARMONIC DISTORTION

vs. CLOCK FREQUENCY

SPURIOUS-FREE DYNAMIC RANGE

vs. CLOCK FREQUENCY

-70

-75

13.5

13.0

12.5

12.0

11.5

11.0

10.5

100

95

90

85

80

75

70

65

60

f

= 100kHz

IN

-80

-85

-90

-95

-100

8

10

12

14

16

18

20

8

10

12

14

16

18

20

8

10

12

14

16

18

20

f

(MHz)

f

(MHz)

f (MHz)

CLK

_______________________________________________________________________________________

7

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Typical Operating Characteristics (continued)

(Aꢄ

= +5ꢄ, Dꢄ

= +3ꢄ, AGID = DGID = ꢆꢄ, ꢄ

= ꢄ

= +2ꢃ5ꢄ (external reVerence), see the Typical Operating Circuits,

REFML

DD

REF

V

= 1ꢆMHz 5ꢆ% dꢅty, ꢁITCꢀK/EXTCLK = AGID (external clock), LHDI = DGID, T = +25°Cꢃ)

A

CꢀK

OUTPUT HISTOGRAM

(DC INPUT)

CONVERSION TIME

vs. TEMPERATURE

CONVERSION TIME

vs. ANALOG SUPPLY VOLTAGE

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

4500

4000

3500

3000

2500

2000

1500

1000

500

2.0

t

INTERNAL CLOCK

t

CONV

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3815

2306

1562

341

154

0

13

1

0

-40

-15

10

35

60

85

8209 8210 8211 8212 8213 8214 8215 8216 8217

DIGITAL OUTPUT CODE

4.750

4.875

5.000

5.125

5.250

TEMPERATURE (°C)

ANALOG SUPPLY VOLTAGE (V)

Pin Description

PꢁI

IAoE

FUICTꢁOI

Analog Lꢅpply ꢁnpꢅtꢃ Aꢄ

is the power inpꢅt Vor the analog section oV the converterꢃ Apply +5ꢄ to

DD

1, 15, 17

Aꢄ

DD

Aꢄ ꢃ Sypass Aꢄ

to AGID with a ꢆꢃ1µF capacitor at each Aꢄ

inpꢅtꢃ

DD

2, 3, 14,

16, 23

AGID

Analog Groꢅndꢃ AGID is the power retꢅrn Vor Aꢄ ꢃ Connect all AGIDs togetherꢃ

DD

4

A

ꢁI

Analog ꢁnpꢅt

5, 7–12

ꢁꢃCꢃ

ꢁnternally Connectedꢃ Connect ꢁꢃCꢃ to AGIDꢃ

Midscale ꢄoltage Sypassꢃ For the MAX1319, connect a 2ꢃ2µF and a ꢆꢃ1µF capacitor Vroꢂ MLꢄ to

AGIDꢃ For the MAX1323/MAX1327, connect MLꢄ directly to AGIDꢃ

6

MLꢄ

Clock-Mode Lelect ꢁnpꢅtꢃ Use ꢁITCꢀK/EXTCLK to select the internal or external conversion clockꢃ

ꢁITCꢀK/

EXTCLK

13

Connect ꢁITCꢀK/EXTCLK to Aꢄ

to select the internal clockꢃ Connect ꢁITCꢀK/EXTCLK to AGID to

DD

ꢅse an external clock connected to CꢀKꢃ

Midscale ReVerence Sypass or ꢁnpꢅtꢃ REF

is the bypass point Vor an internally generated reVerence

ML

voltageꢃ For the MAX1319, connect a ꢆꢃ1µF capacitor Vroꢂ REF to AGIDꢃ For the MAX1323/

18

19

REF

ML

MAX1327, connect REF

directly to REF and bypass with a ꢆꢃ1µF capacitor Vroꢂ REF to AGIDꢃ

ML

ADC ReVerence Sypass or ꢁnpꢅtꢃ REF is the bypass point Vor an internally generated reVerence

voltageꢃ Sypass REF with a ꢆꢃꢆ1µF capacitor to AGIDꢃ REF can be driven externally by a precision

external voltage reVerenceꢃ

REF

Positive ReVerence Sypassꢃ REF+ is the bypass point Vor an internally generated reVerence voltageꢃ Sypass

REF+ with a ꢆꢃ1µF capacitor to AGIDꢃ Also bypass REF+ to REF- with a 2ꢃ2µF and a ꢆꢃ1µF capacitorꢃ

2ꢆ

21

REF+

CꢇM

ReVerence Coꢂꢂon Sypassꢃ CꢇM is the bypass point Vor an internally generated reVerence voltageꢃ

Sypass CꢇM to AGID with a 2ꢃ2µF and a ꢆꢃ1µF capacitorꢃ

8

_______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Pin Description (continued)

PꢁI

IAoE

FUICTꢁOI

Iegative ReVerence Sypassꢃ REF- is the bypass point Vor an internally generated reVerence voltageꢃ Sypass

REF- with a ꢆꢃ1µF capacitor to AGIDꢃ Also bypass REF- to REF+ with a 2ꢃ2µF and a ꢆꢃ1µF capacitorꢃ

22

REF-

24

25

26

27

28

29

3ꢆ

31

32

33

34

35

36

37

38

Dꢆ

D1

Digital ꢇꢅt Sit ꢆ oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 1 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 2 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 3 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 4 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 5 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 6 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 7 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 8 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 9 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 1ꢆ oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 11 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 12 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

Digital ꢇꢅt Sit 13 oV 14-Sit Parallel Data Sꢅsꢃ High iꢂpedance when RD = 1 or CS = 1ꢃ

D2

D3

D4

D5

D6

D7

D8

D9

D1ꢆ

D11

D12

D13

Dꢄ

Digital Lꢅpply ꢁnpꢅtꢃ Apply +2ꢃ7ꢄ to +5ꢃ25ꢄ to Dꢄ ꢃ Sypass Dꢄ

to DGID with a ꢆꢃ1µF capacitorꢃ

DD

Digital Lꢅpply GIDꢃ DGID is the power retꢅrn Vor Dꢄ ꢃ Connect DGID to AGID at only one point

DD

(see the Layout, Grounding, and Bypassing section)ꢃ

39

4ꢆ

DGID

End-oV-Conversion ꢇꢅtpꢅtꢃ EOC goes low to indicate the end oV a conversionꢃ EOC retꢅrns high aVter

one clock periodꢃ

EOC

End-oV-ꢀast-Conversion ꢇꢅtpꢅtꢃ EOLC goes low to indicate the end oV the last conversionꢃ EOLC

retꢅrns high when CꢇIꢄLT goes low Vor the next conversion seqꢅenceꢃ For the MAX1319/MAX1323/

MAX1327, EOLC gives the saꢂe inVorꢂation as EOCꢃ

41

EOLC

Read ꢁnpꢅtꢃ Pꢅlling RD low initiates a read coꢂꢂand oV the parallel data bꢅses, Dꢆ–D13ꢃ Dꢆ–D13 are

high iꢂpedance while either RD or CS is highꢃ

42

43

44

RD

ꢁꢃCꢃ2

CS

ꢁnternally Connected 2ꢃ Connect ꢁꢃCꢃ2 to Dꢄ

ꢃ

DD

Chip-Lelect ꢁnpꢅtꢃ Pꢅlling CS low activates the digital interVaceꢃ Dꢆ–D13 are high iꢂpedance while

either CS or RD is highꢃ

Convert-Ltart ꢁnpꢅtꢃ Driving CꢇIꢄLT high places the device in hold ꢂode and initiates the

conversion processꢃ The analog inpꢅts are saꢂpled on the rising edge oV CꢇIꢄLTꢃ When CꢇIꢄLT

is low the analog inpꢅts are trackedꢃ

45

46

CꢇIꢄLT

CꢀK

External-Clock ꢁnpꢅtꢃ CꢀK accepts an external clock signal ꢅp to 15MHzꢃ Connect CꢀK to DGID Vor

internally clocked conversionsꢃ To select external clock ꢂode, set ꢁITCꢀK/EXTCLK = ꢆꢃ

47

48

LHDI

Lhꢅtdown ꢁnpꢅtꢃ Let LHDI = ꢆ Vor norꢂal operationꢃ Let LHDI = 1 Vor shꢅtdown ꢂodeꢃ

AꢀꢀꢇI is not iꢂpleꢂentedꢃ Connect AꢀꢀꢇI to DGIDꢃ

AꢀꢀꢇI

_______________________________________________________________________________________

9

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

MAX1319

MAX1323

MAX1327

DV

DD

AV

DD

D13

D0

14

SRAM

OUTPUT

DRIVERS

14-BIT

ADC

A

S/H

IN

MSV

*

CS

INTERFACE

AND

CONTROL

REF+

COM

REF-

RD

CONVST

SHDN

CLK

5kΩ

REF

ALLON

EOC

REF

MS

EOLC

DGND

2.500V

INTCLK/EXTCLK

AGND

*SWITCH CLOSED ON UNIPOLAR DEVICE, OPEN ON BIPOLAR DEVICES

Figure 1. Functional Diagram

Analog Inputs

Detailed Description

T/H

The MAX1319/MAX1323/MAX1327 are 14-bit, 526ksps,

1ꢃ6µs conversion-tiꢂe ADCsꢃ These devices are available

with ꢆ to +5ꢄ, 5ꢄ, and 1ꢆꢄ inpꢅt rangesꢃ The ꢆ to +5ꢄ

device Veatꢅres 6ꢄ Vaꢅlt-tolerant inpꢅts (see the Typical

Operating Circuits)ꢃ The 5ꢄ and 1ꢆꢄ devices Veatꢅre

16ꢃ5ꢄ Vaꢅlt-tolerant inpꢅts (see the Typical Operating

Circuits)ꢃ ꢁnternal or external reVerence, and clock capa-

bility oVVer great Vlexibility and ease oV ꢅseꢃ A 16ꢃ6MHz,

14-bit, parallel data bꢅs oꢅtpꢅts the conversion resꢅltꢃ

Figꢅre 1 shows the Vꢅnctional diagraꢂ oV these devicesꢃ

The tiꢂe reqꢅired Vor the T/H to acqꢅire an inpꢅt signal

depends on the inpꢅt soꢅrce iꢂpedanceꢃ ꢁV the inpꢅt sig-

nal’s soꢅrce iꢂpedance is high, the acqꢅisition tiꢂe

lengthens and ꢂore tiꢂe ꢂꢅst be allowed between con-

versionsꢃ The acqꢅisition tiꢂe (t

) is the ꢂaxiꢂꢅꢂ

tiꢂe the device takes to acqꢅire the signalꢃ Use the Vol-

lowing Vorꢂꢅla to calcꢅlate the acqꢅisition tiꢂe:

ACQ

t

= 1ꢆ (R + R ) x 6pF

L ꢁI

ACQ

where R = 2ꢃ2kΩ, R = the inpꢅt signal’s soꢅrce

ꢁI

L

iꢂpedance, and t

is never less than 18ꢆnsꢃ A

ACQ

soꢅrce iꢂpedance oV less than 1ꢆꢆΩ does not signiVi-

cantly aVVect the ADC’s perVorꢂanceꢃ

10 ______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

To iꢂprove the inpꢅt signal bandwidth ꢅnder AC condi-

Power-Saving Modes

tions, drive the inpꢅt with a wideband bꢅVVer (>5ꢆMHz)

that can drive the ADC’s inpꢅt capacitance and settle

qꢅicklyꢃ For exaꢂple, the MAX4265 can be ꢅsed Vor +5ꢄ

ꢅnipolar devices, or the MAX435ꢆ can be ꢅsed Vor 5ꢄ

bipolar inpꢅtsꢃ

Shutdown Mode

Dꢅring shꢅtdown, the analog and digital circꢅits in the

device power down and the device draws less than

1ꢆꢆµA Vroꢂ Aꢄ , and less than 1ꢆꢆµA Vroꢂ Dꢄ

ꢃ

DD

Lelect shꢅtdown ꢂode ꢅsing the LHDI inpꢅtꢃ Let

LHDI high to enter shꢅtdown ꢂodeꢃ AVter coꢂing oꢅt

oV shꢅtdown, allow the 1ꢂs wake-ꢅp beVore ꢂaking the

Virst conversionꢃ When ꢅsing an external clock, apply at

least 2ꢆ clock cycles with CꢇIꢄLT high beVore ꢂaking

the Virst conversionꢃ When ꢅsing internal clock ꢂode,

wait at least 2µs beVore ꢂaking the Virst conversionꢃ

The T/H apertꢅre delay is typically 13nsꢃ Figꢅre 2 shows

a siꢂpliVied eqꢅivalent inpꢅt circꢅit, illꢅstrating the ADC’s

saꢂpling architectꢅreꢃ

Input Bandwidth

The inpꢅt tracking circꢅitry has a 1ꢆMHz sꢂall-signal

bandwidth, ꢂaking it possible to digitize high-speed

transient events and ꢂeasꢅre periodic signals with

bandwidths exceeding the ADC’s saꢂpling rate by

ꢅsing ꢅndersaꢂpling techniqꢅesꢃ To avoid high Vre-

qꢅency signals being aliased into the Vreqꢅency band

oV interest, anti-alias Viltering is recoꢂꢂendedꢃ

Clock Modes

These devices provide an internal clock oV 1ꢆMHz

(typ)ꢃ Alternatively, an external clock can be ꢅsedꢃ

Internal Clock

ꢁnternal clock ꢂode Vrees the ꢂicroprocessor Vroꢂ the

bꢅrden oV rꢅnning the ADC conversion clockꢃ For inter-

Input Range and Protection

These devices provide 1ꢆꢄ, 5ꢄ or ꢆ to +5ꢄ analog

inpꢅt voltage rangesꢃ Figꢅre 2 shows the typical inpꢅt cir-

cꢅitꢃ ꢇvervoltage protection circꢅitry at the analog inpꢅt

provides 16ꢃ5ꢄ Vaꢅlt protection Vor the bipolar inpꢅt

devices and 6ꢃꢆꢄ Vaꢅlt protection Vor the ꢅnipolar inpꢅt

deviceꢃ This Vaꢅlt protection circꢅit liꢂits the cꢅrrent going

into or oꢅt oV the device to less than 5ꢆꢂA, providing an

added layer oV protection Vroꢂ ꢂoꢂentary overvoltage or

ꢅndervoltage conditions at the analog inpꢅtꢃ

nal clock operation, connect ꢁITCꢀK/EXTCLK to Aꢄ

and connect CꢀK to DGIDꢃ

DD

External Clock

For external clock operation, connect ꢁITCꢀK/EXTCLK

to AGID and connect an external clock soꢅrce to CꢀKꢃ

Iote that ꢁITCꢀK/EXTCLK is reVerenced to the analog

power sꢅpply, Aꢄ ꢃ The external clock Vreqꢅency can

DD

be ꢅp to 15MHz, with a dꢅty cycle between 3ꢆ% and

7ꢆ%ꢃ Clock Vreqꢅencies oV 1ꢆꢆkHz and lower can be

ꢅsed, bꢅt the droop in the T/H circꢅits redꢅces linearityꢃ

Selecting an Input Buffer

Most applications reqꢅire an inpꢅt bꢅVVer to achieve 14-

bit accꢅracyꢃ Althoꢅgh slew rate and bandwidth are

iꢂportant, the ꢂost critical speciVication is settling tiꢂeꢃ

The saꢂpling reqꢅires a relatively brieV saꢂpling inter-

val oV 15ꢆnsꢃ At the beginning oV the acqꢅisition, the

internal saꢂpling capacitor array connects to the

aꢂpliVier oꢅtpꢅt, caꢅsing soꢂe oꢅtpꢅt distꢅrbanceꢃ

Ensꢅre the aꢂpliVier is capable oV settling to at least 14-

bit accꢅracy dꢅring this intervalꢃ Use a low-noise, low-

distortion, wideband aꢂpliVier (sꢅch as the MAX433ꢆ or

MAX4265), which settles qꢅickly and is stable with the

ADC’s capacitive load (in parallel with any bypass

capacitors on the analog inpꢅts)ꢃ

MAX1319

MAX1323

MAX1327

5pF

R1

A

IN

C

PAR

R2

1pF

V

BIAS

INPUT RANGE (V) R1 (kΩ) R2 (kΩ)

0 TO +5

3.33

6.67

5.00

2.86

2.35

5

10

13.33

Figure 2. Typical Input Circuit

______________________________________________________________________________________ 11

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Vaceꢃ The parallel interVace goes high iꢂpedance when

RD = 1 or CS = 1ꢃ

Applications Information

Digital Interface

The parallel digital interVace oꢅtpꢅts the 14-bit conver-

sion resꢅltꢃ The interVace inclꢅdes the Vollowing control

signals: chip select (CS), read (RD), end oV conversion

(EOC), end oV last conversion (EOLC), convert start

(CꢇIꢄLT), shꢅtdown (LHDI), all on (AꢀꢀꢇI), internal

clock select (ꢁITCꢀK /EXTCLK), and external clock

inpꢅt (CꢀK)ꢃ Figꢅres 3 and 4, Table 1, and the Timing

Characteristics table show the operation oV the inter-

Starting a Conversion

To start a conversion ꢅsing internal clock ꢂode, pꢅll

CꢇIꢄLT low Vor at least the acqꢅisition tiꢂe (t )ꢃ The

ACQ

T/H acqꢅires the signal while CꢇIꢄLT is low, and con-

version begins on the rising edge oV CꢇIꢄLTꢃ The end-

oV-conversion signal (EOC) or the end-oV-last-conversion

signal (EOLC) pꢅlses low when the conversion resꢅlt is

available (Figꢅre 3)ꢃ

SAMPLE

t

13

ACQ

CONVST

TRACK

t

HOLD

TRACK

t

EOC1

12

EOC

t

3

RD

t

10

D0–D13

CH0

t

11

Figure 3. Reading a Conversion—Internal Clock

Tablꢇ 1. Rꢇfꢇrꢇꢄcꢇ Bypass Capacitꢃrs

ꢁIPUT VOꢀTAGE RAIGE

ꢀOCATꢁOI

UIꢁPOꢀAR (µF)

2ꢃ2 || ꢆꢃ1

ꢆꢃꢆ1

BꢁPOꢀAR (µF)

IA

MLꢄ Sypass Capacitor to AGID

REF

Sypass Capacitor to AGID

ꢆꢃꢆ1

ML

REF Sypass Capacitor to AGID

REF+ Sypass Capacitor to AGID

REF+ to REF- Capacitor

ꢆꢃꢆ1

ꢆꢃ1

2ꢃ2 || ꢆꢃ1

ꢆꢃ1

2ꢃ2 || ꢆꢃ1

ꢆꢃ1

REF- Sypass Capacitor to AGID

CꢇM Sypass Capacitor to AGID

2ꢃ2 || ꢆꢃ1

NA = Not applicable (connect MSV directly to AGND).

12 ______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

To start a conversion ꢅsing external clock ꢂode, pꢅll

CꢇIꢄLT low Vor at least the acqꢅisition tiꢂe (t )ꢃ The

low at all tiꢂes; it can be low dꢅring the RD cycles, or it

can be the saꢂe as RDꢃ

ACQ

T/H acqꢅires the signal while CꢇIꢄLT is low, and con-

version begins on the rising edge oV CꢇIꢄLTꢃ Apply an

external clock to the CꢀK pinꢃ To avoid T/H droop

degrading the saꢂpled analog inpꢅt signals, the Virst

clock pꢅlse shoꢅld occꢅr within 1ꢆµs Vroꢂ the rising

edge oV CꢇIꢄLT, and have a ꢂiniꢂꢅꢂ clock Vreqꢅency

oV 1ꢆꢆkHzꢃ The conversion resꢅlt is available Vor read on

the rising edge oV the 17th clock cycle (Figꢅre 4)ꢃ

AVter initiating a conversion by bringing CꢇIꢄLT high,

wait Vor EOC or EOLC to go low (aboꢅt 1ꢃ6µs in internal

clock ꢂode or 17 clock cycles in external clock ꢂode)

beVore reading the Virst conversion resꢅltꢃ Read the

conversion resꢅlt by bringing RD low and latching the

data to the parallel digital-oꢅtpꢅt bꢅsꢃ Sring RD high to

release the digital bꢅsꢃ

Power-Up Reset

AVter applying power, allow the 1ꢃꢆꢂs wake-ꢅp tiꢂe to

elapse beVore initiating the Virst conversionꢃ ꢁV ꢅsing an

external clock, apply 2ꢆ clock pꢅlses to CꢀK with

CꢇIꢄLT high beVore initiating the Virst conversionꢃ ꢁV

ꢅsing an internal clock, hold CꢇIꢄLT high Vor at least

2ꢃꢆµs aVter the wake-ꢅp tiꢂe is coꢂpleteꢃ

ꢁn both internal and external clock ꢂodes, CꢇIꢄLT

ꢂꢅst be held high ꢅntil the last conversion resꢅlt is

readꢃ For best operation, the rising edge oV CꢇIꢄLT

ꢂꢅst be a clean, high-speed, low-jitter digital signalꢃ

ꢁt is necessary to have a period oV inactivity on the digi-

tal bꢅs dꢅring signal aqꢅisitionꢃ t

is the period

QUꢁET

between the RD rising edge and the Valling edge oV

CꢇIꢄLT shown in Figꢅre 4ꢃ Allow a ꢂiniꢂꢅꢂ oV 5ꢆns

Reference

Vor t

ꢃ

QUꢁET

Internal Reference

The internal reVerence circꢅits provide Vor analog inpꢅt

voltages oV ꢆ to +5ꢄ ꢅnipolar (MAX1319), 5ꢄ bipolar

(MAX1323) or 1ꢆꢄ bipolar (MAX1327)ꢃ ꢁnstall external

capacitors Vor reVerence stability, as indicated in Table 1,

and as shown in the Typical Operating Circuitsꢃ

Reading a Conversion Result

Reading During a Conversion

Figꢅres 3 and 4 show the interVace signals Vor initiating

a read operation dꢅring a conversion cycleꢃ CS can be

SAMPLE

t

13

ACQ

HOLD

CONVST

TRACK

t

19

t

16

17

2

1

3

16

17

18

19

20

1

CLK

EOC

t

18

t

QUIET

t

12

t

20

CS

RD

t

2

t

9

8

t

3

t

10

D0–D13

t

11

Figure 4. Reading a Conversion—External Clock

______________________________________________________________________________________ 13

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

power sꢅpply is very noisy, a Verrite bead can be con-

nected as a lowpass Vilter, as shown in Figꢅre 5ꢃ

Transfer Functions

SUPPLIES

Bipolar ±1ꢀ0 Device

Table 2 and Figꢅre 6 show the two’s coꢂpleꢂent trans-

Ver Vꢅnction Vor the MAX1327 with a 1ꢆꢄ inpꢅt rangeꢃ

The Vꢅll-scale inpꢅt range (FLR) is eight tiꢂes the volt-

age at REFꢃ The internal +2ꢃ5ꢆꢆꢄ reVerence gives a

+2ꢆꢄ FLR, while an external +2ꢄ to +3ꢄ reVerence

allows an FLR oV +16ꢄ to +24ꢄ, respectivelyꢃ Calcꢅlate

the ꢀLS size ꢅsing the Vollowing eqꢅation:

+5V

RETURN

+3V TO +5V

RETURN

OPTIONAL

FERRITE

BEAD

8 × ꢄ

REFADC

14

1 ꢀLS =

2

AV

DV

DD

AGND

DGND

V

DD

GND

This eqꢅals 1ꢃ22ꢆ7ꢂꢄ with a +2ꢃ5ꢄ internal reVerenceꢃ

The inpꢅt range is centered aboꢅt ꢄ ꢃ Iorꢂally, MLꢄ

DIGITAL

CIRCUITRY

MLꢄ

MAX1319

MAX1323

MAX1327

= AGID, and the inpꢅt is syꢂꢂetrical at aboꢅt zeroꢃ For

a cꢅstoꢂ ꢂidscale voltage, drive MLꢄ with an external

voltage soꢅrceꢃ Ioise present on MLꢄ directly coꢅples

into the ADC resꢅltꢃ Use a precision, low-driVt voltage reV-

erence with adeqꢅate bypassing to prevent MLꢄ Vroꢂ

degrading ADC perVorꢂanceꢃ For ꢂaxiꢂꢅꢂ Vꢅll-scale

range, be careVꢅl not to violate the absolꢅte ꢂaxiꢂꢅꢂ

voltage ratings oV the analog inpꢅts when choosing MLꢄꢃ

Figure 5. Power-Supply Grounding and Bypassing

External Reference

Connect a +2ꢃꢆꢄ to +3ꢃꢆꢄ external reVerence at REF

ML

Deterꢂine the inpꢅt voltage as a Vꢅnction oV ꢄ

MLꢄ

ing eqꢅation:

,

REF

and/or REFꢃ When connecting an external reVerence,

the inpꢅt iꢂpedance is typically 5kΩꢃ The external reV-

erence ꢂꢅst be able to drive 2ꢆꢆµA oV cꢅrrent and be

less than 3Ω oꢅtpꢅt iꢂpedanceꢃ For ꢂore inVorꢂation

aboꢅt ꢅsing external reVerences see the Transfer

Functions sectionꢃ

ꢄ

, and the oꢅtpꢅt code in deciꢂal ꢅsing the Vollow-

ꢄ

= ꢀLS × CꢇDE + ꢄ

1ꢆ MLꢄ

CH_

Bipolar ±±0 Device

Table 3 and Figꢅre 7 show the two’s coꢂpleꢂent transVer

Vꢅnction Vor the MAX1323 with a 5ꢄ inpꢅt rangeꢃ The

FLR is Voꢅr tiꢂes the voltage at REFꢃ The internal +2ꢃ5ꢆꢆꢄ

reVerence gives a +1ꢆꢄ FLR, while an external +2ꢄ to

+3ꢄ reVerence allows an FLR oV +8ꢄ to +12ꢄ, respective-

lyꢃ Calcꢅlate the ꢀLS size ꢅsing the Vollowing eqꢅation:

Layout, Grounding, and Bypassing

For best perVorꢂance ꢅse PC boardsꢃ Soard layoꢅt

shoꢅld ensꢅre that digital and analog signal lines are

separated Vroꢂ each otherꢃ Do not rꢅn analog and digi-

tal lines parallel to one another (especially clock lines),

or do not rꢅn digital lines ꢅnderneath the ADC pack-

ageꢃ Figꢅre 5 shows the recoꢂꢂended systeꢂ groꢅnd

connectionsꢃ A single-point analog groꢅnd (star groꢅnd

point) shoꢅld be established at AGID, separate Vroꢂ

the logic groꢅndꢃ All other analog groꢅnds and DGID

shoꢅld be connected to this groꢅndꢃ Io other digital

systeꢂ groꢅnd shoꢅld be connected to this single-point

analog groꢅndꢃ The groꢅnd retꢅrn to the power sꢅpply

Vor this groꢅnd shoꢅld be low iꢂpedance and as short

as possible Vor noise-Vree operationꢃ High-Vreqꢅency

4 × ꢄ

REFADC

14

1 ꢀLS =

2

This eqꢅals ꢆꢃ61ꢆ4ꢂꢄ when ꢅsing the internal reVerenceꢃ

The inpꢅt range is centered aboꢅt ꢄ ꢃ Iorꢂally,

MLꢄ

MLꢄ = AGID, and the inpꢅt is syꢂꢂetrical at aboꢅt

zeroꢃ For a cꢅstoꢂ ꢂidscale voltage, drive MLꢄ with an

external voltage soꢅrceꢃ Ioise present on MLꢄ directly

coꢅples into the ADC resꢅltꢃ Use a precision, low-driVt

voltage reVerence with adeqꢅate bypassing to prevent

MLꢄ Vroꢂ degrading ADC perVorꢂanceꢃ For ꢂaxiꢂꢅꢂ

Vꢅll-scale range, be careVꢅl not to violate the absolꢅte

noise in the ꢄ

power sꢅpply ꢂay aVVect the high-

DD

speed coꢂparator in the ADCꢃ Sypass these sꢅpplies

to the single-point analog groꢅnd with ꢆꢃ1µF and 2ꢃ2µF

bypass capacitors close to the deviceꢃ ꢁV the +5ꢄ

14 ______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Tablꢇ 2. 10V Bipꢃlar Cꢃꢆꢇ Tablꢇ

8 x V

REFADC

DECꢁoAꢀ

EQUꢁVAꢀEIT VOꢀTAGE (V)

ꢁIPUT

0x1FFF

0x1FFE

0x1FFD

0x1FFC

TWO’L COoPꢀEoEIT

BꢁIARY OUTPUT CODE

OUTPUT

(CODE

(V

= 2.5Vꢂ

= 0V)

REF

V

oLV

)

10

ꢆ1 1111 1111 1111 ➔

8191

819ꢆ

1

9ꢃ9988

9ꢃ9976

ꢆꢃꢆꢆ12

ꢆ

0x0001

0x0000

0x3FFF

ꢆx1FFF

8 x V

REFADC

ꢆ1 1111 1111 111ꢆ ➔

ꢆx1FFE

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

ꢆxꢆꢆꢆ1

0x2003

0x2002

0x2001

0x2000

8 x V

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

REFADC

2¹⁴

1 LSB =

ꢆ

ꢆxꢆꢆꢆꢆ

11 1111 1111 1111 ➔

-1

-ꢆꢃꢆꢆ12

-9ꢃ9988

-1ꢆꢃꢆꢆꢆꢆ

-8192 -8190

-1

(MSV)

INPUT VOLTAGE (V

0

+1

+8189 +8191

IN LSBs)

MSV

ꢆx3FFF

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

- V

CH_

-8191

-8192

ꢆx2ꢆꢆ1

Figure 6. 10V Bipolar Transfer Function

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

ꢆx2ꢆꢆꢆ

4 x V

REFADC

Tablꢇ 3. 5V Bipꢃlar Cꢃꢆꢇ Tablꢇ

0x1FFF

0x1FFE

0x1FFD

0x1FFC

DECꢁoAꢀ

ꢁIPUT

TWO’L COoPꢀEoEIT

BꢁIARY OUTPUT CODE

EQUꢁVAꢀEIT VOꢀTAGE (V)

OUTPUT

(CODE

(V

= 2.5Vꢂ

= 0V)

REF

V

oLV

)

10

0x0001

0x0000

0x3FFF

4 x V

REFADC

ꢆ1 1111 1111 1111 ➔

8191

819ꢆ

1

4ꢃ9994

4ꢃ9988

ꢆꢃꢆꢆꢆ6

ꢆ

ꢆx1FFF

ꢆ1 1111 1111 111ꢆ ➔

ꢆx1FFE

0x2003

0x2002

0x2001

0x2000

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

4 x V

REFADC

2¹⁴

1 LSB =

ꢆxꢆꢆꢆ1

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

ꢆ

ꢆxꢆꢆꢆꢆ

-8192 -8190

-1

(MSV)

INPUT VOLTAGE (V

0

+1

+8189 +8191

IN LSBs)

MSV

11 1111 1111 1111 ➔

-1

-ꢆꢃꢆꢆꢆ6

-4ꢃ9994

-5ꢃꢆꢆꢆꢆ

- V

CH_

ꢆx3FFF

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

Figure 7. 5V Bipolar Transfer Function

-8191

-8192

ꢆx2ꢆꢆ1

ꢂaxiꢂꢅꢂ voltage ratings oV the analog inpꢅts when

choosing MLꢄꢃ Deterꢂine the inpꢅt voltage as a Vꢅnc-

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

ꢆx2ꢆꢆꢆ

tion oV ꢄ

, ꢄ

, and the oꢅtpꢅt code in deciꢂal

MLꢄ

REF

ꢅsing the Vollowing eqꢅation:

= ꢀLS × CꢇDE + ꢄ

MLꢄ

ꢄ

CH_

1ꢆ

______________________________________________________________________________________ 15

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Tablꢇ 4. 0 tꢃ +5V Uꢄipꢃlar Cꢃꢆꢇ Tablꢇ

2 x V

REFADC

DECꢁoAꢀ

EQUꢁVAꢀEIT VOꢀTAGE (V)

OUTPUT (V = V

(CODE

ꢁIPUT

0x3FFF

0x3FFE

0x3FFD

0x3FFC

BꢁIARY OUTPUT CODE

REF

REFoL

)

= 2.5V)

10

11 1111 1111 1111 ➔

16383

16382

8193

8192

8191

1

4ꢃ9997

ꢆx3FFF

0x2001

0x2000

0x1FFF

2 x V

REFADC

11 1111 1111 111ꢆ ➔

4ꢃ9994

2ꢃ5ꢆꢆ3

2ꢃ5ꢆꢆꢆ

2ꢃ4997

ꢆꢃꢆꢆꢆ3

ꢆ

ꢆx3FFE

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

ꢆx2ꢆꢆ1

0x0003

0x0002

0x0001

0x0000

1ꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

2 x V

REFADC

1 LSB =

ꢆx2ꢆꢆꢆ

2¹⁴

ꢆ1 1111 1111 1111 ➔

ꢆx1FFF

0

2

8192

8190 8194

16,381 16,383

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆ1 ➔

(MSV)

ꢆxꢆꢆꢆ1

INPUT VOLTAGE (LSBs)

ꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ꢆꢆꢆꢆ ➔

ꢆ

ꢆxꢆꢆꢆꢆ

Figure 8. 0 to +5V Unipolar Transfer Function

Unipolar ꢀ to +±0 Device

Table 4 and Figꢅre 8 show the oVVset binary transVer Vꢅnc-

tion Vor the MAX1319 with a ꢆ to +5ꢄ inpꢅt rangeꢃ The

FLR is two tiꢂes the voltage at REFꢃ The internal +2ꢃ5ꢆꢆꢄ

reVerence gives a +5ꢄ FLR, while an external +2ꢄ to +3ꢄ

reVerence allows an FLR oV +4ꢄ to +6ꢄ, respectivelyꢃ

Calcꢅlate the ꢀLS size ꢅsing the Vollowing eqꢅation:

ꢄ

= ꢀLS × CꢇDE + ꢄ

- 2ꢃ5ꢆꢆꢄ

(

)

CH_

1ꢆ

MLꢄ

Definitions

Integral Nonlinearity (INL)

ꢁntegral nonlinearity is the deviation oV the valꢅes on an

actꢅal transVer Vꢅnction Vroꢂ a straight lineꢃ For these

devices this straight line is a line drawn between the

endpoints oV the transVer Vꢅnction, once oVVset and gain

errors have been nꢅlliViedꢃ

2 × ꢄ

REFADC

14

1 ꢀLS =

2

Differential Nonlinearity (DNL)

DiVVerential nonlinearity is the diVVerence between an

actꢅal step width and the ideal valꢅe oV 1 ꢀLSꢃ For

these devices, the DIꢀ oV each digital oꢅtpꢅt code is

ꢂeasꢅred and the worst-case valꢅe is reported in the

Electrical Characteristics tableꢃ A DIꢀ error speciVica-

tion oV less than 1 ꢀLS gꢅarantees no ꢂissing codes

and a ꢂonotonic transVer Vꢅnctionꢃ

This eqꢅals ꢆꢃ3ꢆ52ꢂꢄ when ꢅsing the internal reVerenceꢃ

The inpꢅt range is centered aboꢅt ꢄ , which is inter-

MLꢄ

nally set to +2ꢃ5ꢆꢆꢄꢃ For a cꢅstoꢂ ꢂidscale voltage,

drive REF with an external voltage soꢅrce and MLꢄ

ML

will Vollow REF ꢃ Ioise present on MLꢄ or REF

ML

directly coꢅples into the ADC resꢅltꢃ Use a precision,

low-driVt voltage reVerence with adeqꢅate bypassing to

prevent MLꢄ Vroꢂ degrading ADC perVorꢂanceꢃ For

ꢂaxiꢂꢅꢂ Vꢅll-scale range, be careVꢅl not to violate the

absolꢅte ꢂaxiꢂꢅꢂ voltage ratings oV the analog inpꢅts

when choosing MLꢄꢃ Deterꢂine the inpꢅt voltage as a

Unipolar Offset Error

For the ꢅnipolar MAX1319, the ideal ꢂidscale transition

Vroꢂ ꢆx1FFF to ꢆx2ꢆꢆꢆ occꢅrs at MLꢄ (see Figꢅre 8)ꢃ

The ꢅnipolar oVVset error is the aꢂoꢅnt oV deviation

between the ꢂeasꢅred ꢂidscale transition point and

the ideal ꢂidscale transition pointꢃ

Vꢅnction oV ꢄ

, ꢄ

, and the oꢅtpꢅt code in deciꢂal

REF MLꢄ

ꢅsing the Vollowing eqꢅation:

16 ______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Bipolar Offset Error

Total Harmonic Distortion

Total harꢂonic distortion (THD) is the ratio oV the RML

sꢅꢂ oV the Virst Vive harꢂonics oV the inpꢅt signal to the

Vꢅndaꢂental itselVꢃ This is expressed as:

For the bipolar MAX1323/MAX1327, the ideal zero-point

transition Vroꢂ ꢆx3FFF to ꢆxꢆꢆꢆꢆ occꢅrs at MLꢄ, which

is ꢅsꢅally connected to groꢅnd (see Figꢅres 6 and 7)ꢃ

The bipolar oVVset error is the aꢂoꢅnt oV deviation

between the ꢂeasꢅred zero-point transition and the

ideal zero-point transitionꢃ

⎡

⎢

⎤

⎥

2

ꢄ

+ ꢄ + ꢄ + ꢄ

3 4 5

2

THD = 2ꢆ × log

ꢄ

1

⎢

⎣

⎥

⎦

Gain Error

The ideal Vꢅll-scale transition Vroꢂ ꢆx1FFE to ꢆx1FFF

occꢅrs at 1 ꢀLS below Vꢅll scale (see the Transfer

Functions section)ꢃ The gain error is the aꢂoꢅnt oV devi-

ation between the ꢂeasꢅred Vꢅll-scale transition point

and the ideal Vꢅll-scale transition point, once oVVset error

has been nꢅlliViedꢃ

where ꢄ is the Vꢅndaꢂental aꢂplitꢅde and ꢄ throꢅgh

2

1

ꢄ are the 2nd- throꢅgh 5th-order harꢂonicsꢃ

5

Spurious-Free Dynamic Range

Lpꢅrioꢅs-Vree dynaꢂic range (LFDR) is the ratio oV the

RML aꢂplitꢅde oV the Vꢅndaꢂental (ꢂaxiꢂꢅꢂ signal

coꢂponent) to the RML valꢅe oV the next largest Vre-

qꢅency coꢂponentꢃ

Signal-to-Noise Ratio

For a waveVorꢂ perVectly reconstrꢅcted Vroꢂ digital

saꢂples, signal-to-noise ratio (LIR) is the ratio oV the

Vꢅll-scale analog inpꢅt (RML valꢅe) to the RML qꢅanti-

zation error (residꢅal error)ꢃ The ideal, theoretical ꢂini-

ꢂꢅꢂ analog-to-digital noise is caꢅsed by qꢅantization

noise error only and resꢅlts directly Vroꢂ the ADC’s res-

olꢅtion (I bits):

Aperature Delay

Apertꢅre delay (t ) is the tiꢂe delay Vroꢂ the saꢂpling

AD

clock edge to the instant when an actꢅal saꢂple is takenꢃ

Aperture Jitter

Apertꢅre Jitter (t ) is the saꢂple-to-saꢂple variation in

AJ

apertꢅre delayꢃ

LIR = (6ꢃꢆ2 × I + 1ꢃ76)dS

Small-Signal Bandwidth

A sꢂall -2ꢆdSFL analog inpꢅt signal is applied to an

ADC in a ꢂanner that ensꢅres that the signal’s slew

rate does not liꢂit the ADC’s perVorꢂanceꢃ The inpꢅt

Vreqꢅency is then swept ꢅp to the point where the

aꢂplitꢅde oV the digitized conversion resꢅlt has

decreased by -3dSꢃ

where I = 14 bitsꢃ

ꢁn reality, there are other noise soꢅrces besides qꢅanti-

zation noise; therꢂal noise, reVerence noise, clock jitter,

etcꢃ LIR is coꢂpꢅted by taking the ratio oV the RML

signal to the RML noise, which inclꢅdes all spectral

coꢂponents ꢂinꢅs the Vꢅndaꢂental, the Virst Vive har-

ꢂonics, and the DC oVVsetꢃ

Full-Power Bandwidth

A large -ꢆꢃ5dSFL analog inpꢅt signal is applied to an

ADC, and the inpꢅt Vreqꢅency is swept ꢅp to the point

where the aꢂplitꢅde oV the digitized conversion resꢅlt

has decreased by -3dSꢃ This point is deVined as Vꢅll-

power inpꢅt bandwidth Vreqꢅencyꢃ

Signal-to-Noise Plus Distortion

Lignal-to-noise plꢅs distortion (LꢁIAD) is the ratio oV the

Vꢅndaꢂental inpꢅt Vreqꢅency’s RML aꢂplitꢅde to the

RML eqꢅivalent oV all the other ADC oꢅtpꢅt signalsꢃ

⎡

⎢

⎣

⎤

⎥

⎦

Lignal

(Ioise + Distortion)

RML

LꢁIAD(dS) = 2ꢆ × log

RML

Effective Number of Bits

EVVective nꢅꢂber oV bits (EIꢇS) indicates the global

accꢅracy oV an ADC at a speciVic inpꢅt Vreqꢅency and

saꢂpling rateꢃ An ideal ADC’s error consists oV qꢅanti-

zation noise onlyꢃ With an inpꢅt range eqꢅal to the Vꢅll-

scale range oV the ADC, calcꢅlate the EIꢇS as Vollows:

Chip Information

TRAILꢁLTꢇR CꢇUIT: 8ꢆ,ꢆꢆꢆ

PRꢇCELL: ꢆꢃ6µꢂ SiCMꢇL

LꢁIAD - 1ꢃ76

EIꢇS =

6ꢃꢆ2

______________________________________________________________________________________ 17

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Typical Operating Circuits

I.C.2

38

13

+3V

DV

INTCLK/EXTCLK

DD

+5V

0.1µF

MAX1319

1

39

DGND

GND

AV

DD

0.1µF

15

17

0.1µF

2.2µF

44

42

45

47

48

46

40

41

CS

RD

6

MSV

CONVST

SHDN

ALLON

CLK

UNIPOLAR

CONFIGURATION

DIGITAL

INTERFACE

AND

0.01µF

18

19

REF

MS

CONTROL

0.01µF

EOC

0.1µF

20

EOLC

REF+

REF-

0.1µF

2.2µF

37

36

35

34

33

32

31

30

29

28

27

26

25

24

22

D13

D12

D11

D10

D9

0.1µF

2.2µF

21

0.1µF

COM

2, 3, 14, 16, 23

GND

AGND

D8

12

11

10

9

PARALLEL

DIGITAL

OUTPUTS

D7

I.C.

CH0

D6

D5

D4

8

D3

7

D2

5

D1

ANALOG

INPUTS

0 TO +5V

4

D0

18 ______________________________________________________________________________________

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Typical Operating Circuits (continued)

I.C.2

38

39

13

1

+3V

DV

INTCLK/EXTCLK

DD

+5V

0.1µF

MAX1323

MAX1327

DGND

GND

AV

DD

AV

DD

AV

DD

0.1µF

15

17

44

42

45

47

48

46

40

41

CS

RD

6

18

19

MSV

REF

CONVST

SHDN

ALLON

CLK

BIPOLAR

CONFIGURATION

DIGITAL

INTERFACE

AND

0.01µF

MS

CONTROL

REF

0.1µF

EOC

20

REF+

EOLC

0.1µF

2.2µF

37

36

35

34

33

32

31

30

29

28

27

26

25

24

22

D13

D12

D11

D10

D9

REF-

0.1µF

2.2µF

21

0.1µF

COM

2, 3, 14, 16, 23

GND

AGND

D8

12

11

10

9

PARALLEL

DIGITAL

OUTPUTS

D7

I.C.

CH0

D6

D5

D4

8

D3

7

D2

5

BIPOLAR

ANALOG

INPUTS

D1

4

D0

______________________________________________________________________________________ 19

526ksps, Single-Channel,

14-Bit, Parallel-Interface ADCs

Package Information

(The package drawing(s) in this data sheet ꢂay not reVlect the ꢂost cꢅrrent speciVicationsꢃ For the latest package oꢅtline inVorꢂation

go to www.maxim-ic.cꢃm/packaꢅꢇsꢃ)

PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm

1

21-0054

E

2

PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm

2

21-0054

E

2

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed ULA

is a registered tradeꢂark oV Maxiꢂ ꢁntegrated Prodꢅcts, ꢁncꢃ


型号：	MAX1323
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	526ksps, Single-Channel, 14-Bit, Parallel-Interface ADCs
文件：	总20页 (文件大小：256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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