MAX13345EETD+T [MAXIM]
Interface Circuit, BICMOS, PDSO14, 3 X 3 MM, 0.80 MM HEIGHT, LEAD FREE, DFN-14;
| 型号： | MAX13345EETD+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, BICMOS, PDSO14, 3 X 3 MM, 0.80 MM HEIGHT, LEAD FREE, DFN-14 电信 信息通信管理 光电二极管 电信集成电路 |
| 文件： | 总18页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0621; Rev 0; 10/06
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
General Description
Features
ꢀ USB 2.0 (Full-Speed, 12Mbps)-Compliant
The MAX13342E/MAX13345E USB-compliant trans-
ceivers are designed to minimize the area and external
components required to interface low-voltage ASICs to
USB. The devices comply with USB 2.0 specification for
full-speed-only (12Mbps) operation. The transceivers
include an internal 3.3V regulator, an internal 1.5k D+
pullup resistor, and built-in 15kV ESD protection cir-
cuitry to protect the USB I/0 ports (D+,D-). The
MAX13345E also has internal series resistors, allowing
it to be wired directly to a USB connector.
Transceiver
ꢀ Internal Pullup
ꢀ V
Detection
BUS
ꢀ Internal Series Resistors (MAX13345E)
15ꢀV (ꢁBM) ESD Protection on Dꢂ, D-, and V
ꢀ
BUS
ꢀ Enumeration Input Controls Dꢂ Pullup Resistor
ꢀ Supports 3-Wire DAT/SE0 Interface
These devices operate with logic-supply voltages as
low as +2.3V, ensuring compatibility with low-voltage
ASICs. A low-power mode reduces current consump-
tion to less than 45µA. An enumerate function controls
the D+ pullup resistor, allowing devices to logically dis-
connect while remaining plugged in.
ꢀ ꢂ2.3V to ꢂ3.6V Interface Voltage (V )
L
ꢀ No Power-Supply Sequencing Required
ꢀ Low USB Output Impedance (MAX13342E)
Ordering Information
The MAX13342E has controlled output impedance of
PIN-
PACKAGE
TOP
MARK
2
(max) on D+/D-, allowing the use of external switch-
PART
PKG CODE
es to multiplex two different USB devices onto a single
USB connector. The MAX13345E has 43.5 (max)
internal resistors on D+/D- for direct connection to the
USB connector.
14 TDFN-EP
(3mm x 3mm)
MAX13342EETD+
MAX13342EEBC+*
MAX13345EETD+
MAX13345EEBC+*
ACZ
ACU
ADA
ACX
T1433-2
B12-3
12 UCSP
(2.0mm x 1.5mm)
The MAX13342E/MAX13345E are equipped with DAT
and SE0 interface signals. These transceivers provide a
USB detection function that monitors the presence of
14 TDFN-EP
(3mm x 3mm)
T1433-2
B12-3
USB V
and signals the event.
BUS
12 UCSP
(2.0mm x 1.5mm)
These devices operate over the extended -40°C to +85°C
temperature range and are available in UCSP™ 2.0mm x
1.5mm and 14-pin TDFN (3mm x 3mm) packages.
*Future product—contact factory for availability.
+Denotes lead-free package.
EP = Exposed pad.
UCSP™ is a trademark of Maxim Integrated Products, Inc.
Applications
Typical Operating Circuits
PDAs
SYSTEM
VOLTAGE
SUPPLY
PC Peripherals
Cellular Telephones
Data Cradles
MP3 Players
V
V
L
BUS
1 F
0.1 F
MAX13342E
BD
V
TRM
SYSTEM
DAT
SEO
OE
INTERFACE
1 F
ENUM
SUS
Pin Configurations and Selector Guide appear at end of data
sheet.
D+
D-
USB
CONNECTOR
31.6
31.6
GND
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
ABSOLUTE MAXIMUM RATINGS
(All voltages refer to GND unless otherwise noted.)
Continuous Power Dissipation (T = +70°C)
A
Supply Voltage (V
System Supply Voltage (V ).....................................-0.3V to +6V
) .............................................-0.3V to +6V
14-Pin TDFN (derate 18.5mW/°C above +70°C) .......1482mW
4mm x 3mm UCSP
BUS
L
Output of Internal Regulator (V
Input Voltage (D+, D-)..............................................-0.3V to +6V
SUS, BD ........................................................-0.3V to (V + 0.3V)
) .........-0.3V to (V
+ 0.3V)
(derate 6.5mW/°C above +70°C)..............................518mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Bump Soldering ...............................................................+235°C
Lead Soldering (10s) ...................................................... +300°C
TRM
BUS
L
L
ENUM, SE0, DAT ..........................................-0.3V to (V + 0.3V)
Short-Circuit Current to V
or GND (D+, D-).............. 150mA
BUS
Maximum Continuous Current (all other pins).................. 15mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CꢁARACTERISTICS
(V
= +4.0V to +5.5V, V = +2.3V to +3.6V, T = T
to T
, unless otherwise noted. Typical values are at V
= +5.0V, V =
BUS L
BUS
L
A
MIN
MAX
+2.5V, T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY INPUTS (V
, V
, V )
BUS TRM L
V
Input Range
V
V
4.0
2.3
3.0
5.5
3.6
3.6
V
V
V
BUS
BUS
V Input Range
V
L
L
Regulated Supply-Voltage Output
3.3
1.5
TRM
Full-speed transmitting/receiving at
12Mbps, C = 50pF on D+ and D-
L
Operating V Supply Current
I
10
mA
mA
BUS
VBUS
Full-speed transmitting/receiving at 12Mbps,
Operating V Supply Current
L
I
VL
C = 15pF receiver outputs, V = 2.5V
L
L
Full-speed idle, V >2.7V, V <0.3V
500
500
10
D+
D-
Full-Speed Idle and SE0 Supply
Current
I
µA
µA
µA
µA
µA
µA
V
VBUS(IDLE)
SE0: V <0.3V, V <0.3
D-
D+
Static V Supply Current
L
I
Full-speed idle, SE0 or suspend mode
VL(STATIC)
SE0 = DAT= open;
SUS = OE = high
Suspend Supply Current
I
30
45
25
5
VBUS(SUSP)
Disable-Mode Supply Current
I
V = GND or open
L
VBUS(DIS)
V
= GND or open, OE = low,
BUS
Sharing-Mode V Supply Current
L
I
VL(SHARING)
SE0 = DAT = low or high, SUS = high
D+/D- Supply Current
I
V
= GND or open
20
3.6
D+/D-
BUS
V
Power-Supply Detection
BUS
V
V > 2.3V
L
0.8
TH_VBUS
Threshold
V
Power-Supply Detection
BUS
V
100
850
mV
mV
VBUSHYS
Hysteresis
V Power-Supply Threshold
V
L
TH_VL
2
_______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
ELECTRICAL CꢁARACTERISTICS (continued)
(V
= +4.0V to +5.5V, V = +2.3V to +3.6V, T = T
to T
, unless otherwise noted. Typical values are at V
= +5.0V, V
L
=
BUS
L
A
MIN
MAX
BUS
+2.5V, T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS AND OUTPUTS (DAT, SE0, OE, ENUM, SUS, BD)
V
0.7 x V
V
V
Input-High Voltage
Input-Low Voltage
Output-Voltage High
Output-Voltage Low
Input Leakage Current
Input Capacitance
IH
L
V
0.3 x V
IL
L
V
I
= 2mA
SOURCE
V - 0.4
L
V
OH
V
I = 2mA
SINK
0.4
+1
V
OL
I
-1
µA
pF
LKG
Measured from input to GND
|V - V
10
ANALOG INPUTS AND OUTPUTS (Dꢂ/D-)
V
|
D-
200
0.8
2.0
mV
V
Differential Input Sensitivity
ID
D+
Differential Common-Mode
Voltage Range
V
Includes V range
2.5
0.8
CM
ID
Single-Ended Input Voltage High
Single-Ended Input Voltage Low
V
V
V
IHSE
V
V
V
ILSE
Receiver Single-Ended
Hysteresis
200
mV
HYS
Output-Voltage Low
R = 1.5kΩ from D+ or D- to 3.6V
0.3
3.6
+1
V
V
OLD
OHD
L
Output-Voltage High
V
R = 15kΩ from D+ or D- to GND
2.8
-1
L
Off-State Leakage Current
Transceiver Capacitance
Tri-state driver
µA
pF
C
Measured from D+ or D- to GND
MAX13342E
20
IND
4
14
43
Driver Output Impedance
Internal Pullup Resistor
Input Impedance
R
Ω
OUT
MAX13345E
28
R
PU
1.425
1.500
1.575
kΩ
MΩ
Drivers off, tri-state driver, ENUM = 0,
V
Z
1
IN
, V = 0 OR +3.6V
D+ D-
LINEAR REGULATOR
External Capacitor
C
Compensation of linear regulator
1
µF
OUT
ESD PROTECTION (Dꢂ, D-)
Human Body Model
15
8
kV
kV
IEC 61000-4-2 Air-Gap
Discharge
IEC 61000-4-2 Contact
Discharge
8
kV
_______________________________________________________________________________________
3
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
TIMING CꢁARACTERISTICS
(V
= +4V to +5.5V, V = +2.3V to +3.6V, ENUM = V , T = T
to T
, unless otherwise noted. Typical values are at V
=
BUS
BUS
L
L
A
MIN
MAX
+5V, V = +2.5V, T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TRANSMITTER ( C = 50pF)
L
10% to 90% of |V
-V
| with an external
OHD OLD
Rise Time
Fall Time
t
31.6Ω series resistor (MAX13342E),
Figures 3, 8
4
4
20
ns
ns
FR
10% to 90% of |V
-V
| with an external
OHD OLD
t
31.6Ω series resistor (MAX13342E),
20
FF
Figures 3, 8
Rise-and-Fall Time Matching
(Note 1)
t
/t
Figures 3, 8
90
110
%
V
LR LF
V
,
CRS_L
Output Signal Crossover (Note 2)
Figure 4
1.3
2
V
CRS_F
Low-to-high transition,
Figures 4, 8
t
t
t
V > 2.3V
20
20
18
18
18
18
PLH_DRV
PHL_DRV
PZH_DRV
L
Driver
Propagation Delay
ns
ns
ns
High-to-low transition,
Figures 4, 8
V > 2.3V
L
Off-to-high transition,
Figures 5, 8
V > 2.3V
L
Driver-Enabled Delay Time
Driver Disable Delay
Off-to-low transition,
Figures 5, 8
t
V > 2.3V
L
PZL_DRV
PHZ_DRV
High-to-off transition,
Figure 5, 9
t
V > 2.3V
L
Low-to-off transition,
Figures 5, 9
t
V > 2.3V
L
PLZ_DRV
RECEIVER (C = 15pF)
L
Low-to-high transition,
Figures 6,10
t
t
V > 2.3V
20
20
18
18
20
20
22
22
PLH_RCV
L
Differential Receiver
Propagation Delay
ns
ns
ns
ns
High-to-low transition,
Figures 6,10
V > 2.3V
L
PHL_RCV
Low-to-high transition,
Figures 6,10
t
t
PLH_SE
PHL_SE
PHZ_SE
Single-Ended Receiver
Propagation Delay
High-to-low transition,
Figures 6,10
High-to-off transition,
Figure 7
t
V > 2.3V
L
Single-Ended Receiver Disable
Delay
Low-to-off transition,
Figure 7
t
V > 2.3V
L
PLZ_SE
PZH_SE
Off-to-high transition,
Figure 7
t
V > 2.3V
L
Single-Ended Receiver Enable
Delay
Off-to-low transition,
Figure 7
t
V > 2.3V
L
PZL_SE
Note 1: Parameters are 100% production tested at +25°C, unless otherwise noted. Limits over temperature are guaranteed by design.
_______________________________________________________________________________________
4
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Typical Operating Characteristics
(V
= +5V, V = +3.3V, T = +25°C, unless otherwise noted.)
L A
BUS
DIFFERENTIAL RECEIVER PROPAGATION
DELAY vs. V
DIFFERENTIAL RECEIVER PROPAGATION
SINGLE-ENDED RECEIVER PROPAGATION
DELAY vs. V
DELAY vs. V
L
BUS
L
20
18
16
14
12
10
8
20
18
16
14
12
10
8
30
28
26
24
22
20
18
16
14
12
10
OE = SUS = HIGH
T
= +85 C
A
T = +25 C
A
T
= +85 C
A
T
= +25 C
A
T
= -40 C
T
= +25 C
A
A
T
= +85 C
A
6
T
= -40 C
A
4
6
2
T
= -40 C
A
4
0
1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
4.0
-40
0
4.3
4.6
4.9
(V)
5.2
5.5
1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
V (V)
L
V
V (V)
L
BUS
SINGLE-ENDED RECEIVER PROPAGATION
TRANSMITTER SKEW
vs. TEMPERATURE
RECEIVER SKEW
vs. TEMPERATURE
DELAY vs. V
BUS
20
18
16
14
12
10
8
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
OE = SUS = HIGH
T
= +85 C
A
T
= +25 C
A
T
= -40 C
A
6
4
2
0
4.0
4.3
4.6
4.9
(V)
5.2
5.5
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE ( C)
TEMPERATURE ( C)
BUS
V SUPPLY CURRENT
V
SUPPLY CURRENT
V
vs. V
SUSPEND CURRENT
L
BUS
BUS
vs. D+/D- CAPACITANCE
vs. D+/D- CAPACITANCE
SUPPLY VOLTAGE
BUS
26
24
22
20
18
16
14
12
10
8
1.7
1.6
1.5
40
38
36
34
32
30
28
26
24
22
20
V = 2.5V
L
T
= +85 C
A
T
= +25 C
A
1.4
1.3
1.2
1.1
1.0
T
= -40 C
A
0
22 44 66 88 110 132 154 176 198 220
CAPACITANCE (pF)
22 44 66 88 110 132 154 176 198 220
CAPACITANCE (pF)
4.0
4.3
4.6
4.9
(V)
5.2
5.5
V
BUS
_______________________________________________________________________________________
5
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Typical Operating Characteristics (continued)
(V
= +5V, V = +3.3V, T = +25°C, unless otherwise noted.)
BUS
L
A
MAX13342E/MAX13345E
TRANSMITTING
MAX13342E/MAX13345E
RECEIVING
D-
2V/div
SEO
2V/div
D+
2V/div
DAT
2V/div
DAT
2V/div
D+
SEO
2V/div
(2V/div)
D-
20ns/div
100ns/div
MAX13342E/MAX13345E
BUS DETECTION
EYE DIAGRAM
4
3
VBUS
2V/div
2
1
0
BD
1V/div
-1
4 s
0
10 20 30 40 50 60 70 80
TIME (ns)
6
_______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Pin Description
PIN
NAME
FUNCTION
TDFN
UCSP
Regulated Output Voltage. V
provides a 3.3V output derived from V
. Bypass V
to GND
TRM
BUS
TRM
with a 1µF (min) low-ESR capacitor, such as ceramic or plastic film types. V
provides power
TRM
1
B1
V
to internal circuitry and the internal D+ pullup resistor. Do not use V
to power external
TRM
TRM
circuitry. These USB transceivers can also be powered by an externally regulated 3.3V supply
connected to both V and V
BUS
TRM.
System-Side Power-Supply Input. Connect V to the systems logic-level power supply. Bypass V
L
to GND with a 0.1µF (min) low-ESR ceramic capacitor.
L
2
3
A1
A2
V
L
Logic-Side Data Input/Output. SE0 operates as an input when OE is low and as an output when
OE is high. As an input, when SE0 is active high, D+ and D- are both driven low. As an output,
SE0 goes active high when both D+ and D- are low. (See Tables 3 and 4.)
SE0
Logic-Side Data Input/Output. DAT operates as an input for data on D+/D- when OE is low. DAT
operates as the output of the differential receiver on D+/D- when OE is high. (See Tables 3 and 4.)
4
5, 12
6
A3
—
DAT
N.C.
SUS
BD
No Connection. Leave N.C. unconnected. N.C. is not internally connected.
Suspend Input. Drive SUS low for normal transceiver operation. Drive SUS high for low-power
state.
B3
A4
7
USB Detector Output. A high on BD indicates that V
is present.
BUS
Output Enable. OE controls the USB transmitter outputs (D+/D-) and the interface signals (DAT,
SE0) when in USB mode. Drive OE high to operate D+/D- as inputs and to operate the logic
interface signals as outputs. Drive OE low to operate D+/D- as outputs and to operate the logic
interface signals as inputs.
8
B4
OE
9
C4
C3
GND
D-
Ground
Negative USB Differential Data Input/Output. D- is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D- operates as an input when OE is high
and as an output when OE is low.
10
Positive USB Differential Data Input/Output. D+ is wired to the USB connector directly
(MAX13345E) or through a series resistor (MAX13342E). D+ operates as an input when OE is
high and as an output when OE is low.
11
13
C2
B2
D+
Enumerate. Drive ENUM high to connect the internal 1.5kΩ resistor from D+ to V
low to disconnect the internal 1.5kΩ resistor.
. Drive ENUM
TRM
ENUM
USB-Side Power-Supply Input. Connect V
GND with a 1µF ceramic capacitor.
to the incoming USB power supply. Bypass V
to
BUS
BUS
14
EP
C1
V
BUS
—
EP
Exposed Paddle. Connect EP to GND.
_______________________________________________________________________________________
7
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
MAX13342E
MAX13345E
V
L
V
BUS
BD
LDO
REGULATOR
V
TRM
ENUM
SEO
DAT
MAX13345E
OE
D+
D-
SUS
LEVEL
TRANSLATOR
AND LOGIC
Figure 1. MAX13342E/MAX13345E Functional Diagram
The MAX13345E uses internal series resistors on D+/D-
to allow direct interface to the USB connector. A low-
power mode reduces current consumption to less than
45µA. An enumerate function controls connection of the
internal D+ pullup resistor.
Detailed Description
The MAX13342E/MAX13345E USB-compliant trans-
ceivers are designed to minimize the area and external
components required to interface low-voltage ASICs to
USB. The devices comply with the USB 2.0 specifica-
tion for full-speed (12Mbps) operation. The transceivers
include an internal 3.3V regulator, an internal 1.5k D+
pullup resistor, and built-in 15kV (HBM) ESD protec-
tion circuitry to protect D+, D-. Figure 1 is the
MAX13342E/MAX13345E functional diagram.
The MAX13342E/MAX13345E are equipped with DAT
and SE0 interface signals and support the 3-wire USB
tranceiver interface. Although the 3-wire interface is
commonly associated with USB On-the-Go trans-
ceivers, the MAX13342E/MAX13345E support USB
peripherals only. These transceivers provide a USB
The MAX13342E has controlled output impedance of
12 (max) on D+/D-, allowing the use of external
switches to multiplex two different USB devices onto a
single USB connector.
V
detection function that monitors the presence of
BUS
BUS
USB V
and signals the event.
8
_______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
45µA of supply current. The single-ended D+ and D-
receivers are still active when driving SUS high.
Interface
The MAX13342E/MAX13345E control signals are used
to control the USB D+/D- lines. V powers the logic-
L
Sharing Mode
side interface and sets the input and output thresholds
of these signals. The control signals for the MAX13342E
and MAX13345E are DAT, SE0, and OE.
Connect V to a system power supply and leave V
L
BUS
(or V
and V
) unconnected or connected to
BUS
TRM
GND. D+ and D- are tri-stated, allowing other circuitry
to share the USB D+ and D- line. V consumes less
L
Power-Supply Configuration
Normal Operating Mode
See Table 1 for various power-supply configurations.
than 5µA of supply current. When operating the trans-
ceivers in sharing mode, the SUS input is ignored, and
the interface signals (SE0, DAT) are high impedance.
V
V
supplies power to the USB transceivers. Connect
BUS
BUS
Disable Mode
to a system power supply and leave V
L
to a +4V to +5.5V supply. Connect V to a +2.3V
L
Connect V
to +3.6V supply. V
is typically connected directly to
BUS
BUS
unconnected or connect to ground. In disable mode,
D+ and D- are tri-stated, and V and/or V (or
the USB connector. An internal regulator provides 3.3V
to internal circuitry, and a regulated 3.3V output at
BUS
TRM
V
and V
) consume less than 25µA. When oper-
V
, in addition to powering the internal D+ pullup
BUS
TRM
TRM
ating the transceivers in disable mode, OE, SUS, and
inputs to the interface control signals are ignored.
(See Table 2.)
resistor. The MAX13342E and MAX13345E can be
powered by connecting both V
external regulator.
and V
to a 3.3V
TRM
BUS
Low-Power Mode
Operate the transceivers in low-power mode by assert-
ing SUS high. In low-power mode, the USB differential
receiver is turned off and V
consumes less than
BUS
Table 1. Power-Supply Configuration
V
(V)
V
(V)
V (V)
L
CONFIGURATION
Normal mode
NOTES
—
BUS
TRM
+4.0 to +5.5
+4.0 to +5.5
+3.0 to +3.6 output
+3.0 to +3.6 output
High Z
+2.3 to +3.6
GND or floating
+2.3 to +3.6
Disable mode
Sharing mode
Table 2
Table 2
GND or Floating
Table 2. Disable-Mode and Sharing-Mode Connection
INPUTS/OUTPUTS
DISABLE MODE
SꢁARING MODE
V
/ V
4V to 5.5V
Floating or connected to GND
2.3V to 3.6V input
High impedance
High impedance
High impedance
Low
BUS
TRM
V
Floating or connected to GND
High impedance
High impedance
High impedance
Low
L
D+ and D-
DAT, SE0
SUS
BD
_______________________________________________________________________________________
9
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
3-Wire DAT/SE0 Interface
SUS
SUS determines whether the MAX13342E/MAX13345E
The MAX13342E/MAX13345E use DAT and SE0 to
drive data or a single-ended zero onto the D+/D- lines.
When OE is low, SE0 is an input and functions as a
single-ended zero driver. When SE0 is high, both D+
and D- are driven low. When SE0 is driven low, the
D+/D- outputs are controlled by DAT.
operate in normal mode or in suspend mode. Drive
SUS low for normal operation. Drive SUS high to enable
suspend mode. In suspend mode, the single-ended
receivers (D+/D-) are active to detect a wake-up event.
Supply current decreases to less than 45µA in suspend
mode.
DAT is used to send data on D+/D- when both OE and
SE0 are low. When DAT is high, D+ is driven high and
D- is driven low. When DAT is low, D+ is driven low and
D- is driven high.
The MAX13342E/MAX13345E can transmit data on D+
and D- while in suspend mode. This function is used to
signal a remote wake-up event.
In receive mode (OE = high), DAT is the output of the
differential receiver connected to D+ and D-. SE0 only
goes active high when both D+ and D- are low.
ENUM
A 1.5k pullup resistor on D+ is used to indicate full-
speed (12Mbps) operation. Drive ENUM high to con-
nect the internal pullup resistor from D+ to V
. Drive
TRM
Control Signals
USB Detection
The MA13342E/MAX13345E USB detection function
ENUM low to disconnect the internal pullup resistor
from D+ to V
.
TRM
indicates that V
is present. The MAX13342E/
D+ and D-
BUS
MAX13345E push-pull bus detection output (BD) moni-
D+ and D- are bidirectional signals and are ESD pro-
tected to 15kV (HBM). OE controls the direction of D+
and D- when in USB normal mode (Tables 3 and 4).
tors V
, and asserts high when V
and V are pre-
BUS L
BUS
sent. BD asserts low if V
is less than +3.6V and
BUS
enters sharing mode.
V
TRM
voltage
OE
L
An internal linear regulator generates the V
TRM
OE controls the direction of communication when V
(+3.3V typ). V
derives power from V
(see the
BUS
powers the
TRM
TRM
and V
are both present. When OE is low, DAT and
Power-Supply Configuration section). V
BUS
SE0 operate as logic inputs and D+/D - are outputs.
When OE is high, DAT and SE0 operate as logic out-
puts and D+/D- are inputs.
internal USB circuitry and provides the pullup voltage
for the internal 1.5k resistor. Bypass V to GND
TRM
with a 1µF ceramic capacitor as close to the device as
possible. Do not use V
circuitry.
to provide power to external
TRM
10 ______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Table 3. Transmit Truth Table
Table 4. Receive Truth Table
(OE = 0, SUS = 0)
(OE = 1, SUS = 0)
INPUTS
OUTPUTS
INPUTS
OUTPUTS
DAT
SE0
0
Dꢂ
0
D-
1
Dꢂ
0
D-
0
DAT
*DAT
**0
SE0
1
0
0
1
1
1
0
0
0
1
0
0
1
0
1
0
**1
0
1
0
0
1
1
X
0
*Last state
**D+/D- differential receiver output
X = Undefined
Applications Information
USB Data Transfer
Transmitting Data
External Capacitors
Use three external capacitors for proper operation.
Bypass V to GND with a 0.1µF ceramic capacitor.
The MAX13342E/MAX13345E transmit USB data to the
USB differentially on D+ and D- when OE is low. The
D+ and D- outputs are determined by SE0 and DAT
(see Table 3).
L
Bypass V
to GND with a 1µF ceramic capacitor.
to GND with a 1µF (min) ceramic or plas-
BUS
TRM
Bypass V
tic capacitor. Place all capacitors as close to the
device as possible.
Receiving Data
Drive OE high and SUS low to receive data on D+/D-.
Differential data received on D+ and D- appear at DAT.
SE0 goes high only when both D+ and D- are low
(Table 4).
UCSP Application Information
For the latest application details on UCSP construction,
dimensions, tape carrier information, printed circuit
board (PCB) techniques, bump-pad layout, and recom-
mended reflow temperature profile, as well as the latest
information on reliability testing results, refer to
Application Note 1891: UCSP—A Wafer-Level Chip-
Scale Package available on Maxim’s website at
www.maxim-ic.com/ucsp.
External Resistors
(MAX13342E)
The MAX13342E provides low internal resistance on
D+/D-. Two external series resistors for impedance
matching are required for USB. Place the resistors in
between the MAX13342E and the USB connector (see
Figure 2).
______________________________________________________________________________________ 11
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
a 100pF capacitor charged to the ESD voltage of inter-
ESD Protection
est, which is then discharged into the test device
The MAX13342E/MAX13345E feature 15kV (HBM) ESD
through a 1.5k resistor.
protection on D+ and D-. The ESD structures withstand
high ESD in all states: normal operation, suspend, and
powered down. For the 15kV ESD structures to work
correctly, a 1µF or greater capacitor must be connected
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment; it does not specifi-
cally refer to integrated circuits. The MAX13342E/
MAX13345E help the user design equipment that meets
level 4 of IEC 61000-4-2, without the need for additional
ESD-protection components. The major difference
between tests done using the Human Body Model and
IEC 61000-4-2 is a higher peak current in IEC 61000-4-
2 because series resistance is lower in the IEC 61000-
4-2 model. Hence, the ESD withstand voltage
measured to IEC 61000-4-2 is generally lower than that
measured using the Human Body Model. Figure 13
shows the IEC 61000-4-2 model. The Air-Gap
Discharge Method involves approaching the device
with a charged probe. The Contact Discharge Method
connects the probe to the device before the probe
is energized.
from V
to GND. V
and D+/D- are characterized
TRM
BUS
for protection to the following limits:
•
•
15kV using the Human Body Model
8kV using the IEC 61000-4-2 Contact Discharge
Method
•
8kV using the IEC 61000-4-2 Air-Gap Method
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 11 shows the Human Body Model, and Figure
12 shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
SYSTEM
VOLTAGE
SUPPLY
USB CONNECTOR
USB
V
V
L
BUS
POWER
1.0 F
0.1 F
MAX13342E
BD
V
TRM
SYSTEM
INTERFACE
DAT
SEO
OE
1.0 F
31.6
D+
D-
D+
ENUM
SUS
31.6
D-
GND
GND
Figure 2. Adding External Resistors to the USB Connector for the MAX13342E
12 ______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Timing Diagrams/Test Circuits
t
, t
FR LR
t
, t
FF LF
OE
V
OHD
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D+ PULLED TO
3.0V WITH 150
t
PZL_DRV
90%
90%
.
D+
t
PLZ_DRV
10%
10%
V
OLD
D+
DAT CONNECTED TO
V , SE0 CONNECTED
L
TO GND. D+ PULLED
TO GND WITH 150
t
PZH_DRV
.
Figure 3. Rise and Fall Times
t
PHZ_DRV
DAT CONNECTED TO
V , SE0 CONNECTED
L
TO GND. D- PULLED
TO V WITH 150
.
L
D-
D-
RISE/FALL TIMES < 4ns
DAT
SEO
t
t
PZL_DRV
PLZ_DRV
DAT CONNECTED TO
GND, SE0 CONNECTED
TO GND. D- PULLED
TO GND WITH 150
t
PZH_DRV
.
t
t
PLH_DRV
PHL_DRV
t
PHZ_DRV
D-
Figure 5. Enable and Disable Timing, Transmitter
V
, V
CRS_F CRS_L
INPUT RISE/FALL TIME < 4ns
D+
+3V
D+/D-
0V
Figure 4. Timing of DAT, SE0 to D+ and D-
V
L
t
t
,
PLH_RCV
PLH_SE
t
t
,
PHL_RCV
PHL_SE
DAT/SEO
Figure 6. D+/D- to DAT, SE0 Propagation Delays
______________________________________________________________________________________ 13
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
FOR THE MAX13342E
OE
TEST
POINT
D+ CONNECTED TO
GND, D- CONNECTED TO
+3.0V. DAT PULLED TO
L
31.6
220
D+/D-
DUT
V WITH 330
.
DAT
DAT
50pF
t
t
PZL_SE
PLZ_SE
D+ CONNECTED TO
+3.0V, D- CONNECTED TO
GND. DAT PULLED TO
GND WITH 330
t
PZH_SE
NOTES:
1) V = 0 FOR t
PHZ
FOR t
2) V = V
TRM
PLZ
.
t
PHZ_SE
D+ CONNECTED TO
+3.0V, D- CONNECTED
TO GND. SE0 PULLED
Figure 9. Load for Disable Time Measurements
TO V WITH 330
.
L
SE0
SE0
t
t
PZL_SE
PLZ_SE
TEST
POINT
D+ CONNECTED TO
GND, D- CONNECTED
TO GND. SE0 PULLED
TO GND WITH 330
t
PZH_SE
DAT/SEO
DUT
.
15pF
t
PHZ_SE
LOAD FOR:
Figure 7. Receiver Enable and Disable Timing
1) D+/D- TO DAT/SEO PROPAGATION DELAYS
2) DAT/SEO RISE/FALL TIMES
FOR THE MAX13342E
Figure 10. Load for Receiver Propagation Delay and Receiver
Rise/Fall Times
TEST
POINT
31.6
D+/D-
DUT
50pF
15k
LOAD FOR:
1) ENABLE TIME (D+/D-) MEASUREMENT
2) DAT/SEO TO D+/D- PROPAGATION DELAY
3) D+/D- RISE/FALL TIMES
Figure 8. Load for Transmitter Propagation Delay, Enable Time,
Transmitter Rise/Fall Times
14 ______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
R
R
D
1.5k
C
1M
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
100pF
36.8%
STORAGE
CAPACITOR
SOURCE
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 11. Human Body ESD Test Model
Figure 12. Human Body Model Current Waveform
R
R
D
330
C
50M TO 100M
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
150pF
STORAGE
CAPACITOR
SOURCE
Figure 13. IEC 61000-4-2 ESD Test Model
______________________________________________________________________________________ 15
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Typical Application Circuit
SYSTEM
VOLTAGE
SUPPLY
1 F
V
BUS
MULTIMEDIA
PROCESSOR
V
L
0.1 F
MAX13342E
MAX4717
BD
NC1
V
TRM
SYSTEM
INTERFACE
DAT
SEO
OE
COM1
1 F
31.6
NO1
NC2
USB
CONNECTOR
ENUM
SUS
D+
D-
COM2
31.6
GND
NO2
GPIO
IN1, IN2
Pin Configurations
TOP VIEW
(BUMP SIDE DOWN)
TOP VIEW
1
2
3
4
+
14 13 12 11 10
9
8
V
L
SEO
DAT
BD
A
B
C
MAX13342E
V
SUS
D-
OE
ENUM
TRM
MAX13342E
MAX13345E
MAX13345E
V
GND
D+
BUS
*EP
6
+
1
2
3
4
5
7
2.0mm x 1.5mm UCSP
3mm x 3mm TDFN
*CONNECT EP TO GND
Chip Information
PROCESS: BiCMOS
16 ______________________________________________________________________________________
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/pacꢀages.)
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
H
21-0137
2
PACKAGE VARIATIONS
COMMON DIMENSIONS
MIN. MAX.
SYMBOL
PKG. CODE
T633-1
N
6
D2
1.50–0.10 2.30–0.10 0.95 BSC
1.50–0.10 2.30–0.10
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.95 REF
1.95 REF
2.00 REF
2.00 REF
2.40 REF
2.40 REF
0.40–0.05
0.40–0.05
0.30–0.05
0.30–0.05
0.30–0.05
A
0.70
2.90
2.90
0.00
0.20
0.80
3.10
3.10
0.05
0.40
T633-2
6
D
E
0.95 BSC
T833-1
8
1.50–0.10 2.30–0.10 0.65 BSC
1.50–0.10 2.30–0.10 0.65 BSC
1.50–0.10 2.30–0.10 0.65 BSC
T833-2
8
A1
L
T833-3
8
T1033-1
T1033-2
T1433-1
T1433-2
10
10
14
14
1.50–0.10 2.30–0.10 0.50 BSC MO229 / WEED-3 0.25–0.05
k
0.25 MIN.
0.20 REF.
1.50–0.10 2.30–0.10
0.25–0.05
0.20–0.05
0.20–0.05
A2
0.50 BSC MO229 / WEED-3
1.70–0.10 2.30–0.10 0.40 BSC
1.70–0.10 2.30–0.10 0.40 BSC
- - - -
- - - -
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
H
21-0137
2
______________________________________________________________________________________ 17
3-Wire Interface Full-Speed USB Transceivers
With/Without Internal Series Resistors
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/pacꢀages.)
PACKAGE OUTLINE, 4x3 UCSP
1
21-0104
F
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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