MAX1379_技术文档

19-4126; Rev 1; 2/ꢀ9

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

General Description

Features

♦ Dual, Simultaneous-Sampling, 12-Bit Successive

The MAX1377/MAX1379/MAX1383 feature two simulta-

neous-sampling, low-power, 12-bit ADCs with serial

interface and internal voltage reference. Fast sampling

rate, low power dissipation, and excellent dynamic per-

formance make the MAX1377/MAX1379/MAX1383

ideal for industrial process control, motor control, and

RF applications.

Approximation Register (SAR) ADCs

♦ 2 x 2 Mux Inputs or Two Differential Inputs

♦ 1.25Msps Sampling Rate per ADC

♦ Internal or External Reference

♦ Excellent Dynamic Performance

70dB SINAD (MAX1377)

Conversion results are available through a SPI™-/

QSPI™-/MICROWIRE™-/DSP-compatible interface with

independent serial digital outputs for each channel. The

serial outputs allow twice as much data to be transferred

at the given clock rate. The conversion results for both

ADCs can also be output on a single digital output for

microcontrollers (µCs) and DSPs with only a single serial

input available.

71dB SINAD (MAX1379/MAX1383)

84dBc/SFDR

1MHz Full-Linear Bandwidth

♦ 2.7V to 3.6V Low-Power Operation (MAX1377)

50mW (Normal Operation)

6mW (Partial Power-Down)

3µW (Full Power-Down)

♦ 4.75V to 5.25V Low-Power Operation (MAX1379)

90mW (Normal Operation)

The MAX1377 operates from a 2.7V to 3.6V analog sup-

ply and the MAX1379/MAX1383 operate from a 4.75V

to 5.25V analog supply. A separate 1.8V to AVDD digi-

tal supply allows interfacing to low voltage logic without

the use of level translators.

10mW (Partial Power-Down)

5µW (Full Power-Down)

♦ 4.75V to 5.25V Low-Power Operation (MAX1383)

280mW (Normal Operation)

2.5µW (Full Power-Down)

Two power-down modes, partial and full, allow the

MAX1377/MAX1379 and MAX1383 (full power-down only)

to save power between conversions. Partial power-down

mode reduces the supply current to 2mA while leaving

the reference enabled for quick power-up. Full power-

down mode reduces the supply current to 1µA.

♦ 20MHz, SPI-Compatible, 3-Wire Serial Interface

User-Selectable Single (0.625Msps max) or Dual

Outputs (1.25Msps max)

♦ Input Range: 10V (MAX1383), 0ꢀV

or

REF

V

REF

/2 (MAX1377/MAX1379)

♦ Small 20-Pin TQFN Package

The MAX1377/MAX1379 inputs accept voltages

SPI/QSPI are trademarks of Motorola, Inc.

between zero and the reference voltage or

V

/2.

REF

MICROWIRE is a trademark of National Semiconductor Corp.

The MAX1383 offers an input voltage range of 1ꢀV,

which is ideal for industrial and motor-control applica-

tions. The input to each of the ADCs supports either a

true-differential input or two single-ended inputs.

Functional Diagram

V

AVDD

L

AIN1A

AIN1B

The MAX1377/MAX1379/MAX1383 are available in a

2ꢀ-pin TQFN package, and are specified for the automo-

tive (-4ꢀ°C to +125°C) temperature range.

MAX1377

MAX1379

MAX1383

12-BIT

SAR

ADC1

MUX

T/H

DOUT1

OUTPUT

BUFFER

Applications

Bill Validation

CS

REF

SERIAL

INTERFACE

AND TIMING

REFSEL

CNVST

SCLK

Motor Control

Communications

Data Acquisition

Portable Instruments

A = 1

INTERNAL

REFERENCE

RGND

U/B

S/D

CONTROL

LOGIC

Ordering Information

V

L

PART

TEMP RANGE

PIN-PACKAGE

2ꢀ TQFN-EP*

AIN2A

AIN2B

12-BIT

SAR

ADC2

T/H

MUX

DOUT2

OUTPUT

BUFFER

MAX1377ATP+

MAX1379ATP+

MAX1383ATP+

-4ꢀ°C to +125°C

AGND

SEL

DGND

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Pin Configuration appears at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

ABSOLUTE MAXIMUM RATINGS

AVDD to AGND ........................................................-ꢀ.3V to +6V

RGND to DGND.....................................................-ꢀ.3V to +ꢀ.3V

DGND to AGND.....................................................-ꢀ.3V to +ꢀ.3V

Maximum Current into Any Pin (except power-supply pins).....5ꢀmA

V to DGND..............................................................-ꢀ.3V to +6V

L

SCLK, CS, CNVST, U/B, S/D, SEL,

REFSEL to DGND.......................................-ꢀ.3V to (V + ꢀ.3V)

Continuous Power Dissipation (T = +7ꢀ°C)

L

A

DOUT_ to DGND...........................................-ꢀ.3V to (V + ꢀ.3V)

2ꢀ-Pin Thin QFN (derate 34.5mW/°C above +7ꢀ°C) ...2758.6mW

Operating Temperature Range .........................-4ꢀ°C to +125°C

Junction Temperature......................................................+15ꢀ°C

Storage Temperature Range.............................-6ꢀ°C to +15ꢀ°C

Lead Temperature (soldering, 1ꢀs) .................................+3ꢀꢀ°C

L

AIN1A, AIN1B, AIN2A, AIN2B to AGND

MAX1377/MAX1379 .............................-ꢀ.3V to (AVDD + ꢀ.3V)

MAX1383..............................................................-12V to +12V

RGND to AGND.....................................................-ꢀ.3V to +ꢀ.3V

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—MAX1377

(V

= 2.7V to 3.6V, V = 1.8V to AVDD, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 2.ꢀ48V, REFSEL = V , S/D = DGND, C

=

AVDD

L

SCLK

REF

L

REF

1µF; T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

PARAMETER

DC ACCURACY

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Resolution

12

-1.25

-1

Bits

LSB

Relative Accuracy

Differential Nonlinearity

Offset Error

INL

(Note 1)

+1.25

DNL

+1.5

8

Offset-Error Matching

Gain Error

12

6

(Note 2)

79/MAX183

Gain-Error Matching

Gain Temperature Coefficient

6

2

8ꢀ

ppm/^oC

AIN1A to AIN1B, AIN2A to AIN2B

AIN1A to AIN2A, AIN1B to AIN2B

DC Input Isolation

dB

DYNAMIC SPECIFICATIONS (f = 500kHz, 2V

sine wave, 1.25Msps, 20MHz f

)

SCLK

IN

P-P

Unipolar

66

67

66

67

69.5

7ꢀ

-84

-86

-78

5

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

SINAD

SNR

dB

Bipolar

Unipolar

Bipolar

Total Harmonic Distortion

Spurious-Free Dynamic Range

Intermodulation Distortion

Full-Power Bandwidth

THD

SFDR

IMD

Up to the 5th harmonic

-74

-76

dB

f

= 1ꢀ3.5kHz, f

= 113.5kHz

IN2

dB

IN1

-3dB point

(S/N + D) > 68dB, 1V input

MHz

Full-Linear Bandwidth

1

CONVERSION RATE (Figure 4)

Minimum Conversion Time

t

16 clock cycles per conversion (Note 3)

Dual output mode, S/D = ꢀ

ꢀ.8ꢀꢀ

µs

CONV

1.25

Maximum Throughput Rate

Msps

Single output mode, S/D = 1

ꢀ.625

Minimum Throughput Rate for

Full Bandwidth Signal

(Note 4)

1ꢀ

ksps

2

_______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

ELECTRICAL CHARACTERISTICS—MAX1377 (continued)

(V

= 2.7V to 3.6V, V = 1.8V to AVDD, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 2.ꢀ48V, REFSEL = V , S/D = DGND, C

=

AVDD

L

SCLK

REF

L

REF

1µF; T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

PARAMETER

Track-and-Hold Acquisition Time

Aperture Delay

SYMBOL

CONDITIONS

MIN

TYP

125

2

MAX

UNITS

ns

t

ACQ

ns

Aperture-Delay Matching

Aperture Jitter

2

ns

(Note 5)

3ꢀ

ps

External Clock Frequency

f

2ꢀ

MHz

SCLK

ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)

Input Range

U/B = ꢀ, V

- RGND

ꢀ

V

AIN_A

REF

Differential Input Range

Absolute Voltage Range

DC Leakage Current

Input Impedance

U/B = 1, V

- V

-V

/2

+V

/2

REF

AIN_A

AIN_B

REF

ꢀ

AVDD

1

V

µA

kΩ

pF

34

16

Input Capacitance

At each analog input

EXTERNAL REFERENCE (REFSEL = 1)

AVDD

+ ꢀ.ꢀ5

Absolute Input Voltage Range

V

1.ꢀ

V

REF

Input Capacitance

DC Leakage Current

Input Current

5ꢀ

pF

µA

1

Time averaged at maximum throughput rate

8ꢀꢀ

INTERNAL REFERENCE (REFSEL = 0)

Reference Voltage Level

2.ꢀ28

2.ꢀ48

1

2.ꢀ68

V

I

= ꢀ to 1mA

SOURCE

Load Regulation

mV/mA

= ꢀ to 5ꢀµA

1

SINK

Voltage Temperature Coefficient

5ꢀ.ꢀ

ppm/^oC

DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)

ꢀ.3 x

Input-Voltage Low

Input-Voltage High

V

IL

V

L

ꢀ.7 x

V

IH

V

L

Input Leakage Current

I

1ꢀ

µA

IL

DIGITAL OUTPUT (DOUT1, DOUT2)

Output Load Capacitance

Output-Voltage Low

C

For stated timing performance

3ꢀ

pF

V

DOUT

V

I

= 5mA

ꢀ.4

OL

OH

OL

SINK

V

L

Output-Voltage High

V

I

= 1mA, V ≥ 2.7V

V

SOURCE

L

- ꢀ.5V

Output Leakage Current

POWER REQUIREMENTS

Analog Supply Voltage

Digital Supply Voltage

I

High-impedance mode (Figure 9)

ꢀ.2

3.ꢀ

µA

AVDD

2.7

1.8

3.6

V

AVDD

L

_______________________________________________________________________________________

3

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

ELECTRICAL CHARACTERISTICS—MAX1377 (continued)

(V

= 2.7V to 3.6V, V = 1.8V to AVDD, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 2.ꢀ48V, REFSEL = V , S/D = DGND, C

=

AVDD

L

SCLK

REF

L

REF

1µF; T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

Normal operation

MIN

TYP

13

2

MAX

UNITS

15

mA

Analog Supply Current

I

Partial power-down mode (Note 5)

Full power-down mode (Note 5)

AVDD

1

5

1ꢀ

1.5

3

µA

mA

mV

Average Static Supply Current

Digital Supply Current

8

I

f

= 2ꢀMHz, V = 3V, C = 3ꢀpF

1

VL

SCLK

L

Power-Supply Rejection

PSR

V

= 3V 1ꢀ%, full-scale input

ꢀ.2

AVDD

ELECTRICAL CHARACTERISTICS—MAX1379

(V

= 4.75V to 5.25V, V = 3V, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 4.ꢀ96V, REFSEL = V , S/D = DGND, C

= 1µF; T

=

AVDD

L

SCLK

REF

L

REF

A

T

MIN

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution

12

-1.25

-1

Bits

LSB

Relative Accuracy

Differential Nonlinearity

Offset Error

INL

(Note 1)

+1.25

DNL

+1

8

Offset-Error Matching

Gain Error

9

(Note 2)

6

Gain-Error Matching

Gain Temperature Coefficient

9

79/MAX183

2

8ꢀ

ppm/^oC

AIN1A to AIN1B, AIN2A to AIN2B

AIN1A to AIN2A, AIN1B to AIN2B

DC Input Isolation

dB

DYNAMIC SPECIFICATIONS (f = 500kHz , 4V

sine wave, 1.25Msps, 20MHz f

)

SCLK

IN

P-P

Unipolar

69

7ꢀ

71

72

-84

-78

5

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

SINAD

SNR

dB

Bipolar

Unipolar

Bipolar

Total Harmonic Distortion

Spurious-Free Dynamic Range

Intermodulation Distortion

Full-Power Bandwidth

THD

SFDR

IMD

Up to the 5th harmonic

-76

dB

f

= 1ꢀ3.5kHz, f

= 113.5kHz

IN2

dB

IN1

-3dB point

(S/N + D) > 68dB, 1V input

MHz

Full-Linear Bandwidth

1

CONVERSION RATE (Figure 6)

Minimum Conversion Time

t

16 clock cycles per conversion (Note 3)

Dual-output mode, S/D = ꢀ

ꢀ.8

µs

CONV

1.25

Maximum Throughput Rate

Msps

Single-output mode, S/D = 1

ꢀ.625

Minimum Throughput Rate for

Full Bandwidth Signal

(Note 4)

1ꢀ

ksps

4

_______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

ELECTRICAL CHARACTERISTICS—MAX1379 (continued)

(V

= 4.75V to 5.25V, V = 3V, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 4.ꢀ96V, REFSEL = V , S/D = DGND, C

= 1µF; T =

REF A

AVDD

L

SCLK

REF

L

T

MIN

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

125

2

MAX

UNITS

ns

Track-and-Hold Acquisition Time

Aperture Delay

t

ACQ

ns

Aperture-Delay Matching

Aperture Jitter

2

ns

(Note 5)

3ꢀ

ps

External Clock Frequency

f

2ꢀ

MHz

SCLK

ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)

Input Range

U/B = ꢀ, V

- RGND

ꢀ

V

REF

AIN_A

V

Differential Input Range

Absolute Voltage Range

DC Leakage Current

Input Impedance

U/B = 1, V

- V

-V

/2

+V

/2

AIN_A

AIN_B

REF

ꢀ

AVDD

1

V

µA

kΩ

pF

34

16

Input Capcitance

At each analog input

EXTERNAL REFERENCE (REFSEL = 1)

AVDD

+ ꢀ.ꢀ5

Absolute Input Voltage Range

V

1.ꢀ

V

REF

Input Capacitance

DC Leakage Current

Input Current

5ꢀ

pF

µA

1

Time averaged at maximum throughput rate

8ꢀꢀ

INTERNAL REFERENCE (REFSEL = 0)

Reference Voltage Level

4.ꢀ86

4.ꢀ96

1

4.1ꢀ6

V

I

= ꢀ to 1mA

SOURCE

Load Regulation

mV/mA

= ꢀ to 5ꢀµA

1

SINK

Voltage Temperature Coefficient

5ꢀ.ꢀ

ppm/^oC

DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)

ꢀ.3 x

Input-Voltage Low

Input-Voltage High

V

IL

V

L

ꢀ.7 x

V

IH

V

L

Input Leakage Current

I

1ꢀ

µA

IL

DIGITAL OUTPUT (DOUT1, DOUT2)

Output Load Capacitance

Output-Voltage Low

C

For stated timing performance

3ꢀ

pF

V

DOUT

V

I

= 5mA

ꢀ.4

OL

OH

OL

SINK

V -

L

ꢀ.5V

Output-Voltage High

V

I

= 1mA, V ≥ 2.7V

V

SOURCE

L

Output Leakage Current

POWER REQUIREMENTS

Analog Supply Voltage

Digital Supply Voltage

I

High-impedance mode (Figure 9)

ꢀ.2

5.ꢀ

µA

AVDD

4.25

1.8

5.25

V

AVDD

L

_______________________________________________________________________________________

5

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

ELECTRICAL CHARACTERISTICS—MAX1379 (continued)

(V

= 4.75V to 5.25V, V = 3V, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 4.ꢀ96V, REFSEL = V , S/D = DGND, C

= 1µF; T =

REF A

AVDD

L

SCLK

REF

L

T

MIN

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

PARAMETER

SYMBOL

CONDITIONS

Normal operation

MIN

TYP

16

2

MAX

UNITS

18

mA

Analog Supply Current

I

Partial power-down mode (Note 5)

Full power-down mode (Note 5)

AVDD

5

1ꢀ

3

µA

Average Static Supply Current

Digital Supply Current

9

mA

f

= 2ꢀMHz, V = 5V, C = 3ꢀpF

2

SCLK

L

I

mA

mV

VL

= 2ꢀMHz, V = 3V, C = 3ꢀpF

1

L

Power-Supply Rejection

PSR

V

= 5V 1ꢀ%, full-scale input

ꢀ.2

3

AVDD

ELECTRICAL CHARACTERISTICS—MAX1383

(V

= 4.75V to 5.25V, V = 1.8V to AVDD, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 2.5ꢀV, REFSEL = V , S/D = DGND, C

=

AVDD

L

SCLK

REF

L

REF

1µF; T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

DC ACCURACY

Resolution

12

-1.5

-1

Bits

LSB

Relative Accuracy

Differential Nonlinearity

INL

(Note 1)

+1.5

12

16

1ꢀ

8

DNL

Unipolar

Bipolar

Offset Error

LSB

79/MAX183

Offset-Error Matching

Gain Error

LSB

(Note 2)

Gain-Error Matching

Gain Temperature Coefficient

6

2

74

8ꢀ

ppm/^oC

AIN1A to AIN1B, AIN2A to AIN2B

AIN1A to AIN2A, AIN1B to AIN2B

DC Input Isolation

dB

DYNAMIC SPECIFICATIONS (f = 100kHz, 20V

sine wave, 1.25Msps, 20MHz f

)

SCLK

IN

P-P

Unipolar

67

69

67

69

71

72

71

72

-84

-86

-78

1ꢀ

1

Signal-to-Noise Plus Distortion

Signal-to-Noise Ratio

SINAD

SNR

dB

Bipolar

Unipolar

Bipolar

Total Harmonic Distortion

Spurious-Free Dynamic Range

Intermodulation Distortion

Full-Power Bandwidth

THD

SFDR

IMD

Up to the 5th harmonic

-72

dB

f

= 1ꢀ3.5kHz, f

= 113.5kHz

IN2

dB

IN1

-3dB point

(S/N + D) > 68dB, 1V input

MHz

Full-Linear Bandwidth

CONVERSION RATE (Figure 4)

Minimum Conversion Time

t

16 clock cycles per conversion (Note 3)

Dual output mode, S/D = ꢀ

ꢀ.8ꢀꢀ

µs

CONV

1.25

Maximum Throughput Rate

Msps

Single output mode, S/D = 1

ꢀ.625

6

_______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

ELECTRICAL CHARACTERISTICS—MAX1383 (continued)

(V

= 4.75V to 5.25V, V = 1.8V to AVDD, f

= 2ꢀMHz (5ꢀ% duty cycle), V

= 2.5ꢀV, REFSEL = V , S/D = DGND, C

=

AVDD

L

SCLK

REF

L

REF

1µF; T = T

to T

, unless otherwise noted. Typical values are at T = +25°C.)

MAX A

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Minimum Throughput Rate for

Full Bandwidth Signal

(Note 4)

(Note 5)

1ꢀ

ksps

Track-and-Hold Acquisition Time

Aperture Delay

t

125

2

ns

ACQ

Aperture-Delay Matching

Aperture Jitter

2

ns

3ꢀ

ps

External Clock Frequency

f

2ꢀ

MHz

SCLK

ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)

Input Range

U/B = ꢀ, V

- RGND

-1ꢀ

+1ꢀ

V

AIN_A

Differential Input Range

Absolute Voltage Range

Input Impedance

U/B = 1, V

- V

AIN_B

AIN_A

V

1ꢀ

kΩ

pF

Input Capacitance

At each analog input

EXTERNAL REFERENCE (REFSEL = 1)

Absolute Input Voltage Range

Input Capacitance

V

1.25

2.48

2.5

V

REF

5ꢀ

pF

µA

Input Current

Time averaged at maximum throughput rate

16ꢀꢀ

INTERNAL REFERENCE (REFSEL = 0)

Reference Voltage Level

2.5ꢀ

1

2.52

V

I

= ꢀ to 1mA

SOURCE

Load Regulation

mV/mA

ppm/^oC

= ꢀ to 5ꢀµA

1

SINK

Voltage Temperature Coefficient

5ꢀ.ꢀ

DIGITAL INPUTS (SCLK, CNVST, U/B, S/D, SEL, REFSEL)

Input-Voltage Low

V

ꢀ.3 x V

V

IL

IH

IL

L

Input-Voltage High

V

ꢀ.7 x V

L

Input Leakage Current

DIGITAL OUTPUTS (DOUT1, DOUT2)

I

1ꢀ

µA

Output Load Capacitance

Output-Voltage Low

C

For stated timing performance

3ꢀ

pF

V

DOUT

V

I

= 5mA

ꢀ.4

OL

OH

OL

SINK

Output-Voltage High

V

= 1mA, V ≥ 2.7V

V - ꢀ.5V

L

V

SOURCE

L

Output Leakage Current

POWER REQUIREMENTS

Analog Supply Voltage

Digital Supply Voltage

I

High-impedance mode (Figure 9)

ꢀ.2

5.ꢀ

µA

AVDD

4.75

1.8

5.25

AVDD

65

V

L

Normal operation

55

ꢀ.5

44

2

mA

µA

mA

mV

Analog Supply Current

I

AVDD

Full power-down mode (Note 5)

1ꢀ

Average Static Supply Current

Digital Supply Current

58

I

f

= 2ꢀMHz, V = 3V, C = 3ꢀpF

3.ꢀ

VL

SCLK

L

Power-Supply Rejection

PSR

V

= 5V 1ꢀ%, full-scale input

5

3ꢀ

AVDD

_______________________________________________________________________________________

7

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

TIMING CHARACTERISTICS (Figures 6, 10)

V

= 4.25V to 5.25V, V = 1.8V to AVDD, V

= 4.ꢀ96V, f

= 2ꢀMHz for MAX1379, 5ꢀ% duty cycle, C = 3ꢀpF, T = T

to

MIN

AVDD

L

REF

SCLK

L

A

T

MAX

, unless otherwise noted. Typical values are at T = +25°C.)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

5ꢀ

TYP

MAX

UNITS

ns

SCLK Clock Period

SCLK Duty Cycle

t

CP

t

/t

45

55

%

CH CL

SCLK Pulse-Width High

SCLK Pulse-Width Low

t

22.5

ns

CH

t

ns

CL

C = 3ꢀpF, V = 5V

14

17

24

L

SCLK Rise to DOUT_ Transition

t

ns

C = 3ꢀpF, V = 3V

DOUT

L

C = 3ꢀpF, V = 1.8V

L

DOUT_ Remains Valid After

SCLK

t

4

ns

DHOLD

CNVST Fall to SCLK Fall

CNVST Pulse Width

t

C = 3ꢀpF

L

1ꢀ

2ꢀ

ns

SETUP

t

CSW

Power-Up Time; Full Power-Down

SEL to CNVST Fall

t

External load on REF < 3µF

2

ms

PWR-UP

t

1ꢀꢀ

1ꢀ

12ꢀ

ns

SEL_SETUP

SEL Hold to CNVST Fall

CS Fall To CNVST Fall

ns

t

External load on REF < 3µF

No external load

2

ms

CST

Restart Time; Partial Power-Down

t

16

Cycles

RCV

Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset

error have been nulled.

Note 2: Offset nulled.

Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period. Clock has 5ꢀ% duty cycle.

Note 4: At sample rates below 1ꢀksps, the input full linear bandwidth is reduced to 5kHz.

Note 5: SCLK and CNVST not switching during measurement.

79/MAX183

Typical Operating Characteristics

(V

= 5V/3V, V = 3V, f

= 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1377 BIPOLAR FFT

0

f

= 1.25MHz

= 20MHz

= 100kHz

f

= 1.25MHz

= 20MHz

= 250kHz

f

= 1.25MHz

= 20MHz

SCLK

= 500kHz

SAMPLE

-20

SCLK

IN

SINAD = 60.052dB

SNR = 69.073dB

THD = -92.267dB

SFDR = 93.225dB

SINAD = 68.720dB

SNR = 68.769dB

THD = -88.244dB

SFDR = 91.237dB

SINAD = 68.542dB

SNR = 68.554dB

THD = -90.391dB

SFDR = 94.350dB

-40

-60

-80

-40

-60

-80

-40

-60

-80

V

= 2.048V

V

= 2.048V

V

= 2.048V

REF

-100

-120

-100

-120

-100

-120

0

100

200

300 400

500

600

0

100

200

300 400

500

600

0

100

200

300 400

500

600

ANALOG INPUT FREQUENCY (kHz)

8

_______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Typical Operating Characteristics (continued)

(V

= 5V/3V, V = 3V, f

= 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1377 UNIPOLAR FFT

0

f

= 1.25MHz

= 20MHz

= 100kHz

f

= 1.25MHz

= 20MHz

= 250kHz

f

= 1.25MHz

= 20MHz

SCLK

= 500kHz

SAMPLE

-20

SCLK

IN

SINAD = 69.324dB

SNR = 69.400dB

THD = -86.952dB

SFDR = 89.213dB

SINAD = 68.947dB

SNR = 69.054dB

THD = -85.101dB

SFDR = 86.718dB

SINAD = 68.645dB

SNR = 68.715dB

THD = -83.617dB

SFDR = 88.709dB

-40

-60

-80

-40

-60

-80

-40

-60

-80

V

= 2.048V

V

= 2.048V

V

= 2.048V

REF

-100

-120

-100

-120

-100

-120

0

100

200

300 400

500

600

0

100

200

300 400

500

600

0

100

200

300 400

500

600

ANALOG INPUT FREQUENCY (kHz)

MAX1377 BIPOLAR INL

vs. DIGITAL OUTPUT CODE

MAX1377 UNIPOLAR INL

vs. DIGITAL OUTPUT CODE

MAX1377 UNIPOLAR DNL

vs. DIGITAL OUTPUT CODE

1.0

0.8

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

500 1000 1500 2000 2500 3000 3500 4000 4500

DIGITAL OUTPUT CODE

0

500 1000 1500 2000 2500 3000 3500 4000 4500

DIGITAL OUTPUT CODE

0

500 1000 1500 2000 2500 3000 3500 4000 4500

DIGITAL OUTPUT CODE

MAX1379 UNIPOLAR INL

vs. DIGITAL OUTPUT CODE

MAX1379 BIPOLAR INL

vs. DIGITAL OUTPUT CODE

MAX1377 BIPOLAR DNL

vs. DIGITAL OUTPUT CODE

1.0

0.8

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

1024

2048

3072

4096

0

1024

2048

3072

4096

0

500 1000 1500 2000 2500 3000 3500 4000 4500

DIGITAL OUTPUT CODE

_______________________________________________________________________________________

9

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

Typical Operating Characteristics (continued)

(V

= 5V/3V, V = 3V, f

= 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1379 BIPOLAR DNL

vs. DIGITAL OUTPUT CODE

MAX1379 UNIPOLAR DNL

vs. DIGITAL OUTPUT CODE

MAX1379 OFFSET ERROR

vs. TEMPERATURE

1.0

0.8

1.0

0.8

0

-0.3

-0.6

-0.9

-1.2

-1.5

0.6

0.4

0.2

0

CHANNEL 1

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

CHANNEL 2

-15

0

1024

2048

3072

4096

0

1024

2048

3072

4096

-40

10

35

60

85

DIGITAL OUTPUT CODE

TEMPERATURE (°C)

MAX1379 GAIN ERROR

vs. TEMPERATURE

MAX1379 FFT PLOT

0

2.0

1.6

1.2

0.8

0.4

0

CHANNEL 2

f

= 1.8Msps

= 28.8MHz

= 100kHz

SAMPLE

f

= 1.8Msps

= 28.8MHz

= 250kHz

SAMPLE

-20

SCLK

IN

SINAD = 70.43dB

SNR = 70.72dB

THD = -82.33dB

SFDR = 82.78dB

SINAD = 70.05dB

SNR = 70.32dB

THD = -82.35dB

SFDR = 83.22dB

-40

-60

-80

-40

-60

-80

79/MAX183

CHANNEL 1

V

= 4.096V

REF

V

= 4.096V

REF

-100

-120

-100

-120

0

300

600

900

0

300

600

900

-40

-15

10

35

60

85

ANALOG INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

MAX1379 TOTAL HARMONIC DISTORTION

vs. SOURCE IMPEDENCE

MAX1379 FFT PLOT

-72

-74

-76

-78

-80

-82

-84

-86

0

f

= 1.8Msps

= 28.8MHz

= 300kHz

SAMPLE

-20

SCLK

f

= 500kHz

IN

f

= 1.8Msps

SAMPLE

SINAD = 70dB

SNR = 70.27dB

THD = -82.2dB

SFDR = 81.81dB

-40

-60

-80

= 28.8MHz

-40

-60

-80

SCLK

= 500kHz

IN

SINAD = 69.58dB

SNR = 69.75dB

THD = -83.79dB

SFDR = 84.69dB

V

= 4.096V

REF

V

= 4.096V

REF

f

= 100kHz

IN

-100

-120

-100

-120

0

200

400

600

800

10

100

SOURCE IMPEDANCE (Ω)

1000

0

300

600

900

ANALOG INPUT FREQUENCY (kHz)

10 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Typical Operating Characteristics (continued)

(V

= 5V/3V, V = 3V, f = 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1379 AVDD FULL POWER-DOWN

MAX1379 AVDD PARTIAL POWER-DOWN

CURRENT vs. TEMPERATURE

MAX1379 INTERMODULATION PLOT

CURRENT vs. TEMPERATURE

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

f

= 1.8Msps

= 28.8MHz

= 250kHz

= 300kHz

SAMPLE

-20

SCLK

IN1

-40

-60

-80

IMD = -81.53dB

= 4.096V

V

REF

-100

-120

0

300

600

900

-40 -25 -10

5

20 35 50 65 80

-40 -25 -10

5

20 35 50 65 80

ANALOG INPUT FREQUENCY (kHz)

TEMPERATURE (°C)

MAX1379 AVDD SUPPLY CURRENT

vs. TEMPERATURE

MAX1379 AVDD SUPPLY CURRENT

vs. CONVERSION RATE

20

18

16

14

12

10

8

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

6

4

2

0

-40 -25 -10

5

20 35 50 65 80

0

400

800

1200

1600

2000

TEMPERATURE (°C)

CONVERSION RATE (kHz)

MAX1379 INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

MAX1379 FULL-SCALE AMPLITUDE

vs. FREQUENCY

3850

3800

3750

3700

3650

3600

3550

4.10

4.09

4.08

4.07

4.06

4.05

4.04

4.03

4.02

4.01

T

= +25°C

A

T

= -40°C

= +85°C

A

T

A

1

10

4.20

4.45

4.70

AVDD (V)

4.95

5.20

FREQUENCY (MHz)

______________________________________________________________________________________ 11

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

Typical Operating Characteristics (continued)

(V

= 5V/3V, V = 3V, f = 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1383 BIPOLAR INL

vs. DIGITAL OUTPUT CODE

MAX1383 BIPOLAR DNL

vs. DIGITAL OUTPUT CODE

MAX1383 UNIPOLAR INL

vs. DIGITAL OUTPUT CODE

1.0

0.8

1.0

0.8

1.0

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

1024

2048

3072

4096

625

0

1024

2048

3072

4096

0

1024

2048

3072

4096

DIGITAL OUTPUT CODE

MAX1383 UNIPOLAR DNL

vs. DIGITAL OUTPUT CODE

MAX1383 OFFSET ERROR

vs. TEMPERATURE

MAX1383 GAIN ERROR

vs. TEMPERATURE

1.0

0.8

10

8

4

2

CHANNEL 1

0.6

0.4

CHANNEL 2

0.2

6

79/MAX183

0

CHANNEL 2

-0.2

-0.4

-0.6

-0.8

-1.0

4

CHANNEL 1

-2

-4

2

0

1024

2048

3072

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

DIGITAL OUTPUT CODE

TEMPERATURE (°C)

MAX1383 TOTAL HARMONIC DISTORTION

vs. SOURCE IMPEDANCE

MAX1383 AVDD FULL POWER-DOWN

CURRENT vs. TEMPERATURE

MAX1383 FFT PLOT

0

-20

-87.0

-87.5

-88.0

-88.5

-89.0

-89.5

-90.0

2000

1800

1600

1400

1200

1000

800

f

= 1.25Msps

SAMPLE

= 20MHz

= 100kHz

SINAD = 70.07dB

SNR = 70.15dB

THD = -87.39dB

SFDR = 90.1dB

SCLK

IN

-40

-60

V

= 2.5V

REF

-80

600

400

-100

-120

f

= 100kHz

IN

200

= 1.25Msps

SAMPLE

0

125

250

375

500

0

100

200

300

400

500

-40 -25 -10

5

20 35 50 65 80 95 110 125

ANALOG INPUT FREQUENCY (kHz)

SOURCE IMPEDANCE (Ω)

TEMPERATURE (°C)

12 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Typical Operating Characteristics (continued)

(V

= 5V/3V, V = 3V, f

= 2ꢀMHz, T = +25°C, unless otherwise noted.)

SCLK A

AVDD

L

MAX1383 AVDD SUPPLY CURRENT

vs. TEMPERATURE

MAX1383 AVDD SUPPLY CURRENT

vs. CONVERSION RATE

MAX1383 FULL-SCALE AMPLITUDE

vs. FREQUENCY

56

54

52

50

48

46

44

42

56

55

54

53

52

51

50

0

-1

-2

-3

CONVERTING AT 1.25Msps

STATIC

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

500

1000

1500

2000

1

10

TEMPERATURE (°C)

CONVERSION RATE (kHz)

FREQUENCY (MHz)

MAX1383 AVDD SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1383 AVDD SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1383 INTERNAL REFERENCE VOLTAGE

vs. ANALOG SUPPLY VOLTAGE

56

54

52

50

48

46

44

42

40

54

52

50

48

46

44

42

40

2.497

2.496

2.495

2.494

2.493

2.492

2.491

2.490

EXTERNAL REFERENCE

INTERNAL REFERENCE

TEMPERATURE AT T = +25°C

A

TEMPERATURE AT T = -40°C

A

CONVERTING AT 1.25Msps

STATIC

CONVERTING AT 1.25Msps

STATIC

TEMPERATURE AT T = +85°C

A

TEMPERATURE AT T = +125°C

A

4.25

4.45

4.65

4.85

(V)

5.05

5.25

4.25

4.45

4.65

4.85

(V)

5.05

5.25

4.75

4.85

4.95

5.05

(V)

5.15

5.25

V

CC

MAX1383 INTERNAL REFERENCE VOLTAGE

vs. TEMPERATURE

MAX1383 EXTERNAL REFERENCE SUPPLY

CURRENT vs. TEMPERATURE

MAX1383 DIGITAL SUPPLY CURRENT

vs. TEMPERATURE

2.499

2.497

2.495

2.493

2.491

2.489

1.48

1.47

1.46

1.45

1.44

1.43

1.42

1.70

1.68

1.66

1.64

1.62

1.60

V

= 5V

AVDD

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

______________________________________________________________________________________ 13

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

Pin Description

NAME

FUNCTION

Reference-Select Input. Drive REFSEL high to select external reference mode and power down the

internal reference. Drive REFSEL low to select internal reference mode.

1

REFSEL

Internal Reference Output/External Reference Input. For internal reference mode, bypass REF to

RGND with a ≥ 1µF capacitor. For external reference mode, apply a reference voltage at REF.

2

3

REF

Reference Ground/Common Negative Input. In bipolar mode, RGND is the reference ground. In

unipolar mode, RGND is the common negative input for all four analog inputs (see Figure 3).

RGND

4, 18

5

AGND

AVDD

Analog Ground

Analog-Supply Input. Bypass AVDD with a 1ꢀµF || 1ꢀnF capacitor to ground.

Primary/Positive Analog Input Channel 2. AIN2A is the primary channel 2 input (AIN2A) if using

single-ended inputs (U/B is low) and the positive channel 2 input (AIN2+) if using differential inputs

(U/B is high) (see Figure 3).

6

AIN2A

AIN2B

Secondary/Negative Analog Input Channel 2. AIN2B is the secondary channel 2 input (AIN2B) if

using single-ended inputs (U/B is low) and the negative channel 2 input (AIN2-) if using differential

inputs (U/B is high) (see Figure 3).

7

8

Unipolar/Bipolar Input. Drive U/B low to select unipolar mode. Drive U/B high to select bipolar

mode. In bipolar mode, the analog inputs are differential.

U/B

9

DGND

Digital Supply Ground

1ꢀ

11

12

13

V

Digital Supply Input. Bypass V with a 1ꢀµF || 1ꢀnF capacitor to ground.

L

DOUT2

DOUT1

SCLK

Serial-Data Output 2. Data is clocked out on the rising edge of SCLK.

Serial-Data Output 1. Data is clocked out on the rising edge of SCLK.

Serial-Clock Input. Clocks data out of the serial interface. SCLK also sets the conversion time.

79/MAX183

Conversion-Start Input. Forcing CNVST high prepares the device for a conversion. Conversion

begins on the falling edge of CNVST.

14

15

CNVST

Active-Low, Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT1

and DOUT2 are high impedance, the serial interface resets, and the device powers down.

CS

Single-Output/Dual-Output Selection Input. Drive S/D high to route ADC2 data through DOUT1 after

ADC1 data. Drive S/D low for dual outputs with ADC1 data going to DOUT1 and ADC2 data going

to DOUT2. See the Single-/Dual-Output Modes (S/D) section.

16

17

19

S/D

SEL

Analog-Input Selection Input. If U/B is low (unipolar mode), drive SEL low to select the primary

inputs, AIN1A and AIN2A. Drive SEL high to select the secondary inputs, AIN1B and AIN2B. In

bipolar mode, SEL is ignored.

Secondary/Negative Analog Input Channel 1. AIN1B is the secondary channel 1 input (AIN1B) if

using single-ended inputs (U/B is low) and the negative channel 1 input (AIN1-) if using differential

inputs (U/B is high) (see Figure 3).

AIN1B

Primary/Positive Analog Input Channel 1. AIN1A is the primary channel 1 input (AIN1A) if using

single-ended inputs (U/B is low) and the positive channel 1 input (AIN1+) if using differential inputs

(U/B is high) (see Figure 3).

2ꢀ

—

AIN1A

EP

Exposed Pad. EP is internally connected to AGND.

14 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

For the MAX1383, t

has a typical constant value of

ACQ

Detailed Description

125ns. Also, it has a typical constant input impedance

The MAX1377/MAX1379/MAX1383 use an input track

and hold (T/H) and SAR circuitry to convert an analog

input signal to a digital 12-bit output. The dual serial

interface requires a minimum of three digital lines

(SCLK, CNVST, and DOUT) and provides easy interfac-

ing to microprocessors (µPs) and DSPs. Four digital

lines are required for dual-output mode.

of 11kΩ. Since the input voltage seen at the pin is a

function of a resistive voltage divider i.e., V x R /(R

IN

IN IN

+ R ) = V x 11kΩ/(11kΩ + R ), it is very important to

X

IN

X

select an R << 11kΩ to avoid large gain error.

X

MAX1377/MAX1379 Unipolar Mode

The MAX1377/MAX1379 support two simultaneously

sampled, single-ended conversions in unipolar mode.

Drive U/B low for unipolar mode. In unipolar mode,

switches A–D in Figure 3a close according to the posi-

tion of SEL. Drive SEL low to close switches A and D

and designate AIN1A and AIN2A as the active, single-

ended inputs referenced to RGND. Drive SEL high to

close switches B and D and select AIN1B and AIN2B

as the active, single-ended inputs referenced to RGND.

The output code in unipolar mode is straight binary.

See Figure 4a for the unipolar transfer function.

Input T/H Circuit

Upon power-up, the input T/H circuit enters its tracking

mode immediately. Following a conversion, the T/H

enters the tracking mode on the 14th SCLK rising edge

of the previous conversion (Figure 6). The T/H enters the

hold mode on the falling edge of CNVST. The time

required for the T/H to acquire an input signal is deter-

mined by how quickly the input capacitance is charged.

If the input signal’s source impedance is high, the acqui-

sition time lengthens. For the MAX1377/MAX1379, the

acquisition time, t

, is the minimum time needed for

the signal to be acquired (see the Definitions section).

is calculated by the following equation:

ACQ

MAX1377/MAX1379 Bipolar Mode

Drive U/B high to configure the inputs for bipolar/differ-

ential mode. Switches A and C in Figure 3a are closed,

designating AIN1A (AIN2A) and AIN1B (AIN2B) as the

active, differential inputs. In bipolar mode, SEL is

ignored. The output code is in two’s complement.

Figure 5 shows the transfer function for bipolar mode.

t

ACQ

t

≥ 9 x (R + R ) x C (MAX1377/MAX1379)

S IN IN

ACQ

where R = 45ꢀΩ, C = 16pF, and R is the source

IN

S

impedance of the input signal.

Figure 1 shows the acquisition time as tested using the

circuit of Figure 2. The acquisition time is the time

between the rising edge of a 1V to 3V step input and

the falling edge of CONVST which produced a stable

sample. Rs represents the source impedance of the

function generator (5ꢀΩ) and Rx represents the vari-

able filter resistance.

MAX1383 Input Mode

A

1ꢀV input mode is available on the MAX1383. It is

accomplished by utilizing a resistive divider on the

input followed by a low distortion amplifier to drive the

track and hold circuit. Special high voltage ESD struc-

tures are also utilized on these channels. When using

Rs

Rx

ADC

1800

1600

1400

1200

1000

1V TO 3V

STEP

C

CONVST

C = 1nF

800

Figure 2. Test Circuit

600

400

200

0

C = 120pF

AIN1A

(AIN2A)

C

R

IN

A

TO ADC+

TO ADC-

AIN1B

(AIN2B)

B

C

D

0

50

100

150

200

R

IN

SOURCE IMPEDANCE, Rx (Ω)

RGND

Figure 1. MAX1377/MAX1379 Acquisition Time vs. Source

Impedance

Figure 3a. MAX1377/MAX1379 Equivalent Input Circuit

______________________________________________________________________________________ 15

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

the MAX1383, the signal bandwidth is limited to 1ꢀꢀkHz

by specification. Since 1ꢀV signals are divided down to

a 2.5V range, this version should only be used with sig-

nals greater than 5V. For those applications with signals

5V or less, use the MAX1377/MAX1379 for best SNR per-

formance. The configuration is shown on Figure 3b.

1ꢀV input swings. All inputs must not exceed the stat-

ed ranges for accurate conversions.

Internal Reference Mode

Drive REFSEL low to select internal reference mode. The

MAX1377 includes an on-chip 2.ꢀ48V reference; the

MAX1379 has a 4.ꢀ96V reference; and the MAX1383

includes a 2.5V internal reference. The reference output

at REF can be used as a reference voltage source for

other components. REF can source up to 2mA. Bypass

REF with a 1ꢀnF capacitor and a 4.7µF capacitor to

RGND. It is important to select a low ESR capacitor and

keep the trace resistance as low as possible.

Input Bandwidth

The ADC’s input-tracking circuitry has a 5MHz small-

signal bandwidth, allowing the ADC to digitize high-

speed transient events and measure periodic signals

with bandwidths exceeding the ADC’s sampling rate by

using undersampling techniques. To avoid high-fre-

quency signals being aliased into the frequency band

of interest, anti-alias filtering is recommended.

FULL-SCALE

TRANSITION

Analog Input Protection

Internal protection diodes that clamp the analog input

to AVDD and AGND allow the analog inputs to swing

from AGND - ꢀ.3V to AVDD + ꢀ.3V without damage to

the MAX1377 and MAX1379. The MAX1383 can handle

MAX1383

111...111

+FS = 4V

REF

111...110

111...101

ZS = 0

-FS = -4V

REF

8 x V

4096

REF

1 LSB =

REF (2.5V)

R2

000...011

000...010

000...001

000...000

R

IN

~ 11KΩ (typ)

R1

R4

INA

3pF

INPUT

T/H

79/MAX183

R3

V

- 1 LSB

REF

+FS

+FS - 3/2 LSB

-FS

INTERNAL

SIGNAL

INPUT VOLTAGE (LSB)

GROUND

Figure 4b. MAX1383 Single-Ended Input

Figure 3b. MAX1383 Equivalent Input Circuit

FULL-SCALE

TRANSITION

FULL-SCALE

TRANSITION

MAX1377/

MAX1379

011...111

011...100

111...111

111...110

111...101

V

REF

2

+FS =

V

FS =

REF

ZS = 0

-FS =

ZS = 0

-V

000...010

000...001

REF

2

REF

V

4096

REF

1 LSB =

V

4096

1 LSB =

000...000

111...111

MAX1383

ZS = 0

111...110

111...101

+FS = 4V

REF

-FS = -4V

REF

000...011

000...010

000...001

000...000

8 x V

REF

1 LSB =

100...001

100...000

4096

V

- 1 LSB

REF

+FS

FS

FS - 3/2 LSB

-FS

0

3

1

2

+FS - 3/2 LSB

DIFFERENTIAL INPUT VOLTAGE (LSB)

INPUT VOLTAGE (LSB)

Figure 4a. MAX1377/MAX1379 Unipolar Transfer Function (U/B

Figure 5. Bipolar Transfer Function (U/B = High)

= Low)

16 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

The internal reference is continuously powered-up dur-

ing both normal and partial power-down modes. In full

power-down mode, the internal reference is disabled.

Allow at least 2ms recovery time after a power-on reset

or exiting full power-down mode for the reference to

settle to its intended value.

Serial Interface

Initialization After Power-Up

Upon initial power-up, the MAX1377/MAX1379/ MAX1383

require a complete conversion cycle to initialize the inter-

nal calibration. Following this initialization, the ADC is

ready for normal operation. This initialization is only

required after a hardware power-on reset and is not

required after exiting partial or full power-down mode.

Input Voltage Range (MAX1383)

The input range on the MAX1383 has an 8x relationship

with the reference voltage. For example, when the refer-

ence voltage (internal or external) is 2.5V, the input

Starting a Conversion and Reading the Output

With SCLK idling high or low, a falling edge on CNVST

begins a conversion (see Figure 6). This causes the

analog input stage to transition from track to hold

mode. SCLK provides the timing for the conversion

process, and data is shifted out as each bit of the result

is determined. A rising edge in CNVST forces the

device into one of three modes. The mode is deter-

mined by the clock cycle in which the transition occurs

and whether the device is set for single or dual outputs.

Figures 7 and 8 show each mode that is activated with

a rising CNVST edge for single and dual outputs.

range is 1ꢀV (2ꢀV ).

P-P

External Reference Mode

Drive REFSEL high to select external reference mode.

Apply a reference voltage at REF. Bypass REF with

a 1ꢀnF capacitor and a 4.7µF capacitor to RGND. As

with the internal reference, it is important to select a low

ESR capacitor and keep the trace resistance as low

as possible.

CS

t

CSW

CNVST

t

SETUP

t

CH

13

1

14

SCLK

t

CL

ACQ

t

DOUT

t

CST

D11

D10

D7

D5

D3

D2

D0

D9

D6

D4

D1

D8

DOUT_

t

DHOLD

TRACKING

INTERNAL T/H STATE

HOLD MODE

Figure 6. Detailed Serial-Interface Timing Diagram

CS

CNVST

POWER-DOWN

CONTINUOUS MODE

DOUT1 HI-Z

DOUT1 GOES HI-Z

29

4

14

28

2

3

SCLK

1

Figure 7. Single-Output CNVST Transition Modes

______________________________________________________________________________________ 17

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

CS

CNVST

SCLK

POWER-DOWN

CONTINUOUS MODE DOUT_ HI-Z

16

17

15

4

14

1

2

3

DOUT_ HI-Z

Figure 8. Dual-Output CNVST Transition Modes

SINGLE CONVERSION

CNVST

1

8

16

9

SCLK

D2

D1

D5

D4

D7

D6

D3

D0

D11

D10

D9

D8

0

DOUT_

HIGH-Z

CONTINUOUS-CONVERSION

SELECTION WINDOW*

CONTINUOUS CONVERSION

CNVST

79/MAX183

1

8

14

16

9

SCLK

D2

D1

D5

D4

D7

D6

D3

D0

D11

D10

D9

D8

0

DOUT_

*CNVST MUST GO HIGH BETWEEN THE 14TH RISING AND 16TH FALLING EDGES OF SCLK.

TO MAINTAIN CONTINUOUS CONVERSIONS, DOUT_ REMAINS LOW BETWEEN

CONVERSION RESULTS IN CONTINUOUS-CONVERSION DUAL-OUTPUT MODE.

Figure 9. Dual-Output Mode, Single and Continuous Conversions

For continuous operation in single-output mode, pull

CNVST high after the 14th rising and before the 28th

rising edge of SCLK. In dual-output mode, if CNVST

returns high after the 14th rising and before the 16th

falling edge of SCLK, DOUT_ remains active so continu-

ous conversions can be sustained. If CNVST is low

during the 16th edge of SCLK (dual-conversion mode)

and the 28th falling edge of SCLK (single-output mode),

DOUT_ returns to its high-impedance state on the next

rising edge of CNVST or SCLK, enabling the serial inter-

face to be shared by multiple devices. See Figures 9

and 1ꢀ for single and continuous conversion timing

diagrams.

DOUT1 (and DOUT2, if S/D = low) transitions from high

impedance to being actively driven low once the ADC

enters hold mode. DOUT_ remains low for the first three

SCLK pulses and begins outputting the conversion result

after the 4th rising edge of SCLK, MSB first. DOUT_ tran-

sitions complete t

after each SCLK rising edge and

DOUT

the DOUT_ values remain valid for t

after the next

HOLD

rising edge of SCLK. A total of 16 SCLK pulses are

required to complete a normal conversion in dual-output

mode and 28 SCLK pulses in single-output mode.

DOUT_ goes low after the 16th rising edge of SCLK and

goes high-impedance when CNVST goes high.

18 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Power-Down Modes

Single-/Dual-Output Modes (S/D)

In dual-output mode, conversion results from the two

channels appear on separate outputs. DOUT1 outputs

the result from channel 1 and DOUT2 outputs the result

from channel 2. Drive S/D low to operate in dual-output

mode. For DSPs with two-buffer and two-input-stream

capability, use the dual-output mode to allow for easier

DSP software for dual streams. Two buffer locations can

be used so the streams do not need to be separated.

Partial Power-Down (PPD)

Reduce power consumption by placing the MAX1377/

MAX1379 in partial power-down mode. Partial power-

down mode is ideal for infrequent data sampling and

applications requiring fast wake-up times. Pull CNVST

high after the 3rd and before the 14th rising edge of

SCLK to place the device in partial power-down mode.

This reduces the analog supply current to 2mA. While

in partial power-down mode, the internal reference

remains enabled (if REFSEL = GND). Figure 11 shows

the timing sequence to enter partial power-down mode.

In single-output mode, the results from both channels

appear on DOUT1. The channel 2 conversion result fol-

lows the channel 1 conversion result (see Figure 1ꢀ).

The MSB (D11) of the channel 2 conversion result

appears on DOUT1 after the 16th rising edge of SCLK.

The LSB (Dꢀ) of the channel 2 conversion result

appears on DOUT1 after the 27th rising edge of SCLK

and is ready to be clocked in on the 28th rising edge of

SCLK. DOUT2 is high-impedance when S/D is high.

Full Power-Down Mode (FPD)

Full power-down mode is ideal for infrequent data sam-

pling and very low-supply current applications. To enter

full power-down mode, place the MAX1377/MAX1379/

MAX1383 first in partial power-down mode. Perform the

CNVST/SCLK sequence necessary to enter partial

power-down mode. Repeat the same sequence to enter

full power-down mode. In full power-down mode, the

internal reference is disabled to minimize power con-

sumption. Figure 12 shows the timing sequence to

enter full power-down mode.

If CNVST goes high after the 28th rising edge of SCLK,

DOUT1 goes high impedance until the next conversion

is initiated (single-conversion mode). If CNVST goes

high after the 14th rising edge and before the 28th ris-

ing edge of SCLK, DOUT1 is actively driven low until

the next conversion results are ready (continuous- con-

version mode).

Another way to enter the full power-down mode is to

drive CS high. If CS is high, the MAX1377/MAX1379/

MAX1383 act as if the full power-down sequence were

issued. To exit the CS-initiated power-down mode,

drive CS low. Allow 2ms for the reference to wake up

and settle before performing a conversion.

Note: In single-output mode, the conversion speed is

limited to ꢀ.625Msps by the maximum SCLK.

SINGLE CONVERSION

(SINGLE OUTPUT)

CNVST

8

SCLK

9

1

0

16

17

D10

24

28

D9

D8 D7 D6 D5

CHANNEL 2

D2

D0

D1

D9

D7

CHANNEL 1

CONVERSION RESULT

D5

D3 D2

D0 D11

0

D10

D8

D6

D4

D1

D4 D3

D11

DOUT1

HIGH-Z

CONVERSION RESULT

CONTINUOUS CONVERSION

(SINGLE OUTPUT)

CNVST

SCLK

1

8

9

14

16

17

D10

24

D4 D3

25

D2

27 28

D0

D9

D8 D7 D6 D5

CHANNEL 2

CONVERSION RESULT

D9

D7

CHANNEL 1

CONVERSION RESULT

D5

D3 D2 D0 D11

D1

0

D10

D8

D6

D4

D11

DOUT1

Figure 1ꢀ. Single-Output Mode, Single and Continuous Conversions

______________________________________________________________________________________ 19

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

PPD WINDOW

CNVST

SCLK

CNVST MUST GO HIGH AFTER THE 3RD

BUT BEFORE THE 14TH

SCLK RISING EDGE

3

9

1

14

DOUT_ GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH

1ST SCLK RISING EDGE

0

DOUT_

MODE

0

D11

D10

D9

D8

D7

NORMAL

PARTIAL POWER-DOWN

ENABLED

REF

Figure 11. Partial Power-Down Timing Sequence

EXECUTE PARTIAL POWER-DOWN SEQUENCE TWICE

DOUT_ ENTERS THREE-STATE ONCE CNVST GOES HIGH

CNVST

SCLK

1ST SCLK RISING EDGE

DOUT_

1ST SCLK RISING EDGE

D8 D7

0

D10

0

D11

0

D9

0

79/MAX183

NORMAL

FPD

PPD

MODE

REF

ENABLED

DISABLED

Figure 12. Full Power-Down Mode Timing Sequence

Exiting Partial and Full Power-Down Modes

Drive CNVST low and allow at least 14 SCLK cycles to

elapse before driving CNVST high to exit partial or full

power-down mode. When exiting partial power-down

mode, conversions can begin immediately without hav-

ing to wait for the reference to wake-up. When exiting

full power-down mode, allow at least 2ms recovery time

after exiting to ensure that the internal reference has

settled.

Applications Information

SPI and MICROWIRE

The MAX1377/MAX1379/MAX1383 are compatible with

all four modes programmed with the CPHA and CPOL

bits in the SPI or MICROWIRE control register.

Conversion begins with a CNVST falling edge. DOUT_

goes low, indicating a conversion is in progress. Two

consecutive 8-bit reads are required to get the full 12

bits from the ADC. DOUT_ transitions on the rising edge

In partial or full power-down mode, maintain idle SCLK

low or high to minimize power.

of SCLK. DOUT_ is guaranteed to be valid t

after

DOUT

the rising edge of SCLK and remains valid until t

after the next SCLK rising edge (see Figure 13).

DHOLD

20 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

For CPOL = ꢀ and CPHA = ꢀ or CPOL = 1 and CPHA =

1, the data is clocked into the µC on the rising edge of

SCLK. For CPOL = ꢀ and CPHA = 1 or CPOL = 1 and

CPHA = ꢀ, the data is clocked into the µC on the falling

edge of SCLK. The MAX1377/MAX1379/MAX1383 are

compatible with all CPOL/CPHA configurations since

the data is valid on the falling and rising edge of SCLK.

clock cycles from the µC to clock out the 12 bits of

data. The conversion result contains three zeros fol-

lowed by the 12 data bits, and a trailing zero with the

data in the MSB-first format.

Three-Phase Motor Controller

The MAX1377/MAX1379/MAX1383 are ideally suited for

motor-control systems (Figure 16). The devices’ simulta-

neously sampled inputs eliminate the need for complicat-

ed DSP algorithms that realign sequentially sampled

data into a simultaneous sample set. The 1ꢀV

(MAX1383) input allows for standard industrial inputs,

eliminating the need for voltage-scaling amplifiers.

QSPI

Unlike SPI, which requires two 8-bit reads to acquire

the 12 bits of data from the ADC, QSPI allows the mini-

mum number of clock cycles necessary to clock in the

data. The MAX1377/MAX1379/MAX1383 require 16

I/O

SCK

CNVST

SCLK

MISO1

DOUT1

t

MISO2

DOUT

DHOLD

DOUT2

MAX1377

MAX1379

MAX1383

3V TO 5V

DOUT_

SS

A) SPI

CNVST

CS

SCK

Figure 13. Data Valid and Hold Times

SCLK

MISO1

DOUT1

DOUT2

MAX1377

MAX1379

MAX1383

MISO2

3V TO 5V

SUPPLIES

ANALOG

SUPPLY

DIGITAL

SUPPLY

RETURN

SS

OPTIONAL

FERRITE

BEAD

B) QSPI

I/O

SK

SI1

CNVST

SCLK

DOUT1

DOUT2

MAX1377

MAX1379

MAX1383

SI2

AVDD

V

L

AGND

DGND

V

GND

DD

DIGITAL

CIRCUITRY

MAX1377

MAX1379

MAX1383

C) MICROWIRE

Figure 15. Common Serial-Interface Connections to the

MAX1377/MAX1379/MAX1383

Figure 14. Power-Supply Grounding and Bypassing

______________________________________________________________________________________ 21

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

MAX1383

AIN1A

12-BIT

ADC

T/H

MISO1

MISO2

AIN1B

DSP-BASED DIGITAL

PROCESSING ENGINE

AIN2A

AIN2B

12-BIT

ADC

IGBT CURRENT DRIVERS

CURRENT

SENSORS

I

PHASE2

I

PHASE1

THREE-PHASE ELECTRIC MOTOR

PHASE 2

79/MAX183

PHASE 1

PHASE 3

SIN/COS

POSITION

RESOLVER

I

= - I

- I

PHASE3

PHASE1 PHASE2

Figure 16. Three-Phase Motor Control

22 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Wireless Communication

V

AVDD

L

Use the MAX1377/MAX1379/MAX1383 in a variety of

wireless communication systems. These devices allow

precise, simultaneous sampling of the I and Q signals

of quadrature RF receiver systems. Figure 17 shows the

MAX1377 in a simplified quadrature system. The device

has a differential input option that allows either full dif-

ferential or psuedo-differential signals. The 2:1 input

mux allows measurement of RSSI and other system-

monitoring functions with this device.

V

L

MAX1377

I

12-BIT

ADC

QUADRATURE

DEMODULATOR

Q

12-BIT

ADC

DSP

PROCESSING

T/R

Layout, Grounding, and Bypassing

For best performance, use PCBs with ground planes.

Ensure that digital and analog signal lines are separat-

ed from each other. Do not run analog and digital

(especially clock) lines parallel to one another or digital

lines underneath the ADC package.

DAC

QUADRATURE

TRANSMITTER

Figure 17. Quadrature Wireless-Communication System

Establish a single-point analog ground (star ground point)

at AGND, separate from the digital ground, DGND.

Connect all other analog grounds and DGND to this star

ground point for further noise reduction. The ground return

to the power supply for this ground should be low imped-

ance and as short as possible for noise-free operation.

See Figure 14.

Aperture Delay

Aperture delay (t ) is the time defined between the

AD

falling edge of CNVST and the instant when an actual

sample is taken.

Signal-to-Noise Ratio

For a waveform perfectly reconstructed from digital

samples, signal-to-noise ratio (SNR) is the ratio of full-

scale analog input (RMS value) to the RMS quantization

error (residual error). The theoretical minimum analog-

to-digital noise is caused by quantization error, and

results directly from the ADC’s resolution (N bits):

High-frequency noise in the AVDD power supply affects

the ADC’s high-speed comparator. Bypass the supply

to the single-point analog ground with ꢀ.ꢀ1µF and 1ꢀµF

bypass capacitors. Minimize capacitor lead lengths for

best supply-noise rejection.

Definitions

SNR = (6.ꢀ2 x N + 1.76)dB

Integral Nonlinearity

Integral nonlinearity (INL) is the deviation of the values

on an actual transfer function from a straight line. This

straight line can be either a best-straight-line fit or a line

drawn between the end points of the transfer function,

once offset and gain errors have been nulled. The static

linearity parameters for the MAX1377/MAX1379/

MAX1383 are measured using the end-points method.

In reality, there are other noise sources besides quanti-

zation noise, including thermal noise, reference noise,

clock jitter, etc. Therefore, SNR is computed by taking

the ratio of the RMS signal to the RMS noise, which

includes all spectral components minus the fundamen-

tal, the first five harmonics, and the DC offset.

Signal-to-Noise Plus Distortion

Signal-to-noise plus distortion (SINAD) is the ratio of the

fundamental input frequency’s RMS amplitude to the

RMS equivalent of all other ADC output signals:

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between

an actual step width and the ideal value of 1 LSB. A

DNL error specification of 1 LSB or less guarantees no

missing codes and a monotonic transfer function.

SINAD(dB) = 2ꢀ x log(SignalRMS/NoiseRMS)

Effective Number of Bits

Effective number of bits (ENOB) indicates the global

accuracy of an ADC at a specific input frequency and

sampling rate. An ideal ADC’s error consists of quanti-

Aperture Jitter

Aperture jitter (t ) is the sample-to-sample variation in

AJ

the time between the samples.

______________________________________________________________________________________ 23

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

zation noise only. With an input range equal to the full-

scale range of the ADC, calculate the ENOB as follows:

Intermodulation Distortion

Any device with nonlinearities creates distortion prod-

ucts when two sine waves at two different frequencies

(f1 and f2) are input into the device. Intermodulation

distortion (IMD) is the total power of the IM2 to IM5

intermodulation products to the Nyquist frequency rela-

tive to the total input power of the two input tones, f1

and f2. The individual input tone levels are at

-6dBFS.

SINAD−1.76

⎛

⎞

ENOB=

⎜

⎝

⎟

⎠

6.ꢀ2

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the first five harmonics of the input signal to the

fundamental itself. This is expressed as:

Pin Configuration

⎛

⎞

⎟

2

V

+ V + V + V

3 4 5

2

⎜

THD = 2ꢀ×log

TOP VIEW

V

⎜

⎟

1

⎝

⎠

15

14

13

12

11

where V is the fundamental amplitude, and V through

5

harmonics.

1

2

V

are the amplitudes of the 2nd- through 5th-order

V

10

9

S/D 16

SEL 17

L

DGND

Spurious-Free Dynamic Range

MAX1377

MAX1379

MAX1383

Spurious-free dynamic range (SFDR) is the ratio of the

RMS amplitude of the fundamental (maximum signal

component) to the RMS value of the next largest distor-

tion component.

8

AGND 18

AIN1B 19

U/B

7

AIN2B

AIN2A

(EXPOSED PAD)*

+

20

6

AIN1A

Full-Power Bandwidth

Full-power bandwidth is the frequency at which the input

signal amplitude attenuates by 3dB for a full-scale input.

1

2

3

4

5

79/MAX183

Full-Linear Bandwidth

Full-linear bandwidth is the frequency at which the sig-

nal-to-noise plus distortion (SINAD) is equal to 56dB.

TQFN

*CONNECT PAD TO AGND

Selector Guide

INTERNAL

REFERENCE

VOLTAGE (V)

INPUT VOLTAGE

RANGE

SAMPLING RATE

(Msps)

PART

SUPPLY VOLTAGE (V)

MAX1377

MAX1379

MAX1383

2.7 to 3.6

4.75 to 5.25

2.ꢀ48

4.ꢀ96

2.5

ꢀ to V

V

/2

1.25

REF,

REF

REF,

1ꢀV

Package Information

Chip Information

For the latest package outline information and land patterns, go

PROCESS: BiCMOS

to www.maxim-ic.com/packages.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

2ꢀ TQFN-EP

T2ꢀ55-4

21-0140

24 ______________________________________________________________________________________

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling

ADCs with Serial Interface

79/MAX183

Revision History

REVISION

NUMBER

REVISION

DATE

PAGES

CHANGED

DESCRIPTION

ꢀ

1

7/ꢀ8

2/ꢀ9

Initial release of the MAX1377/MAX1379

Initial release of the MAX1383

—

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25

Maxim is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX1379
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Dual, 12-Bit, 1.25Msps Simultaneous-Sampling ADCs with Serial Interface
文件：	总25页 (文件大小：2297K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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