MAX1428ETN [MAXIM]
15-Bit, 80Msps ADC with -78.4dBFS Noise Floor for IF Applications; 15位，80Msps ADC与IF应用-78.4dBFS本底噪声
| 元器件型号： | MAX1428ETN |
| 生产厂家： | 
MAXIM INTEGRATED PRODUCTS
|
| 描述和应用： | 15-Bit, 80Msps ADC with -78.4dBFS Noise Floor for IF Applications |
| PDF文件： | 总18页 (文件大小：716K) |
| 下载文档： | 下载PDF数据表文档文件 |
| 型号参数：MAX1428ETN参数 | |
| 是否Rohs认证 | 不符合 |
| 生命周期 | Obsolete |
| IHS 制造商 | MAXIM INTEGRATED PRODUCTS INC |
| 零件包装代码 | QFN |
| 包装说明 | HVQCCN, |
| 针数 | 56 |
| Reach Compliance Code | compliant |
| ECCN代码 | 3A001.A.5.A.5 |
| HTS代码 | 8542.39.00.01 |
| 风险等级 | 5.92 |
| 最大模拟输入电压 | 2.56 V |
| 最小模拟输入电压 | |
| 最长转换时间 | 0.0125 µs |
| 转换器类型 | ADC, PROPRIETARY METHOD |
| JESD-30 代码 | S-XQCC-N56 |
| JESD-609代码 | e0 |
| 长度 | 8 mm |
| 湿度敏感等级 | 3 |
| 模拟输入通道数量 | 1 |
| 位数 | 15 |
| 功能数量 | 1 |
| 端子数量 | 56 |
| 最高工作温度 | 85 °C |
| 最低工作温度 | -40 °C |
| 输出位码 | 2'S COMPLEMENT BINARY |
| 输出格式 | PARALLEL, WORD |
| 封装主体材料 | UNSPECIFIED |
| 封装代码 | HVQCCN |
| 封装形状 | SQUARE |
| 封装形式 | CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE |
| 峰值回流温度（摄氏度） | 245 |
| 认证状态 | Not Qualified |
| 采样速率 | 80 MHz |
| 采样并保持/跟踪并保持 | TRACK |
| 座面最大高度 | 0.8 mm |
| 标称供电电压 | 5 V |
| 表面贴装 | YES |
| 温度等级 | INDUSTRIAL |
| 端子面层 | TIN LEAD |
| 端子形式 | NO LEAD |
| 端子节距 | 0.5 mm |
| 端子位置 | QUAD |
| 处于峰值回流温度下的最长时间 | NOT SPECIFIED |
| 宽度 | 8 mm |
| Base Number Matches | 1 |
MAX34334CSE前5页PDF页面详情预览
19-3433; Rev 0; 10/04
IT
TION K
VALUA
E
BLE
AVAILA
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
General Description
Features
♦
80Msps Minimum Sampling Rate
♦
-78.4dBFS Noise Floor
♦
Excellent Dynamic Performance
73.9dB SNR at f
IN
= 70MHz and A
IN
= -2dBFS
83dBc/91dBc Single-Tone SFDR1/SFDR2 at
f
IN
= 70MHz and A
IN
= -2dBFS
-82dB Multitone SFDR at f
IN1
= 69MHz
and f
IN2
= 71MHz
♦
Less than 0.25ps Sampling Jitter
♦
Fully Differential Analog Input Voltage Range of
2.56V
P-P
♦
CMOS-Compatible Two’s-Complement Data Output
♦
Separate Data Valid Clock and Overrange Outputs
♦
Flexible-Input Clock Buffer
♦
EV Kit Available for MAX1428
(Order MAX1427EVKIT)
MAX1428
The MAX1428 is a 5V, high-speed, high-performance
analog-to-digital converter (ADC) featuring a fully differ-
ential wideband track-and-hold (T/H) and a 15-bit con-
verter core. The MAX1428 is optimized for multichannel,
multimode receivers, which require the ADC to meet very
stringent dynamic performance requirements. With a
noise floor of -78.4dBFS, the MAX1428 allows for the
design of receivers with superior sensitivity.
The MAX1428 achieves two-tone, spurious-free dynamic
range (SFDR) of -82dBc for input tones of 69MHz and
71MHz. Its excellent signal-to-noise ratio (SNR) of 73.9dB
and single-tone SFDR performance (SFDR1/SFDR2) of
83dBc/91dBc at f
IN
= 70MHz and a sampling rate of
80Msps make this part ideal for high-performance digital
receivers.
The MAX1428 operates from an analog 5V and a digital
3V supply, features a 2.56V
P-P
full-scale input range,
and allows for a sampling speed of up to 80Msps. The
input T/H operates with a -1dB full-power bandwidth of
260MHz.
The MAX1428 features parallel, CMOS-compatible out-
puts in two’s-complement format. To enable the interface
with a wide range of logic devices, this ADC provides a
separate output driver power-supply range of 2.3V to
3.5V. The MAX1428 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extended
industrial (-40°C to +85°C) temperature range.
Note that IF parts MAX1418, MAX1428, and MAX1430
(see
Pin-Compatible Higher/Lower Speed Versions
Selection
table) are recommended for applications that
require high dynamic performance for input frequen-
cies greater than f
CLK
/3. Unlike its baseband counter-
part MAX1427, the MAX1428 is optimized for input
frequencies greater than f
CLK
/3.
Ordering Information
PART
MAX1428ETN
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
56 Thin QFN-EP*
*EP
= Exposed paddle.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Single- and Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
Power Amplifier Linearity Correction
Antenna Array Processing
Pin-Compatible Higher/Lower
Speed Versions Selection
PART
MAX1418
MAX1419
MAX1427
MAX1428
MAX1429
MAX1430
SPEED GRADE
(Msps)
65
65
80
80
100
100
TARGET
APPLICATION
IF
Baseband
Baseband
IF
Baseband
IF
Pin Configuration appears at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
MAX1428
ABSOLUTE MAXIMUM RATINGS
AV
CC
, DV
CC
, DRV
CC
to GND.................................. -0.3V to +6V
INP, INN, CLKP, CLKN, CM to GND........-0.3V to (AV
CC
+ 0.3V)
D0–D14, DAV, DOR to GND..................-0.3V to (DRV
CC
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
56-Pin Thin QFN (derate 47.6mW/°C above +70°C) ...3809.5mW
Operating Temperature Range ...........................-40°C to +85°C
Thermal Resistance
θ
J
A
...................................................21°C/W
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
ANALOG INPUT (INP, INN)
Differential Input Voltage Range
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
Full-Power Analog Bandwidth
CONVERSION RATE
Maximum Clock Frequency
Minimum Clock Frequency
Aperture Jitter
CLOCK INPUT (CLKP, CLKN)
Full-Scale Differential Input
Voltage
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
DYNAMIC CHARACTERISTICS
Thermal + Quantization
Noise Floor
NF
Analog input <-35dBFS
-78.4
dBFS
V
DIFFCLK
V
CM
R
INCLK
C
INCLK
Fully differential input drive, V
CLKP
- V
CLKN
Self-biased
0.5 to
3.0
2.4
2
±15%
1
V
V
kΩ
pF
f
CLK
f
CLK
t
AJ
80
20
0.21
MHz
MHz
ps
RMS
V
DIFF
V
CM
R
IN
C
IN
FPBW
-1dB
-1dB rolloff for a full-scale input
Fully differential inputs drive, V
DIFF
= V
INP
- V
INN
Self-biased
2.56
4.163
1
±15%
1
260
V
P-P
V
kΩ
pF
MHz
INL
DNL
f
IN
= 15MHz
f
IN
= 70MHz, no missing codes guaranteed
-12
-4
15
±1.5
±0.4
+12
+4
Bits
LSB
LSB
mV
%FS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
SYMBOL
CONDITIONS
f
IN
= 5MHz at -2dBFS
f
IN
= 15MHz at -2dBFS
Signal-to-Noise Ratio (Note 1)
SNR
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Signal-to-Noise and Distortion
(Note 1)
f
IN
= 15MHz at -2dBFS
SINAD
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Spurious-Free Dynamic Range
(HD2 and HD3)
(Note 1)
f
IN
= 15MHz at -2dBFS
SFDR1
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
f
IN
= 5MHz at -2dBFS
Spurious-Free Dynamic Range
(HD4 and Higher)
(Note 1)
f
IN
= 15MHz at -2dBFS
SFDR2
f
IN
= 35MHz at -2dBFS
f
IN
= 70MHz at -2dBFS
f
IN
= 170MHz at -6dBFS
Two-Tone Intermodulation
Distortion
Two-Tone Spurious-Free
Dynamic Range
Digital Output-Voltage Low
Digital Output-Voltage High
TTIMD
SFDR
TT
f
IN1
= 69MHz at -8dBFS,
f
IN2
= 71MHz at -8dBFS
f
IN1
= 69MHz at -12dBFS < f
IN1
< -100dBFS,
f
IN2
= 71MHz at -12dBFS < f
IN2
< -100dBFS
83.9
78.0
71.0
72.0
MIN
TYP
75.3
75.3
74.8
73.9
69.0
74.9
74.9
74.4
73.4
68.2
88.0
88.0
87.0
83.0
78.0
95.0
95.0
95.0
91.0
80.0
-82
-95
dBc
dBFS
dBc
dBc
dB
dB
MAX
UNITS
MAX1428
DIGITAL OUTPUTS (D0–D14, DAV, DOR)
V
OL
V
OH
DRV
CC
- 0.5
0.5
V
V
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 2.5V)
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
Duty
Cycle
t
AD
t
DAT
t
DAV
t
LATENCY
(Note 3)
(Note 3)
3.0
5.3
50
±5
230
4.5
6.5
3
7.5
8.7
%
ps
ns
ns
Clock
Cycles
_______________________________________________________________________________________
3
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
MAX1428
ELECTRICAL CHARACTERISTICS (continued)
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, GND = 0, INP and INN driven differentially with -2dBFS, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical
values are at T
A
= +25°C, unless otherwise noted.
≥+25°C
guaranteed by production test, <+25°C guaranteed by design and char-
acterization.)
PARAMETER
CLKP Rising Edge to
DATA Not Valid
CLKP Rising Edge to
DATA Valid (Guaranteed)
DATA Setup Time
(Before DAV Rising Edge)
DATA Hold Time
(After DAV Rising Edge)
SYMBOL
t
DNV
t
DGV
t
SETUP
t
HOLD
(Note 3)
(Note 3)
(Note 3)
(Note 3)
CONDITIONS
MIN
2.6
3.4
t
CLKP
-
0.5
t
CLKN
-
3.6
TYP
3.8
5.2
t
CLKP
+ 1.3
t
CLKN
- 2.8
50 ±5
230
(Note 3)
(Note 3)
2.8
5.3
4.1
6.3
3
(Note 3)
(Note 3)
(Note 3)
(Note 3)
2.5
3.2
t
CLKP
+ 0.2
t
CLKN
-
3.5
3.4
4.4
t
CLKP
+ 1.7
t
CLKN
- 2.7
5 ±3%
(Note 2)
(Note 2)
2.3 to
3.5
2.3 to
3.5
400
f
CLK
= 80MHz, C
L
= 5pF
38
2095
450
44
5.2
7.4
t
CLKP
+ 2.8
t
CLKN
- 2.0
6.5
8.6
MAX
5.7
8.6
t
CLKP
+ 2.4
t
CLKN
- 2.0
UNITS
ns
ns
ns
ns
TIMING CHARACTERISTICS (DV
CC
= DRV
CC
= 3.3V)
Duty
CLKP/CLKN Duty Cycle
Effective Aperture Delay
Output Data Delay
Data Valid Delay
Pipeline Latency
CLKP Rising Edge to
DATA Not Valid
CLKP Rising Edge to
DATA Valid (Guaranteed)
DATA Setup Time
(Before DAV Rising Edge)
DATA Hold Time
(After DAV Rising Edge)
POWER REQUIREMENTS
Analog-Supply Voltage Range
Digital-Supply Voltage Range
Output-Supply Voltage Range
Analog Supply Current
Digital + Output Supply Current
Total Power Dissipation
AV
CC
DV
CC
DRV
CC
I
AVCC
I
DVCC
+
I
DRVCC
PDISS
t
AD
t
DAT
t
DAV
t
LATENCY
t
DNV
t
DGV
t
SETUP
t
HOLD
%
ps
ns
ns
Clock
Cycles
ns
ns
ns
ns
V
V
V
mA
mA
mW
Note 1:
Dynamic performance is based on a 32,768-point data record with a sampling frequency of f
SAMPLE
= 80.019456MHz, an
input frequency of f
IN
= f
SAMPLE
x (28667/32768) = 70.004814MHz, and a frequency bin size of 2442Hz. Close-in (f
IN
±29.3kHz) and low-frequency (DC to 58.6kHz) bins are excluded from the spectrum analysis.
Note 2:
Apply the same voltage levels to DV
CC
and DRV
CC
.
Note 3:
Guaranteed by design and characterization.
4
_______________________________________________________________________________________
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
MAX1428
Typical Operating Characteristics
(AV
CC
= 5V, DV
CC
= DRV
CC
= 2.5V, INP and INN driven differentially with a -2dBFS amplitude, CLKP and CLKN driven differentially
with a 2V
P-P
sinusoidal input signal, C
L
= 5pF at digital outputs, f
CLK
= 80MHz, T
A
= 25°C. All AC data is based on a 32k-point FFT
record and under coherent sampling conditions.)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1428 toc01
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1428 toc02
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
f
CLK
= 80.0195MHz
f
IN
= 69.9999MHz
A
IN
= -1.98dBFS
SNR = 73.9dBc
SINAD = 73.2dBc
SFDR1 = 82.8dBc
SFDR2 = 95.3dBc
HD2 = -90.3dBFS
HD3 = -84.7dBFS
MAX1428 toc03
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
35
f
CLK
= 80.0195MHz
f
IN
= 15.0012MHz
A
IN
= -2.07dBFS
SNR = 75.4dBc
SINAD = 75.1dBc
SFDR1 = 89.4dBc
SFDR2 = 99dBc
HD2 = -92.1dBFS
HD3 = -91.4dBFS
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
f
CLK
= 80.0195MHz
f
IN
= 35.001186MHz
A
IN
= -2.07dBFS
SNR = 75dBc
SINAD = 74.5dBc
SFDR1 = 86.2dBc
SFDR2 = 94.6dBc
HD2 = -91.8dBFS
HD3 = -88.3dBFS
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
40
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1428 toc04
TWO-TONE IMD PLOT
(32,768-POINT DATA RECORD,
COHERENT SAMPLING)
MAX1428 toc05
SNR vs. ANALOG INPUT FREQUENCY
(f
CLK
= 80.0195MHz, A
IN
= -2dBFS)
76
75
74
SNR (dBc)
73
72
71
70
MAX1428 toc06
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
-120
0
5
10
15
20
25
30
35
f
CLK
= 80.019456MHz
f
IN
= 168.09995MHz
A
IN
= -5.96dBFS
SNR = 69dBc
SINAD = 67.8dBc
SFDR1 = 77.8dBc
SFDR2 = 79.8dBc
HD2 = -85.6dBFS
HD3 = -83.8dBFS
0
-20
AMPLITUDE (dBFS)
-40
-60
-80
-100
f
IN1
f
IN2
f
CLK
= 80.0195MHz
f
IN1
= 68.9987MHz
A
IN1
= -8.05dBFS
f
IN2
= 71.0012MHz
A
IN2
= -8.06dBFS
IMD = -82dBc
2f
IN1
+ f
IN2
2f
IN1
- f
IN2
f
IN1
+ 2f
IN2
77
69
-120
40
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
68
5
25
45
65
85 105 125 145 165 185
f
IN
(MHz)
_______________________________________________________________________________________
5
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