15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
BACK-TO-BACK DIODE
AV
CC
DV DRV
CC CC
0.1µF
T2-1T-KK81
50Ω
50Ω
INP
INN
D0–D14
MAX1428
15
0.1µF
0.01µF 0.1µF
0.01µF
CLKP
GND
CLKN
Figure 5. Transformer-Coupled Clock Input Configuration
held to 3V
differential or less. If a larger amplitude
P-P
Applications Information
signal is provided (to maximize the zero-crossing slew
rate), then the diodes serve to limit the differential sig-
nal swing at the clock inputs.
Differential, AC-Coupled Clock Input
The clock inputs to the MAX1428 are designed to be
driven with an AC-coupled differential signal, and best
performance is achieved under these conditions.
However, it is often the case that the available clock
source is single ended. Figure 5 demonstrates one
method for converting a single-ended clock signal into
a differential signal through a transformer. In this exam-
ple, the transformer turns ratio from the primary to sec-
ondary side is 1:1.414. The impedance ratio from
primary to secondary is the square of the turns ratio, or
1:2, so that terminating the secondary side with a 100Ω
differential resistance results in a 50Ω load looking into
the primary side of the transformer. The termination
resistor in this example comprises the series combina-
tion of two 50Ω resistors with their common node AC-
coupled to ground. Alternatively, a single 100Ω resistor
across the two inputs with no common-mode connec-
tion could be employed.
Any differential-mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR perfor-
mance of the MAX1428. Any differential-mode coupling
of the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that
the clock lines be well isolated from the analog signal
input and from the digital outputs. See the PC Board
Layout Considerations section for more discussion on
noise coupling.
Differential, AC-Coupled Analog Input
The analog inputs (INP and INN) are designed to be dri-
ven with a differential AC-coupled signal. It is extremely
important that these inputs be accurately balanced. Any
common-mode signal applied to these inputs degrades
even-order distortion terms. Therefore, any attempt at
driving these inputs in a single-ended fashion results in
significant even-order distortion terms.
In the example of Figure 5, the secondary side of the
transformer is coupled directly to the clock inputs.
Since the clock inputs are self-biasing, the center tap of
the transformer must be AC-coupled to ground or left
floating. If the center tap of the secondary were DC-
coupled to ground, then it would be necessary to add
blocking capacitors in series with the clock inputs.
Figure 6 presents one method for converting a single-
ended signal to a balanced differential signal using a
transformer. The primary-to-secondary turns ratio in this
example is 1:1.414. The impedance ratio is the square
of the turns ratio, so in this example, the impedance
ratio is 1:2. To achieve a 50Ω input impedance at the
primary side of the transformer, the secondary side is
terminated with a 112Ω differential load. This load, in
shunt with the differential input resistance of the
MAX1428, results in a 100Ω differential load on the sec-
ondary side. It is reasonable to use a larger transformer
turns ratio to achieve a larger signal step-up, and this
may be desirable to relax the drive requirements for the
circuitry driving the MAX1428. However, the larger the
Clock jitter is generally improved if the clock signal has
a high slew rate at the time of its zero crossing.
Therefore, if a sinusoidal source is used to drive the
clock inputs, it is desirable that the clock amplitude be
as large as possible to maximize the zero-crossing
slew rate. The back-to-back Schottky diodes shown in
Figure 5 are not required as long as the input signal is
12 ______________________________________________________________________________________
5V 过电压保护回路电路解析：复杂原理源于简单设计
先进封装：台积电、英特尔、三星等大厂的新战场
探秘台积电 SoW：从起源到应用的深度剖析
英特尔战略调整：舍弃 18A，全力进军 1.4nm 制程
概述
规格参数
数据手册
