MAX1438ECQ+D [MAXIM]
Low-Voltage and Low-Power Operation;
| 型号： | MAX1438ECQ+D |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Voltage and Low-Power Operation 信息通信管理 转换器 |
| 文件： | 总23页 (文件大小：1091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3741; ꢁev 1; 8/10
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
General Description
Features
o Low-Voltage and Low-Power Operation
o Optional On-Board Clock-Shaping Circuitry
o Serial Scalable Low-Voltage Signaling
(SLVS)/Low-Voltage Differential Signaling (LVDS)
Outputs
The MAX1434/MAX1436/MAX1437/MAX1438 evaluation
kits (EV kits) are fully assembled and tested circuit
boards that contain all the components necessary to
evaluate the performance of this family of octal 10-/12-
bit analog-to-digital converters (ADCs). These ADCs
accept differential analog input signals. The EV kits
generate these signals from user-provided single-
ended input sources. The EV kits’ digital outputs can be
easily sampled with a user-provided high-speed logic
analyzer or data-acquisition system. The EV kits also
feature an on-board deserializer to simplify integration
with standard logic analysis systems. The EV kits oper-
ate from 1.8V and 3.3V (plus 1.5V if the FPGA is used)
power supplies and include circuitry that generates a
clock signal from an AC signal provided by the user.
o On-Board LVPECL Differential Output Drivers
o On-Board Deserializer
o LVDS Test Mode
o Fully Assembled and Tested
Part Selection Table
Ordering Information
PART
TYPE
EV Kit
EV Kit
EV Kit
EV Kit
PART NUMBER
MAX1434ECQ+D
MAX1436ECQ+D
MAX1437ECQ+D
MAX1438ECQ+D
BITS
10
SPEED (Msps)
MAX1434EVKIT
MAX1436EVKIT
MAX1437EVKIT
MAX1438EVKIT
50
40
50
65
12
12
12
+Denotes lead(Pb)-free and ꢁoHS compliant.
D = Dry Pack.
Component List
DESIGNATION QTY
DESCRIPTION
DESIGNATION QTY
DESCRIPTION
220µF 20ꢀ, 6.3V tantalum
capacitors (C-case)
AVX TPSC227M006ꢁ0250
C1–C8, C10,
C11, C12,
C57–C64,
C81–C85,
C139, C140,
C147–C156
C45, C46, C47,
8
C86–C89, C143
0.1µF 10ꢀ, 10V X5ꢁ ceramic
36 capacitors (0402)
TDK C1005X5ꢁ1A104K
C48, C49, C50,
0
Not installed, capacitors (C-case)
C144
10µF 10ꢀ, 10V X5ꢁ ceramic
capacitors (1210)
TDK C3225X5ꢁ1A106K
C51, C52, C53,
6
C9, C29–C44,
C56, C77, C78,
C80, C92, C93, 28
C134–C137,
C146
C90, C91, C145
1.0µF 10ꢀ, 6.3V X5ꢁ ceramic
capacitors (0402)
TDK C1005X5ꢁ0J105K
2.2µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitor (0603)
TDK C1608X5ꢁ0J225M
C54
1
C13–C20,
0
Not installed, ceramic capacitors
(0603)
0.01µF 10ꢀ, 25V X7ꢁ ceramic
capacitors (0402)
TDK C1005X7ꢁ1E103K
C55,
C157–C176
C65–C72
21
0
39pF 5ꢀ, 50V C0G ceramic
capacitors (0402)
TDK C1005C0G1H390J
C21–C28,
16
C73–C76,
C122–C125
Not installed, ceramic capacitors
(0402)
C126–C133
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Component List (continued)
DESIGNATION QTY
DESCRIPTION
DESIGNATION QTY
DESCRIPTION
10µF 10ꢀ, 4V X5ꢁ ceramic
capacitors (0603)
TDK C1608X5ꢁ0G106K
ꢁ45–ꢁ50,
ꢁ100–ꢁ103
C79, C138,
10 100Ω 1ꢀ resistors (0603)
3
C142
ꢁ51
1
3
1
1
1
2
2
1
1
1
100kΩ potentiometer, 19-turn, 3/8in
4.02kΩ 1ꢀ resistors (0603)
5kΩ potentiometer, 19-turn, 3/8in
2kΩ 1ꢀ resistor (0603)
0.1µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitors (0201)
TDK C0603X5ꢁ0J104M
ꢁ52, ꢁ53, ꢁ56
ꢁ54
C94–C121
C141
28
1
ꢁ55
100µF 20ꢀ, 6.3V X5ꢁ ceramic
capacitor (1210)
TDK C3225X5ꢁ0J107M
ꢁ57
13.0kΩ 1ꢀ resistor (0603)
4.7kΩ 5ꢀ resistors (0603)
330Ω 5ꢀ resistors (1206)
162Ω 1ꢀ resistor (0603)
10kΩ 5ꢀ resistor (0603)
Momentary contact switch
ꢁ94, ꢁ95
ꢁ96, ꢁ97
ꢁ99
Dual Schottky diode (SOT23)
Central Semi CMPD6263S or
Diodes Inc. BAS70-04
D1
1
ꢁ104
D2, D3
2
9
Green surface-mount LEDs (0603)
SMA PC-mount vertical connectors
SW1
IN0–IN7,
CLOCK
1:1 800MHz ꢁF transformers
Mini-Circuits ADT1-1WT
T1–T8
8
0
J1–J8, JU14
J9–J13, J15
J14
9
6
1
2-pin headers
TP1–TP8, TP13,
TP14, TP15
Test points, not installed
Dual-row, 40-pin (2 x 20) headers
9-pin header
TP9–TP12
TP16
4
1
1
PC test points (red)
JU1–JU11,
JU13
PC test point (black)
12 3-pin headers
U1
See EV kit specific component list
JU12
1
1
Dual-row, 8-pin (2 x 4) header
Single LVDS line receivers (8 SO)
Maxim MAX9111ESA
U2
1
Digital logic n-channel MOSFET
(SOT23)
Central Semi 2N7002
N1
Low-noise, low-distortion op amp
(5 SOT23)
U3
1
ꢁ1–ꢁ8,
ꢁ22–ꢁ25,
ꢁ62–ꢁ73
Maxim MAX4250EUK
0
Not installed, resistors (0603)
TinyLogic UHS dual inverter
(6 SC70)
U4
1
ꢁ9–ꢁ16,
ꢁ26–ꢁ35,
ꢁ77–ꢁ81,
Fairchild NC7WZ04P6X
Virtex II platform FPGA (256 FGBGA)
Xilinx XC2V80-5FG256C or
Xilinx XC2V80-5FG256I
0
9
Not installed, resistors (0402)
U5
U6
1
1
ꢁ87–ꢁ93, ꢁ98
ꢁ17–ꢁ21,
ꢁ58–ꢁ61
PꢁOM (SO-20)
Xilinx XC18V01SO20C
49.9Ω 1ꢀ resistors (0603)
ꢁ36,
ꢁ105–ꢁ133
LVDS/anything-to-LVPECL translators
(8 µMAX®)
Maxim MAX9375EUA
30 49.9Ω 1ꢀ resistors (0402)
16 10Ω 1ꢀ resistors (0805)
U7–U16
10
ꢁ37–ꢁ44, ꢁ74,
ꢁ75, ꢁ76,
None
None
14 Shunts (JU1–JU14)
ꢁ82–ꢁ86
PCB: MAX1434/6/7/8 EVALUATION
KIT
1
Evluate:67/MAX1438
µMAX is a registered trademark of Maxim Integrated Products, Inc.
2
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
EV Kit Component List
EV KIT PART NUMBER
MAX1434EVKIT
DESIGNATION
DESCRIPTION
MAX1434ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1436ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1437ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1438ECQ+D (100 TQFP-EP 14mm x 14mm x 1mm)
MAX1436EVKIT
U1
MAX1437EVKIT
MAX1438EVKIT
Component Suppliers
SUPPLIER
AVX Corporation
PHONE
WEBSITE
www.avxcorp.com
843-946-0238
631-435-1110
805-446-4800
888-522-5372
718-934-4500
847-803-6100
Central Semiconductor Corp.
Diodes Incorporated
Fairchild Semiconductor Corp.
Mini-Circuits
www.centralsemi.com
www.diodes.com
www.fairchildsemi..com
www.minicircuits.com
www.component.tdk.com
TDK Corp.
Note: Indicate that you are using the MAX1434, MAX1436, MAX1437, or MAX1438 when contacting these component suppliers.
Procedure
Quick Start
Recommended Equipment
The EV kit is a fully assembled and tested surface-
mount board. Follow the steps below to verify board
operation. Do not turn on power supplies or enable
signal generators until all connections are completed.
•
DC power supplies:
Clock (CVDD) 3.3V, 100mA
1) Verify that shunts are installed in the following
locations:
Analog (AVDD) 1.8V, 500mA
Digital (OVDD) 1.8V, 150mA
Optional
Buffers (VPECL) 3.3V, 400mA
Deserializer Core (VD1.5) 1.5V, 200mA
Deserializer I/O (VD3.3) 3.3V, 200mA
JU1 (pins 2-3) → single termination
JU2 (pins 2-3) → LVDS outputs
JU3 (pins 2-3) → normal operation
JU4 (pins 2-3) → ADC enabled
JU7 (pins 2-3) → two’s-complement output
JU8 (pins 2-3) → FPGA enabled
•
•
•
•
•
Signal generator with low phase noise and low jitter
for clock input signal (e.g., HP 8662A, HP 8644B)
JU9, JU10, JU11 (pins 2-3) → channels 0–3
Signal generator for analog signal inputs (e.g., HP
8662A, HP 8644B)
output from FPGA
JU12 (pins 3-4) → internal reference enabled
JU14 (not installed) → disconnect external ref-
erence buffer
Logic analyzer or data-acquisition system (e.g., HP
16500C, TLA715)
Analog bandpass filters (e.g., Allen Avionics, K&L
Microwave) for input signal and clock signal
2) Verify that shunts are installed in the following
locations for configuring the specific EV kit:
Digital voltmeter
a)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→ 39MHz to 50MHz clock frequency range for
the MAX1434 EV kit.
_______________________________________________________________________________________
3
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
b)
JU5 (pins 1-2), JU6 (pins 2-3), JU13 (pins 2-3)
→ 32.5MHz to 40MHz clock frequency range for
the MAX1436 EV kit.
frequency with an amplitude ≤1.4V . All signal
P-P
generators should be phase-locked.
19) Verify that the PꢁOGꢁAMMING LED (D2) is off.
c)
d)
JU5, JU6, JU13 (pins 2-3) → 45MHz to 50MHz
clock frequency range for the MAX1437 EV kit.
20) Momentarily press switch SW1 and verify that the
LOCKED LED (D3) is on.
JU5, JU6, JU13 (pins 2-3) → 45MHz to 65MHz
clock frequency range for the MAX1438 EV kit.
21) Enable the logic analyzer.
22) Collect data using the logic analyzer.
3) Connect the clock signal generator to the input of
the clock bandpass filter.
Detailed Description of Hardware
4) Connect the output of the clock bandpass filter to
the clock SMA connector.
The EV kit is a fully assembled and tested circuit board
that contains all the components necessary to evaluate
the performance of the MAX1438, MAX1437, MAX1436,
or MAX1434.
5) Connect the analog input signal generator to the
input of the analog bandpass filter.
The ADCs accept differential input signals; however,
on-board transformers (T1–T8) convert the single-
ended signals applied to the IN0–IN7 SMA connectors,
to the required differential signal. The input signals of
the ADC can be measured using a differential oscillo-
scope probe at headers J1–J8.
6) Connect the output of the analog bandpass filter to
either one of the SMA connectors labeled IN0–IN7.
The analog input signals can also be monitored at
the 2-pin headers J1–J8.
Note: All eight channels can be operated indepen-
dently or simultaneously.
Output level translators (U7–U16) buffer and convert
the SLVS or LVDS output signals of the ADC to higher
voltage LVPECL signals, which can be captured by a
wide variety of logic analyzers. The SLVS/LVDS output
signals are accessible at header J9 and the LVPECL
output signals are accessible at header J15.
7) Connect the logic analyzer to either header J9
(SLVS- or LVDS-compatible signals) or J10–J13
(deserialized 3.3V CMOS-compatible signals). See
the Output Bit Locations section in this document
for header connections.
8) Connect the 1.8V, 500mA power supply to AVDD.
Connect the ground terminal of this supply to GND.
The EV kit PC board is designed as a six-layer board to
optimize performance of the ADC. Separate analog,
digital, clock, and buffer power planes minimize noise
coupling between analog and digital signals. 50Ω
coplanar transmission lines are used for analog and
clock inputs. 100Ω differential coplanar transmission
lines are used for all digital LVDS outputs. All differential
outputs are terminated with 100Ω termination resistors
between the true and complementary digital outputs.
The trace lengths of the 100Ω differential SLVS/LVDS
lines are matched to within a few thousands of an inch
to minimize layout-dependent data skew.
9) Connect the 1.8V, 150mA power supply to OVDD.
Connect the ground terminal of this supply to GND.
10) Connect the 3.3V, 100mA power supply to CVDD.
Connect the ground terminal of this supply to GND.
11) Connect the 3.3V, 400mA power supply to VPECL.
Connect the ground terminal of this supply to GND.
12) Connect the 1.5V, 200mA power supply to VD1_5.
Connect the ground terminal of this supply to GND.
13) Connect the 3.3V, 200mA power supply to VD3_3.
Connect the ground terminal of this supply to GND.
Power Supplies
For best performance, the EV kit requires separate ana-
log, digital, clock, and buffer power supplies. Two 1.8V
power supplies are used to power the analog (AVDD)
and digital (OVDD) portion of the ADC. The clock cir-
cuitry (CVDD) is powered by a 3.3V power supply. A
separate 3.3V power supply (VPECL) is used to power
the output buffers (U7–U16) of the EV kit. 1.5V (VD1_5)
and 3.3V (VD3_3) power supplies are required to power
the deserializer circuit.
14) Turn on the VD3_3 power supply.
15) Turn on the VD1_5 power supply.
16) Verify that the PꢁOGꢁAMMING LED (D2) and the
LOCKED LED (D3) are off.
17) Turn on the remaining power supplies.
M
18) Enable the signal generators. Set the clock signal
generator to output as specified to configuration
signal, with a 2.6V
amplitude or higher. Set the
P-P
analog input signal generators to output the desired
4
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Power-Down
Table 2. MAX1434 PLL Jumper Settings
Jumper JU4 controls the power-management feature of
(JU5, JU6, JU13)
data converter U1. See Table 1 for jumper JU4 shunt
positions.
CLOCK INPUT RANGE
(MHz)
JUMPER
Table 1. Power-Down Jumper Settings (JU4)
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
SHUNT
POWER-DOWN
EV KIT FUNCTION
2-3
2-3*
2-3
2-3
1-2
1-2
1-2
1-2
2-3
2-3*
1-2
1-2
2-3
2-3
1-2
1-2
2-3
1-2*
2-3
1-2
2-3
1-2
2-3
1-2
Unused
POSITION CONNECTIONS
39.0
27.0
19.5
13.5
9.8
50.0
39.0
27.0
19.5
13.5
9.8
1-2
AVDD
GND
ADC disabled
ADC enabled
2-3*
*Default configuration: JU4 (2-3).
Clock
By default, the user-provided AC-coupled clock signal
applied to the EV kit CLOCK SMA connector is buffered
on board with two inverters (U4). In this mode, diode
D1 limits the amplitude of the clock signal. Overdriving
the clock input can increase the slew rate of the differ-
ential signal, thereby reducing clock jitter. The frequen-
cy of the signal should not exceed the maximum
sampling rate of the ADC. The sinusoidal input signal
6.8
4.8
6.8
*Default configuration: JU5, JU6 (2-3), JU13 (1-2).
Table 3. MAX1436 PLL Jumper Settings
(JU5, JU6, JU13)
frequency (f
) determines the sampling rate of the
CLK
CLOCK INPUT RANGE
JUMPER
ADC. The clock signal applied to the ADC can be
observed at test point TP10.
(MHz)
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
Optional Clock-Shaping Circuit
The EV kit also features an optional on-board clock-
shaping circuit that generates a clock signal with vari-
able duty cycle from the AC-coupled sine-wave signal
applied to the CLOCK SMA connector. The MAX9111
differential line receiver (U2) processes the clock input
signal and generates the required CMOS clock signal.
To use this circuitry, cut the trace on the printed circuit
(PC) board at ꢁ78 and install 0Ω resistors at ꢁ35 and
ꢁ77. The signal’s duty cycle can be adjusted with poten-
tiometer ꢁ54. With a 3.3V clock supply voltage (CVDD),
a clock signal with a 50ꢀ duty cycle (recommended)
can be achieved by adjusting ꢁ54 until a voltage of
1.32V is produced across test points TP12 and TP16.
2-3
2-3*
2-3
2-3
1-2
1-2
1-2
1-2
2-3
2-3*
1-2
1-2
2-3
2-3
1-2
1-2
2-3
1-2*
2-3
1-2
2-3
1-2
2-3
1-2
Unused
32.5
22.5
16.3
11.3
8.1
40.0
32.5
22.5
16.3
11.3
8.1
5.6
4.0
5.6
*Default configuration: JU5, JU6 (2-3), JU13 (1-2).
PLL Frequency Mode Selection
When driving the EV kit with clock signals lower than
the maximum specified sampling rate of the ADC, the
phased-locked-loop (PLL) circuit of the ADC must be
set accordingly. ꢁefer to the PLL Inputs (PLL0–PLL3)
section in the ADC data sheet for further details about
the operation of the internal PLL. Jumpers JU5, JU6,
and JU13 control the PLL mode of the ADC. See Tables
2, 3, 4, or 5 for shunt positions. Configure jumpers JU5,
JU6, and JU13 accordingly and ensure that the clock
signal frequency falls between the minimum and maxi-
mum limits listed in Table 2 through Table 5.
________________________________________________________________________________________
5
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Table 4. MAX1437 PLL Jumper Settings
Table 6. Reference Jumper Settings (JU12)
(JU5, JU6, JU13)
SHUNT
REFADJ PIN
EV KIT FUNCTION
POSITION CONNECTION
CLOCK INPUT RANGE
JUMPER
(MHz)
Internal reference disabled.
Apply an external reference
voltage at the ꢁEFIO pad.
Verify that a shunt is installed
on jumper JU14.
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
Connected to
AVDD
MIN
MAX
1-2
2-3*
2-3
2-3
2-3
1-2
1-2
1-2
1-2
2-3*
2-3
1-2
1-2
2-3
2-3
1-2
1-2
2-3*
1-2
2-3
1-2
2-3
1-2
2-3
1-2
45.0
32.5
22.5
16.3
11.3
8.1
50.0
45.0
32.5
22.5
16.3
11.3
8.1
Internal reference enabled.
Verify that a shunt is not
installed on jumper JU14.
Connected to
GND
3-4*
Connected to
ꢁEFIO through
ꢁ57 and ꢁ51
Increase full-scale range by
adjusting potentiometer ꢁ51.
5-6**
7-8**
5.6
Connected to
GND through
ꢁ57 and ꢁ51
Compensate for gain errors by
adjusting potentiometer ꢁ51.
4.0
5.6
*Default configuration: JU5, JU6, JU13 (2-3).
*Default configuration: JU12 (3-4).
**ꢁefer to the Full-Scale ꢁange Adjustments using the Internal
ꢁeference section in the MAX1434, MAX1436, MAX1437, or
MAX1438 IC data sheet.
Table 5. MAX1438 PLL Jumper Settings
(JU5, JU6, JU13)
CLOCK INPUT RANGE
ence. Use the 2 x 4 header JU12 to configure the
desired reference mode. See Table 6 for the appropri-
ate shunt settings.
JUMPER
(MHz)
JU13
(PLL1)
JU6
(PLL2)
JU5
(PLL3)
MIN
MAX
Output Signal
The ADC features eight serial LVDS-compatible digital
outputs. Each output transmits the converted analog
input signals of channels 0 through 7. Two additional
outputs (CLKOUT and FꢁAME) are provided for data
synchronization. ꢁefer to the MAX1434, MAX1436,
MAX1437, or MAX1438 data sheet for more details.
2-3*
2-3
2-3
2-3
1-2
1-2
1-2
1-2
2-3*
2-3
1-2
1-2
2-3
2-3
1-2
1-2
2-3*
1-2
2-3
1-2
2-3
1-2
2-3
1-2
45.0
32.5
22.5
16.3
11.3
8.1
65.0
45.0
32.5
22.5
16.3
11.3
8.1
Output Format
The digital output coding can be chosen to be two’s
complement or straight offset binary by configuring
jumper JU7. See Table 7 for the appropriate jumper
configuration.
5.6
4.0
5.6
*Default configuration: JU5, JU6, JU13 (2-3).
Input Signal
Although the ADC accepts differential analog input sig-
nals, the EV kit only requires a single-ended analog
Table 7. Output Format Jumper Settings (JU7)
SHUNT
T/B PIN
input signal with an amplitude of less than 1.4V
pro-
P-P
DESCRIPTION
POSITION CONNECTION
vided by the user. On-board transformers (T1–T8) con-
vert the single-ended analog input signal and generate
differential analog signals at the ADCs’ differential input
pins. Connect the single-ended analog input signals to
SMA connectors IN0–IN7 for channel 0 to channel 7,
respectively.
Straight Offset Binary Selected.
Digital output in straight offset
binary format.
1-2
AVDD
GND
Evluate:67/MAX1438
Two’s Complement Selected.
Digital output in two’s-
2-3*
complement format.
Reference Voltage
The EV kit can be configured to use the ADC’s 1.24V
internal reference, or a stable, low-noise, external refer-
*Default configuration: JU7 (2-3).
6
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Double-Termination Settings
The ADC features trimmed, internal 100Ω termination
Table 10. LVDS Test Pattern Jumper
Settings (JU3)
resistors between the positive (true) and negative
(complementary) line of each output (D0–D7, CLKOUT,
and FꢁAME). The EV kit circuit also features 100Ω ter-
mination resistors located at the far end of each differ-
ential output pair. Activating the internal termination
helps eliminate unwanted reflections on the signal
traces. Use jumper JU1 to activate either single or dou-
ble-termination. See Table 8 for appropriate shunt posi-
tions that select the termination architecture.
SHUNT
POSITION CONNECTION
LVDSTEST PIN
EV KIT FUNCTION
Test pattern transmitted, LSB
first, on all SLVS/LVDS outputs
1-2
AVDD
GND
2-3*
Normal operation
*Default configuration: JU3 (2-3).
Output Bit Locations
The digital outputs of the ADC are connected to the 40-
pin header J9. All PC board trace lengths are matched
to minimize data skew and improve the overall dynamic
performance of the device. Additionally, 10 drivers
(U7–U16) buffer and level-translate the digital outputs
to LVPECL-compatible signals. The drivers increase the
differential voltage swing, and are capable of driving
large capacitive loads, which may be present at the
logic analyzer connection. The outputs of the buffers
are connected with 40-pin header J15. See Table 11 for
bit locations of headers J9 and J15.
Table 8. Double-Termination Jumper
Settings (JU1)
SHUNT
DT PIN
EV KIT FUNCTION
POSITION CONNECTION
Double Termination Selected.
Outputs are double-terminated.
1-2
AVDD
GND
Single Termination Selected.
Outputs are single-terminated.
2-3*
*Default configuration: JU1 (2-3).
Table 11. Output Bit Locations
SLVS/LVDS Outputs
UNBUFFERED BUFFERED
The ADC is capable of generating SLVS or LVDS signals
at its outputs. Jumper JU2 controls this feature of the
ADC. See Table 9 for shunt positions. ꢁegardless of
which output signal type is selected, the output buffers
(U7–U16) will convert the data to LVPECL logic levels.
When operating in SLVS output mode, JU1 must be con-
figured for double-termination (shunt across pins 1 and 2).
SIGNAL
DESCRIPTION
Channel 0
Channel 1
Channel 2
Channel 3
Clock
(LVDS or SLVS) (LVPECL)
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
P
N
J9-1
J9-2
J15-1
J15-2
CH0
J9-5
J15-5
CH1
J9-6
J15-6
J9-9
J15-9
CH2
J9-10
J9-13
J9-14
J9-17
J9-18
J9-21
J9-22
J9-25
J9-26
J9-29
J9-30
J9-33
J9-34
J9-37
J9-38
J15-10
J15-13
J15-14
J15-17
J15-18
J15-21
J15-22
J15-25
J15-26
J15-29
J15-30
J15-33
J15-34
J15-37
J15-38
Table 9. SLVS/LVDS Jumper Settings (JU7)
SHUNT
POSITION CONNECTION
SLVS/LVDS PIN
CH3
ADC OUTPUT
1-2
AVDD
GND
SLVS
LVDS
CLKOUT
FꢁAME
CH4
2-3*
*Default configuration: JU7 (2-3).
Frame
LVDS Test Pattern
Channel 4
Channel 5
Channel 6
Channel 7
To debug signal integrity problems, the ADC can gen-
erate a factory-set test pattern on all of the output chan-
nels. Jumper JU3 controls this feature. See Table 10 for
the appropriate shunt positions. The test pattern for the
MAX1436, MAX1437, and MAX1438 is 0000 1011 1101.
The test pattern for the MAX1434 is 00 0101 1101 (MSB
to LSB).
CH5
CH6
CH7
P = True (+).
N = Complementary (-).
_______________________________________________________________________________________
7
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
On-Board Deserializer
The EV kit features an on-board deserializer that con-
verts the serial outputs of the ADC to a parallel data
stream. The deserializer uses a delay-locked loop (DLL)
to synchronize itself with the incoming serial data stream.
After every change in ADC clock frequency, reset
this DLL by pressing switch SW1. If the LOCKED LED
D3 is not lit, the serial data stream is not synchronized
and the outputs of the deserializer are not valid.
Deserializer Output Enabled
Jumper JU8 controls the output enabled of the deseri-
alizer. See Table 14 for jumper JU8 configuration.
Table 14. Deserializer Output Enables (JU8)
EV KIT FUNCTION
POSITION
SHUNT
1-2
Deserializer output disabled
Deserializer output enabled
Channel 0 through channel 7 data is captured on head-
ers J10–J13. Only four channels can be captured at
one time on the EV kit. Configure jumpers JU9, JU10,
and JU11 to select the location of the channels. See
Table 12 for jumper JU9, JU10, JU11 configuration.
See Table 13 for bit locations.
2-3*
*Default configuration: JU8 (2-3).
Table 12. Output Channel Locations (JU9,
JU10, JU11)
JU9 (S2) JU10 (S1) JU11 (S0)
J10 J11 J12 J13
SHUNT
SHUNT
SHUNT
POSITION POSITION POSITION
2-3
2-3
2-3
2-3
1-2
1-2
2-3
2-3
1-2
1-2
2-3
2-3
2-3
1-2
2-3
1-2
2-3
1-2
CH0 CH1 CH2 CH3
CH4 CH5 CH6 CH7
CH0 CH4 CH1 CH5
CH0 CH6 CH1 CH7
CH2 CH4 CH3 CH5
CH2 CH6 CH3 CH7
Table 13. Output Bit Locations (J10–J13)
BIT
CLK
D11
D10
D9
POSITION
J11-38
J10-38
J10-26
J10-24
J10-22
J10-20
J10-18
J10-16
J10-14
J10-12
J10-10
J10-8
J12-38
J12-26
J12-24
J12-22
J12-20
J12-18
J12-16
J12-14
J12-12
J12-10
J12-8
J13-38
J13-26
J13-24
J13-22
J13-20
J13-18
J13-16
J13-14
J13-12
J13-10
J13-8
J11-26
J11-24
J11-22
J11-20
J11-18
J11-16
J11-14
J11-12
J11-10
J11-8
D8
D7
D6
D5
D4
D3
D2
Evluate:67/MAX1438
D1
J10-6
J11-6
J12-6
J13-6
D0
J10-4
J11-4
J12-4
J13-4
Note: Odd numbered pins are connected to ground.
ꢁemaining pins are no connects.
8
_______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
R E F P
R E F N
D D
D D
D D
D D
D D
D D
O V
O V
O V
O V
O V
O V
O V
O V
N . C .
N . C .
N . C .
N . C .
N . C .
N . C .
N . C .
D D
D D
D D
D D
D D
D D
O V
O V
O V
O V
C V
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
A G N D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
D D
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
A V
I N 7 N
I N 7 P
Figure 1. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—ADC (Sheet 1 of 6)
_______________________________________________________________________________________
9
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
L
R
Figure 2. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—Clock, Voltage ꢁeference (Sheet 2 of 6)
Evluate:67/MAX1438
10 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
C C
C C
V
G N D
G N D
G N D
G N D
V
C C
V
C C
V
C C
V
C C
V
G N D
G N D
G N D
G N D
C C
V
C C
V
C C
V
C C
V
G N D
G N D
G N D
G N D
C C
V
C C
V
Figure 3. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—LVPECL Level Translators (Sheet 3 of 6)
______________________________________________________________________________________ 11
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
C C
C C
V
G N D
G N D
G N D
G N D
V
C C
V
C C
V
C C
V
C C
V
G N D
G N D
G N D
G N D
C C
V
C C
V
Figure 4. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—LVPECL Level Translators (Sheet 4 of 6)
Evluate:67/MAX1438
12 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 5. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—Deserializer Input and Outputs (Sheet 5 of 6)
______________________________________________________________________________________ 13
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Figure 6. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Schematic—PꢁOM and FPGA (Sheet 6 of 6)
Evluate:67/MAX1438
14 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 7. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Component Placement Guide—Component Side
______________________________________________________________________________________ 15
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 8. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout—Component Side
16 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 9. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 2)—Ground Planes
______________________________________________________________________________________ 17
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 10. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 3)—Power Planes
18 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 11. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 4)—Signal Layer
______________________________________________________________________________________ 19
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 12. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout (Inner Layer 5)—Signal Layer
20 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 13. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit PC Board Layout—Solder Side
______________________________________________________________________________________ 21
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Figure 14. MAX1434/MAX1436/MAX1437/MAX1438 EV Kit Component Placement Guide—Solder Side
22 ______________________________________________________________________________________
MAX1434/MAX1436/MAX1437/MAX1438
Evaluation Kits
Evluate:67/MAX1438
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/05
Initial release
—
Added lead-free parts to Part Selection Table and EV Kit Component List and
updated Component Suppliers
1
8/10
1, 3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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