MAX14548AE [MAXIM]
100Mbps, 16-Channel LLTs; 100Mbps的， 16通道LLTs
| 型号： | MAX14548AE |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 100Mbps, 16-Channel LLTs |
| 文件： | 总17页 (文件大小：1912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5248; Rev 0; 4/10
100Mbps, 16-Channel LLTs
General Description
Features
The MAX14548E/MAX14548AE 16-channel, bidirectional
level translators (LLTs) provide the level shifting neces-
sary for 100Mbps data transfer in multivoltage systems.
S Bidirectional Level Translation
S 100Mbps Guaranteed Data Rate
S +1.7V to +3.6V Supply Voltage Range for V
S +1.1V to +3.6V Supply Voltage Range for V
CC
Externally applied voltages, V
and V , set the logic
CC
L
levels on either side of the device. Logic signals present
on the V side of the device appear as a high-voltage
L
L
(V > V )
CC L
logic signal on the V
side of the device and vice versa.
CC
S -40NC to +85NC Extended Operating Temperature
The devices feature a programming frequency input (PF) that
adjusts the one-shot accelerator on-time to guarantee a bit
Range
rate of 100Mbps with a load capacitance < 15pF and V >
1.1V (MAX14548E) or V > 1.4V (MAX14548AE) when driven
L
low. The MAX14548E can drive capacitive loads up to
50/R 1.1pF with a guaranteed bit rate of 40Mbps when
Applications
CMOS Logic-Level Translation
Low-Voltage ASIC Level Translation
Smart Card Readers
L
V > 1.1/R 1.1V and PF is driven high. The MAX14548AE
L
can drive capacitive loads up to 50pF with a guaranteed
Portable Communication Devices
Cell Phones
bit rate of 40Mbps when V > 1.1V and PF is driven high.
L
The device operate at full speed with external drivers
that source as low as 4mA output current. Each I/O chan-
GPS
Telecommunications Equipment
nel is pulled up to V
or V by an internal 35FA current
CC
L
source, allowing both devices to be driven by either
push-pull or open-drain drivers.
The devices feature multiple power-saving features
including an enable input (EN) that places the device
into a low-power shutdown mode when driven low and
an automatic shutdown mode that disables the part
when V
is less than V . The MAX14548AE output driv-
CC
L
er is designed to operate at full speed (100Mbps) with
V > 1.4V, which reduces the dynamic supply current vs.
L
Typical Operating Circuit appears at end of data sheet.
the MAX14548E. The state of I/O V
and I/O V are in
CC_
L_
high-impedance state during shutdown.
The devices operate with V voltages from +1.7V to
CC
+3.6V and V voltages from +1.1V to +3.6V, making
L
them ideal for data transfer between low-voltage ASICs/
PLDs and higher voltage systems. The devices are avail-
able in a 40-bump WLP (2.16mm x 3.46mm) package
with 0.4mm ball pitch, and operate over the extended
-40NC to +85NC temperature range.
Ordering Information/Selector Guide
BIT RATE (PF = LOW)
LOAD CAPACITANCE < 15pF
(Mbps)
BIT RATE (PF = HIGH)
LOAD CAPACITANCE < 50pF
(Mbps)
LOW DYNAMIC
SUPPLY
PIN-
PACKAGE
PART
CURRENT
MAX14548EEWL+
MAX14548AEEWL+
40 WLP
40 WLP
100
100
40
40
—
Yes (V > 1.1V)
L
Note: All devices operate over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
100Mbps, 16-Channel LLTs
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
Junction-to-Ambient Thermal Resistance (B
)
JA
V
I/O V
, V , EN, PF.......................................................-0.3V to +4V
(Note 1) ........................................................................58NC/W
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature .....................................................+150NC
Soldering Temperature (reflow) ......................................+260NC
CC
L
................................................... -0.3V to (V
+ 0.3V)
CC_
CC
I/O V ......................................................... -0.3V to (V + 0.3V)
Short-Circuit Duration I/O V
L_
L
,
L_
I/O V
to GND....................................................Continuous
CC_
Continuous Power Dissipation (T = +70NC)
A
40-Bump WLP (derate 17.2mW/NC above +70NC)....1379mW
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +1.7V to +3.6V, V = +1.1V to +3.6V, V
> V , EN = V , C
= 1FF, C = 1FF, T = -40NC to +85NC, unless otherwise
VCC VL A
L
CC
L
L
noted. Typical values are at V
= +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
V Supply Range
V
1.1
1.7
3.6
3.6
40
V
V
L
L
V
CC
Supply Range
V
CC
Supply Current from V
Supply Current from V
I
I/O V
I/O V
= V , I/O V = V
FA
FA
CC
QVCC
CC_
CC
L_
L
I
= V , I/O V = V
20
L
QVL
CC_
CC
L_
L
V
Shutdown Supply
T = +25NC, EN = GND, unconnected
A
I/O pins
CC
I
0.1
0.1
0.1
2.9
2.6
0.1
1
1
2
FA
SHDN-VCC
Current
T
= +25NC, EN = GND, unconnected
A
I/O pins
= +25NC, EN = V , V = GND,
CC
V Shutdown Mode Supply
L
Current
I
FA
SHDN-VL
T
A
L
unconnected I/O pins
One I/O switching at
25MHz; all other I/O
MAX14548E
Dynamic Supply Current
I
mA
D
connected to V
or
CC
MAX14548AE
V ; C
= 0pF
L
LOAD
I/O V
Leakage Current
, I/O V Three-State
CC_ L_
I
T
T
= +25NC, EN = GND
= +25NC
6
1
FA
LEAK
A
A
EN, PF Input Leakage Current
I
FA
LEAK_EN_PF
V Shutdown Threshold
V
0.3
0.3
V
L
TH_VL
V - V
L
Shutdown Threshold
CC
V
V
V
rising (V = 3.6V) (Note 4)
0.05
0.2
0.65
0.85
V
V
TH_H
CC
L
High
V - V
L
Shutdown Threshold
CC
V
falling (V = 3.6V) (Note 4)
0.52
TH_L
CC
L
Low
I/O V Pullup Current
I
I/O V = GND, I/O V = GND
CC_
10
15
125
90
FA
FA
L_
VL_PU_
L_
I/O V
Pullup Current
I
I/O V = GND, I/O V = GND
CC_ L_
CC_
VCC_PU_
I/O V to I/O V
L_
Resistance
DC
CC_
R
(Note 5)
3
kI
IOVL_IOVCC
2
100Mbps, 16-Channel LLTs
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +1.7V to +3.6V, V = +1.1V to +3.6V, V
> V , EN = V , C
= 1FF, C = 1FF, T = -40NC to +85NC, unless otherwise
VCC VL A
L
CC
L
L
noted. Typical values are at V
= +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ESD PROTECTION
Unpowered
device
Human Body
Model,
Q12
I/O V
, I/O V
kV
kV
CC_
L_
C
C
= 1FF,
= 1FF
VCC
Powered device
Q5
Q2
VL
All Other Pins
LOGIC LEVELS
I/O V Input-Voltage High
L_
Threshold
V -
L
0.2
V
(Note 6)
(Note 6)
(Note 6)
(Note 6)
V
V
V
V
IHL
I/O V Input-Voltage Low
L_
Threshold
V
0.15
0.2
ILL
I/O V
Input-Voltage High
V
CC
0.4
-
CC_
V
IHC
Threshold
I/O V Input-Voltage Low
CC_
V
ILC
Threshold
V -
0.25
L
1.1V < V < 1.3V
L
EN, PF Input-Voltage High
Threshold
V
V
IH
V -
L
0.4
V = 1.8V
L
1.1V < V < 1.3V
0.4
0.4
EN, PF Input-Voltage Low
Threshold
L
V
V
V
V
V
V
IL
V = 1.8V
L
4/5 x
I/O V Output-Voltage High
V
OHL
I/O V source current = 10FA
L_
L_
V
L
I/O V Output-Voltage Low,
L_
Drop to GND
I/O V sink current = 20FA,
1/3 x
V
L
L_
V
OLL
I/O V
I/O V
I/O V
< 0.05V
CC_
CC_
CC_
4/5 x
I/O V
Output-Voltage High
V
source current = 10FA
CC_
OHC
V
CC
I/O V
Output-Voltage Low,
sink current = 20FA,
1/3 x
V
CC
CC_
V
OLC
Drop to GND
I/O V < 0.05V
L_
RISE/FALL TIME ACCELERATOR STAGE
On rising edge
On falling edge
On rising edge
On falling edge
2.65
2.5
PF = low
ns
ns
I
Accelerator Pulse Duration
4
PF = high
3.7
V = 1.62V
L
7
V Output Accelerator Source
L
Impedance
V = 3.2V
L
4.43
14.2
11.2
15.3
15.3
20.3
19.5
V
CC
V
CC
= 2.2V
= 3.6V
V
CC
Output Accelerator
I
Source Impedance
V = 1.62V
L
V Output Accelerator Sink
L
Impedance
I
V = 3.2V
L
V
= 2.2V
= 3.6V
V
CC
Output Accelerator Sink
CC
CC
I
Impedance
V
3
100Mbps, 16-Channel LLTs
HIGH-SPEED TIMING CHARACTERISTICS—MAX14548E
(V
CC
= +1.7V to +3.6V, V = +1.1V to +3.6V, V
> V , EN = V , PF = low, C
= 1FF, C = 1FF, C
P15pF, C P15pF,
IOVCC
L
CC
L
L
VCC
VL
IOVL
T
= -40NC to +85NC, unless otherwise noted. Typical values are at V = +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC L A
A
PARAMETER
SYMBOL
CONDITIONS
Input rise time < 2ns, Figure 1
Input fall time < 2ns, Figure 1
Input rise time < 2ns, Figure 2
Input fall time < 2ns, Figure 2
MIN
TYP
MAX
UNITS
ns
I/O V
I/O V
Rise Time
Fall Time
t
2
2
2
2
CC_
CC_
RVCC
t
ns
FVCC
I/O V Rise Time
t
ns
L_
RVL
I/O V Fall Time
L_
t
ns
FVL
Propagation Delay
t
t
Input rise time < 2ns, Figure 1
2.75
ns
PVL-VCC
PVCC-VL
(Driving I/O V
)
L_
Propagation Delay
(Driving I/O V
Input rise time < 2ns, Figure 2
Input rise time/fall time < 2ns
2.26
0.2
27
ns
ns
Fs
)
CC_
Channel-to-Channel Skew
Propagation Delay from
t
SKEW
t
R
= 1MI, Figure 3
= 1MI, Figure 3
EN-VCC
LOAD
LOAD
I/O V to I/O V
After EN
L_
CC_
Propagation Delay from
I/O V to I/O V After EN
t
R
0.05
Fs
EN-VL
CC_
L_
Push-pull operation
100
0.3
Maximum Data Rate
Mbps
Open-drain operation
HIGH-SPEED TIMING CHARACTERISTICS—MAX14548AE
(V
CC
= +1.7V to +3.6V, V = +1.4V to +3.6V, V
> V , EN = V , PF = low, C
= 1FF, C = 1FF, C
P15pF, C P15pF,
IOVCC
L
CC
L
L
VCC
VL
IOVL
T
= -40NC to +85NC, unless otherwise noted. Typical values are at V = +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC L A
A
PARAMETER
SYMBOL
CONDITIONS
Input rise time < 2ns, Figure 1
Input fall time < 2ns, Figure 1
Input rise time < 2ns, Figure 2
Input rise time < 2ns, Figure 2
MIN
TYP
MAX
UNITS
ns
I/O V
I/O V
Rise Time
Fall Time
t
2
2
2
2
CC_
CC_
RVCC
t
ns
FVCC
I/O V Rise Time
t
ns
L_
RVL
I/O V Fall Time
L_
t
ns
FVL
Propagation Delay
t
t
Input rise time < 2ns, Figure 1
2.75
ns
PVL-VCC
PVCC-VL
(Driving I/O V
)
L_
Propagation Delay
(Driving I/O V
Input rise time < 2ns, Figure 2
Input rise time/fall time < 2ns
2.26
0.2
27
ns
ns
Fs
)
CC_
Channel-to-Channel Skew
Propagation Delay from
t
SKEW
t
R
= 1MI, Figure 3
= 1MI, Figure 3
EN-VCC
LOAD
LOAD
I/O V to I/O V
After EN
L_
CC_
Propagation Delay from
I/O V to I/O V After EN
t
R
0.05
Fs
EN-VL
CC_
L_
Push-pull operation
100
0.3
Maximum Data Rate
Mbps
Open-drain operation
4
100Mbps, 16-Channel LLTs
LOW-SPEED TIMING CHARACTERISTICS—MAX14548E
(V
CC
= +1.7V to +3.6V, V = +1.1V to +3.6V, V
> V , EN = V , PF = high, C
= 1FF, C = 1FF, C
P50pF, C P50pF,
IOVCC
L
CC
L
L
VCC
VL
IOVL
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V = +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC L A
PARAMETER
SYMBOL
CONDITIONS
Input rise time < 6ns, Figure 1
Input fall time < 6ns, Figure 1
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 2
MIN
TYP
MAX
UNITS
ns
I/O V
I/O V
Rise Time
Fall Time
t
6
6
6
6
CC_
CC_
RVCC
t
ns
FVCC
I/O V Rise Time
t
ns
L_
RVL
I/O V Fall Time
L_
t
ns
FVL
Propagation Delay
t
t
Input rise time < 6ns, Figure 1
4
ns
PVL-VCC
PVCC-VL
(Driving I/O V
)
L_
Propagation Delay
(Driving I/O V
Input rise time < 6ns, Figure 2
Input rise time/fall time < 6ns
3.37
0.2
27
ns
ns
Fs
)
CC_
Channel-to-Channel Skew
Propagation Delay from
t
0.5
SKEW
t
R
= 1MI, Figure 3
= 1MI, Figure 3
EN-VCC
LOAD
LOAD
I/O V to I/O V
After EN
L_
CC_
Propagation Delay from
I/O V to I/O V After EN
t
R
0.06
Fs
EN-VL
CC_
L_
Push-pull operation
40
Maximum Data Rate
Mbps
Open-drain operation
0.3
LOW-SPEED TIMING CHARACTERISTICS—MAX14548AE
(V
CC
= +1.7V to +3.6V, V = +1.1V to +3.6V, V
> V , EN = V , PF = high, C
= 1FF, C = 1FF, C
P50pF, C P50pF,
IOVCC
L
CC
L
L
VCC
VL
IOVL
T
A
= -40NC to +85NC, unless otherwise noted. Typical values are at V = +2.8V, V = +1.8V and T = +25NC.) (Notes 2, 3)
CC L A
PARAMETER
SYMBOL
CONDITIONS
Input rise time < 6ns, Figure 1
Input fall time < 6ns, Figure 1
Input rise time < 6ns, Figure 2
Input rise time < 6ns, Figure 2
MIN
TYP
MAX
UNITS
ns
I/O V
I/O V
Rise Time
Fall Time
t
6
6
6
6
CC_
CC_
RVCC
t
ns
FVCC
I/O V Rise Time
t
ns
L_
RVL
I/O V Fall Time
L_
t
ns
FVL
Propagation Delay
t
t
Input rise time < 6ns, Figure 1
4
ns
PVL-VCC
PVCC-VL
(Driving I/O V
)
L_
Propagation Delay
(Driving I/O V
Input rise time < 6ns, Figure 2
Input rise time/fall time < 6ns
3.37
0.2
27
ns
ns
Fs
)
CC_
Channel-to-Channel Skew
Propagation Delay from
t
SKEW
t
R
= 1MI, Figure 3
= 1MI, Figure 3
EN-VCC
LOAD
LOAD
I/O V to I/O V
After EN
L_
CC_
Propagation Delay from
I/O V to I/O V After EN
t
R
0.06
Fs
EN-VL
CC_
L_
Push-pull operation
40
Maximum Data Rate
Mbps
Open-drain operation
0.3
Note 2: All units are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by
A
design and not production tested.
Note 3: V must be less than or equal to V
during normal operation. However, V can be greater than V
during startup and
L
CC
L
CC
shutdown conditions.
Note 4: When V
is below V by more than the V - V
shutdown threshold, the device turns off its pullup generators and
CC
CC
L
L
I/O V
and I/O V enter their respective shutdown states.
CC_
L_
Note 5: Guaranteed by design.
Note 6: Input thresholds are referenced to the boost circuit.
5
100Mbps, 16-Channel LLTs
t
t
FVCC
RVCC
V
V
CC
L
90%
90%
V
EN
V
CC
L
I/O V
L_
MAX14548E
MAX14548AE
50%
50%
V
V
CC
L
50%
50%
I/O V
I/O V
CC_
L_
I/O V
10%
10%
CC_
C
IOVCC
t
t
PLH
PLH
t
= t
OR t
PVL-VCC PLH PHL
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
Figure 1. Push-Pull Driving I/O V Test Circuit and Timing
L_
t
t
FVL
RVL
V
V
CC
L
I/O V
CC_
V
EN
V
CC
L
MAX14548E
MAX14548AE
V
V
CC
L
90%
50%
90%
50%
50%
50%
I/O V
L_
I/O V
CC_
10%
I/O V
10%
C
IOVCC
L_
t
t
t
PLH
PLH
= t OR t
PVCC-VL PLH
PHL
NOTE: THE INPUT RISE/FALL TIMES ARE < 2ns FOR HIGH SPEED AND < 6ns FOR LOW SPEED.
Figure 2. Push-Pull Driving I/O V
Test Circuit and Timing
CC_
6
100Mbps, 16-Channel LLTs
V
EN
L
MAX14548E
MAX14548AE
EN
V
L
V
CC
t’
O
EN-VCC
I/O V
CC_
V
L
SOURCE
I/O V
L_
O
I/O V
L_
V
CC
R
R
LOAD
C
IOVCC
V
/2
I/O V
CC
CC_
O
V
L
V
CC
V
L
EN
EN
MAX14548E
MAX14548AE
LOAD
I/O V
O
V
t”
L
V
CC
EN-VCC
V
L
SOURCE
I/O V
L_
O
I/O V
L_
CC_
I/O V
CC_
V
CC
V
/2
CC
C
IOVCC
O
t
IS WHICHEVER IS LARGER BETWEEN t'
AND t"
.
EN-VCC
EN-VCC
EN-VCC
EN
V
L
MAX14548E
MAX14548AE
V
EN
L
V
CC
t’
O
EN-VL
SOURCE
V
CC
I/O V
I/O V
L_
CC_
I/O V
CC_
O
C
IOVL
V
L
V
R
CC
LOAD
V
/2
I/O V
L
L_
O
EN
V
L
MAX14548E
MAX14548AE
EN
V
L
V
CC
t”
EN-VL
V
L
O
SOURCE
V
CC
R
LOAD
I/O V
CC_
I/O V
CC_
O
I/O V
L_
C
V
I/O V
L
L_
IOVL
V
/2
L
O
t
IS WHICHEVER IS LARGER BETWEEN t'
AND t"
.
EN-VL
EN-VL
EN-VL
Figure 3. Enable Test and Timing
7
100Mbps, 16-Channel LLTs
Typical Operating Characteristics
(V
CC
= 1.8V, V = 1.4V, C = 15pF, R
= 150I, data rate = 100Mbps, push-pull driver, T = +25NC, unless otherwise noted.)
L
L
SOURCE A
V SUPPLY CURRENT vs. V SUPPLY
V
CC
SUPPLY CURRENT vs. V SUPPLY
V
SUPPLY CURRENT vs. V SUPPLY
VOLTAGE (DRIVING ONE I/O V )
L_
L
CC
L
CC CC
VOLTAGE (DRIVING ONE I/O V
)
L_
VOLTAGE (DRIVING ONE I/O V
)
CC_
250
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7
6
5
4
3
2
1
0
C
= 15pF
C
= 15pF
LOAD
LOAD
PF = LOW
PF = HIGH
200
150
100
50
DATA RATE = 40Mbps
MAX14548E
MAX14548AE
= 3.6V
MAX14548AE
MAX14548AE
V
CC
C
= 15pF
LOAD
MAX14548E
PF = LOW
MAX14548E
DATA RATE = 40Mbps
0
1.700
2.175
2.650
3.125
3.600
1.1
1.6
2.1
2.6
3.1
3.6
1.700
2.175
2.650
3.125
3.600
V
CC
SUPPLY VOLTAGE (V)
V SUPPLY VOLTAGE (V)
L
V
CC
SUPPLY VOLTAGE (V)
V SUPPLY CURRENT vs. CAPACITIVE LOAD
V
CC
SUPPLY CURRENT vs. CAPACITIVE
LOAD (DRIVING ONE I/O V )
L_
V
CC
SUPPLY CURRENT vs. V SUPPLY
L
L
(DRIVING ONE I/O V
)
VOLTAGE (DRIVING ONE I/O V
)
CC
CC_
1800
1600
1400
1200
1000
800
600
400
200
0
3500
7
6
5
4
3
2
1
0
MAX14548E
PF HIGH
MAX14548E
PF HIGH
3000
2500
2000
1500
1000
500
MAX14548AE
PF HIGH
MAX14548AE
PF HIGH
MAX14548E
= 3.6V
MAX14548AE
MAX14548AE
PF LOW
MAX14548E
PF LOW
MAX14548E
PF LOW
V
CC
MAX14548AE
PF LOW
C
= 15pF
LOAD
PF = HIGH
DATA RATE = 40Mbps
DATA RATE = 40Mbps
20 30
DATA RATE = 40Mbps
0
10
40
50
10
20
30
40
50
1.1
1.6
2.1
2.6
3.1
3.6
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
V SUPPLY VOLTAGE (V)
L
RISE TIME vs. CAPACITIVE LOAD
ON I/O V (DRIVING ONE I/O V )
FALL TIME vs. CAPACITIVE LOAD
RISE TIME vs. CAPACITIVE LOAD
ON I/O V (DRIVING ONE I/O V
ON I/O V (DRIVING ONE I/O V )
)
CC
CC
L
CC
L
L
2.5
2.0
1.5
1.0
0.5
0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
t
FVCC
t
FVL
MAX14548AE (PF HIGH)
t
MAX14548AE (PF HIGH)
FVCC
MAX14548AE (PF HIGH)
t
FVCC
t
RVL
MAX14548E (PF HIGH)
MAX14548AE (PF LOW)
t
RVCC
MAX14548AE (PF LOW)
t
RVCC
MAX14548E
(PF LOW)
t
t
RVCC
MAX14548AE
(PF LOW)
FVL
t
t
FVCC
MAX14548E
(PF HIGH)
RVCC
MAX14548E
(PF HIGH)
MAX14548E
(PF LOW)
t
RVL
DATA RATE = 40Mbps
DATA RATE = 40Mbps
MAX14548E (PF LOW)
DATA RATE = 40Mbps
10
20
30
40
50
10
20
30
40
50
10
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
8
100Mbps, 16-Channel LLTs
Typical Operating Characteristics (continued)
(V
CC
= 1.8V, V = 1.4V, C = 15pF, R
= 150I, data rate = 100Mbps, push-pull driver, T = +25NC, unless otherwise noted.)
L
L
SOURCE A
FALL TIME vs. CAPACITIVE LOAD
ON I/O V (DRIVING ONE I/O V
PROPAGATION DELAY vs. CAPACITIVE
)
LOAD ON I/O V (DRIVING ONE I/O V )
L
CC
CC
L
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
t
PVL-VCC
t
FVL
MAX14548E
(PF LOW)
MAX14548AE (PF HIGH)
t
FVL
MAX14548E (PF HIGH)
t
PVL-VCC
t
PVL-VCC
MAX14548E
(PF HIGH)
MAX14548AE
(PF LOW)
t
PVL-VCC
t
t
RVL
RVL
MAX14548AE
(PF HIGH)
MAX14548E
(PF LOW)
MAX14548AE
(PF LOW)
DATA RATE = 40Mbps
DATA RATE = 40Mbps
10
20
30
40
50
10
20
30
40
50
CAPACITIVE LOAD (pF)
CAPACITIVE LOAD (pF)
TYPICAL I/O V DRIVING
L_
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O V (DRIVING ONE I/O V
(DATA RATE = 100Mbps, C
= 10pF),
IOVCC
)
CC
L
PF = LOW, MAX14548E
MAX14548E toc13
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
t
PVCC-VL
MAX14548E
(PF HIGH)
I/O V
1V/div
L
t
PVCC-VL
t
PVCC-VL
MAX14548AE
(PF HIGH)
MAX14548E
(PF LOW)
I/O V
t
CC
PVCC-VL
1V/div
MAX14548AE
(PF LOW)
DATA RATE = 40Mbps
20 30
CAPACITIVE LOAD (pF)
10
40
50
10ns/div
TYPICAL I/O V DRIVING
TYPICAL I/O V
(DATA RATE = 100Mbps, C
DRIVING
= 10pF),
IOVL
L_
CC_
(DATA RATE = 40Mbps, C
= 47pF),
IOVCC
PF = HIGH, MAX14548E
PF = LOW, MAX14548E
MAX14548E toc14
MAX14548E toc15
I/O V
I/O V
CC
L
1V/div
1V/div
I/O V
1V/div
L
I/O V
1V/div
CC
20ns/div
10ns/div
9
100Mbps, 16-Channel LLTs
Typical Operating Characteristics (continued)
(V
CC
= 1.8V, V = 1.4V, C = 15pF, R
= 150I, data rate = 100Mbps, push-pull driver, T = +25NC, unless otherwise noted.)
A
L
L
SOURCE
TYPICAL I/O V
(DATA RATE = 40Mbps, C
DRIVING
TYPICAL I/O V DRIVING
L_
CC_
= 47pF),
(DATA RATE = 100Mbps, C
= 10pF),
IOVL
IOVCC
PF = HIGH, MAX14548E
PF = LOW, MAX14548AE
MAX14548E toc16
MAX14548E toc17
I/O V
1V/div
CC
I/O V
1V/div
L
I/O V
CC
1V/div
I/O V
L
1V/div
20ns/div
10ns/div
TYPICAL I/O V DRIVING
TYPICAL I/O V
(DATA RATE = 100Mbps, C
DRIVING
= 10pF),
IOVL
L_
CC_
(DATA RATE = 40Mbps, C
= 47pF),
IOVCC
PF = HIGH, MAX14548AE
PF = LOW, MAX14548AE
MAX14548E toc18
MAX14548E toc19
I/O V
1V/div
CC
I/O V
1V/div
L
I/O V
1V/div
I/O V
1V/div
L
CC
20ns/div
10ns/div
TYPICAL I/O V
(DATA RATE = 40Mbps, C
DRIVING
CC_
= 47pF),
IOVL
PF = HIGH, MAX14548AE
MAX14548E toc20
I/O V
CC
1V/div
I/O V
L
1V/div
20ns/div
10
100Mbps, 16-Channel LLTs
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
MAX14548E
MAX14548AE
1
2
3
4
5
6
7
8
+
A
I/O V 1
I/O V 2
I/O V 3
I/O V 4
I/O V 5
I/O V 6
I/O V 7
I/O V 8
L
L
L
L
L
L
L
L
B
C
D
E
I/O V 9
L
I/O V 10
I/O V 11
I/O V 12
L
I/O V 13
L
I/O V 14
I/O V 15
I/O V 16
L
L
L
L
L
GND
V
V
EN
PF
V
V
L
GND
L
CC
CC
I/O V
I/O V
1
9
I/O V 2
CC
I/O V 3
CC
I/O V 4
CC
I/O V 5
CC
I/O V 6
CC
I/O V 7
CC
I/O V 8
CC
CC
I/O V 10 I/O V 11 I/O V 12 I/O V 13 I/O V 14 I/O V 15 I/O V 16
CC
CC
CC
CC
CC
CC
CC
CC
WLP
(2.16mm × 3.46mm)
Pin Description
PIN
A1
NAME
I/O V 1
FUNCTION
Input/Output 1. Referenced to V .
L
L
A2
I/O V 2
Input/Output 2. Referenced to V .
L
L
A3
I/O V 3
Input/Output 3. Referenced to V .
L
L
A4
I/O V 4
Input/Output 4. Referenced to V .
L
L
A5
I/O V 5
Input/Output 5. Referenced to V .
L
L
A6
I/O V 6
Input/Output 6. Referenced to V .
L
L
A7
I/O V 7
Input/Output 7. Referenced to V .
L
L
A8
I/O V 8
Input/Output 8. Referenced to V .
L
L
B1
I/O V 9
Input/Output 9. Referenced to V .
L
L
B2
I/O V 10
Input/Output 10. Referenced to V .
L
L
B3
I/O V 11
Input/Output 11. Referenced to V .
L
L
B4
I/O V 12
Input/Output 12. Referenced to V .
L
L
B5
I/O V 13
Input/Output 13. Referenced to V .
L
L
B6
I/O V 14
Input/Output 14. Referenced to V .
L
L
B7
I/O V 15
Input/Output 15. Referenced to V .
L
L
B8
I/O V 16
L
Input/Output 16. Referenced to V .
L
C1, C8
GND
Ground
11
100Mbps, 16-Channel LLTs
Pin Description (continued)
PIN
NAME
FUNCTION
Logic Supply Voltage, +1.1V to +3.6V. Bypass V to GND with a 1FF capacitor placed as close as
possible to the device.
L
C2, C7
V
L
Power-Supply Voltage, +1.7V to +3.6V. Bypass V
to GND with a 0.1FF ceramic capacitor. For full
CC
C3, C6
V
CC
ESD protection, connect an additional 1FF ceramic capacitor from V
to GND as close as possible
CC
to the V
input.
CC
C4
C5
EN
PF
Enable Input. Drive EN to GND for shutdown mode, or drive EN to V or V
for normal operation.
L
CC
Programmable Frequency Input. Drive PF low for high-frequency operation. Drive PF high for lower
frequency operation.
D1
D2
D3
D4
D5
D6
D7
D8
E1
E2
E3
E4
E5
E6
E7
E8
I/O V
1
2
3
4
5
6
7
8
9
Input/Output 1. Referenced to V
Input/Output 2. Referenced to V
Input/Output 3. Referenced to V
Input/Output 4. Referenced to V
Input/Output 5. Referenced to V
Input/Output 6. Referenced to V
Input/Output 7. Referenced to V
Input/Output 8. Referenced to V
Input/Output 9. Referenced to V
.
.
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
I/O V
.
.
.
.
.
.
.
I/O V 10 Input/Output 10. Referenced to V
.
.
.
.
.
.
.
CC
CC
CC
CC
CC
CC
CC
CC
I/O V 11 Input/Output 11. Referenced to V
CC
I/O V 12 Input/Output 12. Referenced to V
CC
I/O V 13 Input/Output 13. Referenced to V
CC
I/O V 14 Input/Output 14. Referenced to V
CC
I/O V 15 Input/Output 15. Referenced to V
CC
I/O V 16 Input/Output 16. Referenced to V
CC
12
100Mbps, 16-Channel LLTs
The devices feature a programmable frequency input
Functional Diagram
(PF) that guarantees a bit rate of 100Mbps with a load
capacitance < 15pF and V > 1.1V (MAX14548E) or V >
L
L
V
V
CC
L
1.4V (MAX14548AE) when driven low. The MAX14548E
can drive capacitive loads up to 50pF with a guaranteed
bit rate of 40Mbps when V R1.1V and PF is driven high.
The MAX14548AE can drive capacitive loads up to 50pF
L
MAX14548E
MAX14548AE
with a guaranteed bit rate of 40Mbps when V R1.1V and
L
PF is driven high.
I/O V 1
I/O V
I/O V
1
2
L
CC
Level Translation
For proper operation, ensure that 1.7V P V
P 3.6V,
CC
1.1V P V P V . When power is supplied to V while
L
CC
L
V
CC
is less than V , the devices automatically enter a
low-power mode and the I/Os are in high-impedance
mode. The devices also enter shutdown mode when
L
I/O V 2
L
CC
EN = 0. In both conditions where EN = 0 or V > V
,
L
CC
there is a known high-impedance state on I/O V and
L_
I/O V . The maximum data rate depends heavily on
CC_
I/O V 15
L
I/O V 15
CC
the load capacitance (see the rise/fall time graphs in the
Typical Operating Characteristics), output impedance of
the driver, and the operating voltage range.
I/O V 16
L
I/O V 16
CC
Input Driver Requirements
The device architecture is based on an nMOS pass gate
and output accelerator stages (Figure 4). The accelera-
tors are active only when there is a rising/falling edge on
a given I/O. A short pulse is then generated where the
output accelerator stages become active and charge/
discharge the capacitances at the I/Os. Due to its archi-
tecture, both input stages become active during the
one-shot pulse. This can lead to some current feeding
into the external source that is driving the translator.
However, this behavior helps speed up the transition on
the driven side.
EN
PF
GND
Detailed Description
The MAX14548E/MAX14548AE 16-channel, bidirectional
level translators (LLTs) provide the level shifting neces-
sary for 100Mbps data transfer in multivoltage systems.
Externally applied voltages, V
levels on either side of the device. Logic signals present
on the V side of the device appear as a high-voltage
The devices have internal current sources capable of
sourcing 35FA to pull up the I/O lines. These internal
pullup current sources allow the inputs to be driven with
open-drain drivers and push-pull drivers. It is not recom-
mended to use external pullup resistors on the I/O lines.
The architecture of the devices permit either side to be
driven with a minimum of 4mA drivers or larger.
and V , set the logic
CC
L
L
logic signal on the V
side of the device and vice versa.
CC
The devices operate at full speed with external drivers
that source as little as 4mA output current (min). Each
I/O channel is pulled up to V
35FA current source, allowing the devices to be driven
by either push-pull or open-drain drivers.
or V by an internal
CC
L
Output Load Requirements
The device I/Os are designed to drive CMOS inputs.
Do not load the I/O lines with a resistive load less than
25kI and do not place an RC circuit at the input of
these devices to slow down the edges. If a slower rise/
fall time is required, refer to the MAX3000E/MAX3001E/
MAX3002–MAX3012 data sheet.
The devices feature an enable input (EN) that places the
device into a low-power shutdown mode when driven
low. They also feature an automatic shutdown mode that
disables the part when V
is less than V .
CC
L
13
100Mbps, 16-Channel LLTs
V
CC
V
L
ENABLE
ENABLE
ENABLE
30µA
30µA
I/O V
L_
I/O V
CC_
V
L
V
CC
BOOST
CIRCUIT
V
L
V
CC
BOOST
CIRCUIT
NOTE 1: THE MAX14548E/MAX14548AE ARE ENABLED WHEN V <
V
- 0.2V AND EN = V .
CC L
L
Figure 4. Simplified Functional Diagram for One I/O Line
Shutdown Mode
The EN input places the devices into a low-power shut-
down mode when driven low. The automatic shutdown
Applications Information
Layout Recommendations
Use standard high-speed layout practices when laying
out a board with the MAX14548E/MAX14548AE. For
example, to minimize line coupling, place all other signal
lines not connected to the devices at least 1x the sub-
strate height of the PCB away from the input and output
lines of the devices.
mode disables the devices when V
is unconnected or
CC
less than V . When V
is less than V or EN = GND, the
L
CC
L
devices enter shutdown mode.
Data Rate and Capacitive Load (PF Input)
The programmable frequency input (PF) adjusts the one-
shot accelerator to guarantee a 100Mbps bit rate with a
Power-Supply Decoupling
To reduce ripple and the chance of introducing data
load capacitance <15pF and V > 1.1V (MAX14548E)
L
or V > 1.4V (MAX14548AE) when driven low. The
L
errors, bypass V and V
to ground with 0.1FF ceramic
L
CC
MAX14548E can drive capacitive loads up to 50pF with
capacitors. Place all capacitors as close as possible to
the power-supply inputs. For full ESD protection, bypass
a guaranteed 40Mbps bit rate when V > 1.1V and PF
L
is driven high. The MAX14548AE can drive capacitive
loads up to 50pF with a guaranteed 40Mbps bit rate
V
CC
with a 1FF ceramic capacitor located as close as
possible to the V
input.
CC
when V > 1.1V and PF is driven high.
L
14
100Mbps, 16-Channel LLTs
R
C
R
D
1MΩ
1500Ω
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I 100%
P
90%
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPS
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 5a. Human Body ESD Test Model
Figure 5b. Human Body Current Waveform
Unidirectional vs. Bidirectional Level
Translator
The devices bidirectional level translators can operate as
a unidirectional device by selecting one I/O as the input
and the corresponding I/O as an output. These devices
provide the smallest solution (WLP package) for level
translation applications.
Use with External Pullup/Pulldown
Resistors
Due to the architecture of the devices, it is not recom-
mended to use external pullup or pulldown resistors
on the bus. In certain applications, the use of external
pullup or pulldown resistors is desired to have a known
bus state when there is no active driver on the bus. The
devices include internal pullup current sources that set
the bus state when the device is enabled. In shutdown
ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
mode, the state of I/O V
ance.
and I/O V is high imped-
CC_
L_
The I/O V and I/O V
against static electricity.
pins have extra protection
Open-Drain Signaling
L_
CC_
The devices are designed to pass open-drain as well
as CMOS push-pull signals. When used with open-drain
signaling, the rise time is dominated by the interaction
of the internal pullup current source and the parasitic
load capacitance. The devices include internal rise time
accelerators to speed up transitions, eliminating any
need for external pullup resistors. For applications such
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 5a shows the Human Body Model, and Figure
5b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the test device through a
1.5kI resistor.
2
M
as I C or 1-Wire that require an external pullup resistor,
refer to the MAX13046E and MAX13047E data sheets.
1-Wire is a registered trademark of Maxim Integrated
Products, Inc.
15
Typical Operating Circuit
+1.8V
+2.8V
1µF
0.1µF
1µF
V
L
V
CC
+1.8V
SYSTEM
+2.8V
SYSTEM
CONTROLLER
MAX14548A
MAX14548AE
PF
PF
EN
EN
I/O V
I/O V
CC_
DATA
DATA
L_
16
16
GND
GND
GND
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
40 WLP
W402B3+1
21-0437
100Mbps, 16-Channel LLTs
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
0
4/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
17
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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