MAX14550EETB+ [MAXIM]
SPST, 1 Func, 1 Channel, BICMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, TDFN-10;
| 型号： | MAX14550EETB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | SPST, 1 Func, 1 Channel, BICMOS, PDSO10, 3 X 3 MM, ROHS COMPLIANT, TDFN-10 信息通信管理 光电二极管 |
| 文件： | 总17页 (文件大小：1537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4745; Rev 2; 1/10
USB Host Charger Identification Analog Switch
General Description
Features
The MAX14550E is a USB Hi-Speed analog switch with
a USB host charger (dedicated charger) identification
circuit. The MAX14550E supports both the USB Battery
Charging Specification Revision 1.0 and a set resistor
S USB 2.0 Hi-Speed Switching
S Low 4.0pF On-Capacitance
S Low 4.0ω On-Resistance
M
bias for Apple -compliant devices.
S Ultra-Low 0.1ω On-Resistance Flatness
S +2.8V to +5.5V Supply Range
The MAX14550E features a high-performance Hi-Speed
USB switch with low 4pF (typ) on-capacitance and low
4I (typ) on-resistance. In addition, the MAX14550E
features two digital inputs (CB0 and CB1) to switch
between pass-through and charger modes. The USB
host charger identification circuit allows a host USB port
to support USB chargers with shorted D+/D- detection
and to provide support for Apple-compliant devices
using a resistor bias. When an Apple-compliant device
is attached to the port, the MAX14550E provides the
voltage from the resistor-divider. The MAX14550E uses
the internal or external resistor based on the voltage at
RDP. If a USB Revision 1.0-compliant device is attached,
the MAX14550E connects a short across DP and DM to
allow correct charger detection. The MAX14550E auto-
detection circuit can be disabled and either a DP/DM
short or resistor network is chosen as the default.
S Ultra-Low 7µA Supply Current
S Automatic USB Charger Identification Circuit
S Optional External Resistor-Divider with Auto
Selection
S
15ꢀV High ESD HBM Protection on DP/DM
S 3mm x 3mm, 10-Pin TDFN Pacꢀage
Applications
Laptops
Netbooks
Cell Phones
Ordering Information
The MAX14550E has enhanced high electrostatic dis-
charge (ESD) protection on the DP and DM inputs up to
Q15kV Human Body Model (HBM).
PIN-
PACKAGE MARK
-40NC to +85NC 10 TDFN-EP*
AWG
TOP
PART
TEMP RANGE
MAX14550EETB+
The MAX14550E is available in a 10-pin (3mm x 3mm)
TDFN package and is specified over the -40NC to +85NC
extended temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit appears at end of data sheet.
Apple is a registered trademark of Apple, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
USB Host Charger Identification Analog Switch
ABSOLUTE MAXIMUM RATINGS
CC
RDM, CB_ to GND ...............................................-0.3V to +6V
Continuous Current Into Any Terminal ........................... Q30mA
V
, DP, DM, TDP, TDM, RDP,
Operating Temperature Range.......................... -40NC to +85NC
Maximum Junction Temperature.....................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (Reflow) .......................................260NC
Continuous Power Dissipation (T = +70NC)
A
10-Pin TDFN (derate 24.4mW/NC above +70NC).......1951mW
Thermal Resistance (Note 1)
Junction-to-Ambient Thermal Resistance (B )...........41NC/W
JA
Junction-to-Case Thermal Resistance (B )..................9NC/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.8V to +5.5V, T = T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25NC, unless
CC A
A
J
otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
2.8
TYP
MAX
5.5
2
UNITS
Power-Supply Voltage
V
CC
V
V
V
= V
= V
0.7
6.5
CB0
CB
CC
= 0V, V
= V
10
CB0
CB
CC
External resistors used,
V
CB0
V
CB0
= V
= 0V or
7
12
CB
V
CC
= 3.3V
= V , V
= 0V
CC CB
Internal resistors used,
V
V
= V
= 0V or
76
120
CB0
CB0
CB
= V , V
= 0V
CC CB
Supply Current
I
FA
CC
V
V
= V
= V
CC
2.5
8.5
7
CB0
CB
= 0V, V
= V
15
CB0
CB
CC
External resistors used,
V
CB0
V
CB0
= V
= 0V or
9
16
CB
V
CC
= 5.5V
= V , V
= 0V
CC CB
Internal resistors used,
V
V
= V
= 0V or
125
180
2
CB0
CB0
CB
= V , V
= 0V
CC CB
Supply Current Increase
Analog Signal Range
ANALOG SWITCH
DI
0V PV
0V PV
PV or V PV
PV
FA
CC
CB_
IL
IH
CB_
CC
V
, V
DP DM
0
V
V
CC
On-Resistance TDP/TDM
Switch
R
PV , I or I = 10mA
DM
4
6.5
I
I
ONT
DP/DM
CC DP
On-Resistance Match
Between Channels TDP/TDM
Switch
DR
V
= V
= 400mV, I or I = 10mA
DM
0.1
ONT
DP
DM
DP
2
USB Host Charger Identification Analog Switch
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.8V to +5.5V, T = T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25NC, unless
CC A
A
J
otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
= V , 0V PV PV
MIN
TYP
MAX
UNITS
On-Resistance Flatness TDP/
TDM Switch
V
,
CC
DP
DM
DP
R
FLATT
0.1
I
I
= I
= 10mA
DP
DM
On-Resistance RDP/RDM
Switch
0.4V PV
10mA
PV , I
= I
RDM
=
RDP/RDM
CC RDP
R
4
7.5
I
I
I
ONR
On-Resistance Flatness RDP/
RDM Switch
V
RDP
= V
, 0.4V PV
PV
,
RDM
RDP
CC
R
0.1
50
FLATR
I
= I
= 10mA
RDP
RDM
On-Resistance of DP/DM
Short
V
= 0V, V
= V , V = V
,
CB0
CB
CC DP
DM
R
70
SHORT
0V PV PV , I = I = 1mA
DM
DP
CC DP
TDP/TDM Off-Leakage
Current
I
I
,
V
V
= 5.5V, V
= 5.5V to 0V, V
= V , V
= 0V, V
=
TDPOFF
CC
CB0
CC CB
DP
-250
-250
+250
+250
nA
nA
= V
= 0V to 5.5V
TDMOFF
DM
TDP
TDM
I
,
V
V
= 5.5V, V
= V
= V
,
DPON
CC
CB0
CB
CC
DP/DM On-Leakage Current
DYNAMIC PERFORMANCE
Turn-On Time
I
= V
= 5.5V to 0V
DMON
DP
DM
V
TDP
or V
= 1.5V, R = 300I,
TDM L
t
20
2.5
60
100
5
Fs
Fs
ps
ps
pF
ON
C = 35pF, V = V , V = 0V, Figure 1
L
IH
CC IL
V
TDP
or V
= 1.5V, R = 300I,
TDM L
Turn-Off Time
t
OFF
C = 35pF, V = V , V = 0V, Figure 1
L
IH
CC IL
TDP/TDM Switch Propagation
Delay
t
, t
R = R = 50I
L S
PLH PHL
Output Skew Between
Switches
Skew between DP and DM when connected
to TDP and TDM, R = R = 50I, Figure 2
t
40
SK(O)
L
S
f = 1MHz, V
(Note 3)
= 0V, V
= 500mV
BIAS
SIGNAL P-P
TDP/TDM Off-Capacitance
C
OFF
2.0
DP/DM On-Capacitance
(Connected to TD_ )
f = 240MHz, V
= 0V,
BIAS
C
4.0
1000
-20
5.5
pF
MHz
dB
ON
V
= 500mV
P-P
SIGNAL
-3dB Bandwidth
BW
R = R = 50I
L S
V
, V = 0dBm, R = R = 50I,
TDP DP L S
Off-Isolation
V
ISO
f = 250MHz, Figure 3
V
, V = 0dBm, R = R = 50I,
TDP DP
L
S
Crosstalk
V
CT
-25
dB
f = 250MHz, Figure 3
INTERNAL RESISTORS
DP/DM Short Pulldown
RP1/RP2 Ratio
R
350
500
1.5
700
1.515
156.25
0.872
116.25
kI
Ratio
kI
PD
RT
1.485
93.75
0.854
69.75
RP
RP1 + RP2 Resistance
RM1/RM2 Ratio
R
125
0.863
93
RP
RT
Ratio
kI
RM
RM
RM1 + RM2 Resistance
R
3
USB Host Charger Identification Analog Switch
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.8V to +5.5V, T = T = -40NC to +85NC, unless otherwise noted. Typical values are at V
= +3.3V, T = +25NC, unless
CC A
A
J
otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
> 0.4V, DM falling
MIN
TYP
MAX
UNITS
COMPARATORS
V
V
1.9
44
2.1
45
2.3
46
V
RDP
DM Comparator Threshold
V
DMF
< 0.3V, DM falling
%V
CC
RDP
DP and RDP Comparator
Threshold
V
DPR
DP or RDP falling
0.3
0.35
1
0.4
V
DM Comparator Hysteresis
%V
DMF
DPR
DP and RDP Comparator
Hysteresis
1
%V
DM Comparator Debounce
Time
t
V
V
from 2.8V to 1.5V
from 0.7V to 0V
30
30
100
100
200
200
Fs
DM
DM
DP Comparator Debounce
Time
t
Fs
DP
DP
DIGITAL I/O (CB0, CB1)
Input Logic Voltage High
Input Logic Voltage Low
Input Logic Hysteresis
V
1.4
V
V
IH
V
0.4
IL
V
100
mV
HYST
V
= 5.5V, 0V PV
PV or
CB_ IL
CC
Input Leakage Current
I
-250
+250
nA
IN
V PV
IH
PV
CC
CB_
ESD PROTECTION
All Pins
Human Body Model
Human Body Model
Q2
kV
kV
ESD Protection Level (DP and
DM Only)
Q15
Note 2: All devices are 100% production tested at T = +25NC. Specifications over temperature are guaranteed by design.
A
Note 3: Guaranteed by design.
Test Circuits/Timing Diagrams
V
CC
V
t
t
< 5ns
< 5ns
R
F
IH
LOGIC
INPUT
CB1
V
CC
50%
V
IL
D_
TD_
CB0
V
IN
V
OUT
t
OFF
R
L
C
L
LOGIC
INPUT
V
t
OUT
ON
MAX14550E
0.9 x V
OUT
0.9 x V
0UT
GND
SWITCH
OUTPUT
0V
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
L
R
L
V
= V
IN (
OUT
)
R + R
L
ON
Figure 1. Switching Time
4
USB Host Charger Identification Analog Switch
Test Circuits/Timing Diagrams (continued)
RISE TIME DELAY = |t
- t
|
INRISE OUTRISE
MAX14550E
FALL TIME DELAY = |t
- t
|
INFALL OUTFALL
R
R
S
S
TDP
DP
RISE TIME TO FALL TIME MISMATCH = |t
- t
|
OUTFALL OUTRISE
IN+
IN-
OUT+
OUT-
C
C
L
L
TDM
DM
V
CC
CB0
CB1
V
CC
t
INFALL
t
INRISE
10%
V
V
CC
90%
90%
V
IN+
50%
50%
10%
0V
CC
V
IN-
0V
CC
t
OUTFALL
t
OUTRISE
V
V
90%
90%
V
50%
50%
OUT+
10%
10%
0V
CC
V
OUT-
0V
t
SK(0)
Figure 2. Output Signal Skew
5
USB Host Charger Identification Analog Switch
Test Circuits/Timing Diagrams (continued)
V
OUT
V
V
CC
CC
OFF-ISOLATION = 20log
CROSSTALK = 20log
NETWORK
ANALYZER
V
IN
V
OUT
50I
50I
V
V
CB0
IN
V
0V OR V
IN
CB1
TDP
DP*
CC
MAX14550E
MEAS
REF
OUT
50I
50I
SWITCH IS ENABLED.
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
*FOR CROSSTALK, THIS PIN IS DM.
TDM AND DP ARE OPEN.
OFF-ISOLATION IS MEASURED BETWEEN TD_ AND "OFF" D_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 3. Off-Isolation and Crosstalk
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
RDP/RDM ON-RESISTANCE
vs. SUPPLY VOLTAGE
TDP/TDM ON-RESISTANCE
vs. SUPPLY VOLTAGE
TDP/TDM ON-RESISTANCE vs. V
TDP/TDM
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
V
= 2.8V
V
= 3.3V
CC
CC
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 2.8V
CC
T
T
= +85°C
= +25°C
A
A
V
= 5.5V
CC
T
= -40°C
V
= 5.5V
A
CC
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
(V)
V
V
V
TDP
RDP
TDP/TDM
6
USB Host Charger Identification Analog Switch
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
TDP/DP LEAKAGE CURRENT
vs. TEMPERATURE
RDP/RDM ON-RESISTANCE vs. V
RDP/RDM
10
9
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
T
= +85°C
A
ON-LEAKAGE
T
T
= +85°C
= +25°C
= -40°C
A
T
A
= +25°C
A
T
A
= -40°C
T
A
V
CB0
V
CB1
V
RDP
= V
CC
= 0V
= V
OFF-LEAKAGE
V
= 3.3V
CC
CC
2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
(V)
-45 -30 -15
0
15 30 45 60 75 90
V
V
TEMPERATURE (°C)
CC
RDP/RDM
TURN-ON/TURN-OFF TIME
vs. SUPPLY VOLTAGE
LOGIC-INPUT THRESHOLD
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. LOGIC LEVEL
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
250
200
150
100
50
16
14
12
10
8
CB_ RISING
INTERNAL RESISTOR-
DIVIDER
t
ON
CB_ FALLING
6
EXTERNAL RESISTOR-
DIVIDER
t
OFF
4
2
0
0
2.8 3.1 3.4 3.7 4.0 4.3 4.6 4.9 5.2 5.5
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
LOGIC LEVEL (V)
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
(V)
V
(V)
V
CC
CC
EYE DIAGRAM
FREQUENCY RESPONSE
MAX14550E toc11
0
-10
-20
-30
-40
-50
-60
-70
-80
0.5
0.4
ON-LOSS
0.3
0.2
0.1
OFF-ISOLATION
CROSSTALK
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1
10
100
1000
n
TIME (x 10 - 9)s
FREQUENCY (MHz)
7
USB Host Charger Identification Analog Switch
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DP RISING
DP RISING
AUTODETECTION MODE
MAX14550E toc13
MAX14550E toc14
MAX14550E toc12
V
= 2.8V, R = 300I, C = 35pF
V
= 4V, R = 300I, C = 35pF
CC
L
L
CC
L
L
DM
500mV/div
DP
500mV/div
0V
INTERNAL RESISTOR-
DIVIDERS ENABLED
4µs/div
4µs/div
100µs/div
Pin Configuration
TOP VIEW
+
CB0
DP
1
10 CB1
TDP
2
3
4
5
9
8
7
6
DM
TDM
MAX14550E
GND
RDP
V
CC
*EP
RDM
TDFN
(3mm × 3mm)
*CONNECT EP TO GND.
Pin Description
PIN
1
NAME
CB0
DP
FUNCTION
Switch Control Bit 0. See the Switch Control section.
USB Connector D+ Connection
USB Connector D- Connection
Ground
2
3
DM
4
GND
RDP
RDM
5
External Resistor Bias Input for D+ and Selection for External Resistors in RDP and RDM
External Resistor Bias Input for D-
6
7
V
Power Supply. Bypass V to GND through a 0.1FF capacitor. Place the capacitor as close as possible to the device.
CC
CC
8
TDM
TDP
CB1
EP
USB Transceiver D- Connection
9
USB Transceiver D+ Connection
10
—
Switch Control Bit 1. See the Switch Control section.
Exposed Pad. Connect EP to GND. Do not use EP as the main ground connection.
8
USB Host Charger Identification Analog Switch
Functional Diagram
V
TDM
TDP
V
CC
CC_SW
RP1
RP2
DP
RDP
V
CC_SW
ESD
PROTECTION
MAX14550E
RM1
RM2
DM
RDM
0.4V
500kI
0.4V
R
S
CONTROL
LOGIC
Q
2.1V
GND
CBO
CB1
Connect RDP to a voltage above 0.4V (max) to use
external resistors (Figure 4). Internal resistor-dividers are
always disconnected from the supply voltage when exter-
Detailed Description
The MAX14550E is a combination of a Hi-Speed USB
analog switch and a charger host identification detec-
tion analog switch, which allows USB hosts to identify
the USB port as a charger port when the USB host is in
a low-power mode and cannot enumerate USB devices.
The MAX14550E features a high-performance, Hi-Speed
USB switch with low 4pF on-capacitance and low 4Ion-
resistance. DP and DM can survive signals between 0V
and 6V with any supply voltage.
nal resistor-dividers are detected at RDP (V
> 0.4V).
RDP
Switch Control
The MAX14550E features two digital inputs, CB0 and
CB1, for mode selection (Table 1). Connect CB0 and
CB1 to a logic-level low voltage for autodetection mode
(see the Autodetection section).
Connect CB0 and CB1 to a logic-level high voltage for
normal Hi-Speed USB bypass functionality.
Resistor-Dividers
The MAX14550E features an internal resistor-divider for
biasing or can operate with external resistors. Connect
RDP to ground to use the internal resistor-divider (see
the Typical Operating Circuit). The user must provide 5V
when the internal resistor-divider
is used. When the MAX14550E is not operated with the
internal resistor-dividers, the device disconnects the
Connect CB0 to a logic-level low and CB1 to a logic-level
high voltage to select charger mode. Optionally, CB0
and CB1 can be forced to set the detection to a par-
ticular state. The USB Implementers Forum (USB-IF) has
defined that dedicated chargers have D+ and D- shorted
together. In USB charger mode, DP and DM are shorted
together for dedicated charging functionality. Connect
CB0 to a logic-level high and CB1 to a logic-level low
voltage to force the resistor network to be connected to
DP and DM.
supply voltage to V
CC
internal resistor-dividers’ pullup voltage (V
minimize supply current requirements.
) to
CC_SW
9
USB Host Charger Identification Analog Switch
3.3V TO 5.0V
USB
TRANSCEIVER
0.1µF
D-
D+
V
CC
TDM
TDP
V
CC_SW
5.0V
RP1
RP2
75kI
DP
D+
RDP
V
CC_SW
49.9kI
USB
CONNECTOR
ESD
PROTECTION
MAX14550E
RM1
RM2
43.2kI
49.9kI
DM
D-
RDM
0.4V
500kI
0.4V
R
S
CB0 AND CB1
00 - AUTO MODE
01 - FORCE SHORT
10 - FORCE RESISTOR
11 - TDP = DP, TDM = DM
CONTROL
LOGIC
Q
2.1V
GND
CBO
CB1
Figure 4. Operation with External Resistors
age at DM > 0.35V (typ), the short remains connected. If
the voltage at DM drops below 0.35V (typ), the short is
removed and the resistor network is reconnected to DP
and DM.
Autodetection
The MAX14550E features autodetection mode for dedi-
cated chargers and USB masters. CB0 and CB1 must
both be set low to activate autodetection mode.
DP and DM feature a 100Fs (typ) debounce time to reject
transients.
In autodetection mode, the MAX14550E initially connects
the resistor network to DP and DM. The MAX14550E
monitors the voltage at DM to determine the type of
device attached. If the voltage at DM is 2.1V (typ) or
higher, the voltage stays as is.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
If the voltage at DM is below the 2.1V (typ) threshold,
the internal switch disconnects DP from the resistor
network and DM. DP and DM are shorted together. The
MAX14550E then monitors the voltage at DM to deter-
mine when to reconnect the resistor network. If the volt-
The Air-Gap test involves approaching the device with a
charged probe. The Contact-Discharge method connects
the probe to the device before the probe is energized.
10
USB Host Charger Identification Analog Switch
Table 1. Digital Input States
INTERNAL OR
RDP
EXTERNAL
RESISTOR
CONNECTED TO
DP/DM
V
(V)
DP/DM
POSITION
CC
< 0.4V = INTERNAL RESISTOR
> 0.4V = EXTERNAL RESISTOR
CB0
CB1
COMMENT
3.3
RDP < 0.4V
RDP > 0.4V
X
0
X
0
—
—
Not recommended
Auto mode
Autodetection
circuit active
External resistor
Auto mode
disabled
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Shorted
Not connected
External resistor
Not connected
Internal resistor
Not connected
Internal resistor
Not connected
External resistor
Not connected
External resistor
Not connected
3.3
Connected to
resistor-divider
Auto mode
disabled
Connected to
TDP/TDM
USB traffic active
Auto mode
Autodetection
circuit active
Auto mode
disabled
Shorted
RDP < 0.4V
Connected to
resistor-divider
Auto mode
disabled
Connected to
TDP/TDM
USB traffic active
Auto mode
5.0
Autodetection
circuit active
Auto mode
disabled
Shorted
RDP > 0.4V
Connected to
resistor-divider
Auto mode
disabled
Connected to
TDP/TDM
USB traffic active
11
USB Host Charger Identification Analog Switch
up to Q15kV (Human Body Model) without damage. The
ESD structures withstand high ESD both in normal opera-
tion and when the device is powered down. After an ESD
event, the device continues to function without latchup
(Figures 5a and 5b).
Extended ESD Protection
(Human Body Model)
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges up to Q2kV
(Human Body Model) encountered during handling and
assembly. DP and DM are further protected against ESD
Table 2. Tested Portable Device
MANUFACTURER/
SPECIFICATION
MAX14550E
DETECTION METHOD/COMMENTS
SUPPORT
DEVICE
IDENTIFICATION
iPhone 2G, 3G, and
3GS; iPod classic®;
iPod video; iPod
touch (1st and 2nd
generations);
iPod®andsome
iPhones®
Immediately draws 500mA when 5V is
None
attached to V
BUS
Apple
iPod nano® (3rd,
4th, 5th generation);
and iPod mini
USB FS/HS configuration: draws
< 500mA
D+/D- voltage detection: <1A
iPod touch®
and iPhone 3G
Resistor-divider on
D+ and D-
USB FS/HS configuration: draws
< 500mA. Follows CEA-936-A
specification, which is the only known
company to use this specification.
All phones with
mini-USB
Resistor to GND on
ID line
Motorola
Depends on model
USB FS/HS configuration: draws
Some models look for < 500mA. Some models look for
RIM
BlackBerry®
Depends on model
Full support
shorted D+/D-
shorted D+/D- with a pullup to 2.7V for
dedicated charger.
QUALCOMM®-
based phones
Immediately draws 500mA when 5V is
HTC
None
attached to V
BUS
2009 and newer
LG and Samsung
models with micro-
USB connector
Device uses a specific method
(voltages and timing well defined)
USB-IF Standard
China Standard
—
—
Shorted D+/D-
Shorted D+/D-
Method not defined
Depends on model
iPod, iPhone, iPod touch, iPod classic, and iPod nano are registered trademarks of Apple, Inc.
BlackBerry is a registered trademark/servicemark of Research In Motion Limited.
QUALCOMM is a registered trademark of QUALCOMM Incorporated.
12
USB Host Charger Identification Analog Switch
R
D
R
C
1500Ω
1MΩ
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
S
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 5b. Human Body Current Waveform
Figure 5a. Human Body ESD Test Model
Timing Charts
5V
V
BUS
HOST
SW
S0
PT
S3
AT
S0
S3
S0
PT
PT
AT
iPod ATTACH IN S0
USB CONNECTION
ATTACH
DETACH
ATTACH
≤ 100mA
≤ 1000mA
≤ 100mA
≤ 500mA
≤ 500mA
≤ 500mA
CHARGING CURRENT
5V
V
BUS
HOST
SW
S3
AT
S0
PT
S3
AT
S0
S3
AT
S0
PT
PT
iPod ATTACH IN S3
USB CONNECTION
ATTACH
≤ 100mA
≤ 1000mA
≤ 1000mA
≤ 500mA
≤ 1000mA
≤ 500mA
CHARGING CURRENT
NOTE: WHEN USING THIS TIMING, IT IS RECOMMENDED TO SUPPLY V WITH V , AND V
SHOULD BE IMMEDIATELY DISCHARGED WHEN V
IS TURNED OFF.
CC
BUS
BUS
BUS
13
USB Host Charger Identification Analog Switch
Timing Charts (continued)
S0 TO S3 TRANSITION
5V
V
BUS
HOST
SW
S0
PT
S3
S0
S3
AT
PT
AT
iPod ATTACH IN S3
USB CONNECTION
ATTACH
CHARGING CURRENT
≤ 500mA
≤ 1000mA
≤ 500mA
≤ 1000mA
5V
5V
4.0V
0.8V
V
BUS
0.8V
> 0.5s
< 3s
HOST
SW
S0
S3
< 1ms
14
USB Host Charger Identification Analog Switch
Timing Charts (continued)
S3 TO S0 TRANSITION
5V
V
BUS
HOST
S0
PT
S3
S0
S3
AT
PT
AT
SW
iPod ATTACH IN S3
USB CONNECTION
ATTACH
CHARGING CURRENT
≤ 500mA
≤ 1000mA
≤ 500mA
≤ 1000mA
5V
5V
4.0V
0.8V
4.0V
V
BUS
0.8V
>0.5s
<3s
HOST
SW
S3
S0
t
FALL TO 4.0V
t
< t
AT TO PT FALL TO 4.0V
t
AT TO PT
AT
PT
NOTE: THIS TIMING IS TO AVOID THE VOLTAGE FROM THE RESISTOR-DIVIDER FROM APPEARING ON DP/DM WHILE V
GROUNDED BY 15kΩ.
IS OFF BY SWITCHING DP/DM TO TDP/TDM, WHICH IS
BUS
15
Typical Operating Circuit
5.0V
USB
TRANSCEIVER
0.1µF
D-
D+
V
CC
TDM
TDP
V
V
CC_SW
RP1
RP2
DP
D+
RDP
CC_SW
USB
CONNECTOR
ESD
PROTECTION
MAX14550E
RM1
RM2
DM
D-
RDM
0.4V
500kI
0.4V
R
S
CONTROL
LOGIC
Q
2.1V
GND
CBO
CB1
LOW = AUTO MODE (LAPTOP IN
SLEEP/STANDBY)
MICROCONTROLLER
HIGH = TDP = DP, TDM = DM
(LAPTOP AWAKE - USB ACTIVE)
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/pacꢀages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 TDFN-EP
T1033+1
21-0137
USB Host Charger Identification Analog Switch
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
8/09
Initial release.
—
• Replaced the Lead Temperature with Soldering Temperature in the Absolute
Maximum Ratings section.
• Changed the “DP/DM On-Capacitance” specification in the Electrical Characteristics
table conditions from f = 1MHz to f = 240MHz and 6.0pF (max) to 5.5pF (max).
• Replaced TOC11 (Eye Diagram) in the Typical Operating Characteristics section.
• Replaced Table 1 and added Table 2.
2, 3, 7, 11,
12, 13
1
2
11/09
1/10
• Added the Timing Chart.
Replaced the timing diagrams in Timing Charts.
13, 14,15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
17
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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