MAX14693ATP+ [MAXIM]
Buffer/Inverter Based Peripheral Driver,;
| 型号： | MAX14693ATP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Buffer/Inverter Based Peripheral Driver, 驱动 信息通信管理 接口集成电路 |
| 文件： | 总19页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
General Description
Benefits and Features
● Robust, High-Power Protection Reduces System
The MAX14691–MAX14693 adjustable overvoltage,
undervoltage, and overcurrent protection devices guard
systems against overcurrent faults in addition to positive
overvoltage and reverse-voltage faults. When used with
an optional external pMOSFET, the devices also protect
downstream circuitry from voltage faults up to +58V, -60V
(for -60V external pFET rating). The devices feature a low,
31mΩ, on-resistance integrated FET.
Downtime
• Wide Operating Input Range: +5.5V to +58V
• -60V Negative Input Tolerance (for -60V External
pFET Rating
• Low 31mΩ (typ) R
ON
• Reverse Current-Blocking Protection with External
pFET
● Enables Fast Startup and Brownout Recovery
• Thermal Foldback Current-Limit Protection
• Dual-Stage Current Limiting
- 1.0x Startup Current (MAX14691)
- 1.5x Startup Current (MAX14692)
- 2.0x Startup Current (MAX14693)
● Flexible Design Enables Reuse and Less
Requalification
During startup, the devices are designed to charge large
capacitances on the output in a continuous mode for
applications where large reservoir capacitors are used
on the inputs to downstream devices. Additionally, the
devices feature a dual-stage, current-limit mode in which
the current is continuously limited to 1x, 1.5x, and 2x
the programmed limit, respectively, for a short time after
startup. This enables faster charging of large loads during
startup.
The MAX14691–MAX14693 also feature reverse-current
and overtemperature protection. The devices are available
in a 20-pin (5mm x 5mm) TQFN package and operate
over the -40°C to 125°C temperature range.
• Adjustable OVLO and UVLO Thresholds
• Programmable Forward Current Limit From 0.6A
to 6A with ±15% Accuracy Over Full Temperature
Range
• Normal and High-Voltage Enable Inputs
(EN and HVEN)
Applications
• Protected External pFET Gate Drive
● Saves Board Space and Reduces External BOM
Count
● Industrial Power Systems
● Control and Automation
● Motion System Drives
● Human Machine Interfaces
● High-Power Applications
• 20-Pin 5mm x 5mm TQFN Package
• Integrated nFET
Ordering Information appears at end of data sheet.
Typical Application Circuit
VIN
*R1, R2, R3, AND R4 ARE ONLY
CIN
REQURED FOR ADJUSTABLE
UVLO/OVLO FUNCTIONALITY.
OTHERWISE, TIE THE PIN TO
GND TO USE THE INTERNA,L
PRE-PROGRAMMED
CIN_IC
GP
IN
IN IN IN IN
OUT
VIN
R1*
R3*
SYSTEM
UVLO
POWER
THRESHOLD.
CONTROLLER
OUT
OUT
PROTECTED
POWER
220kΩ
R2*
R4*
SYSTEM
INPUT
ADC
MAX14691–
MAX14693
COUT
VIN
OUT
OVLO
HVEN
OUT
SETI
RIPEN
FLAG
EN
GND
ENB
FAULT
EN
HVEN
x
CLTS2
10kΩ
CLTS1
GND
19-7403; Rev 2; 5/15
MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Absolute Maximum Ratings
(All voltages referenced to GND.)
SETI...............................................-0.3V to min (V + 0.3V, 6V)
IN
IN (Note 1).............................................................-0.3V to +58V
Continuous Power Dissipation (T = +70°C)
A
OUT..............................................................-0.3V to V + 0.3V
TQFN (derate 34.5mW/°C above +70°C)..................2758mW
Operating Temperature Range......................... -40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65ºC to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
IN
HVEN (Note 1) .............................................-0.3V to V + 0.3V
IN
GP .....................................max (-0.3V, V - 20V) to V + 0.3V
IN
IN
UVLO, OVLO...............................-0.3V to min (V + 0.3V, 20V)
IN
FLAG, EN, RIPEN, CLTS1, CLTS2.........................-0.3V to +6V
Maximum Current into IN (DC) (Note 2) .................................6A
Note 1: An external pFET or diode is required to achieve negative input protection.
Note 2: DC current-limited by R , as well as by thermal design.
SETI
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 3)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ )...........29°C/W
Junction-to-Case Thermal Resistance (θ ).................2°C/W
JC
JA
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V = 5.5V to 58V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 12V, T = +25°C) (Note 4)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
IN Voltage Range
V
5.5
58
7
V
IN
V
V
V
V
= 0V, V
= 0V, V
= 5V, V < 24V
4
4
EN
HVEN
IN
Shutdown IN Current
I
µA
SHDN
= 5V, V < 40V
10
1.9
100
EN
HVEN
IN
Supply Current
I
= V
= 24V, V = 0V
HVEN
1.4
50
mA
µA
IN
IN
OUT
Shutdown OUT Current
UVLO, OVLO
I
= 0V, V
= 5V
OFF
EN
HVEN
V
V
falling, UVLO trip point
rising
11.5
11.9
12
12.4
3
12.5
13
IN
Internal UVLO Trip Level
UVLO Hysteresis
V
V
%
V
UVLO
IN
% of typical UVLO
V
V
falling
32.2
34.7
34.1
36.2
6
35.8
37.6
IN
Internal OVLO Trip Level
V
OVLO
rising, OVLO trip point
IN
OVLO Hysteresis
% of typical OVLO
%
V
External UVLO Adjustment
Range (Note 5)
5.5
24
0.5
External UVLO Select Voltage
V
0.15
-250
0.38
0.38
V
UVLO_SEL
External UVLO Leakage
Current
I
+250
nA
UVLO_LEAK
External OVLO Adjustment
Range (Note 5)
6
40
V
V
External OVLO Select Voltage
V
0.15
0.5
OVLO_SEL
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Electrical Characteristics (continued)
(V = 5.5V to 58V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 12V, T = +25°C) (Note 4)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
External OVLO Leakage
Current
I
-250
1.18
+250
nA
OVLO_LEAK
External UVLO/OVLO Set
Voltage
V
1.22
1.27
V
V
SET
V
V
falling, UVLO trip point
rising
11.5
11.9
12
12.5
13
OUT
Undervoltage Trip Level on OUT
V
UVLO_OUT
12.4
OUT
GP
Gate Clamp Voltage
V
10
47
16.1
25
20
50
V
Ω
GP
Gate Active Pullup
Gate Active Pulldown
V
= 5V
100
2.4
µA
MΩ
EN
Shutdown Gate Active Pullup
VEN = 0V, V
= 5V
HVEN
INTERNAL FETs
I
T
= 100mA, V ≥ 10V,
IN
= +25°C
LOAD
Internal FETs On-Resistance
R
31
42
mΩ
ON
A
Current Limit Adjustment Range
I
0.6
-10
-15
6
A
LIM
1A ≤ I
≤ 6A (T = +25°C)
+10
+15
LIM
A
Current Limit Accuracy
I
%
LIM_ACC
0.6A ≤ I
≤ 6A
LIM
FLAG Assertion Drop Voltage
Threshold
Increase in (V - V
FLAG asserts, V = 24V
IN
) drop until
IN
OUT
V
490
-10
mV
mV
FA
Reverse Current-Blocking
Threshold
V
V
– V
OUT
0
-16
1.5
RIB
IN
(V – V
) changes from 0.2V to
IN
OUT
Reverse Current-Blocking
Response Time
-0.3V in 100nsec, t
is the interval
RIB
t
1
µs
RIB
between V = V
and V - GP =
IN
OUT
IN
0.5V without capacitive load on GP
Reverse-Blocking Supply
Current
I
V
= 24V
2460
4060
µA
RBS
OUT
LOGIC INPUT (HVEN, CLTS1, CLTS2, EN, RIPEN)
HVEN Threshold Voltage
HVEN Threshold Hysteresis
HVEN Input Leakage Current
V
1
2
5
3.1
66
V
%
HVEN _TH
I
V
= 58V
42
µA
HVEN_LEAK
HVEN
EN, RIPEN, CLTS1, CLTS2
Input Logic-High
V
1.4
V
V
IH
EN, RIPEN, CLTS1, CLTS2
Input Logic-Low
V
0.4
+1
IL
,
EN_LEAK
EN, RIPEN Input Leakage
Current
I
V
, V
= 0V, 5V
-1
µA
µA
EN RIPEN
I
RIPEN_LEAK
CLTS_ Leakage Current
LOGIC OUTPUT (FLAG)
Logic-Low Voltage
CLTS_ = GND
25
I
= 1mA
0.4
1
V
SINK
Input Leakage Current
V
= 5.5V, FLAG deasserted
µA
IN
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Electrical Characteristics (continued)
(V = 5.5V to 58V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V = 12V, T = +25°C) (Note 4)
IN
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SETI
R
x I
V
1.5
V
See Setting the Current-Limit
Threshold section
SETI LIM
RI
Current Mirror Output Ratio
C
25000
IRATIO
DYNAMIC PERFORMANCE (NOTE 6)
V
= 24V, switch OFF to ON, R
LOAD
IN
Switch Turn-On Time
t
= 240Ω, I
= 1A, C = 4.7µF,
68
µs
µs
ON
LIM
OUT
V
from 20% to 80% of V
IN
OUT
Fault Recovery NFET Turn-On
Time
V
> V
, turn-on delay
OUT
UVLO_OUT
t
420
770
ON_NFET
after fault timers expired
Reverse-Current Fault
Recovery Time
t
t
2.18
2.4
3
2.64
ms
µs
µs
REV_REC
OVP_RES
OCP_RES
OVP Switch Response Time
Overcurrent Switch Response
time
t
I
= 4A
3
LIM
Initial start current-limit foldback
timeout (Figure 1)
Startup Timeout
t
1090
21.8
1
1200
24
1320
26.4
2.1
ms
ms
ms
STO
Current is continuously limited to
1x/1.5x/2x in this interval (Figure 1)
Startup Initial Time
IN Debounce Time
t
STI
Interval between V > V
and
IN
UVLO
t
1.5
DEB
V
= 10% of V (Figure 2)
IN
OUT
Blanking Time
t
(Figures 3 and 4)
(Figure 3, Note 7)
21.8
554
24
26.4
792
ms
ms
BLANK
Autoretry Time
t
720
RETRY
THERMAL PROTECTION
Thermal Foldback
T
150
165
10
°C
°C
°C
J_FB
Thermal Shutdown
Thermal Shutdown Hysteresis
T
J_MAX
Note 4: All devices are 100% production-tested at T = +25ºC. Specifications over the operating temperature range are guaranteed
A
by design.
Note 5: Not production-tested, user-adjustable. See the Overvoltage Lockout (OVLO) and Undervoltage Lockout (UVLO) sections.
Note 6: All timing is measured using 20% and 80% levels, unless otherwise specified.
Note 7: The autoretry time-to-blanking time ratio is fixed and is equal to 30.
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Timing Diagrams
tDEB
tSTI
tSTO*
OVLO
UVLO
IN
1x /1.5x /2x I LIMIT
ILIMIT
IOUT
VIN
OUT
GND
THERMALLY-CONTROLLED
CURRENT FOLDBACK
TJMAX
TJ
NOT DRAWN TO SCALE
*IF OUT DOES NOT REACH VIN - VFA WITHIN t STO, THE DEVICE IS LATCHED OFF, AND EN, HVEN, OR IN MUST BE TOGGLED TO RESUME NORMAL
OPERATION .
Figure 1. Startup Timing
< tDEB
< tDEB
tDEB
OVLO
IN UVLO
ON
SWITCH
STATUS
OFF
NOT DRAWN TO SCALE
Figure 2. Debounce Timing
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
HVEN INPUT CURRENT
QUIESCENT IN CURRENT
vs. IN VOLTAGE
QUIESCENT IN CURRENT
vs. TEMPERATURE
vs. VHVEN
toc01
toc02
toc03
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
100
90
80
70
60
50
40
30
20
10
0
VEN = 3V
IN = VHVEN
VEN = 3V
VEN = 3V
V
VIN = 34V
VIN = 24V
VIN = 12V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
11.6
23.2
34.8
46.4
58.0
5.5 13.0 20.5 28.0 35.5 43.0 50.5 58.0
IN VOLTAGE (V)
-50 -25
0
25
50
75 100 125 150
V/HVEN\ (V)
TEMPERATURE (°C)
NORMALIZED ON-RESISTANCE
vs. TEMPERATURE
NORMALIZED ON-RESISTANCE
vs. SUPPLY VOLTAGE
toc05
toc04
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.10
1.05
1.00
0.95
0.90
NORMALIZED TO VIN = 12V
IOUT = 1A
EN = 3V
NORMALIZED TO TA = +25°C
IOUT = 1A
IN = 24V
EN = 3V
V
V
V
-50
0
50
100
150
5.5 13.0 20.5 28.0 35.5 43.0 50.5 58.0
IN VOLTAGE (V)
TEMPERATURE (°C)
NORMALIZED ON-RESISTANCE
NORMALIZED CURRENT LIMIT
vs. SUPPLY VOLTAGE
vs. OUTPUT CURRENT
toc06
toc07
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.03
1.02
1.01
1.00
0.99
0.98
0.97
NORMALIZED TO IOUT = 1A
VIN = 24V
NORMALIZED TO VIN = 12V
ILIM = 37.5kΩ
R
V
EN = 3V
0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0
OUTPUT CURRENT (A)
5.5 13.0 20.5 28.0 35.5 43.0 50.5 58.0
SUPPLY VOLTAGE (V)
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics (continued)
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
NORMALIZED CURRENT LIMIT
vs. TEMPERATURE
SHUTDOWN OUTPUT CURRENT
vs. TEMPERATURE
toc10
SHUTDOWN IN CURRENT
vs. TEMPERATURE
toc08
toc09
1.03
1.02
1.01
1.00
0.99
0.98
0.97
12
10
8
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
NORMALIZED TO TA = +25°C
IN = 24V
ILIM = 37.5kΩ
V
R
58VIN
VIN = +36V
VIN = +24V
VIN = +12V
6
34VIN
24VIN
4
12VIN
2
5.5VIN
0
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SWITCH TURN-ON TIME
vs. TEMPERATURE
SWITCH TURN-OFF TIME
vs. TEMPERATURE
toc11
toc12
200
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
MAX14691
VIN = +24V
RL = 240Ω
CL = 4.7µF
VIN = +24V
RL = 240Ω
CL = 4.7µF
180
160
140
120
100
80
60
40
20
0
-50 -25
0
25
50
75 100 125 150
-50 -25
0
25
50
75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
POWER-UP RESPONSE
REVERSE-BLOCKING RESPONSE
toc13
toc14
24V
20V/div
20V/div
20V/div
VIN
0V
30V
VOUT
24V
VOUT
20V/div
1A/div
0V
IOUT
100mA/div
IOUT
CL = 34mF
ILIM = 1A
VRIPEN = 3V
MAX14692
400µs/div
200ms/div
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Typical Operating Characteristics
(V = 12V, C = 1µF, C
= 4.7µF, T = +25°C, unless otherwise noted.)
A
IN
IN
OUT
CURRENT-LIMIT RESPONSE
FLAG RESPONSE
toc16
toc15
20V/div
20V/div
20V/div
5V/div
VIN
VIN
0V
0V
0V
VOUT
20V/div
1A/div
VOUT
0V
IOUT
VFLAG
ILIM = 1A
IL = 100mA TO SUDDEN SHORT APPLIED
10ms/div
4µs/div
CURRENT-LIMIT RESPONSE
BLANKING TIME
toc17
toc18
AUTORETRY MODE
MAX14693
20V/div
VIN
0V
0V
VOUT
20V/div
1A/div
5V/div
VOUT
IOUT
ILIM = 1A
IL = 100mA TO SHORT ON OUT WITH 1A/s
20ms/div
200ms/div
AUTORETRY TIME
AUTORETRY MODE
toc19
MAX14693
5V/div
VOUT
200ms/div
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Pin Configurations
TOP VIEW
15
14
13
12
11
16
17
18
19
20
10
9
UVLO
OVLO
RIPEN
HVEN
CLTS2
CLTS1
MAX14691–
MAX14693
8
FLAG
7
SETI
6
GND/EP
GP
EN
+
1
2
3
4
5
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
FUNCTION
Switch Input. Bypass IN to ground with a 1µF ceramic capacitor for ±15kV Human Body Model
ESD protection on IN. In applications in which an external pFET is used, a 4.7µF capacitor should
be placed at the drain of the pFET and a reduced capacitor of 10nF to 100nF should be placed at
IN. The maximum slew rate allowed at IN is 30V/µs. IN serves as the under/overvoltage sensed
input when preprogrammed UVLO/OVLO is used.
1–5
IN
6
7
GP
Gate Driver Output for External pFET.
Overload Current-Limit Adjust. Connect a resistor from SETI to GND to program the overcurrent
limit. SETI must be connected to a resistor. If SETI is connected to GND during startup, then the
switch does not turn on. Do not connect more than 30pF to SETI.
SETI
Open Drain Fault Indicator Output. FLAG asserts low when the V - V
voltage exceeds
IN
OUT
8
9
FLAG
OVLO
UVLO
V
, reverse current is detected, thermal shutdown mode is active, OVLO or UVLO threshold is
FA
reached, or SETI is connected to GND.
Externally-Programmable Overvoltage-Lockout Threshold. Connect OVLO to GND to use the
default internal OVLO threshold. Connect OVLO to an external resistor-divider to define a
threshold externally and override the preset internal OVLO threshold.
Externally Programmable Undervoltage-Lockout Threshold. Connect UVLO to GND to use the
default internal UVLO threshold. Connect UVLO to an external resistor-divider to define a threshold
externally and override the preset internal UVLO threshold.
10
Switch Output. Bypass OUT to GND with a 4.7µF ceramic capacitor placed as close as possible to
the device.
11–15
16
OUT
Reverse-Current Protection Enable. Connect RIPEN to GND to disable the reverse-current flow
protection. Connect RIPEN to logic-high to activate the reverse-current flow protection.
58V Capable Active-Low Enable Input. See Table 1.
RIPEN
17
18
19
20
—
HVEN
CLTS2
CLTS1
EN
Current-Limit Type Select 2. See Table 2.
Current-Limit Type Select 1. See Table 2.
Active-High Enable Input. See Table 1.
Ground/Exposed Pad. Connect to a large copper ground plane to maximize thermal performance.
GND/EP
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Functional Diagram
GP
IN IN IN IN IN
OUT
OUT
OUT
OUT
OUT
SETI
MAX14691–
MAX14693
RIPEN
VIN
REVERSE-
CURRENT FLOW
CONTROL
CURRENT-
LIMIT
CONTROL
CHARGE-
PUMP
CONTROL
VUVLO
UVLO
VSEL
FLAG
VIN
CONTROL LOGIC
VOVLO
OVLO
VSEL
EN
150kΩ
150kΩ
HVEN
5V
CLTS1 CLTS2 GND
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
the set limit during this period, while the MAX14692 and
MAX14693 limit the current to 1.5x and 2x the set limit,
respectively. If the temperature of any device rises to the
Detailed Description
The MAX14691—MAX14693 adjustable overvoltage,
undervoltage, and overcurrent protection devices guard
systems against overcurrent faults in addition to positive
overvoltage and reverse-voltage faults. When used with
an optional external pMOSFET, the devices also protect
downstream circuitry from voltage faults up to +58V, -60V
(for -60V external pFET rating). The devices feature a
low, 31mΩ, on-resistance integrated FET. During startup,
the devices are designed to charge large capacitances
on the output in a continuous mode for applications
where large reservoir capacitors are used on the inputs
to downstream devices. Additionally, the devices feature
a dual-stage current-limit mode in which the current is
continuously limited to 1x, 1.5x, and 2x the programmed
limit, respectively, for a short time after startup. This
enables faster charging of large loads during startup.
thermal-foldback threshold (T
), the device enters
J_FB
power-limiting mode (Figure 1). In this mode, the device
thermally regulates the current through the switch to
protect itself while still delivering as much current as
possible to the output regardless of the current-limit type
selected. If the output is not charged within the startup
timeout period (t
), the switch turns off and IN, EN, or
STO
HVEN must be toggled to resume normal operation. The
devices have a 16ms (typ) time delay at the end of startup,
during which the reverse threshold is set at -180mV (typ.)
to prevent false reverse faults due to oscillation. After this
delay, the reverse-current blocking threshold is reduced
to -10mV (V , typ).
RIB
Overvoltage Lockout (OVLO)
The devices feature the option to set the overvoltage-lockout
(OVLO) and undervoltage-lockout (UVLO) thresholds manually
using external voltage-dividers or to use the factory-preset
internal thresholds by connecting the OVLO and/or UVLO
pin(s) to GND. The permitted overvoltage setting range of
the devices is 6V to 40V. Therefore, the pFET and internal
nFET must be kept off in the 40V to 58V range by appropriate
OVLO resistor-divider.
The devices feature two methods for determining the OVLO
threshold. By connecting the OVLO pin to GND, the preset
internal OVLO threshold of 36V (typ) is selected. If the voltage
at OVLO rises above the OVLO select threshold (V
OVLO_
), the device enters adjustable OVLO mode. Connect an
SEL
external voltage-divider to the OVLO pin, as shown in the
Typical Application Circuit to adjust the OVLO threshold.
R3 = 2.2MΩ is a good starting value for minimum current
consumption. Since V
is known, R3 has been chosen,
SET
The adjustable overvoltage range of the devices is 6V to
40V, while the adjustable undervoltage range is 5.5V to
24V. The factory-preset internal threshold for the devices
is 36V (typ), with the preset internal UVLO threshold
being 12V (typ).
and V
is the target OVLO value, R4 can then be
OVLO
calculated by the following equation:
R3× V
SET
R4 =
V
− V
SET
OVLO
The devices’ programmable current-limit threshold can
be set for currents up to 6A in autoretry, latchoff, or
continuous-fault-response mode. When the device is set
to autoretry mode and the current exceeds the threshold
for more than 24ms (typ), both FETs are turned off for
720ms (typ), then turned back on. If the fault is still present,
the cycle repeats. In latchoff mode, if a fault is present
for more than 24ms (typ), both FETs are turned off until
enable is toggled or the power is cycled. In continuous
mode, the current is limited continuously to the programmed
Undervoltage Lockout (UVLO)
The devices feature two methods for determin-
ing the UVLO threshold. By connecting the UVLO pin
to GND, the preset, internal UVLO threshold of 12V
(typ) is selected. If the voltage at UVLO rises above
the UVLO select threshold (V
), the device
UVLO_SEL
enters adjustable UVLO mode. Connect an exter-
nal voltage-divider to the UVLO pin, as shown in the
Typical Application Circuit to adjust the UVLO threshold.
R1 = 2.2MΩ is a good starting value for minimum current
current-limit value. In all modes, FLAG asserts if V
OUT
threshold (V ).
-
IN
V
is greater than the FLAG assertion drop voltage
consumption. Since V
is known, R1 has been chosen,
SET
FA
and V
is the target value, R2 can then be calculated
UVLO
by the following equation:
Startup Control
R1× V
The devices feature a dual-stage startup sequence
that continuously limits the current to 1x/1.5x/2x the set
SET
R2 =
V
− V
SET
UVLO
current limit during the startup initial time (t ), allowing
STI
large capacitors present on the output of the switch to be
rapidly charged. The MAX14691 limits the current to 1x
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Table 1. Enable Inputs
Table 2. Current-Limit Type Select
HVEN
EN
0
SWITCH STATUS
CLTS2
CLTS1
CURRENT-LIMIT TYPE
LATCHOFF MODE
0
0
1
1
ON
ON
0
0
1
1
0
1
0
1
1
AUTORETRY MODE
CONTINUOUS MODE
CONTINUOUS MODE
0
OFF
ON
1
off, with the shortest duration of 420µs (t
is no fault. In latchoff mode, the device will latch off if the
) if there
Switch Control
ON_FET
There are two independent enable inputs on the devices:
HVEN and EN. HVEN is a high-voltage-capable input,
accepting signals up to 58V. EN is a low-voltage input,
accepting a maximum voltage of 5V. In case of a fault
condition, toggling HVEN or EN resets the fault. The
enable inputs control the state of the switch based on the
truth table (Table 1).
overcurrent fault last longer than t
.
BLANK
Autoretry Mode (Figure 3)
In autoretry current-limit mode, when current through the
device reaches the threshold, the t timer begins
BLANK
counting. The FLAG output asserts low when the voltage
drop across the switch rises above V . If the overcurrent
FA
condition is present for t
, the switch is turned off.
Input Debounce
The devices feature a built-in input debounce time (t
The debounce time is a delay between a POR event and
the switch being turned on. If the input voltage rises above
the UVLO threshold voltage or if, with a voltage greater
BLANK
The timer resets if the overcurrent condition disappears
before t has elapsed. A retry time delay (t
).
DEB
)
RETRY
BLANK
starts immediately once t
retry time, the switch remains off and, once t
elapsed, the switch is turned back on. If the fault still
exists, the cycle is repeated and FLAG remains low. If the
fault has been removed, the switch stays on.
has elapsed. During the
BLANK
has
RETRY
than V
present on IN, the enable pins toggle to the
UVLO
on state, the switch turns on after t
the voltage at IN falls below V
. In cases where
DEB
before t
has
UVLO
DEB
passed, the switch remains off (Figure 2). If the voltage
at OUT is already above V when the device
The autoretry feature reduces system power in case of
overcurrent or short-circuit conditions. When the switch is
UVLO_OUT
is turned on through either enable pin or coming out of
OVLO, there is no debounce interval. This is due to the
device already being out of the POR condition with OUT
on during t
limit. When the switch is off during t
no current through the switch. Thus, the output current is
much less than the programmed current limit. Calculate
the average output current using the following equation:
time, the supply current is held at the current
BLANK
time, there is
RETRY
above V
.
UVLO_OUT
Current-Limit Type Select
The devices feature three selectable current-limiting
modes. During power-up, all devices default to continuous
mode and follow the procedure defined in the Startup
Control section. Once the part has been successfully
t
+ t
×K
+ t
BLANK
STI
+ t
RETRY
I
= I
LOAD LIM
t
BLANK
STI
where K is the multiplication factor of the initial current
limit (1x, 1.5x or 2x). With a 24ms (typ) t 24ms
powered on and t
has expired, the device senses the
STO
BLANK,
condition of CLTS1 and CLTS2. The condition of CLTS1
and CLTS2 sets the current-limit mode type according to
Table 2. CLTS1,2 are internally pulled up to an internal 5V
supply. Therefore, the device is in continuous current-limit
mode when CLTS1 and 2 are open. To set CLTS_ state to
low, connect a 10kΩ resistor or below to ground.
In addition to the selectable current-limiting modes, the
device has a protection feature against a severe overload
condition. If the output current exceeds 2 times the set
current limit, the device will turn off the internal nFET and
external pFET immediately and will attempt to restart to
t
, K = 1 and 720ms (typ) t
, the duty cycle is
STI
RETRY
3.1%, resulting in 97% power saving when compared to
the switch being on the entire time.
Latchoff Mode (Figure 4)
In latchoff current-limit mode, when current through the
device reaches the threshold, the t
timer begins
BLANK
counting. FLAG asserts when the voltage drop across the
switch rises above V . The timer resets if the overcurrent
FA
condition disappears before t
has elapsed. The
BLANK
switch turns off if the overcurrent condition remains for the
blanking time. The switch remains off until the control logic
(EN or HVEN) is toggled or the input voltage is cycled.
allow the overcurrent to last for t
time. The off duration
BLANK
depends on fault condition occurred after the FETs turn
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
tBLANK
tBLANK
tRETRY
tDEB
tSTI
tBLANK
tRETRY
tSTI
1x /1.5x /2x ILIMIT
1x /1.5x /2x ILIMIT
ILIMIT
IOUT
VIN
VOUT
VFA
VUVLO_OUT
FLAG
NOT DRAWN TO SCALE
UVLO < VIN < VOVLO, HVEN= LOW, EN = HIGH
V
Figure 3. Autoretry Fault Diagram
tBLANK
tBLANK
tSTI
tBLANK
tDEB
tSTI
1x /1.5x /2x ILIMIT
ILIMIT
1x /1.5x /2x ILIMIT
IOUT
VIN
VOUT
VFA
VUVLO
_
OUT
EN
HVEN
FLAG
NOT DRAWN TO SCALE
VUVLO < VIN < VOVLO
Figure 4. Latchoff Fault Diagram
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
The additional time delay will be 420µs (t ) if voltage
ON_NFET
Continuous Mode (Figure 5)
at OUT is more than or equal to VUVLO_OUT falling at the
end of t delay, otherwise the delay will be 1.5ms
In continuous current-limit mode, when current through
the device reaches the threshold, the device limits the
current to the programmed limit. FLAG asserts when
REV_REC
). After a reverse-current event, the device will attempt
(t
DEB
a restart regardless of the current-type select.
the voltage drop across the switch rises above V , and
FA
deasserts when it falls below V
.
FA
Fault Indicator (FLAG) Output
Reverse-Current Blocking (Figure 6)
FLAG is an open-drain fault-indicator output. It requires
an external pullup resistor to a DC supply. FLAG asserts
when any of the following conditions occur:
The devices feature a current-blocking functionality to be
used with an external pFET. To enable the reverse-current
blocking feature, pull RIPEN high. With RIPEN high, if a
●
●
●
●
●
●
V
- V
> V
IN
OUT FA
reverse-current condition is detected (V - V
< V ),
IN OUT
RIB
Reverse-current protection is tripped
Die temperature exceeds +165°C
SETI is connected to ground
the internal nFET and the external pFET are turned off for
2.4ms (t ). During and after this time, the device
REV_REC
monitors the voltage difference between OUT and IN pins to
determine whether the reverse current is still present. Once
UVLO threshold has not been reached
OVLO threshold is reached
t
expired and the reverse-current condition has
REV_REC
been removed, the nFET and pFET are turned back on after
an additional time delay follows by the dual-stage startup
control mechanism as defined in the Startup Control section.
tDEB
tSTI
tSTO
tSTI
OVLO
UVLO
IN
ILIMIT
1x /1.5x /2x ILIMIT
1x /1.5x /2x ILIMIT
IOUT
THERMAL CURRENT LIMIT
THERMAL CURRENT
LIMIT
VIN
VFA
VOUT_
VOUT
UVLO
TJMAX
TJ
HVEN
EN
FLAG
NOT DRAWN TO SCALE
Figure 5. Continuous Fault Diagram
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Thermal Shutdown Protection
Applications Information
Thermal-shutdown circuitry protects the devices from
overheating. The switch turns off and FLAG asserts when
the junction temperature exceeds +165°C (typ). The
devices exit thermal shutdown and resume normal operation
once the junction temperature cools by 10°C (typ) when
the device is in autoretry or continuous current-limiting
mode. When in latchoff mode, the device remains latched
off until the input voltage is cycled or one of the enable
pins is toggled.
Setting the Current-Limit Threshold
Connect a resistor between SETI and ground to program
the current-limit threshold for the devices. Leaving SETI
unconnected sets the current-limit threshold to 0A and,
since connecting SETI to ground is a fault condition, this
causes the switch to remain off and FLAG to assert. Use
the following formula to calculate the current-limit threshold:
V (Ω × A)
RI
R
(kΩ) =
× C
IRATIO
SETI
The thermal shutdown technology built into the devices
behave in accordance with the selected current-limit mode.
While the devices are in autoretry mode, the thermal limit
uses the autoretry timing when coming out of a fault condition.
When the devices detect an overtemperature fault, the switch
turns off. Once the temperature of the junction falls below the
falling thermal threshold, the device turns on after the time
I
(mA)
LIM
Do not use a R
smaller than 6kΩ. Table 3 shows
SETI
current-limit thresholds for different resistor values at
SETI.
A current mirror with a ratio of C
is implemented
IRATIO
with a current-sense auto-zero operational amplifier.
The mirrored current of the IN-OUT FET is provided on
interval t
. In latchoff mode, the device latches
RETRY
off until the input is cycled or one of the enable pins is
toggled. In continuous current-limiting mode, the device
turns off while the temperature is over the limit, then
the SETI pin. Therefore, the voltage (V ) read on the
SETI
SETI pin should be interpreted as the current through the
IN-OUT FET, as shown below:
turns back on after t
when the temperature reaches
DEB
the falling threshold. There is no retry time for thermal
protection.
V
(V)
SETI
I
= I
× C
=
IRATIO
IN−OUT
SETI
R
(kΩ)
SETI
V
(V)
SETI
× C
=
×I
LIM
IRATIO
V (V)
RI
t
t
t
t
t
t
STI
REV_REC
ON_NFET
STI
REV_REC
DEB
t
t
RIB
RIB
I
IN
1x/1.5x/2x
1x/1.5x/2x
I
IN_REF
I
LIMIT
I
LIMIT
(V /R
RIB DSON
)
V
OUT
V
UVLO_OUT
I
LOAD
NOT DRAWN TO SCALE
Figure 6. Reverse-Current Timing Diagram
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
the devices can cause faults. If the capacitance is too high,
the devices may not be able to charge the capacitor before
the startup timeout. Calculate the maximum capacitive load
IN Bypass Capacitor
In applications in which an external pFET is not used,
connect a minimum of 1µF capacitor from IN to GND
to limit the input voltage drop during momentary output
short-circuit conditions. Larger capacitor values further
reduce the voltage droop at the input caused by load
transients. In applications in which an external pFET is
used, a 4.7µF capacitor is placed at the drain of the pFET,
and the capacitor at IN is reduced to 10nF (100nF max).
(C
) value that can be connected to OUT using the
MAX
following formula:
M x t (ms) + t
(
(ms)
STI
STO
TI
TO
C
(mF) = I (A)
MAX
LIM
V
(V)
IN_MAX
where M is the multiplier (1x/1.5x/2x) applied to the current
limit during startup. For example, when using MAX14691,
Hot Plug-In
In many power applications, an input filtering capacitor
is required to lower the radiated emission and enhance
the ESD capability, etc. In hot-plug applications, parasitic
cable inductance, along with the input capacitor, causes
overshoot and ringing when a powered cable is suddenly
connected to the input terminal. This effect causes the
protection device to see almost twice the applied voltage.
An input voltage of 24V can easily exceed 40V due to
ringing. The devices contain internal protection against
hot-plug input transients on the IN pins, with slew rate
up to 30V/µs. However, in the case where the harsh
industrial EMC test is required, use a transient voltage
suppressor (TVS) placed close to the input terminal that
is capable of limiting the input surge to 58V.
if V
= 30V, t
(min) = 1090ms, t
(min) = 22ms,
results in the theoretical maximum of
MAX
IN_MAX
LIM
STO
STI
and I = 3A, C
111mF. In this case, any capacitance larger than 111mF will
cause a fault condition because the capacitor cannot be
charged to a sufficient voltage before t
STO
has expired. In
practical applications, the output capacitor size is limited by
the thermal performance of the PCB. Poor thermal design
can cause the thermal-foldback current-limiting function of
the device to kick in too early, which may further limit the
maximum capacitance that can be charged. Therefore,
good thermal PCB design is imperative to charge large
capacitor banks.
OUT Freewheeling Diode for Inductive Hard
Short to Ground
OUT Capacitance
In applications with a highly inductive load, a freewheeling
diode is required between the OUT terminal and GND.
This protects the device from inductive kickback that
occurs during short-to-ground events.
For stable operation over the full temperature range and over
the entire programmable current-limit range, connect a 4.7µF
ceramic capacitor from OUT to ground. Other circuits connected
to the output of the device may introduce additional capacitance,
but it should be noted that excessive output capacitance on
PCB Layout Recommendations
To optimize the switch response to output short-circuit
conditions, it is important to reduce the effect of undesirable
parasitic inductance by keeping all traces as short as
possible. Place input and output capacitors as close as
possible to the device (no more than 5mm). IN and OUT
must be connected with wide short traces to the power
bus. During steady-state operation, the power dissipation
is typically low and the package temperature change is
usually minimal.
Table 3. Current-Limit Threshold
vs. Resistor Values
R
(kΩ)
CURRENT LIMIT (A)
SETI
62.5
0.6
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
37.5
25.0
18.75
15.0
12.5
10.7
9.375
8.3
PCB layout designs need to meet two challenges:
high-current input and output paths and important heat
dissipation.
Heat Dissipation
Maxim recommends the use of 2oz copper on FR4 isolator
in a four-layer configuration.
7.5
The layer stack needs to be top (routing), GND (plane),
6.82
6.25
power (plane, connected to V
), and bottom (routing),
OUT
in this order, from top to bottom.
Maxim Integrated
│ 16
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Maxim recommends the use of a GND plane. Connect the
input and output grounds to this plane using at least four
plated vias each. The vias should be 84mils in diameter
(or 60mils x 60mils, if square), with a 35mils plated hole.
Install the IC on an exposed pad landing of minimum
100 x 100 mils, with at least five through vias to the GND
plane. The vias should be 32mils in diameter, with a
16mils plated hole. The hole plating needs to be at least
0.5oz copper.
Additional Information
Provide a minimum of 1in x 1in area of copper plane on
all four layers. It is important to remember that the inner
planes do not contribute much to heat dissipation, due to
FR4 isolation, but are important from an electrical point
of view.
For more information on heat dissipation, see the IC
Application Section on http://www.maximintegrated.
com.
ESD Test Conditions
If possible, keep the top and bottom copper areas clear of
solder mask, as this will greatly improve heat dissipation.
The devices are specified for ±15kV (HBM) ESD on IN
when IN is bypassed to ground with a 1µF, low ESR
ceramic capacitor. No capacitor is required for ±2kV
(HBM) (typ) ESD on IN. All pins have ±2kV (HBM) ESD
protection. In applications in which an external pFET is
used, see the IN Bypass Capacitor section.
Use a similarly large copper area connected directly to the
OUT pins. A dimension of 1in x 1in is also recommended.
This might look oversized for current path requirements,
but is essential for heat dissipation. Keep in mind that
heat is generated at the drain junction of the internal
nMOS pass FET, which is then eliminated through the
five OUT pins and needs to be dissipated on this same
copper area.
HBM ESD Protection
Figure 7 shows the Human Body Model and Figure 8
shows the current waveform it generates when discharged
into low impedance. This model consists of a 100pF
capacitor charged to the ESD voltage of interest, which is
then discharged into the device through a 1.5kΩ resistor.
Current Path Requirements
Connect all five IN pins to a copper area that is at least
150mils wide. Using 2oz copper may reduce this requirement
to 100mils. Remember to provide the same copper trace
width on the source connection, when using the external
pMOS pass FET (with the drain connected to the IN pins).
Use extreme caution when placing the decoupling capacitors
to the IN and OUT pins. The tendency to go as close as
possible to the IC pins might interfere with the minimum
requirement of the trace width above.
It is important to note that the return load current does not
flow through the IC. Therefore, it is important to provide
an external ground trace of at least the same width as the
input/output one.
RC
RD
1MΩ
1.5KΩ
IP 100%
90%
IR
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
AMPERES
36.8%
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
10%
0
TIME
SOURCE
tRL
tDL
CURRENT WAVEFORM
Figure 7. Human Body ESD Test Model
Figure 8. Human Body Current Waveform
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Typical Application Circuit
VIN
*R1, R2, R3, AND R4 ARE ONLY
CIN
REQURED FOR ADJUSTABLE
UVLO/OVLO FUNCTIONALITY.
OTHERWISE, TIE THE PIN TO
GND TO USE THE INTERNA,L
PRE-PROGRAMMED
CIN_IC
GP
IN
IN IN IN IN
OUT
VIN
R1*
R3*
SYSTEM
UVLO
POWER
THRESHOLD.
CONTROLLER
OUT
OUT
PROTECTED
POWER
220kΩ
R2*
R4*
SYSTEM
INPUT
ADC
MAX14691–
MAX14693
COUT
VIN
OUT
OVLO
HVEN
OUT
SETI
RIPEN
FLAG
EN
GND
ENB
FAULT
EN
HVEN
x
CLTS2
10kΩ
CLTS1
GND
Ordering Information
PART
INITIAL CURRENT LIMIT
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
MAX14691ATP+T
MAX14692ATP+T
MAX14693ATP+T
1.0x
1.5x
2.0x
20 TQFN-EP*
20 TQFN-EP*
20 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
20 TQFN-EP
T2055+5C
21-0140
90-0010
Maxim Integrated
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MAX14691–MAX14693
High-Accuracy, Adjustable Power Limiter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
5/14
Initial release
—
Removed future product references for MAX14692 and MAX14693, updated
front page, and replaced Layout and Thermal Dissipation section
1
2
8/14
5/15
1, 16, 18
Improved reverse-current protection and general fault protection performance,
and clarified the IC device operation
10-12, 14-15, 17
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 19
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