概述
数据手册MAX14724EWP+ 概述
Serial-Controlled 8:4 Matrix Switch Multiplexer
MAX14724EWP+ 数据手册
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PDF下载MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
General Description
Benefits and Features
● Flexible Architecture Enables Ease of Design and Control
The MAX14724 is a serial-controlled, 8:4 full-matrix analog
multiplexer. The device operates from either a single wide
supply or dual ±2.5V supplies. A wide operating range
makes the device ideal for battery-powered, portable
instruments. All channels guarantee break-before-make
switching.
• 8:4 Matrix Switch Multiplexer
• Fully Programmable with Simultaneous Updates
• Independent Control of Each Switch
• Serial Control
2
- I C with Address-Select Pin
- SPI with DO for Daisy-Chain
- 1.6V Logic Compatible
● Low Distortion Switching Improves System
Performance
2
The serial control is selectable between I C and SPI. Both
modes provide individual control of each independent switch
so that any combination of switches can be applied.
I C mode provides one address-select pin, allowing for
addressing up to two devices on a single bus. The SPI
mode includes a DO pin that can be used to daisy-chain
multiple devices together with a single select signal.
2
• 1Ω R
(typ) with +5V or ±2.5V Supply
ON
• 0.5Ω R
• 0.2Ω R
Match Between Channels (typ)
Flatness Over Signal Range (typ)
ON
ON
• Low Leakage Current: 5nA at +25°C (typ)
The MAX14724 features bidirectional operation and
can handle rail-to-rail analog signals. All control inputs
are 1.6V-logic compatible. This device is available in
a small 20-pin, 4mm x 4mm, TQFN and 20-bump,
2mm x 1.7mm, wafer-level package (WLP).
● Integrated Protection for System Reliability
• ±30kV HBM on NO_ and COM_
• ±15kV IEC 61000-4-2 Air Gap Discharge on NO_
and COM_
• ±10kV IEC 61000-4-2 Contact Discharge on NO_
and COM_
Applications
● Medical Equipment
● Data Acquisition
● High-Integration Multiplexing Reduces Footprint and
System Complexity
• 20 WLP (2mm x 1.7mm)
● Signal Switching
• 20 TQFN (4mm x 4mm)
● Battery-Powered Equipment
Ordering Information appears at end of data sheet.
Typical Application Circuit
3.3V
V+
2.5V
B1-B4
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
-2.5V
GND
SDA
µCONTROLLER
SCL
V+
2.5V
B5-B8
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
-2.5V
GND
19-7575; Rev 2; 9/15
MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Absolute Maximum Ratings
V+............................................................................-0.3V to +6V
Continuous Power Dissipation
V- .............................................................................-6V to +0.3V
V ............................................................................-0.3V to +6V
L
V+ to V- ...................................................................-0.3V to +6V
20 TQFN (derate 25.6mW/°C above +70°C).............2051mW
20 WLP(derate 21.7mW/°C above +70°C)................1736mW
Operating Temperature Range........................... -40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range............................ -40°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
V
to V-....................................................................-0.3V to +9V
L
NO_, COM_ (Note 1) ..........................(V- - 0.3V) to (V+ + 0.3V)
SCL/SCK, SDA/DI, I2C/CS, ADD/DO .....................-0.3V to +6V
ADD/DO to V-..........................................................-0.3V to +9V
Continuous Current into NO_, COM_ ..............................±50mA
Peak Current into NO_, COM_
(pulsed at 1ms, 10% duty cycle) ................................±100mA
Note 1: Signals on COM_ and NO_ exceeding V+ or V- are clamped by internal diodes.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 2)
Package Thermal Characteristics
TQFN
WLP
Junction-to-Ambient Thermal Resistance (θ ) ..........46°C/W
Junction-to-Ambient Thermal Resistance (θ ) ..........39°C/W
JA
JA
Junction-to-Case Thermal Resistance (θ ).................6°C/W
JC
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V+ = 1.6V to 5V, V- = (V+ - 5.5V) to 0V, V = 0V to 5.5V (Notes 3, 4), T = -40°C to +85°C, unless otherwise noted. Typical values are
L
A
at V+ = 2.5V, V- = -2.5V, V = 2.5V, T = +25°C.) (Note 5)
L
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V+ Supply
V- Supply
V+
V-
1.6
5.5
0
V
V
V+ - 5.5
V- > -2.5V
0
0
5.5
V- + 8
5
V Supply
L
V
V
L
V- ≤ -2.5V
V+ Supply Current
I+
T
T
= +25°C
= +25°C
1
µA
µA
A
A
V Supply Current
I
1.5
5
L
VL
ANALOG SWITCH (Note 6)
V
V
COM_,
Analog Signal Range
V-
V+
3
V
NO_
I
= 10mA, V+ = 2.5V,
COM_
1
V- = -2.5V, V
= V- or V+
NO_
On-Resistance
R
Ω
ON
I
= 10mA, V+ = 3.0V,
COM_
5
V- = 0V, V
= 1.5V
NO_
I
= 10mA, V+ = 2.5V,
COM_
0.5
1.25
V- = -2.5V, V
= V- or V+
NO_
On-Resistance Match Between
Channels (Note 7)
ΔR
Ω
ON
I
= 10mA, V+ = 3.0V,
COM_
1.35
V- = 0V , V
= 1.5V
NO_
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Electrical Characteristics (continued)
(V+ = 1.6V to 5V, V- = (V+ - 5.5V) to 0V, V = 0V to 5.5V (Notes 3, 4), T = -40°C to +85°C, unless otherwise noted. Typical values are
L
A
at V+ = 2.5V, V- = -2.5V, V = 2.5V, T = +25°C.) (Note 5)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.5
UNITS
V+ = 2.5V, V- = -2.5V,
= 10mA, V = -2.5V,
COM_
-1.25V, 0V, 1.25V, 2.5V
On-Resistance Flatness
(Note 8, 9)
R
I
0.2
Ω
ON_FLAT
COM_
T
T
T
T
T
T
= 25°C, Figure 1 (Note 9)
= 125°C, Figure 1 (Note 9)
= 25°C, Figure 1 (Note 9)
= 125°C, Figure 1 (Note 9)
= 25°C, Figure 1 (Note 9)
= 125°C, Figure 1 (Note 9)
-0.25
-0.25
-0.25
+0.005
+0.5
+0.25
µA
µA
µA
µA
µA
µA
A
A
A
A
A
A
NO_ Off-Leakage Current
COM_ Off-Leakage Current
COM_ On-Leakage Current
+0.005
+1.0
+0.25
+0.25
+0.005
+1.5
DIGITAL I/O
2
Input Logic-High
V
SCL/SCK, SDA/DI, I C/CS, ADD/DO
0.7 x V
1.6
V
V
IH
L
2
Input Logic-Low
V
SCL/SCK, SDA/DI, I C/CS, ADD/DO
0.3 x V
IL
L
V Shutdown Threshold High
V
V
L
LIH
V Shutdown Threshold Low
L
V
0.4
+1
V
LIL
Input Leakage Current
I
, I
V
= 0V, V+, or V-
-1
+0.005
1
µA
pF
V
IH IL
IN
Digital Input Capacitance
2
Output Logic-Low (I C Mode)
V
I
I
I
= 3mA
0.4
OL_I2C
OL_SPI
OH_SPI
SINK
SINK
Output Logic-Low (SPI Mode)
V
= 200µA
0.15 x V
V
L
Output Logic-High (SPI Mode)
V
= 200µA
0.85 x V
V
SOURCE
L
DYNAMIC PERFORMANCE
V+ = 2.5V, V- = -2.5V, R = 100Ω,
L
Turn-Off Time
t
0.6
500
1
µs
ns
OFF
C = 35pF, V
= 1V, Figure 2
L
NO_
V+ = 2.5V, V- = -2.5V, R = 100Ω,
L
Break-Before-Make Time
Turn-On Time
t
0
BBM
C = 35pF, V
= 1V, Figure 2
L
NO_
V+ = 2.5V, V- = -2.5V, R = 100Ω,
L
t
2
µs
ON
C = 35pF, V
= 1V, Figure 2
L
NO_
R
= R = 50Ω, V
= 0.5V
,
S
L
NO_
P-P
Bandwidth -3dB
BW
50
MHz
C = 5pF, Figure 3
L
Initial condition: V = V
= GND.
IN
OUT
Q
Q
,
COM_
Charge Injection
C
= 1nF, C
= 1nF, Figure 4,
-15
pC
IN
OUT
NO_
(Note 10)
NO_ Off-Capacitance
COM_ Off-Capacitance
C
V
V
V
= 0V, f = 1MHz, Figure 5
50
85
pF
pF
NO_OFF
NO_
C
= 0V, f = 1MHz, Figure 5
COM_OFF
COM_
= V
= 0V, f = 1MHz,
COM_
NO_
Switch On-Capacitance
Off-Isolation
C
125
-60
pF
dB
ON
V+ - V- = 5V, Figure 5
C = 5pF, R = 50Ω, f = 1MHz,
V
L
L
= 1V
, V+ - V- = 5V,
NO_
RMS
Figure 3
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Electrical Characteristics (continued)
(V+ = 1.6V to 5V, V- = (V+ - 5.5V) to 0V, V = 0V to 5.5V (Notes 3, 4), T = -40°C to +85°C, unless otherwise noted. Typical values are
L
A
at V+ = 2.5V, V- = -2.5V, V = 2.5V, T = +25°C.) (Note 5)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
C = 5pF, R = 50Ω, f = 1MHz,
L
L
Crosstalk
V
= 1V
, V+ - V- = 5V,
-65
dB
NO_
RMS
Figure 3
R = 600Ω, f = 20Hz
L
Total Harmonic Distortion Plus
Noise
to 20kHz,
THD+N
V+ - V- ≥ 3V
0.1
%
V
= 0.5V
,
NO_
P-P
DC bias = (V+ + V-)/2
SPI TIMING CHARACTERISTICS (Figure 14, Note 4)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Time
DI Hold Time
t
+ t
95
35
45
15
15
15
ns
ns
ns
ns
ns
ns
CH
CL
t
CH
t
CL
t
CSS
t
DH
DI Setup Time
t
DS
C = 15pF, (V+ - V-) ≥ 2.7V and
L
50
Output Data Propagation
Delay
V ≥ 2.7V
L
t
ns
DO
C = 15pF, V ≤ 2.7V
125
L
L
DO Rise and Fall Times
t
C = 15pF
10
ns
ns
FT
L
CS Hold Time
t
60
CSH
2
I C TIMING (Figure 6, Note 4)
2
I C Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
t
0.6
0.6
0.6
1.3
0.6
µs
µs
µs
µs
µs
SU:STA
t
HD:STA
t
SU:STO
t
LOW
Clock High Period
t
HIGH
Write setup time,
100
V = (V+ - V-) ≥ 1.8V
L
Data Valid to SCL Rise Time
t
ns
ns
SU:DAT
HD:DAT
Write setup time,
V = (V+ - V-) = 1.6V
L
130
0
Data Hold Time to SCL Fall
t
Write hold time
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Electrical Characteristics (continued)
(V+ = 1.6V to 5V, V- = (V+ - 5.5V) to 0V, V = 0V to 5.5V (Notes 3, 4), T = -40°C to +85°C, unless otherwise noted. Typical values are
L
A
at V+ = 2.5V, V- = -2.5V, V = 2.5V, T = +25°C.) (Note 5)
L
A
PARAMETER
ESD PROTECTION
All COM_ and NO_ pins
All COM_ and NO_ pins
All COM_ and NO_ pins
All Other Pins
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Human Body Model (HBM)
±30
±15
±10
±2
kV
kV
kV
kV
IEC 61000-4-2 Air Gap Discharge
IEC 61000-4-2 Contact Discharge
Human Body Model (HBM)
Note 3:
Note 4:
V
V
maximum operating voltage is 5.5V if V- is greater than -2.5V, otherwise the V maximum operating voltage is (V- + 8V)
L
has to be greater than 1.6V for proper I C and SPI communication and timing.
L
L
2
Note 5: All devices are 100% production tested at T = +25°C. Specifications over temperature are guaranteed by design.
A
Note 6: (V+ - V-) has to be greater than 2.5V for good analog performance since on-resistance varies greatly when (V+ - V-) < 2.5V
(see On-Resistance in Typical Operating Characteristics).
Note 7: ΔR
= R
– R
.
ON
ON(MAX)
ON(MIN)
Note 8: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 9: Guaranteed by design.
Note 10: See the Typical Operating Characteristics for performance across operating range.
Test Circuits/Timing Diagrams
MAX14724
NO_ OFF
LEAKAGE
COM_ OFF
LEAKAGE
NO_
COM_
V
NO_
V
COM_
A
A
ON
LEAKAGE
MAX14724
NO1
COM_
V
COM_
A
NO2-8
V
NO_
A
Figure 1. On/Off-Leakage Current
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Test Circuits/Timing Diagrams (continued)
MAX14724
CS
1V
V
OUT
NO_
NO_
COM_
t
ON
1V
R
L
t
t
BBM
OFF
4
SPI
CONTROL
SPI
V
OUT
R
L
NOTE: V = 1V x
RIF
R
+ R
ON
L
0V
Figure 2. Turn-On/Turn-Off/Break-Before-Make
NETWORK
ANALYZER
50Ω
50Ω
V
V
IN
COM_
NO2-NO8
V
OUT
ON-LOSS = 20log
V
IN
NO1
OUT
MEAS
REF
REF
REF
MAX14724
50Ω
50Ω
50Ω
50Ω
50Ω
NETWORK
ANALYZER
COMB-D
COMA
50Ω
50Ω
V
V
IN
NO2-NO8
V
OUT
OFF-ISOLATION = 20log
V
IN
OUT
NO1
MEAS
MAX14724
50Ω
50Ω
NETWORK
ANALYZER
50Ω
50Ω
V
V
IN
COM_
NO1
NO2-NO8
V
OUT
CROSSTALK = 20log
V
IN
OUT
MEAS
MAX14724
50Ω
50Ω
Figure 3. Insertion Loss, Off-Isolation, and Crosstalk
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Test Circuits/Timing Diagrams (continued)
COM_ CHARGE INJECTION
V+
V+
RS
1MΩ
MAX14724
NO_
COM_
VOUT
CL
1nF
VS
GND
V-
V-
SWITCH
OFF
SWITCH
ON
ΔVOUT
VOUT
NO_ CHARGE INJECTION
V+
V+
ΔVOUT IS THE MEASURED VOLTAGE DUE TO CHARGE
TRANSFER ERROR Q WHEN THE CHANNEL TURNS OF.F
RS
1MΩ
MAX14724
Q = ΔVOUT X CL
COM_
NO_
VOUT
CL
1nF
VS
GND
V-
V-
Figure 4. Charge Injection
V+
V+
NO_
MAX14724
1MHz
COM_
V-
V-
V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.
Figure 5. COM_, NO_ Capacitance
CAPACITANCE
ANALYZER
GND
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Typical Operating Characteristics
(V+ = 5V, V- = 0V, V = V+, T = +25°C, unless otherwise noted.)
L
A
ON-RESISTANCE vs. COM_ VOLTAGE
ON-RESISTANCE vs. COM_ VOLTAGE
25
20
15
10
5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
INO_ = 10mA
TA = +125°C
V+ = +1.8V
TA = +25°C
TA = -40°C
INO_ = 10mA
V+ = 3V
V+ = 5V
V+ = 2.5V, V- = -2.5V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
COM_ VOLTAGE (V)
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
COM_ VOLTAGE (V)
ON-RESISTANCE vs. COM_ VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
TA = +125°C
TA = +25°C
IVL
TA = -40°C
IV+
INO_ = 10mA
V+ = 3V
V+ = VL
0.0
0.5
1.0
1.5
2.0
2.5
3.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
COM_ VOLTAGE (V)
COM_/NO_ CHARGE INJECTION vs.
NO_/COM_ VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
toc05
20
10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
V+ = 5V, V- = 0V, NO_
V+ = 2.5V, V- = -2.5V, NO_
0
IVL
-10
-20
-30
-40
-50
IV+
V+ = 5V, V- = 0V, COM_
V+ = 2.5V, V- = -2.5V, COM_
V+ = VL = 5V
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
NO_/COM_ VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Typical Operating Characteristics (continued)
(V+ = 5V, V- = 0V, V = V+, T = +25°C, unless otherwise noted.)
L
A
ENABLE TURN-ON/TURN-OFF TIME
vs. V+ SUPPLY VOLTAGE
toc08
LOGIC-LEVEL THRESHOLD
vs. SUPPLY VOLTAGE
V
L
toc07
4
3.5
3
1.4
1.2
1
TA = +125°C
TA = +25°C
tON
2.5
2
0.8
0.6
0.4
0.2
0
TA = -40°C
1.5
1
tOFF
0.5
0
VIN = 1V
RL = 100Ω, CL = 35pF
VL = V+
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VL SUPPLY VOLTAGE (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V+ SUPPLY VOLTAGE (V)
ENABLE TURN-ON/TURN-OFF TIME
vs. TEMPERATURE
FREQUENCY RESPONSE
toc09
toc10
1.4
1.2
1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
ON-RESPONSE
tON
0.8
0.6
0.4
0.2
0
OFF-ISOLATION
CROSSTALK
tOFF
VIN = 1V
RL = 100Ω, CL = 35pF
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (ºC)
0.1
1
10
100
FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION PLUS
NOISE (THD+N) vs. FREQUENCY
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
toc12
toc11
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
150
100
50
0.5VP-P
VIN = 5V, ON LEAKAGE
VIN = 5V, OFF LEAKAGE
0
-50
-100
-150
-200
-250
VIN = 0V, ON LEAKAGE
VIN = 0V, OFF LEAKAGE
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0.02
0.2
2
20
FREQUENCY (kHz)
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Pin Configurations
TOP VIEW
(BUMPS ON BOTTOM)
TOP VIEW
MAX14724
1
2
3
4
5
+
15
14
13
12
11
A
V- 16
10
9
NO6
NO5
NO4
NO3
NO2
COMA
NO1
NO2
NO3
NO4
NO5
NO6
NO7
NO8
17
B
GND
MAX14724
COMB
18
8
I2C/CS
C
19
20
7
VL
COMC
I2C/CS ADD/DO SCL/SCK
VL
EP
+
6
V+
D
COMD
V+
GND
V-
SDA/DI
1
2
3
4
5
WLP
(2mm x 1.6mm)
TQFN
(4mm × 4mm)
Pin Description
PIN
NAME
FUNCTION
TQFN
1
WLP
D1
C1
B1
A1
A2
B2
A3
B3
A4
B4
A5
B5
C5
D5
C4
D4
D3
C3
COMD
COMC
COMB
COMA
NO1
Common Terminal D
2
Common Terminal C
3
Common Terminal B
4
Common Terminal A
5
Normally Open Terminal 1
Normally Open Terminal 2
Normally Open Terminal 3
Normally Open Terminal 4
Normally Open Terminal 5
Normally Open Terminal 6
Normally Open Terminal 7
6
NO2
7
NO3
8
NO4
9
NO5
10
11
12
13
14
15
16
17
18
NO6
NO7
NO8
Normally Open Terminal 8
2
SCL/SCK
SDA/DI
ADD/DO
V-
I C Serial Clock/SPI Serial Clock
2
I C Serial Data/SPI Data Input
2
I C Address Bit/SPI Data Output
Negative Supply Voltage Input
GND
Ground
2
2
I2C/CS
I C Select (High)/SPI CS (Low). (See the I C and SPI section).
2
Logic Supply Voltage for SCL/SCK, SDA/DI, ADD/DO, and I C/CS. Drive V low to turn
off all switches and reset all registers.
L
19
20
—
C2
D2
—
V
L
V+
EP
Positive Supply Voltage Input
Exposed Pad (TQFN Only). Internally connected to V-. Can be connected to a large
plane to maximize thermal performance. Not intended as an electrical connection point.
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Functional Diagram
MAX14724
COMA
COMB
COMC
COMD
NO1
NO2
NO3
NO4
NO5
NO6
NO7
NO8
I2C/CS
V+
SCL/SCK
V-
VL
CONTROL
GND
SDA/DI
ADD/DO
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Table 1. Register Map
ADDRESS
0x00
NAME
DIR0
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DEFAULT
DESCRIPTION
Switches 8A-1A direct read/write access
Switches 8B-1B direct read/write access
Switches 8C-1C direct read/write access
Switches 8D-1D direct read/write access
Switches 8A-1A shadow read/write access
Switches 8B-1B shadow read/write access
Switches 8C-1C shadow read/write access
Switches 8D-1D shadow read/write access
Set mux A and B command (reads 0x00)
Set mux C and D command (reads 0x00)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x01
DIR1
0x02
DIR2
0x03
DIR3
0x10
SHDW0
SHDW1
SHDW2
SHDW3
CMD0
CMD1
0x11
0x12
0x13
0x14
0x15
Table 2. Detailed Register Map
DIR0 0x00
BIT
7
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Direct_SW8A-1A
0
0
0
Direct Register Data for SW8A-1A
0 = Switch open
DESCRIPTION
1 = Switch closed
DIR1 0X01
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Direct_SW8B-1B
0
0
Direct Register Data for SW8B-1B
0 = Switch open
DESCRIPTION
1 = Switch closed
DIR2 0X02
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Direct_SW8C-1C
0
0
Direct Register Data for SW8C-1C
0 = Switch open
DESCRIPTION
1 = Switch closed
DIR3 0X03
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Direct_SW8D-1D
0
0
Direct Register Data for SW8D-1D
0 = Switch open
DESCRIPTION
1 = Switch closed
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Table 2. Detailed Register Map (continued)
SHDW0 0X10
BIT
7
0
6
0
5
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Shadow_SW8A-1A
0
0
0
Shadow Register Data for SW8A-1A; temporarily holding register for simultaneous updates.
DESCRIPTION
0 = Switch open
1 = Switch closed
SHDW1 0X11
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Shadow_SW8B-1B
0
0
Shadow Register Data for SW8B-1B; temporarily holding register for simultaneous updates.
DESCRIPTION
0 = Switch open
1 = Switch closed
SHDW2 0X12
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Shadow_SW8C-1C
0
0
Shadow Register Data for SW8C-1C; temporarily holding register for simultaneous updates.
DESCRIPTION
0 = Switch open
1 = Switch closed
SHDW3 0X13
BIT
7
0
6
0
5
0
4
3
2
0
1
0
0
0
BIT NAME
RESET VALUE
Shadow_SW8D-1D
0
0
Shadow Register Data for SW8D-1D; temporarily holding register for simultaneous updates.
DESCRIPTION
0 = Switch open
1 = Switch closed
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Table 2. Detailed Register Map (continued)
CMD0 0X14
BIT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BIT NAME
RESET VALUE
SelB
SelA
0000 = Enable only SW1B (Set DIR1 = 0x01)
0001 = Enable only SW2B (Set DIR1 = 0x02)
0010 = Enable only SW3B (Set DIR1 = 0x04)
0011 = Enable only SW4B (Set DIR1 = 0x08)
0100 = Enable only SW5B (Set DIR1 = 0x10)
0101 = Enable only SW6B (Set DIR1 = 0x20)
0110 = Enable only SW7B (Set DIR1 = 0x40)
0111 = Enable only SW8B (Set DIR1 = 0x80)
1000 = Disable all bank B switches (Set DIR1 = 0x00)
SelB
1001 = Copy B shadow registers (Set DIR1 = SHDW1) to switches
1010 .. 1111 = No change on bank B
0000 = Enable only SW1A (Set DIR0 = 0x01)
0001 = Enable only SW2A (Set DIR0 = 0x02)
0010 = Enable only SW3A (Set DIR0 = 0x04)
0011 = Enable only SW4A (Set DIR0 = 0x08)
0100 = Enable only SW5A (Set DIR0 = 0x10)
0101 = Enable only SW6A (Set DIR0 = 0x20)
0110 = Enable only SW7A (Set DIR0 = 0x40)
0111 = Enable only SW8A (Set DIR0 = 0x80)
1000 = Disable all bank A switches (Set DIR0 = 0x00)
1001 = Copy A shadow registers (Set DIR0 = SHDW0) to switches
1010 .. 1111 = No change on bank A
SelA
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Table 2. Detailed Register Map (continued)
CMD1 0X15
BIT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
BIT NAME
RESET VALUE
SelD
SelC
0000 = Enable only SW1D (Set DIR3 = 0x01)
0001 = Enable only SW2D (Set DIR3 = 0x02)
0010 = Enable only SW3D (Set DIR3 = 0x04)
0011 = Enable only SW4D (Set DIR3 = 0x08)
0100 = Enable only SW5D (Set DIR3 = 0x10)
0101 = Enable only SW6D (Set DIR3 = 0x20)
0110 = Enable only SW7D (Set DIR3 = 0x40)
0111 = Enable only SW8D (Set DIR3 = 0x80)
1000 = Disable all bank D switches (Set DIR3 = 0x00)
SelD
1001 = Copy D shadow registers (Set DIR3 = SHDW3) to switches
1010 .. 1111 = No change on bank D
0000 = Enable only SW1C (Set DIR2 = 0x01)
0001 = Enable only SW2C (Set DIR2 = 0x02)
0010 = Enable only SW3C (Set DIR2 = 0x04)
0011 = Enable only SW4C (Set DIR2 = 0x08)
0100 = Enable only SW5C (Set DIR2 = 0x10)
0101 = Enable only SW6C (Set DIR2 = 0x20)
0110 = Enable only SW7C (Set DIR2 = 0x40)
0111 = Enable only SW8C (Set DIR2 = 0x80)
1000 = Disable all bank C switches (Set DIR2 = 0x00)
1001 = Copy C shadow registers (Set DIR2 = SHDW2) to switches
1010 .. 1111 = No change on bank C
SelC
resets when power is removed from V+, but it is better
Detailed Description
The MAX14724 is a serial-controlled 8:4 full-matrix analog
multiplexer. The serial control is selectable between I C
and SPI. Both modes provide individual control of each
independent switch so that any combination of switches
can be applied.
to use V to signal reset or shutdown since the voltag-
L
es at the analog switch pins (NO_/COM_) must remain
2
between V- and V+, but are independent of V .
L
2
I C and SPI
The I2C/CS pin is used simultaneously to select between
2
The device does not require balanced positive (V+)
and negative (V-) supply voltage. However, the voltage
difference between the two supplies (V+ - V-) should not
exceed 5.5V.
the I C and SPI interfaces and as a chip-select pin
for the SPI interface. When logic-high is applied on
2
I2C/CS, the device enables I C communication. To
enable SPI communication, I2C/CS needs to be driven
low and a serial clock should be applied on SCL/SCK.
After 21 periods of clock on SCL/SCK, the device latches
into SPI mode and I2C/CS operates as a purely chip-
Shutdown
The V supply pin can be used as an active-low shutdown/
L
reset signal. When the voltage at V is below the
L
2
select pin. The device does not resume I C operation if
V Shutdown Threshold Low, all switches are opened and
L
I2C/CS is driven high. To return from the latched SPI state
all registers reset, including the SPI-select latch. None of
the switches can be activated until the voltage at V rises
above the V Shutdown Threshold High. The device also
L
2
and to the I C state, V or V+ must be driven low. Once
L
L
V
or V+ returns high, a logic-high on I2C/CS puts the
L
2
device in the I C state again.
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
2
single switch in bank D, to open all bank D switches, to
copy SHDW3 to DIR3 register, or to leave bank D as is
(no change). The CMD1[3:0] bits allow the user to turn on
I C Serial Interface
Direct Access Registers
Direct-access registers (DIR0–DIR3) allow the user to
read/write the switches eight at a time. These register
addresses support autoincrementing so they can be read
or written sequentially. The switches are updated once the
last bit of the byte is clocked in.
a single switch in bank C, to open all bank C switches, to
copy SHDW2 to DIR2 register, or to leave bank C as is
(no change). The values apply to the switches once both
registers (CMD0 and CMD1) have been written. CMD0
and CMD1 are single 16-bit registers. Therefore, CMD0
must be programmed before CMD1.
Shadow Registers
Serial Addressing
When in I C mode, the device operates as a slave device
that sends/receives data through an I C-compatible
Shadow registers (SHDW0–SHDW3) provide storage
for switch values to allow for simultaneous updates
of the switches. Unlike direct-access registers, these
registers have no immediate effect until the copy command
is issued. The copy command has to be written in the
CMD0 and CMD1 registers. Write to the four registers
with the desired state of each switch and then write the
appropriate command to registers CMD0 and CMD1 to
simultaneously apply the values to the switches.
2
2
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirec-
tional communication between master(s) and slave(s).
A master (typically a microcontroller) initiates all data
transfers to and from the device and generates the SCL
clock that synchronizes the data transfer. The SDA line
operates as both an input and an open-drain output. A
pullup resistor is required on SDA. The SCL line operates
only as an input. A pullup resistor is required on SCL if
there are multiple masters on the 2-wire interface, or if the
master in a single-master system has an open-drain SCL
output. Each transmission consists of a START condition
sent by a master, followed by the MAX14724 7-bit slave
address plus R/W bit, a register address byte, one or more
data bytes, and, finally, a STOP condition (Figure 6).
Set Mux Command Registers
Set mux command registers (CMD0, CMD1) allow the
user to easily select any single switch in a bank. The
CMD0[7:4] bits allow the user to turn on one single switch
in bank B, to open all bank B switches, to copy SHDW1 to
DIR1 register, or to leave bank B as is (no change). The
CMD0[3:0] bits allow the user to turn on a single switch
in bank A, to open all bank A switches, to copy SHDW0
to DIR0 register, or to leave bank A as is (no change).
Similarly, the CMD1[7:4] bits allow the user to turn on a
t
R
SDA
t
BUF
t
t
SU:STA
SU:DAT
t
HD:STA
t
LOW
t
SU:STO
t
HD:DAT
t
SCL
HIGH
t
HD:STA
t
R
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
2
Figure 6. I C Interface Timing Details
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge clock
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from high
to low while SCL is high (Figure 7). When the master has
finished communicating with the slave, it issues a STOP
(P) condition by transitioning SDA from low to high while
SCL is high. The bus is then free for another transmission.
pulse. The SDA line is stable low during the high period
of the clock pulse. When the master is transmitting to the
MAX14724, it generates the acknowledge bit because the
device is the recipient. When the device is transmitting
to the master, the master generates the acknowledge bit
because the master is the recipient. If the device did not
pull SDA low, a not acknowledge (NACK) is indicated.
Bit Transfer
Slave Address
The device features a 7-bit slave address, configured by
the ADD/DO input. To select the slave address, connect
One data bit is transferred during each clock pulse
(Figure 8). The data on SDA must remain stable while
SCL is high.
ADD/DO to GND or V , as indicated in Table 3. The
L
Acknowledge
device has two possible addresses, allowing up to two
MAX14724 devices to share the same interface bus. The
bit following a 7-bit slave address is the R/W bit, which is
low for a write command and high for a read command.
An acknowledge bit (ACK) is a clocked 9th bit (Figure 9),
which the recipient uses to handshake receipt of each byte
of data. Thus, each byte transferred effectively requires 9
SDA
SCL
SDA
SCL
S
P
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
START
CONDITION
STOP
CONDITION
Figure 7. START and STOP Conditions
Figure 8. Bit Transfer
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
SCL
1
2
8
9
SDA BY
TRANSMITTER
SDA BY
RECEIVER
S
Figure 9. Acknowledge
Table 3. Slave Address Configuration
2
LOGIC INPUT
I C SLAVE ADDRESS
A0
(ADD)
R/W
ADD/DO
A6
A5
A4
A3
A2
A1
READ
WRITE
0
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1/0
1/0
0xE9
0xEB
0xE8
0xEA
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
device is to be written by the next byte, if received. If a
STOP (P) condition is detected after the register address
Bus Reset
2
The device resets the bus with the I C START condition
for reads. When the R/W bit is set to 1, the device transmits
data to the master. Therefore, the master is reading from
the device.
is received, the device takes no further action beyond
storing the register address. Any bytes received after the
register address are data bytes. The first data byte goes
into the register selected by the register address, with
subsequent data bytes going into subsequent registers
(Figure 10). If multiple data bytes are transmitted before
a STOP condition, these bytes are stored in subsequent
registers because the register addresses autoincrement
(Figure 11).
Format for Writing
A write to the MAX14724 comprises the transmission
of the slave address with the R/W bit set to zero,
followed by at least 1 byte of information. The first byte of
information is the register address or command byte.
The register address determines which register of the
ADDRESS = 0xE8
REGISTER ADDRESS = 0x01
0 = WRITE
S
1
1
1
0
1
0
0
0
A
P
0
0
0
0
0
0
0
1
A
REGISTER 0x01 WRITE DATA
S = START BIT
P = STOP BIT
A = ACK
d7
d6
d5
d4
d3
d2
d1
d0
A
N = NACK
d_ = DATA BIT
2
Figure 10. Format for I C Write
ADDRESS = 0xE8
REGISTER ADDRESS = 0x01
0 = WRITE
S
1
1
1
0
1
0
0
0
A
0
0
0
0
0
0
0
1
A
REGISTER 0x02 WRITE DATA
REGISTER 0x01 WRITE DATA
d7
d6
d5
d4
d3
d2
d1
d0
A
A/N
d7
d6
d5
d4
d3
d2
d1
d0
P
Figure 11. Format for Writing to Multiple Registers
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Format for Reading
SPI Interface
The device is read using the internally stored register
address as an address pointer, the same way the stored
register address is used as an address pointer for a
write. The pointer autoincrements after each data byte is
read using the same rules for a write. Therefore, a read
is initiated by first configuring the register address by
performing a write (Figure 11). The master can now read
consecutive bytes from the device, with the first data byte
being read from the register address pointed to by the
previously written register address (Figure 12). Once the
master sounds a NACK, the MAX14724 stops sending
valid data.
In SPI mode, the device operates a shift register designed
to work with common serial interfaces. The bits are shift-
ed through so that a large serial chain can be made to
minimize pins needed for a system with multiple devices
(see Figure 21). This shift register is also designed to be
compatible with common microcontroller SPI-type inter-
faces. The switches in the MAX14724 are all transitioned
simultaneously. To update the switches in SPI mode,
the user must shift in a bit with the desired state of each
switch according to the data format listed in Table 4. The
switches are updated at the rising edge of CS, with the last
32 bits of data shifted in only if the number of bits clocked
in is greater than or equal to the number of switches
(32). The DO pin is the serial output of the shift register.
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0xE8
A
S
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
A/N
1 = READ
ADDRESS = 0xE9
REGISTER 0x01 READ DATA
A
Sr
0
1
1
d7
d6
d5
d4
d3
d2
d1
d0
A/N
P
Figure 12. Format for Reads (Repeated START)
0 = WRITE
REGISTER ADDRESS = 0x01
ADDRESS = 0xE8
A
A
S
Sr
d7
1
1
1
1
1
1
0
1
0
0
0
0
0
0
d7
d7
0
d6
d6
0
0
0
0
0
d1
d1
1
d0
d0
A/N
1 = READ
ADDRESS = 0xE9
REGISTER 0x01 READ DATA
0
1
1
d5
d4
d3
d2
A
REGISTER 0x02 READ DATA
REGISTER 0x03 READ DATA
A
d6
d5
d4
d3
d2
d1
d0
d5
d4
d3
d2
A/N
P
Figure 13. Format for Reading Multiple Registers
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
This outputs the data loaded into DI, delayed by 32
clocks, and is intended for creating a serial daisy-chain to
minimize the number of select lines required by the SPI
interface. The first 32 bits out of DO after the falling edge
of CS are the contents of the shift register prior to CS
falling, followed by the data being clocked into DI. The bits
in the shift register are all zero when power is applied or
after shutdown is released.
Note that the data in the shift register may not be the
same as the state of the switches. The DO pin is intended
for daisy-chain applications and not for switch readback.
Note for (V+ - V-) less than 2.7V or V less than 2.7V, the
L
DO propagation delay can limit the maximum SPI oper-
ating frequency. See Figures 14 and 15 for SPI timing
diagrams. The voltage level driven out by the DO buffer is
set by the voltage applied to V . This allows the voltage
L
to be independent of the supply voltage.
CS
t
CH
t
t
CSS
CSH
t
CL
SCLK
t
DS
t
MOSI (DI)
DH
t
DO
MISO (DO)
Figure 14. SPI Timing Details
CS
SCLK
DI
X
d0
d1
SW8D
SW6D’
SW7D
SW5D’
SW6D
SW4D’
SW5D
SW3D’
SW4A
SW2A'
SW3A
SW1A'
SW2A
d0
SW1A
X
DO
SW8D’
SW7D’
d1
‘ REPRESENTS PREVIOUS DATA IN SHIFT REGISTER
D0 AND D1 CAN BE ANY DATA. BITS. THEY ARE THERE SIMPLY TO DEMONSTRATE
THAT THE DEVICE USES THE LAST N BITS RECEIVED TO UPDATE THE SWITCHES.
Figure 15. SPI Timing Diagram
Table 4. SPI Data Format
BYTE
First
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
SW8D
SW8C
SW8B
SW8A
SW7D
SW7C
SW7B
SW7A
SW6D
SW6C
SW6B
SW6A
SW5D
SW5C
SW5B
SW5A
SW4D
SW4C
SW4B
SW4A
SW3D
SW3C
SW3B
SW3A
SW2D
SW2C
SW2B
SW2A
SW1D
SW1C
SW1B
SW1A
Second
Third
Fourth
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MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
(Human Body Model) encountered during handling and
assembly. NO_ and COM_ are further protected against
ESD up to ±30kV (Human Body Model), ±15kV (Air
Gap Discharge method described in IEC 61000-4-2),
and ±10kV (Contact Discharge method described in
IEC 61000-4-2) without damage.
Applications Information
Serial Bus Configurations
The MAX14724 was designed to support a wide variety of
multiplexing applications. Multiple devices can be used in
a system to expand the number of ports being multiplexed.
2
With the address-select pin provided in I C mode, two devices
The ESD structures withstand high ESD both in normal
operation and when the device is powered down. After
an ESD event, the device continues to function without
latchup.
2
can be attached to the same I C bus simultaneously. There
are also several options for addressing multiple devices
when using the SPI interface. Using only three pins on the
microcontroller, as many devices as desired can be loaded
by connecting all CS and SCK pins in parallel and chaining
the DO pin from one device to the DI pin on the next. It
is also acceptable to provide a separate CS pin for each
device so they can be individually addressed and loaded.
Alternatively, a separate data line can be used for each
device to reduce the time required to load all the devices.
Some of the options and tradeoffs are listed in Table 5,
as well as example application diagrams in the typical
application circuit.
ESD Test Condition
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Human Body Model
Figure 16 shows the Human Body Model. Figure 17 shows
the current waveform it generates when discharged into a
low impedance. This model consists of a 100pF capacitor
charged to the ESD voltage of interest that is then discharged
into the device through a 1.5kΩ resistor.
Extended ESD
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges up to ±2kV
Table 5. Benefits and Limitations of Different Serial-Bus Configurations
SERIAL BUS
PINS
BENEFITS
LIMITATIONS
Maximum two devices per bus, slow protocol,
no simultaneous updates across all devices
2
I C (Figure 20)
2
Fewest pins
2
SPI Daisy-Chain
(Figure 21)
Faster than I C with only one additional pin,
3
n x 32 clocks required to load all devices
simultaneous updates across all devices in chain
n x 32 clocks required to load all devices,
requires an additional pin per device, no
simultaneous updates across all devices
SPI Separate CS
Common SPI implementation, quick for single
device updates
n+2
n+2
(Figure 22)
SPI Separate
Data (Figure 23)
Fastest loading for multiple devices,
simultaneous updates across all devices
Requires an additional pin per device, may not
be supported by the SPI controller
R
R
D
1.5kΩ
C
1MΩ
I
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
P
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
36.8%
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
STORAGE
CAPACITOR
S
100pF
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 16. Human Body ESD Test Model
Figure 17. Human Body Current Waveform
Maxim Integrated
│ 21
www.maximintegrated.com
MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
4-2 because series resistance is lower in the IEC 61000-
4-2 model. Hence, the ESD withstand voltage measured
to IEC 61000-4-2 is generally lower than that measured
using the Human Body Model. Figure 18 shows the IEC
61000-4-2 model, and Figure 19 shows the current wave-
form for the IEC 61000-4-2 ESD Contact Discharge test.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. However, it does not
specifically refer to integrated circuits. The major differ-
ence between tests done using the Human Body Model
and IEC 61000-4-2 is higher peak current in IEC 61000-
I
(AMPS)
PEAK
R
R
D
C
50MΩ TO 100MΩ
330Ω
100%
90%
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
150pF
STORAGE
CAPACITOR
S
SOURCE
10%
t
t
R
= 0.7ns TO 1ns
30ns
60ns
Figure 18. IEC 61000-4-2 ESD Test Model
Figure 19. IEC 61000-4-2 ESD Generator Current Waveform
Typical Application Circuit
3.3V
V+
2.5V
B1-B4
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
-2.5V
GND
SDA
SCL
µCONTROLLER
V+
2.5V
B5-B8
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
-2.5V
GND
2
Figure 20. I C-Controlled 8:8 MUX
Maxim Integrated
│ 22
www.maximintegrated.com
MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Typical Application Circuit (continued)
1.8V
V+
5V
B1-B4
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
GND
CS
SCK
µCONTROLLER
MOSI
V+
5V
VL
B5-B8
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
GND
Figure 21. SPI Daisy-Chain 8:8 MUX
1.8V
V+
3V
VL
B1-B4
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
CS1
CS0
GND
µCONTROLLER
SCK
MOSI
V+
3V
VL
B5-B8
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
GND
Figure 22. SPI Separate CS 8:8 Mux
Maxim Integrated
│ 23
www.maximintegrated.com
MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Typical Application Circuit (continued)
V+
2.5V
B1-B4
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
2.5V
A1-A8
NO_
V-
GPIO
-2.5V
CS
GND
D1
µCONTROLLER
D0
SCK
V+
2.5V
B5-B8
VL
I2C/CS
ADD/DO
SDA/DI
SCL/SCK
COM_
MAX14724
A1-A8
NO_
V-
-2.5V
GND
Figure 23. SPI Parallel Data 8:8 Mux
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
-40°C TO +85°C
PIN-PACKAGE
20 TQFN-EP*
20 TQFN-EP*
20 WLP
MAX14724ETP+
MAX14724ETP+T
MAX14724EWP+
MAX14724EWP+T
PACKAGE
PACKAGE
OUTLINE
NO.
LAND
PATTERN NO.
20 WLP
TYPE
CODE
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
20 TQFN
20 WLP
T2044+3C
W201C2+1
21-0139
90-0037
Refer to
Application
Note 1891
21-0779
Chip Information
PROCESS: BiCMOS
Maxim Integrated
│ 24
www.maximintegrated.com
MAX14724
Serial-Controlled 8:4 Matrix Switch Multiplexer
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
3/15
9/15
9/15
0
1
2
Initial release
—
Removed future product designation from MAX14724ATP+T
24
24
Updated Ordering Information
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 25
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