MAX15014BATX+_技术文档

19-0734; Rev 0; 1/07

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

General Description

Features

ꢀ Combined DC-DC Converters and Low-Quiescent-

The MAX15014–MAX15017 combine a step-down DC-

DC converter and a 50mA, low-quiescent-current low-

dropout (LDO) regulator. The LDO regulator is ideal for

powering always-on circuitry in automotive applications.

The DC-DC converter input voltage range is 4.5V to 40V

for the MAX15015/MAX15016, and 7.5V to 40V for the

MAX15014/MAX15017.

Current LDO Regulators

ꢀ 1A DC-DC Converters Operate from 4.5V to 40V

(MAX15015/MAX15016) or 7.5V to 40V

(MAX15014/MAX15017)

ꢀ Switching Frequency of 135kHz

(MAX15014/MAX15016) or 500kHz

(MAX15015/MAX15017)

The DC-DC converter output is adjustable from 1.26V to

32V and can deliver up to 1A of load current. These

devices utilize a feed-forward voltage-mode control

scheme for good noise immunity in the high-voltage

switching environment and offer external compensation

allowing for maximum flexibility with a wide selection of

inductor values and capacitor types. The switching

frequency is internally fixed at 135kHz and 500kHz,

depending on the version chosen. Moreover, the

switching frequency can be synchronized to an exter-

nal clock signal through the SYNC input. Light load effi-

ciency is improved by automatically switching to a

pulse-skip mode. The soft-start time is adjustable with

an external capacitor. The DC-DC converter can be

disabled independent of the LDO, thus reducing the

quiescent current to 47µA (typ).

ꢀ 50mA LDO Regulator Operates from 5V to 40V

Independent of the DC-DC Converter

ꢀ 47µA Quiescent Current with DC-DC Converter

Off and LDO On

ꢀ 6µA System Shutdown Current

ꢀ Frequency Synchronization Input

ꢀ Shutdown/Enable Inputs

ꢀ Adjustable Soft-Start Time

ꢀ Active-Low Open-Drain RESET Output with

Programmable Timeout Delay

ꢀ Thermal Shutdown and Output Short-Circuit

Protection

ꢀ Space-Saving (6mm x 6mm) Thermally Enhanced

36-Pin TQFN Package

The LDO linear regulators operate from 5V to 40V and

deliver a guaranteed 50mA load current. The devices

feature a preset output voltage of 5V (MAX1501_A) or

3.3V (MAX1501_B). Alternatively, the output voltage

can be adjusted from 1.5V to 11V by using an external

resistive divider. The LDO section also features a

RESET output with adjustable timeout period.

Ordering Information

PIN-

PKG

PART

TEMP RANGE

PACKAGE

CODE

Protection features include cycle-by-cycle current limit,

hiccup-mode output short-circuit protection, and thermal

shutdown. All devices are available in a space-saving,

high-power (2.86W), 36-pin TQFN package and are

rated for operation over the -40°C to +125°C automotive

temperature range.

MAX15014AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15014BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15015AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15015BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15016AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15016BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15017AATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

MAX15017BATX+ -40°C to +125°C 36 TQFN-EP* T3666-3

Applications

Car Radios

+Denotes a lead-free package.

*EP = Exposed pad.

Automotive Body Control Modules

Automotive Instrument Cluster

Navigation Systems

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

ABSOLUTE MAXIMUM RATINGS

IN_SW, IN_LDO, DRAIN, EN_SYS, EN_SW

LDO_OUT Output Current.................................Internally Limited

Switch DC Current (DRAIN and LX pins combined)

T = +125°C.......................................................................1.9A

J

to SGND ..............................................................-0.3V to +45V

IN_LDO to IN_SW..................................................-0.3V to +0.3V

LX to SGND ...........................................-0.3V to (V

LX to PGND ...........................................-0.3V to (V

BST to SGND..........................................-0.3V to (V

+ 0.3V)

+ 12V)

T = +150°C.....................................................................1.25A

RESET Sink Current ..............................................................5mA

IN_SW

J

Continuous Power Dissipation (T = +70°C)

A

BST to LX................................................................-0.3V to +12V

PGND to SGND .....................................................-0.3V to +0.3V

REG, DVREG, SYNC, RESET, CT to SGND............-0.3V to +12V

36-Pin TQFN (derate 26.3mW/°C above +70°C)

Single-Layer Board .....................................................2105mW

36-Pin TQFN (derate 35.7mW/°C above +70°C)

Multilayer Board ..........................................................2857mW

Operating Temperature Range .........................-40°C to +125°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range ............................-60°C to +150°C

Lead Temperature (soldering, 10s) ................................+300°C

FB, COMP_SW, SS to SGND....................-0.3V to (V

+ 0.3V)

REG

SET_LDO, LDO_OUT to SGND ..............................-0.3V to +12V

C+ to PGND

(MAX15015/MAX15016 only)................(V

C- to PGND

- 0.3V) to 12V

DVREG

(MAX15015/MAX15016 only) ............-0.3V to (V

+ 0.3V)

DVREG

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

4–MAX5017

(V

= V

= 14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

IN_SW

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

REG

1µF, C

= 0.1µF, C

= 10µF, C

= 0.22µF, T = T = -40°C to +125°C, unless otherwise noted.

DRAIN A J

IN_SW

IN_LDO

LDO_OUT

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

= 1.3V,

MIN

TYP

MAX

UNITS

V

FB

0.7

1.8

MAX15014/MAX15017

System Supply Current (Not

Switching)

I

No load

mA

SYS

V

= 1.3V,

FB

0.85

5.6

1.8

MAX15015/MAX15016

V

= 0V,

FB

MAX15014/MAX15017

Switching System Supply Current

LDO Quiescent Current

I

No load

mA

µA

SW

V

= 0V,

FB

8.6

MAX15015/MAX15016

I

= 100µA

= 50mA

47

130

6

63

200

10

LDO_OUT

V

= 14V,

= 0V

EN_SYS

EN_SW

I

LDO

I

System Shutdown Current

System Enable Voltage

System Enable Hysteresis

System Enable Input Current

BUCK CONVERTER

I

V

= 0V, V

= 0V

µA

V

SHDN

EN_SYS

EN_SW

V

EN_SYS = high, system on

EN_SYS = low, system off

2.4

EN_SYSH

V

0.8

EN_SYSL

220

0.5

0.6

mV

µA

V

= 2.4V

= 14V

2

EN_SYS

I

EN_SYS

MAX15014/MAX15017

MAX15015/MAX15016

7.5

4.5

40.0

Input Voltage Range

V

IN_SW

2

_______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

ELECTRICAL CHARACTERISTICS (continued)

(V

= V

= 14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

REG

IN_SW

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

1µF, C

= 0.1µF, C

= 10µF, C

= 0.22µF, T = T = -40°C to +125°C, unless otherwise noted.

DRAIN A J

IN_SW

IN_LDO

LDO_OUT

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

and IN_LDO rising,

MAX15014/MAX15017

MIN

TYP

MAX

UNITS

V

IN_SW

6.7

7.0

7.4

Undervoltage Lockout Threshold

UVLO

V

TH

V

and IN_LDO rising,

IN_SW

3.90

4.08

4.25

MAX15015/MAX15016

MAX15014/MAX15017

MAX15015/MAX15016

Minimum output

0.54

0.3

1.26

32

Undervoltage Lockout

Hysteresis

UVLO

V

HYST

Output Voltage Range

Output Current

V

A

OUT

Maximum output

I

1

OUT

V

EN_SW = high, switching power supply is on

EN_SW = low, switching power supply is off

2.4

EN_SWH

EN_SW Input Voltage Threshold

EN_SW Hysteresis

V

0.8

EN_SWL

220

0.5

0.6

mV

µA

V

= 2.4V

= 14V

2

EN_SW

Switching Enable Input Current

I

EN_SW

INTERNAL VOLTAGE REGULATOR

MAX15014/MAX15017, V

MAX15015/MAX15016,

= 9V to 40V

7.6

8.4

IN_SW

Output Voltage

V

REG

4.75

5.25

V

= 5.5V to 40V

IN_SW

= 9.0V to 40V, MAX15014/MAX15017

= 5.5V to 40V, MAX15015/MAX15016

1

Line Regulation

Load Regulation

mV/V

V

I

= 0 to 20mA

0.25

0.5

REG

V

= 7.5V (MAX15014/MAX15017),

= 4.5V (MAX15015/MAX15016),

IN_SW

Dropout Voltage

V

I

= 20mA

REG

OSCILLATOR

V

= 0V, MAX15014/MAX15016

= 0V, MAX15015/MAX15017

122

425

136

500

150

575

SYNC

Frequency Range

f

kHz

CLK

V

= 0V, V

= 7.5V, MAX15014

= 4.5V, MAX15016

= 4.5V, MAX15015

= 7.5V, MAX15017

SYNC

IN_SW

90

98

96

98

(135kHz)

V

= 0V, V

SYNC

(135kHz)

Maximum Duty Cycle

D

%

MAX

V

= 0V, V

SYNC

(500kHz)

V

= 0V, V

SYNC

(500kHz)

Minimum LX Low Time

SYNC High-Level Voltage

SYNC Low-Level Voltage

V

= 0V

94

ns

V

SYNC

2.2

0.8

_______________________________________________________________________________________

3

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

ELECTRICAL CHARACTERISTICS (continued)

(V

= V

= 14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

REG

IN_SW

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

1µF, C

= 0.1µF, C

= 10µF, C

= 0.22µF, T = T = -40°C to +125°C, unless otherwise noted.

DRAIN A J

IN_SW

IN_LDO

LDO_OUT

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

100

400

TYP

MAX

200

UNITS

kHz

V

MAX15014/MAX15016

MAX15015/MAX15017

SYNC Frequency Range

f

SYNC

600

Ramp Level Shift (Valley)

ERROR AMPLIFER

Soft-Start Reference Voltage

Soft-Start Current

0.3

V

1.210

7

1.235

12

1.260

17

V

µA

V

SS

I

V

= 0V

SS

FB Regulation Voltage

FB Input Range

V

1.210

0

1.235

1.260

1.5

FB

V

FB Input Current

I

= 1.244V

-250

0.25

+250

4.5

nA

V

FB

COMP Voltage Range

Open-Loop Gain

I

= -500µA to +500µA

COMP

80

1.8

10

dB

MHz

Unity-Gain Bandwidth

f

= 500kHz, MAX15015/MAX15017

= 135kHz, MAX15014/MAX15016

SYNC

PWM Modulator Gain

V/V

4–MAX5017

f

SYNC

CURRENT-LIMIT COMPARATOR

Pulse Skip Threshold

IPFM

100

1.3

200

2

300

2.6

mA

A

Cycle-by-Cycle Current Limit

I

ILIM

Number of Consecutive ILIM

Events to Hiccup

7

—

Clock

periods

Hiccup Timeout

512

POWER SWITCH

Switch On-Resistance

Switch Gate Charge

V

- V = 6V

0.15

0.4

4

0.80

Ω

BST

LX

- V = 6V

nC

LX

= V

= V = V

=

IN_SW

IN_LDO

LX

DRAIN

Switch Leakage Current

BST Quiescent Current

BST Leakage Current

10

600

1

µA

40V, V = 0V

FB

V

= 40V, V

= 40V, V = 0V,

DRAIN FB

BST

400

DVREG = 5V

V

= V

= V = V

=

BST

DRAIN

LX

IN_SW

= 40V, EN_SW = 0V

IN_LDO

CHARGE PUMP (MAX15015/MAX15016)

C- Output Voltage Low

C- Output Voltage High

DVREG to C+ On-Resistance

LX to PGND On-Resistance

LDO

Sinking 10mA

0.1

10

V

Relative to DVREG, sourcing 10mA

Sourcing 10mA

Ω

Sinking 10mA

12

Input Voltage Range

V

5

40

V

IN_LDO

Undervoltage Lockout Threshold

UVLO_LDO

V

rising

IN_LDO

3.90

4.1

0.3

4.25

TH

Undervoltage Lockout Hysteresis UVLO_LDO

HYST

4

_______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

ELECTRICAL CHARACTERISTICS (continued)

(V

= V

= 14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

REG

IN_SW

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

1µF, C

= 0.1µF, C

= 10µF, C

= 0.22µF, T = T = -40°C to +125°C, unless otherwise noted.

IN_SW

IN_LDO

LDO_OUT

DRAIN

A

J

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

Output Current

SYMBOL

CONDITIONS

= 6V (Note 2)

IN

MIN

TYP

MAX

UNITS

I

V

65

200

mA

OUT

I

= 100µA

= 1mA

4.90

4.85

3.22

3.2

5

5.06

5.15

3.35

3.4

LDO_OUT

I

SET_LDO = SGND,

MAX1501_A

6V ≤ V

≤ 40V,

IN_LDO

5

I

= 1mA

LDO_OUT

1mA ≤ I

V

≤ 50mA,

OUT

5

= 14V

IN_LDO

Output Voltage

V

LDO_OUT

I

= 100µA

= 1mA

3.3

LDO_OUT

I

LDO_OUT

SET_LDO = SGND,

MAX1501_B

6V ≤ V

≤ 40V,

IN_LDO

I

= 1mA

LDO_OUT

1mA ≤ I

50mA, V

14V

≤

=

LDO_OUT

3.2

1.5

3.3

3.4

IN_LDO

Adjustable Output Voltage Range

Dropout Voltage

V

> 0.25V

SET_LDO

11.0

0.6

V

ADJ

I

= 10mA

OUT

= 5V,

IN_LDO

MAX1501_A

= 50mA

= 10mA

= 50mA

0.82

0.1

∆V

DO

V

= 4.0V,

IN_LDO

MAX1501_B

0.4

From EN_SYS high to LDO_OUT rise,

R_L= 500Ω, SET_LDO = SGND

Startup Response Time

400

µs

SET_LDO Reference Voltage

Minimum SET_LDO Threshold

SET_LDO Input Leakage Current

V

1.220

1.241

185

1.265

100

V

SET_LDO

(Note 3)

mV

nA

I

V

= 11V

0.5

SET_LDO

I

V

= 10mA, f = 100Hz, 500mV

,

OUT

P-P

78

= 5V

LDO_OUT

Power-Supply Rejection Ratio

Short-Circuit Current

PSRR

dB

I

V

= 10mA, f = 1MHz, 500mV

,

OUT

P-P

24

= 5V

LDO_OUT

I

125

185

300

mA

SC

_______________________________________________________________________________________

5

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

ELECTRICAL CHARACTERISTICS (continued)

(V

= V

= 14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

REG

IN_SW

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

1µF, C

= 0.1µF, C

= 10µF, C

= 0.22µF, T = T = -40°C to +125°C, unless otherwise noted.

DRAIN A J

IN_SW

IN_LDO

LDO_OUT

Typical values are at T = +25°C.) (Note 1)

A

PARAMETER

RESET OUTPUT

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

RESET goes high after rising V

crosses this threshold

LDO_OUT

RESET Threshold

V

90

92.5

95

0.4

1

%V

OUT

RESET

RESET Output Low Voltage

V

I

(V

– V

) / I = 4kΩ

RESET RESET

V

RL

LDO_OUT

V

= 3.3V (For MAX15_ _ _B),

= 5V (For MAX15_ _ _A)

RESET Output High Leakage

Current

RESET

RH

µA

µs

RESET Output Minimum Timeout

Period

When LDO_OUT reaches RESET threshold,

CT = unconnected

50

When EN_SYS goes high, C

=

LDO_OUT

ENABLE to RESET Minimum

Timeout Period

10µF, I

= 50mA, V

= 3.3V,

650

µs

LDO_OUT

CT = unconnected

Delay Comparator Threshold

(Rising)

V

1.220

1.5

1.241

100

1.265

3

V

CT-TH

CTTH-

4–MAX5017

Delay Comparator Threshold

Hysteresis

mV

HYST

CT Charge Current

I

V

= 0V

CT

2

µA

CT-CHQ

CT Discharge Current

I

18

mA

CT-DIS

THERMAL SHUTDOWN

Thermal Shutdown Temperature

Thermal Shutdown Hysteresis

Temperature rising

+160

20

°C

Note 1: Limits at -40°C are guaranteed by design and not production tested.

Note 2: Maximum output current is limited by package power dissipation.

Note 3: This is the minimum voltage needed at SET_LDO for the system to recognize that the user wants an adjustable LDO_OUT.

6

_______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

Typical Operating Characteristics

(V

IN_SW

= V

=14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

REG

=

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

1µF, C

= 0.1µF, C

= 10µF, C = 0.22µF, see Figures 6 and 7, T = +25°C, unless otherwise noted.)

DRAIN A

IN_SW

IN_LDO

LDO_OUT

SYSTEM SHUTDOWN CURRENT

vs. TEMPERATURE

SWITCHING FREQUENCY

vs. TEMPERATURE

SWITCHING FREQUENCY

vs. TEMPERATURE

10

9

8

7

6

5

4

3

2

1

0

140

530

520

510

500

490

480

470

460

450

MAX15015A

MAX15016

MAX15016A

139

138

137

136

135

134

133

132

131

130

-50

0

50

100

150

-60 -40 -20

0

20 40 60 80 100 120 140 160

-60 -40 -20

0

20 40 60 80 100 120 140 160

TEMPERATURE (°C)

MAXIMUM DUTY CYCLE

ERROR AMPLIFIER OPEN-LOOP GAIN

vs. INPUT VOLTAGE (MAX15015A)

vs. INPUT VOLTAGE (MAX15016A)

AND PHASE vs. FREQUENCY

MAX15014 toc06

100

98

96

94

92

90

88

86

84

82

80

100

99

98

97

96

95

94

93

92

91

90

110

100

90

80

70

60

50

40

30

20

10

0

340

300

260

220

180

140

100

60

GAIN

PHASE

-10

0

5

10 15 20 25 30 35 40

INPUT VOLTAGE (V)

0

5

10 15 20 25 30 35 40

INPUT VOLTAGE (V)

0.1

1

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

OUTPUT CURRENT LIMIT

vs. INPUT VOLTAGE

TURN-ON/-OFF WAVEFORM

MAX15014 toc08

MAX15014 toc09

2.5

2.0

1.5

1.0

0.5

0

I

= 1A

I

= 100mA

LOAD

T

= 0°C

A

T

= +25°C

A

EN_SW

2V/div

EN_SW

2V/div

0V

T

= +85°C

A

T

= +135°C

A

V

OUT

2V/div

OUT

2V/div

0V

0

10

20

30

40

50

2ms/div

INPUT VOLTAGE (V)

_______________________________________________________________________________________

7

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

Typical Operating Characteristics (continued)

(V

IN_SW

= V

=14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

REG

1µF, C

= 0.1µF, C

= 10µF, C = 0.22µF, see Figures 6 and 7, T = +25°C, unless otherwise noted.)

DRAIN A

IN_SW

IN_LDO

LDO_OUT

TURN-ON/-OFF WAVEFORM

INCREASING V

IN

OUTPUT VOLTAGE vs. TEMPERATURE

IN

MAX15014 toc11

MAX15014 toc10

3.40

3.38

3.36

3.34

3.32

3.30

3.28

3.26

3.24

3.22

3.20

I

= 100mA

I

= 1A

LOAD

V

IN

V

5V/div

IN

5V/div

0V

I

= 0A

0V

LOAD

V

OUT

V

OUT

2V/div

I

= 1A

LOAD

60

10ms/div

-40 -15

10

35

85 110 135

TEMPERATURE (°C)

EFFICIENCY vs. LOAD CURRENT

(MAX15015A)

EFFICIENCY vs. LOAD CURRENT

(MAX15014)

4–MAX5017

EFFICIENCY vs. LOAD CURRENT

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

0

V

= 3.3V

V

= 3.3V

OUT

V

= 5V

OUT

V

= 7.5V

IN

V

= 7.5V

IN

90

80

70

60

50

40

30

20

10

0

V

= 4.5V

IN

V

= 4.5V

IN

V

= 7.5V

IN

V

= 24V

IN

V

= 12V

IN

V

= 12V

IN

V

= 12V

V

= 24V

IN

V = 24V

IN

V

= 40V

IN

V

= 40V

IN

V

= 40V

IN

MAX15016A

= 0A

I

LDO_OUT

0

1

10

100

1000

100

10

LOAD CURRENT (mA)

1

1000

1

10

100

1000

LOAD CURRENT (mA)

EFFICIENCY vs. LOAD CURRENT

(MAX15017A)

LOAD-TRANSIENT RESPONSE

MAX15014 toc18

MAX15014 toc17

100

90

80

70

60

50

40

30

20

10

V

= 4.5V, I

= 0.25A TO 1A

OUT

V

= 5V

V

= 12V, I

= 0.25A TO 1A

OUT

IN

OUT

IN

MAX15015A

V

OUT

AC-COUPLED

100mV/div

V

= 7.5V

OUT

IN

AC-COUPLED

100mV/div

V

= 24V

IN

V

= 12V

IN

I

LOAD

V

= 40V

IN

500mA/div

I

LOAD

500mA/div

0

1

10

100

1000

200µs/div

LOAD CURRENT (mA)

8

_______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

Typical Operating Characteristics (continued)

(V

IN_SW

= V

=14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

REG

1µF, C

= 0.1µF, C

= 10µF, C = 0.22µF, see Figures 6 and 7, T = +25°C, unless otherwise noted.)

IN_SW

IN_LDO

LDO_OUT

DRAIN A

LX VOLTAGE AND INDUCTOR CURRENT

MAX15014 toc20

MAX15014 toc19

MAX150_ _

V

LX

5V/div

0V

INDUCTOR CURRENT

100mA/div

INDUCTOR CURRENT

200mA/div

I

= 40mA

I

= 160mA

LOAD

2µs/div

MINIMUM LX PULSE WIDTH

vs. LOAD CURRENT

LX VOLTAGE AND INDUCTOR CURRENT

MAX15014 toc21

400

350

300

250

200

150

100

50

V

LX

5V/div

0V

INDUCTOR CURRENT

500mA/div

I

= 1A

V

= 3.3V

OUT

LOAD

0

300 400 500 600 700 800 900 1000

LOAD CURRENT (mA)

2µs/div

LDO QUIESCENT CURRENT

vs. TEMPERATURE

OUTPUT VOLTAGE

vs. TEMPERATURE

OUTPUT VOLTAGE

vs. TEMPERATURE

70

60

50

40

30

20

10

0

5.10

3.31

3.30

3.29

3.28

3.27

3.26

3.25

3.24

3.23

I

= 1mA

LOAD

I

= 100µA

LOAD

5.05

5.00

4.95

4.90

4.85

I

= 1mA

LOAD

I

= 10mA

= 50mA

LOAD

I

= 10mA

LOAD

NO LOAD

I

= 50mA

LOAD

I

LOAD

MAX15015A

85 110 135

MAX15015B

75 100 125

MAX15015B

-50 -25

0

25

50

-40 -15

10

35

60

-40 -15

10

35

60

85 110 135

TEMPERATURE (°C)

_______________________________________________________________________________________

9

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

Typical Operating Characteristics (continued)

(V

IN_SW

= V

=14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

REG

1µF, C

= 0.1µF, C

= 10µF, C = 0.22µF, see Figures 6 and 7, T = +25°C, unless otherwise noted.)

IN_SW

IN_LDO

LDO_OUT

DRAIN A

TURN-ON/-OFF WAVEFORM

TOGGLING EN_SYS

DROPOUT VOLTAGE vs. LOAD CURRENT

POWER-SUPPLY REJECTION RATIO

MAX15014 toc28

900

800

700

600

500

400

300

200

100

0

10

0

I

= 50mA

LOAD

V

= 5V, I

= 0 TO 50mA

IN

LOAD

MAX15015A

T

= +135°C

EN_SYS

2V/div

I

= 50mA

A

LDO_OUT

-10

-20

-30

-40

-50

-60

-70

-80

T

= +85°C

A

I

= 10mA

LDO_OUT

0V

T

= +25°C

A

T

= -40°C

A

V

OUT

2V/div

I

= 1mA

LDO_OUT

2ms/div

0

10

20

30

40

50

0.1k

1k

10k

100k

1M

10M

LOAD CURRENT (mA)

FREQUENCY (Hz)

4–MAX5017

TURN-ON/-OFF WAVEFORM

TOGGLING EN_SYS

TURN-ON/-OFF WAVEFORM

TOGGLING EN_SYS

MAX15014 toc30

MAX15014 toc29

R

= 1kΩ

LOAD

MAX15015B

= 66Ω

R

LOAD

EN_SYS

2V/div

EN_SYS

2V/div

0V

V

LDO_OUT

OUT

1V/div

2V/div

0V

10ms/div

TURN-ON/-OFF WAVEFORM

TOGGLING EN_SYS

INCREASING V

IN

MAX15014 toc32

MAX15014 toc31

I

= 50mA

LOAD

MAX15015B

= 660Ω

R

LOAD

EN_SYS

2V/div

V

IN

5V/div

0V

V

LDO_OUT

V

LDO_OUT

1V/div

2V/div

0V

10ms/div

10 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

Typical Operating Characteristics (continued)

(V

IN_SW

= V

=14V, V

= V

= 2.4V, V

= V

, V

= V

= 0V, C

=

IN_LDO

DRAIN

EN_SYS

EN_SW

REG

DVREG SYNC

SET_LDO

SGND

PGND

REG

1µF, C

= 0.1µF, C

= 10µF, C = 0.22µF, see Figures 6 and 7, T = +25°C, unless otherwise noted.)

IN_SW

IN_LDO

LDO_OUT

DRAIN A

LDO TURN-ON/-OFF WAVEFORM

WITH INCREASING V

TURN-ON/-OFF WAVEFORM

INCREASING V

IN

MAX15014 toc33

MAX15014 toc34

I

= 5mA

LOAD

MAX15015B

R

= 66Ω

LOAD

V

IN

5V/div

V

IN

2V/div

0V

V

LDO_OUT

1V/div

V

LDO_OU

2V/div

10ms/div

TURN-ON/-OFF WAVEFORM

LOAD-TRANSIENT RESPONSE

INCREASING V

IN

MAX15014 toc36

MAX15014 toc35

MAX15015B

R

= 660Ω

LOAD

V

LDO_OUT

IN

AC-COUPLED

100mV/div

5V/div

0V

V

LDO_OUT

I

LOAD

1V/div

20mA/div

0

100µs/div

10ms/div

RESIDUAL SWITCHING NOISE

ON THE LDO OUTPUT

INPUT-VOLTAGE STEP RESPONSE

MAX15014 toc38

MAX15014 toc37

DC-DC

= 1A

LOAD

MAX15015B

= 1mA

I

LOAD

V

IN

20V/div

V

LDO_OUT

10mV/div

0V

V

LDO_OUT

AC-COUPLED

100mV/div

400ns/div

1ms/div

______________________________________________________________________________________ 11

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

Pin Description

NAME

FUNCTION

MAX15014/

MAX15017

MAX15015/

MAX15016

1, 2, 3, 9, 12,

14, 16, 19, 24, 14, 16, 19, 24,

26, 27, 30, 35 26, 27, 30, 35

N.C.

I.C.

No Connection. Not internally connected. Leave unconnected or connect to SGND.

Internally Connected. Leave unconnected.

23, 28

—

Active-Low Reset Output. When the rising V

voltage crosses the reset

LDO_OUT

4

RESET

threshold, RESET goes high after an adjustable delay. Pull up RESET to LDO_OUT

with at least 4kΩ. RESET is an active-low open-drain output.

Signal Ground Connection. Connect SGND and PGND together at one point near

the input bypass capacitor negative terminal.

5

6

5

6

SGND

CT

Reset Timeout Delay Capacitor Connection. CT is pulled low during reset. When out

of reset, CT is pulled up to an internal 3.6V rail with a 2µA current source. When the

rising CT voltage reaches the trip threshold (typically 1.24V), RESET is deasserted.

When EN_SYS is low or in thermal shutdown, CT is low.

4–MAX5017

Switching Regulator Enable Input (Active High). If EN_SW is high and EN_SYS is

high, the switching power supply is enabled. EN_SW is internally pulled down to

SGND through a 0.5µA current sink.

7

8

7

8

EN_SW

EN_SYS

Active-High System Enable Input. Connect EN_SYS high to turn on the system. The

LDO is active if EN_SYS is high; once EN_SYS is high, the switching regulator can

be turned on if EN_SW is high. EN_SYS is internally pulled down to SGND through a

0.5µA current sink.

LDO Feedback Input/Output Voltage Setting. Connect SET_LDO to SGND to select

10

11

10

11

SET_LDO the preset output voltage (5V or 3.3V). Connect SET_LDO to an external resistor-

divider network for adjustable output operation.

Linear Regulator Output. Bypass with at least 10µF low-ESR capacitor from

LDO_OUT LDO_OUT to SGND. In the 5V LDO versions (A), the LDO operates in dropout below

6V down to the UVLO trip point.

LDO Input Voltage. The input voltage range for the LDO extends from 5V to 40V.

Bypass with a 0.1µF ceramic capacitor to SGND.

13

15

13

15

IN_LDO

High-Side Gate Driver Supply. Connect BST to the cathode of the bootstrap diode

and to the positive terminal of the bootstrap capacitor.

BST

Source Connection of Internal High-Side Switch. Connect both LX pins to the

inductor and the cathode of the freewheeling diode.

17, 18

20, 21

17, 18

20, 21

LX

Drain Connection of the Internal High-Side Switch. Connect both DRAIN inputs

together.

DRAIN

Power Ground Connection. Connect the input bypass capacitor negative terminal,

the anode of the freewheeling diode, and the output filter capacitor negative terminal

to PGND. Connect PGND to SGND together at a single point near the input bypass

22

PGND

capacitor negative terminal.

12 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

Pin Description

NAME

C-

FUNCTION

MAX15014/

MAX15017

MAX15015/

MAX15016

—

23

Charge-Pump Flying Capacitor Negative Connection (MAX15015/MAX15016 only)

Gate Drive Supply for the High-Side MOSFET Driver. Connect to REG and to the

anode of the bootstrap diode for MAX15014/MAX15017. Connect to REG for

MAX15015/MAX15016.

25

DVREG

Charge-Pump Flying Capacitor Positive Connection (MAX15015/MAX15016 only).

Connect to the positive terminal of the external pump capacitor and to the anode of

the bootstrap diode.

—

28

C+

Oscillator Synchronization Input. SYNC can be driven by an external clock to

synchronize the switching frequency. Connect SYNC to SGND when not used.

29

31

29

31

SYNC

COMP

Error Amplifier Output. Connect COMP to the compensation feedback network.

Feedback Regulation Point. Connect to the center tap of a resistive divider from

converter output to SGND to set the output voltage. The FB voltage regulates to the

voltage present at SS (1.235V).

32

FB

Soft-Start and Reference Output. Connect a capacitor from SS to SGND to set the

33

34

36

—

33

34

36

—

SS

REG

IN_SW

EP

soft-start time. See the Applications Information section to calculate the value of the

C

capacitor.

SS

Internal Regulator Output. 5V output for the MAX15015/MAX15016 and 8V output for the

MAX15014/MAX15017. Bypass to SGND with at least a 1µF ceramic capacitor.

Supply Input Connection. Connect to IN_LDO and an external voltage source from

4.5V to 40V. EN_SW and EN_SYS must be high and IN_SW must be above its UVLO

threshold for operation of the switching regulator.

Exposed Pad. The exposed pad must be electrically connected to SGND. For an

effective heatsinking, solder the exposed pad to a large copper plane.

______________________________________________________________________________________ 13

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

current falls to 6µA. Additional features include a pro-

Detailed Description

grammable soft-start, cycle-by-cycle current limit,

The MAX15014–MAX15017 combine a voltage-mode

hiccup-mode output short-circuit protection, and thermal

buck converter with an internal 0.5Ω power MOSFET

shutdown.

switch and a low-quiescent-current LDO regulator. The

The LDO linear regulator operates from 5V to 40V and

delivers a guaranteed 50mA load current. The devices

feature a preset output voltage of 5.0V (MAX1501_A) or

3.3V (MAX1501_B). Alternatively, the output voltage

can be adjusted from 1.5V to 11V using an external

resistive divider. The LDO section also features a

RESET output with adjustable timeout period.

buck converter of the MAX15015/MAX15016 has a

wide input voltage range of 4.5V to 40V. The

MAX15014/MAX15017’s input voltage range is 7.5V to

40V. Fixed switching frequencies of 135kHz and

500kHz are available. The internal low R

switch

DS_ON

allows for up to 1A of output current, and the output

voltage can be adjusted from 1.26V to 32V. External

compensation and voltage feed-forward simplify loop

compensation design and allow for a wide variety of L

and C filter components. All devices offer an automatic

switchover to pulse-skipping (PFM) mode, providing

low quiescent current and high efficiency at light loads.

Under no load, PFM mode operation reduces the cur-

rent consumption to 5.6mA for the MAX15014/

MAX15017 and 8.6mA for the MAX15015/MAX15016. In

shutdown (DC-DC and LDO regulator off), the supply

Enable Inputs and UVLO

The MAX15014–MAX15017 feature two logic inputs,

EN_SW (active-high) and EN_SYS (active-high) that can

be used to enable the switching power supply and the

LDO_OUT outputs. When V

is higher than the

EN_SW

threshold and EN_SYS is high, the switching power sup-

ply is enabled. When EN_SYS is high, the LDO is active.

When EN_SYS is low, the entire chip is off (see Table 1).

4–MAX5017

IN_SW

EN_SYS

IN_LDO

C-

C+

DVREG

IN_LDO

MAX15015/MAX15016

7.0V OR 4.1V

LEVEL

SHIFT

PCLK

UVLO_SW

UVLO_LDO

V

REFOK

V

INT

INTOK

LDO_OUT

SET_LOD

-

PASS ELEMENT

+

4.1V

REG

+

V

REG_LDO

REFOK

INT

PREREG

V

INTOK

VINT

V

INTOK

ENABLE LDO

-

MUX

V

REF

V

REF

+

VREG_OK

EN_SW

V

REG_EN

UVLO_SW

TSD

SHDN

-

SHDN

V

INT

V

INT

V

INT

2µA

OUT_LDO

UVLO_LDO

TSD

185mV

V

INT

V

INT

-

SHDN

-

RESET

V

REF

I

SS

THERMAL

SHDN

V

TSD

REF

+

REF

0.925 x V

REF

+

V

REFOK

DELAY COMPARATOR

CT

EN

VREG_ OK

DRAIN

+

SS

FB

+

E/A

-

+

SSA

-

REF_ILIM

+

HIGH-SIDE

CURRENT

SENSE

V

REF

PFM

-

REF_PFM

OVERLOAD

MANAGEMENT

BST

LX

COMP

CLK

OVERL

IN S/W

RAMP

-

DVREG

CPWM

LOGIC

SYNC

SGND

EN

OSC

-

+

PFM

SCLK

PCLK

0.3V

PGND

CLK

Figure 1. MAX15015/MAX15016 Simplified Block Diagram

14 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

IN_SW

EN_SYS

IN_LDO

MAX15014/MAX15017

7.0V OR 4.1V

UVLO_SW

UVLO_LDO

V

REFOK

V

INT

INTOK

-

PASS ELEMENT

+

LDO_OUT

SET_LOD

4.1V

+

V

REG_LDO

REG

REFOK

INT

PREREG

V

INTOK

VINT

V

INTOK

ENABLE LDO

-

MUX

V

REF

V

+

REF

VREG_OK

V

REG_EN

UVLO_SW

TSD

SHDN

-

EN_SW

SHDN

V

INT

V

INT

V

INT

2µA

OUT_LDO

UVLO_LDO

TSD

SHDN

185mV

V

INT

-

V

I

REF

SS

THERMAL

SHDN

V

TSD

REF

+

RESET

REF

0.925 x V

REF

+

REFOK

DELAY COMPARATOR

EN

CT

VREG_ OK

+

DRAIN

+

E/A

-

+

SSA

-

SS

FB

-

REF_ILIM

+

HIGH-SIDE

CURRENT

SENSE

ILIM

V

REF

PFM

-

REF_PFM

OVERLOAD

MANAGEMENT

CLK

BST

LX

COMP

OVERL

IN S/W

RAMP

-

DVREG

CPWM

LOGIC

EN

OSC

-

+

SYNC

SGND

PFM

SCLK

PCLK

0.3V

CLK

PGND

Figure 2. MAX15014/MAX15017 Simplified Block Diagram

Table 1. Enable Inputs Configuration

DC-DC SWITCHING

CONVERTER

EN_SYS

EN_SW

LDO REGULATOR

Low

High

Low

High

Low

High

Off

On

Off

On

The MAX15014–MAX15017 provide undervoltage lock-

out (UVLO). The UVLO monitors the input voltage

IN_LDO

Connect REG externally to DVREG to provide power for

the high-side MOSFET gate driver. Bypass REG to

(V

) and is fixed at 4.1V (MAX15015/MAX15016)

SGND with a ceramic capacitor (C

) of at least 1µF.

REG

or 7V (MAX15014/MAX15017).

Place the capacitor physically close to the MAX15014–

MAX15017 to provide good bypassing. During normal

operation, REG is intended for powering up only the

internal circuitry and should not be used to supply

power to external loads.

Internal Linear Regulator (REG)

REG is the output terminal of a 5V (MAX15015/

MAX15016), or 8V (MAX15014/MAX15017) LDO which

is powered from IN_SW and provides power to the IC.

______________________________________________________________________________________ 15

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

80dB open-loop gain and a 1.8MHz GBW product. See

the Typical Operating Characteristics for the Gain and

Phase vs. Frequency graph.

Soft-Start and Reference (SS)

SS is the 1.235V reference bypass connection for the

MAX15014–MAX15017 and also controls the soft-start

period. At startup, after input voltage is applied at IN_SW,

IN_LDO and the UVLO thresholds are reached, the

device enters soft-start. During soft-start, 14µA is sourced

Oscillator/Synchronization Input (SYNC)

With SYNC connected to SGND, the MAX15014–

MAX15017 use their internal oscillator and switch at a

fixed frequency of 135kHz and 500kHz. The MAX15014/

MAX15016 are the 135kHz options and MAX15015/

MAX15017 are the 500kHz options. For external syn-

chronization, drive SYNC with an external clock from

400kHz to 600kHz (MAX15015/MAX15017) or 100kHz

to 200kHz (MAX15014/MAX15016). When driven with

an external clock, the device synchronizes to the rising

edge of SYNC.

into the capacitor (C ) connected from SS to SGND

SS

causing the reference voltage to ramp up slowly. When

V

reaches 1.244V, the output becomes fully active. Set

SS

the soft-start time (t ) using following equation:

SS

V

×C

SS

I

t

=

SS

where V = soft-start reference voltage = 1.235V (typ),

SS

-6

I

= soft-start current = 14 x 10 A (typ), t is in sec-

PWM Comparator/Voltage Feed-Forward

An internal ramp generator clocked by the internal

oscillator is compared against the output of the error

amplifier to generate the PWM signal. The maximum

SS

onds and C is in Farads.

SS

Internal Charge Pump

(MAX15015/MAX15016)

amplitude of the ramp (V ) automatically adjusts to

RAMP

The MAX15015/MAX15016 feature an internal charge

pump to enhance the turn-on of the internal MOSFET,

allowing for operation with input voltages down to 4.5V.

compensate for input voltage and oscillator frequency

changes. This causes the V / V to be a

4–MAX5017

IN_SW

RAMP

constant 10V/V across the input voltage range of 4.5V to

40V (MAX15015/MAX15016) or 7.5V to 40V (MAX15014/

MAX15017) and the SYNC frequency range of 400kHz

to 600kHz (MAX15015/MAX15017) or 100kHz to 200kHz

(MAX15014/MAX15016).

Connect a flying capacitor (C ) between C+ and C-, a

F

boost diode from C+ to BST, as well as a bootstrap

capacitor (C

) between BST and LX to provide the

BST

gate drive voltage for the high-side n-channel DMOS

switch. During the on-time, the flying capacitor is

charged to V . During the off-time, the positive ter-

DVREG

Output Short-Circuit Protection

(Hiccup Mode)

minal of the flying capacitor (C+) is pumped to two times

and charge is dumped onto C to provide

V

The MAX15014–MAX15017 protect against an output

short circuit by utilizing hiccup-mode protection. In hic-

cup mode, a series of sequential cycle-by-cycle

current-limit events cause the part to shut down and

restart with a soft-start sequence. This allows the

device to operate with a continuous output short circuit.

DVREG

BST

twice the regulator voltage across the high-side DMOS

driver. Use a ceramic capacitor of at least 0.1µF for

C

and C located as close as possible to the device.

F

BST

Gate Drive Supply (DVREG)

DVREG is the supply input for the internal high-side

MOSFET driver. The power for DVREG is derived from

the output of the internal regulator (REG). Connect

DVREG to REG externally. To filter the switching noise,

the use of an RC filter (1Ω and 0.47µF) from REG to

DVREG is recommended. In the MAX15015/MAX15016,

the high-side drive supply is generated using the inter-

nal charge pump along with the bootstrap diode and

capacitor. In the MAX15014/MAX15017, the high-side

MOSFET driver supply is generated using only the boot-

strap diode and capacitor.

During normal operation, the current is monitored at the

drain of the internal power MOSFET. When the current

limit is exceeded, the internal power MOSFET turns off

until the next on-cycle and a counter increments. If the

counter counts seven consecutive current-limit events,

the device discharges the soft-start capacitor and

shuts down for 512 clock periods before restarting with

a soft-start sequence. Each time the power MOSFET

turns on and the device does not exceed the current

limit, the counter is reset.

LDO Regulator

The LDO regulator operates over an input voltage from

5V to 40V, and can be enabled independently of the

DC-DC converter section. Its quiescent current is as

low as 47µA with a load current of 100µA. All devices

Error Amplifier

The output of the internal error amplifier (COMP) is avail-

able for frequency compensation (see the Compensation

Design section). The inverting input is FB, the noninverting

input SS, and the output COMP. The error amplifier has an

16 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

feature a preset output voltage of 5V (MAX1501_A) or

3.3V (MAX1501_B). Alternatively, the output voltage

can be adjusted using an external resistive-divider net-

work connected between LDO_OUT, SET_LDO, and

SGND. See Figure 5.

Inductor Selection

Three key inductor parameters must be specified for

operation with the MAX15014–MAX15017: inductance

value (L), peak inductor current (I

), and inductor

PEAK

saturation current (I

). The minimum required induc-

SAT

tance is a function of operating frequency, input-to-out-

put voltage differential, and the peak-to-peak inductor

RESET Output

The RESET output is typically connected to the reset

input of a microprocessor (µP). A µP’s reset input starts

or restarts the µP in a known state. The MAX15014–

MAX15017 supervisory circuits provide the reset logic

to prevent code-execution errors during power-up,

power-down, and brownout conditions. RESET

changes from high to low whenever the monitored volt-

age drops below the RESET threshold voltage. Once

the monitored voltage exceeds its respective RESET

threshold voltage(s), RESET remains low for the RESET

timeout period, then goes high. The RESET timeout

current (∆I ). Higher ∆I

allows for a lower inductor

P-P

value while a lower ∆I

requires a higher inductor

P-P

value. A lower inductor value minimizes size and cost

and improves large-signal and transient response, but

reduces efficiency due to higher peak currents and

higher peak-to-peak output voltage ripple for the same

output capacitor. On the other hand, higher inductance

increases efficiency by reducing the ∆I . Resistive

P-P

losses due to extra wire turns can exceed the benefit

gained from lower ∆I

levels especially when the

P-P

inductance is increased without also allowing for larger

inductor dimensions. A good compromise is to choose

period is adjustable with an external capacitor (C

connected to CT.

)

CT

∆I

equal to 40% of the full load current. Calculate the

P-P

inductor using the following equation:

Thermal-Shutdown Protection

The MAX15014–MAX15017 feature thermal shutdown

protection which limits the total power dissipation in the

device and protects it in the event of an extended ther-

mal fault condition. When the die temperature exceeds

+160°C, an internal thermal sensor shuts down the part,

turning off the DC-DC converter and the LDO regulator,

and allowing the IC to cool. After the die temperature

falls by 20°C, the part restarts with a soft-start sequence.

V

(V − V

)

OUT

OUT IN

L =

× f × ∆I

IN SW

P−P

V

IN

and V

are typical values so that efficiency is opti-

OUT

mum for typical conditions. The switching frequency

(f ) is internally fixed at 135kHz (MAX15014/

SW

MAX15016) or 500kHz (MAX15015/MAX15017) and

can vary when synchronized to an external clock (see

the Oscillator/Synchronization Input (SYNC) section).

Applications Information

The ∆I , which reflects the peak-to-peak output rip-

P-P

Setting the Output Voltage

Connect a resistive divider (R3 and R4, see Figures 6

and 7) from OUT to FB to SGND to set the output volt-

age. Choose R3 and R4 so that DC errors due to the FB

input bias current do not affect the output-voltage

setting precision. For the most common output-voltage

settings (3.3V or 5V), R3 values in the 10kΩ range are

adequate. Select R3 first and calculate R4 using the

following equation:

ple, is worst at the maximum input voltage. See the

Output-Capacitor Selection section to verify that the

worst-case output ripple is acceptable. The inductor

current (I

) is also important to avoid current run-

SAT

away during continuous output short circuit. Select an

inductor with an I specification higher than the

SAT

maximum peak current limit of 2.6A.

Input-Capacitor Selection

The discontinuous input current of the buck converter

causes large input ripple currents and therefore the

input capacitor must be carefully chosen to keep the

input voltage ripple within design requirements. The

R3

R4 =

⎡

⎢

⎣

⎤

V

OUT

−1

⎥

FB

⎦

input voltage ripple is comprised of ∆V (caused by

Q

the capacitor discharge) and ∆V

(caused by the

ESR

where V = 1.235V.

FB

ESR of the input capacitor). The total voltage ripple is

the sum of ∆V and ∆V . Calculate the input capaci-

Q

ESR

tance and ESR required for a specified ripple using the

following equations:

______________________________________________________________________________________ 17

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

tance, its ESR, and its equivalent series inductance

∆V

ESR

(ESL). The output capacitor supplies the load current

during a load step until the controller responds with a

ESR =

∆I

P−P

2

I

+

OUT_MAX

greater duty cycle. The response time (t

)

RESPONSE

depends on the closed-loop bandwidth of the converter

(see the Compensation Design section). The resistive

drop across the output capacitor’s ESR, the drop

I

×D

OUT_MAX

C

=

IN

∆V ×f

Q

SW

across the capacitor’s ESL (∆V

), and the capacitor

ESL

where C is the sum of C

and additional decou-

IN

DRAIN

discharge causes a voltage droop during the loadstep.

pling capacitance at the buck converter input,

Use a combination of low-ESR tantalum/aluminum elec-

trolytic and ceramic capacitors for better transient load

and voltage ripple performance. Non-leaded capaci-

tors and capacitors in parallel help reduce the ESL.

Keep the maximum output voltage deviation below the

tolerable limits of the electronics being powered. Use

the following equations to calculate the required ESR,

ESL, and capacitance value during a load step:

(V − V )× V

IN

OUT

∆I

=

and

P−P

V

× f ×L

IN SW

V

OUT

D =

V

IN

I

is the maximum output current, D is the duty

OUT_MAX

cycle, and f

is the switching frequency.

SW

∆V

ESR

The MAX15014–MAX15017 include UVLO hysteresis

and soft-start to avoid chattering during turn-on.

However, use additional bulk capacitance if the input

source impedance is high. Use enough input capaci-

tance at lower input voltages to avoid possible under-

shoot below the undervoltage lockout threshold during

transient loading.

ESR =

I

STEP

I

× t

RESPONSE

4–MAX5017

STEP

C

=

OUT

∆V

Q

∆V

× t

STEP

ESL

I

ESL =

STEP

1

Output-Capacitor Selection

The allowable output voltage ripple and the maximum

deviation of the output voltage during load steps deter-

t

≅

RESPONSE

3ƒ

C

mine the output capacitance (C

) and its equivalent

where I

is the load step, t

is the rise time of the

OUT

STEP

load step, t

STEP

series resistance (ESR). The output ripple is mainly

is the response time of the con-

RESPONSE

composed of ∆V (caused by the capacitor discharge)

troller and f is the closed-loop crossover frequency.

Q

C

and ∆V

(caused by the voltage drop across the ESR

ESR

Compensation Design

The MAX15014–MAX15017 use a voltage-mode control

scheme that regulates the output voltage by comparing

the error amplifier output (COMP) with an internal ramp

to produce the required duty cycle. The output lowpass

LC filter creates a double pole at the resonant frequency,

which has a gain drop of -40dB/decade. The error

amplifier must compensate for this gain drop and

phase shift to achieve a stable closed-loop system.

of the output capacitor). The equations for calculating

the peak-to-peak output voltage ripple are:

∆I

P−P

∆V

=

Q

8×C

×f

OUT SW

∆V

= ESR× ∆I

P−P

ESR

Normally, a good approximation of the output voltage rip-

ple is ∆V = ∆V + ∆V . If using ceramic capaci-

RIPPLE

ESR

Q

The basic regulator loop consists of a power modulator,

an output feedback divider, and a voltage error amplifier.

tors, assume the contribution to the output voltage ripple

from ESR and the capacitor discharge to be equal to 20%

The power modulator has a DC gain set by V

RAMP

/

IN

and 80%, respectively. ∆I

is the peak-to-peak inductor

P-P

V

, with a double pole and a single zero set by the

current (see the Input-Capacitor Selection section) and

is the converter’s switching frequency.

output inductance (L), the output capacitance (C

),

OUT

f

SW

and its ESR. The power modulator incorporates a voltage

feed-forward feature, which automatically adjusts for vari-

ations in the input voltage resulting in a DC gain of 10.

The allowable deviation of the output voltage during

fast load transients also determines the output capaci-

18 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

The following equations define the power modulator:

C8

V

IN

G

=

=10

MOD_DC

C7

V

R5

RAMP

C6

R6

1

f

=

LC

2× π × L ×C

OUT

R3

1

V

OUT

f

=

ZESR

2× π ×C

×ESR

EA

OUT

COMP

R4

REF

The switching frequency is internally set at 500kHz for

MAX15015/MAX15017 and can vary from 400kHz to

600kHz when driven with an external SYNC signal. The

switching frequency is internally set at 135kHz for

MAX15014/MAX15016 and can vary from 100kHz to

200kHz when driven with an external sync signal. The

crossover frequency (fC), which is the frequency when

the closed-loop gain is equal to unity, should be set to

around 1/10 of the switching frequency or below.

GAIN

(dB)

CLOSED-LOOP

GAIN

EA

GAIN

The crossover frequency occurs above the LC double-

pole frequency, and the error amplifier must provide a

gain and phase bump to compensate for the rapid gain

and phase loss from the LC double pole, which exhibits

little damping.

f

f f

P2 P3

Z1 Z2

C

FREQUENCY

Figure 3. Error Amplifier Compensation Circuit (Closed-Loop

and Error-Amplifier Gain Plot) for Ceramic Capacitors

This is accomplished by utilizing a Type 3 compensator

that introduces two zeroes and three poles into the con-

trol loop. The error amplifier has a low-frequency pole

value and tend to be more expensive. Aluminum elec-

trolytic capacitors have much larger ESR but can reach

much larger capacitance values.

(f ) near the origin so that tight voltage regulation at DC

P1

can be achieved.

The two zeroes are at:

Compensation when f < f

C

ZESR

This is usually the case when a ceramic capacitor is

selected. In this case, f occurs after f . Figure 3

1

f

=

ZI

ZESR

C

2π ×R5×C7

shows the error amplifier feedback as well as its gain

response.

and

f

is set to 0.5 to 0.8 x f and f is set to f to com-

LC Z2 LC

Z1

1

f

=

Z2

pensate for the gain and phase loss due to the double

pole. To achieve a 0dB crossover with -20dB/decade

2π ×(R3+R6)×C6

slope, poles f and f are set above the crossover fre-

quency f .

P2

P3

and the higher frequency poles are at:

1

C

The values for R3 and R4 are already determined in the

Setting the Output Voltage section. The value of R3 is

also used in the following calculations.

f

=

P2

2π ×R6×C6

and

1

Since f < f < f , then R3 >> R6, and R3 + R6 can

be approximated as R3.

Z2

C

P2

f

=

P3

C7×C8

C7+C8

2π ×R5×

Now we can calculate C6 for zero f

:

Z2

The compensation design primarily depends on the

type of output capacitor. Ceramic capacitors exhibit

very low ESR, and are well suited for high-switching-

frequency applications, but are limited in capacitance

1

C6 =

2π × f ×R3

LC

______________________________________________________________________________________ 19

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

f

occurs between f and f . In this region, the com-

Z2 P2

C

C8

pensator gain (G ) at f is due primarily to C6 and R5.

EA

C

Therefore, G (f ) = 2π x f x C6 x R5 and the modula-

tor gain at f is:

EA C

C

C7

R5

C

C6

R6

G

MOD_DC

2

G

(f ) =

MOD C

R3

(2π × f ) ×L ×C

C

OUT

V

OUT

Since G (f ) x G

(f ) = 1, R5 is calculated by:

MOD C

EA C

EA

COMP

R4

REF

f ×L ×C

×2π

OUT

C

R5 =

C6×G

MOD_DC

GAIN

(dB)

The frequency of f is set to 0.5 x f and now we can

Z1

LC

CLOSED-LOOP

GAIN

calculate C7:

EA

GAIN

1

C7 =

0.5×2π ×R5× f

LC

f

is set at 1/2 the switching frequency (f ). R6 is

SW

P2

then calculated by:

4–MAX5017

f

P3

Z1 Z2

P2

C

FREQUENCY

1

Figure 4. Error Amplifier Compensation Circuit (Closed-Loop

and Error-Amplifier Gain Plot) for Higher ESR Output

Capacitors

R6 =

2π ×C6×(0.5× f

)

SW

Note that if the crossover frequency has been chosen

as 1/10 of the switching frequency, then f = 5xf .

frequency is higher than f but lower than the closed-

LC

P2

C

loop crossover frequency. The equations that define

The purpose of f is to further attenuate the residual

P3

switching ripple at the COMP pin.

the error amplifier’s poles and zeros (f , f , f , and

Z1 Z2 P2

f

P3

) are the same as before. However, f is now lower

P2

If the ESR zero (f

) occurs in a region between

ZESR

than the closed-loop crossover frequency. Figure 4

shows the error amplifier feedback as well as its gain

response for circuits that use higher-ESR output capac-

itors (tantalum or aluminum electrolytic).

f

and f

/ 2, then f can be used to cancel it. This

C

SW P3

way, the Bode plot of the loop gain plot will not flatten

out soon after the 0dB crossover, and will maintain

its -20dB/decade slope up to 1/2 of the switching

frequency.

Again, starting from R3, calculate C6 for zero f

:

Z2

If the ESR zero well exceeds f /2 (or even f ), f

P3

SW

1

C6 =

should in any case be set high enough not to erode the

phase margin at the crossover frequency. For example,

2π × f ×R3

LC

it can be set between 5 x f and 10 x f .

C

and then place f to cancel the ESR zero. R6 is calcu-

P2

The value for C8 is calculated from:

lated as:

C7

C8 =

C

×ESR

C6

OUT

R6 =

(2π ×C7×R5× f −1)

P3

If the value obtained here for R6 is not considerably

smaller than R3, then recalculate C6 using (R3 + R6) in

place of R3. Then use the new value of C6 to obtain a

better approximation for R6. The process can be further

Compensation when f > f

C

ZESR

For larger ESR capacitors such as tantalum and alu-

minum electrolytic, f can occur before f . If f

ZESR

C

ZESR

< f , then f occurs between f and f . f and f

C

P2

P3 Z1

Z2

iterated, and convergence is ensured as long as f <

LC

remain the same as before however, f

is now

P2

f .

ZESR

set equal to f

. The output capacitor’s ESR zero

ZESR

20 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

The error amplifier gain between f and f is approxi-

P2

P3

V

IN_LDO

mately equal to R5 / (R6 || R3).

The ESR zero frequency f

might not be very much

ZESR

higher than the double-pole frequency f , therefore

LC

IN_LDO

the value of R5 can be calculated as:

2

LDO_OUT

SET_LDO

R3×R6

R3+R6

f

C

R5 =

×

2

G

× f

MOD_DC LC

R1

R2

MAX15014–

MAX15017

C7 can still be calculated as:

1

C7 =

0.5×2π ×R5× f

LC

SGND

f

P3

is set at 5xf . Therefore, C8 is calculated as:

C

C7

Figure 5. Setting the Output Voltage Using a Resistive Divider

Connect CT to LDO_OUT to select the internally fixed

C8 =

2π ×C7×R5× f −1

P3

timeout period. C must be low-leakage-type capaci-

CT

Setting the LDO Linear

Regulator Output Voltage

tor. Ceramic capacitors are recommended; do not use

capacitors lower than 200pF to avoid the influence of

parasitic capacitances.

The MAX15014–MAX15017 LDO regulator features Dual

Mode™ operation: it can operate in either a preset voltage

mode or an adjustable mode. In preset voltage mode,

internal trimmed feedback resistors set the internal linear

regulator to 3.3V or 5V (see the Selector Guide). Select

preset voltage mode by connecting SET_LDO to ground.

In adjustable mode, select an output voltage between

1.5V and 11V using two external resistors connected as a

voltage-divider to SET_LDO (see Figure 5). Set the output

voltage using the following equation:

Capacitor Selection and

Regulator Stability

For stable operation over the full temperature range and

with load currents up to 50mA, use a 10µF (min) output

capacitor (C ) with a maximum ESR of 0.4Ω. To

LDO_OUT

reduce noise and improve load-transient response, sta-

bility, and power-supply rejection, use larger output

capacitor values. Some ceramic dielectrics such as Z5U

and Y5V exhibit very large capacitance and ESR varia-

tion with temperature and are not recommended. With

X7R or X5R dielectrics, 15µF should be sufficient for

operation over their rated temperature range. For higher-

ESR tantalum capacitors (up to 1Ω), use 22µF or more to

maintain stability. To improve power-supply rejection

and transient response use a minimum 0.1µF capacitor

between IN_LDO and SGND.

R1

R2

⎛

⎞

V

= V

1+

⎜

⎝

⎟

⎠

OUT

SET_LDO

where V

= 1.241V and the recommended value

SET_LDO

for R2 is around 50kΩ.

Setting the RESET Timeout Delay

The RESET timeout period is adjustable to accommo-

date a variety of µP applications. Adjust the RESET

timeout period by connecting a capacitor (C

between CT and SGND.

Power Dissipation

The MAX15014–MAX15017 are available in a thermally

enhanced package and can dissipate up to 2.86W at

)

CT

T

= +70°C. When the die temperature reaches

A

C

× V

+160°C, the part shuts down and is allowed to cool.

After the die cools by 20°C, the device restarts with a

soft-start. The power dissipated in the device is the

sum of the power dissipated in the LDO, power dissi-

CT− TH

CT

I

t

=

RP

CT− THQ

where V

= delay comparator threshold (rising) =

CT-TH

-6

= CT charge current = 2 x 10 A

CT-THQ

1.241V (typ), I

pated from supply current (P ), transition losses due to

switching the internal power MOSFET (P ), and the

SW

Q

(typ), t is in seconds and C is in Farads.

RP

Dual Mode is a trademark of Maxim Integrated Products, Inc.

______________________________________________________________________________________ 21

CT

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

C

DRAIN

IN_LDO

IN_SW

V

IN

R6

C6

R3

4.5V TO 40V

D1

C8

IN_LDO

IN_SW

DRAIN

C7

R5

BST

LX

COMP

FB

C

BST

L

V

AT 1A

OUT1

V

IN

EN_SW

5V TO 40V

R4

EN_SYS

C+

D2

C

OUT

MAX15015

MAX15016

C

F

C-

RESET

CT

SS

10kΩ

V

AT 50mA

SYNC

REG

OUT2

LDO_OUT

PGND SGND

C

4–MAX5017

C

LDO_OUT

SS

CT

1Ω

C

REG

DVREG

SET_LDO

0.47µF

PGND

SGND

Figure 6. MAX15015/MAX15016 Typical Application Circuit (4.5V to 40V Input Operation)

power dissipated due to the RMS current through the

internal power MOSFET (P ). The total power

R

is the on-resistance of the internal power MOSFET

ON

(see the Electrical Characteristics).

MOSFET

dissipated in the package must be limited such that the

junction temperature does not exceed its absolute max-

imum rating of +150°C at maximum ambient tempera-

ture. Calculate the power lost in the MAX15014–

MAX15017 using the following equations:

The power loss due to switching the internal MOSFET:

V

×I

×(t + t )×f

IN OUT R F SW

P

=

SW

4

The power loss through the switch:

t and t are the rise and fall times of the internal power

R

F

MOSFET measured at LX.

2

) ×R

RMS_MOSFET ON

P

= (I

MOSFET

The power loss due to the switching supply current (I ):

SW

D

3

2

⎡

⎣

⎤

⎥

⎦

I

=

× I

+(I ×I )+I

PK DC

RMS_MOSFET

⎢

P

= V

×I

Q

IN_SW SW

∆I

P−P

2

I

=I

+

PK

OUT

The power loss due to the LDO regulator:

= (V − V )×I

LDO_OUT

∆I

P−P

2

P

I

=I

−

LDO

IN_LDO

LDO_OUT

DC OUT

V

OUT

The total power dissipated in the device will be:

= P + P + P + P

LDO

D =

IN

P

TOTAL

MOSFET

SW

Q

22 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

C

DRAIN

IN_LDO

IN_SW

V

IN

R6

C6

R3

7.5V TO 40V

D1

C8

IN_LDO

IN_SW

DRAIN

C7

R5

BST

LX

COMP

FB

C

BST

L

V

AT 1A

OUT1

V

IN

EN_SW

7.5V TO 40V

R4

EN_SYS

D2

C

OUT

MAX15014

MAX15017

RESET

CT

SS

10kΩ

V

AT 50mA

SYNC

REG

OUT2

LDO_OUT

PGND SGND

C

LDO_OUT

SS

CT

1Ω

C

REG

DVREG

SET_LDO

0.47µF

PGND

SGND

Figure 7. MAX15014/MAX15017 Typical Application Circuit (7.5V to 40V Input-Voltage Operation)

______________________________________________________________________________________ 23

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

Pin Configuration

Chip Information

PROCESS: BiCMOS/DMOS

TOP VIEW

1

2

3

4

5

6

7

8

9

27

26

25

24

23

22

21

20

19

N.C.

+

N.C.

DVREG

N.C.

RESET

SGND

CT

C- (I.C.)

PGND

DRAIN

N.C.

MAX15014–MAX15017

EN_SW

EN_SYS

N.C.

EP*

TQFN

( ) MAX15014/MAX15017

*EP = EXPOSED PAD.

4–MAX5017

Selector Guide

LDO OUTPUT

SWITCHING

FREQUENCY (kHz)

DC-DC MINIMUM

INPUT VOLTAGE (V)

CHARGE

PUMP

PART

ADJUSTABLE

5V

3.3V

OUTPUT

MAX15014A

135

500

135

500

7.5

4.5

7.5

—

X

—

X

—

X

MAX15014B

MAX15015A

MAX15015B

MAX15016A

MAX15016B

MAX15017A

MAX15017B

—

X

—

X

—

X

—

X

—

X

—

24 ______________________________________________________________________________________

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

4–MAX5017

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

______________________________________________________________________________________ 25

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

Package Information (continued)

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

4–MAX5017

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX15014BATX+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators 1A ， 4.5V至40V输入降压型转换器，带有50毫安辅助LDO稳压器转换器稳压器开关式稳压器或控制器电源电路开关式控制器信息通信管理
文件：	总26页 (文件大小：810K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX15014BATX+ [MAXIM]

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