MAX15025CATB+ [MAXIM]
Single/Dual, 16ns, High Sink/source Current Gate Drivers; 单/双通道，16ns ，高吸入/源出电流栅极驱动器
| 型号： | MAX15025CATB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single/Dual, 16ns, High Sink/source Current Gate Drivers |
| 文件： | 总16页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1053; Rev 2; 4/10
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
General Description
Features
The MAX15024/MAX15025 single/dual, high-speed
MOSFET gate drivers are capable of operating at fre-
quencies up to 1MHz with large capacitive loads. The
MAX15024 includes internal source-and-sink output
transistors with independent outputs allowing for control
of the external MOSFET’s rise and fall time. The
MAX15024 is a single gate driver capable of sinking an
8A peak current and sourcing a 4A peak current. The
MAX15025 is a dual gate driver capable of sinking a 4A
peak current and sourcing a 2A peak current. An inte-
grated adjustable LDO voltage regulator provides gate-
drive amplitude control and optimization.
o 8A Peak Sink Current/4A Peak Source Current
(MAX15024)
o 4A Peak Sink Current/2A Peak Source Current
(MAX15025)
o Low 16ns Propagation Delay
o 4.5 V to 28V Supply Voltage Range
o On-Board Adjustable LDO for Gate-Drive
Amplitude Control and Optimization
o Separate Output Driver Supply
The MAX15024A and MAX15025A/C accept transistor-
to-transistor (TTL) input logic levels while the
MAX15024B and MAX15025B/D accept CMOS-input
logic levels. High sourcing/sinking peak currents, a low
propagation delay, and thermally enhanced packages
make the MAX15024/MAX15025 ideal for high-frequency
and high-power circuits. The MAX15024/
MAX15025 operate from a 4.5V to 28V supply. A sepa-
rate output driver supply input enhances flexibility and
permits a soft-start of the power MOSFETs used in syn-
chronous rectifiers.
o Independent Source and Sink Outputs (MAX15024)
o Matched Delays Between Inverting and
Noninverting Inputs (MAX15024)
o Matched Delays Between Channels (MAX15025)
o CMOS or TTL Logic-Level Inputs with Hysteresis
for Noise Immunity
o -40°C to +125°C Operating Temperature Range
o Thermal-Shutdown Protection
The MAX15024/MAX15025 are available in 10-pin
TDFN packages and are specified over the -40°C to
+125°C automotive temperature range.
o 1.95W Thermally Enhanced TDFN Power Packages
Applications
Ordering Information
Synchronous Rectifier Drivers
PART
PIN-PACKAGE
10 TDFN-EP**
10 TDFN-EP**
10 TDFN-EP**
10 TDFN-EP**
10 TDFN-EP**
10 TDFN-EP**
TOP MARK
ATX
Power-Supply Modules
MAX15024AATB+T
MAX15024BATB+T
MAX15025AATB+T
MAX15025BATB+T
MAX15025CATB+T
MAX15025DATB+T
Switching Power Supply
ATY
Pin Configurations
ATZ
AUA
TOP VIEW
AUB
AUC
10
9
8
7
6
Note: All devices are specified over the -40°C to +125°C operating
temperature range.
+Denotes a lead-free package.
**EP = Exposed pad. T = Tape and reel.
See the Selector Guide at the end of the data sheet.
MAX15024
EP*
1
2
3
4
5
TDFN
*EP = EXPOSED PAD.
Pin Configurations continued at end of data sheet.
Block Diagrams appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
ABSOLUTE MAXIMUM RATINGS
V
CC
to GND............................................................-0.3V to +30V
Continuous Power Dissipation (T = +70°C)
A
REG to GND..............-0.3V to the lower of +22V or (V + 0.3V)
10-Pin TDFN, Single-Layer Board
CC
DRV to PGND .........................................................-0.3V to +22V
IN_ ..........................................................................-0.3V to +22V
FB/SET to GND.........................................................-0.3V to +6V
P_OUT to DRV........................................................-22V to +0.3V
N_OUT to PGND.....................................................-0.3V to +22V
(derate 18.5mW/°C above +70°C)...........................1481.5mW
Junction-to-Case Thermal Resistance (Note 1) ..............8.5°C/W
10-Pin TDFN, Multilayer Board
(derate 24.4mW/°C above +70°C)...........................1951.2mW
Junction-to-Case Thermal Resistance (Note 1) ..............8.5°C/W
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
OUT1, OUT2 to PGND..............................-0.3V to (V
+ 0.3V)
DRV
PGND to GND .......................................................-0.3V to +0.3V
P_OUT, N_OUT Continuous Source/Sink Current* .......... 200mA
OUT1, OUT2 Continuous Source/Sink Current*................200mA
*Continuous output current is limited by the power dissipation of the package.
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, see www.maxim-ic.com/thermal.tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX15024 ELECTRICAL CHARACTERISTICS
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T =
REG A J A J
CC
DRV
+ 25°C). (Note 2)
4/MAX1025
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
V
V
powered only, V
=
CC
REG
MAX15024B
MAX15024A
6.5
4.5
28.0
28.0
decoupled with
DRV
minimum 1µF to GND
Input Voltage Range
V
V
CC
V
V
V
= V
= V
= V
= V
= V
(MAX15024B)
(MAX15024A)
6.5
4.5
18.0
18.0
2.3
CC
CC
CC
REG
REG
REG
DRV
DRV
V
Turn-On Voltage
V
_
= 10V, IN+ = V , IN- = GND
1.7
V
DRV
DRV ON
CC
Quiescent Supply Current
IN_ = V
or GND
700
1350
µA
CC
Quiescent Supply Current
Under UVLO Condition
IN_ = V
or GND
250
µA
CC
Switching Supply Current
Switching at 250kHz, C = 0F
1.5
3.4
3.0
3.8
mA
V
L
V
Undervoltage Lockout
UVLO_ V
V
rising
3.0
CC
CC
CC
V
Undervoltage-Lockout
CC
300
mV
µs
Hysteresis
Undervoltage Lockout to
V
V
rising
falling
100
2
CC
CC
V
CC
Output Delay
REG REGULATOR (V
Output Voltage
= 12V, REG = V
, C = 1µF, FB/SET = GND)
L
CC
DRV
9
10
0.4
0.2
11
0.9
0.5
V
V
V
12V < V
< 28V, 0 < I
< 10mA
LOAD
REG
CC
V
V
V
= 6.5V, I
= 4.5V, I
= 100mA
CC
LOAD
Dropout Voltage
V _
R DO
= 50mA
CC
CC
LOAD
Load Regulation
Line Regulation
= 12V, I
= 0 to 100mA
1
%
LOAD
12V < V
< 28V
10
mV
CC
External resistive divider connected at
FB/SET
FB/SET Reference Voltage
1.10
-125
1.23
220
1.35
V
FB/SET Threshold
V
V
falling
mV
nA
FB
FB
FB/SET Input Leakage Current
= 4.5V (Note 3)
+125
2
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T =
CC
DRV
REG
A
J
A
J
+ 25°C). (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER OUTPUT (SINK)
T
T
= +25°C
0.45
0.60
A
V
= V
= V
= 10V,
= 4.5V,
CC
REG
DRV
sinking 100mA
= +125°C
0.625
0.850
A
Driver Output Resistance
R
Ω
ON-N
V
= V = V
CC
REG
DRV
T
= +25°C
0.50
0.65
0.9
A
A
sinking 100mA
(MAX15024A)
T
= +125°C
0.7
8
Peak Output Current
I
V
= 10V
A
PK-N
N_OUT
2
SOA condition: C x V
≤ 20µJ,
L
DRV
Maximum Load Capacitance
200
500
nF
for V
= 10V
DRV
Latchup Robustness
mA
DRIVER OUTPUT (SOURCE)
T
T
= +25°C
0.875
1.2
1.500
2.0
A
V
= V
= V
= 10V,
= 4.5V,
CC
REG
DRV
sourcing 100mA
= +125°C
A
Driver Output Resistance
R
Ω
ON-P
V
= V = V
CC
REG
DRV
T
= +25°C
0.95
1.25
1.65
2.20
A
A
sourcing 100mA
(MAX15024A)
T
= +125°C
Peak Output Current
Latchup Robustness
LOGIC INPUTS
I
V
= 0V
4
A
PK-P
P_OUT
500
mA
MAX15024A
MAX15024B
MAX15024A
MAX15024B
MAX15024A
MAX15024B
2.0
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic Input Hysteresis
V
V
V
V
IH
4.25
0.8
2
V
IL
0.4
1
Logic Input Current Leakage
Input Capacitance
V
= 18V or V
-75
0.01
10
+75
µA
pF
IN
GND
SWITCHING CHARACTERISTICS FOR V
(see Figure 1)
= V
= V
= 10V, P_OUT AND N_OUT ARE CONNECTED TOGETHER
CC
DRV
REG
C
C
C
C
C
C
C
C
= 1nF
3
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
Rise Time
Fall Time
t
= 5nF
12
24
3
ns
ns
R
= 10nF
= 1nF
t
= 5nF
8
F
= 10nF
16
16
16
Turn-On Delay Time
Turn-Off Delay Time
t
= 1nF (Note 3)
= 1nF (Note 3)
8
8
32
32
ns
ns
D-ON
t
D-OFF
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
C
= 1nF (Note 3)
-9
1
+9
ns
LOAD
_______________________________________________________________________________________
3
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15024 ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T
=
CC
DRV
REG
A
J
A
J
+ 25°C). (Note 2)
PARAMETER
SWITCHING CHARACTERISTICS FOR V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
= V
= V
REG
= 4.5V (see Figure 1) (MAX15024A)
CC
DRV
C
C
C
C
C
C
C
C
= 1nF
= 5nF
= 10nF
= 1nF
= 5nF
= 10nF
= 1nF
= 1nF
3
11
22
2.5
8
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
Rise Time
Fall Time
t
R
t
ns
F
16
18
18
Turn-On Delay Time
Turn-Off Delay Time
t
ns
ns
D-ON
t
D-OFF
Mismatch Propagation Delays
from Inverting and Noninverting
Inputs to Output
C
= 1nF
2
ns
ns
LOAD
Minimum Input Pulse Width that
Changes the Output
t
15
PW
4/MAX1025
THERMAL CHARACTERISTICS
Thermal-Shutdown
Temperature
Temperature rising
+160
15
°C
°C
Thermal-Shutdown
Temperature Hysteresis
MAX15025 ELECTRICAL CHARACTERISTICS
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T =
REG A J A J
CC
DRV
+25°C). (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
V
V
powered only,
CC
MAX15025B/D
6.5
4.5
28
28
= V
decoupled
REG
DRV
with minimum 1µF
to GND
Input Voltage Range
V
MAX15025A/C
(MAX15025B/D)
V
V
CC
V
V
= V
= V
= V
= V
6.5
4.5
18.0
18.0
CC
CC
REG
REG
DRV
(MAX15025A/C)
DRV
V
= V
= 10V, IN1 = V , IN2 = V
REG CC CC
CC
V
Turn-On Voltage
V
_
DRV ON
1.7
2.3
DRV
(MAX15025A/B) or GND for (MAX15025C/D)
Quiescent Supply Current
IN_ = V
or GND
or GND
700
250
1350
µA
µA
CC
CC
Quiescent Supply Current
Under UVLO Condition
IN_ = V
Switching Supply Current
Switching at 250kHz, C = 0F
1.5
3.4
3.0
3.8
mA
V
L
V
Undervoltage Lockout
UVLO_ V
V rising
CC
3.0
CC
CC
4
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T =
REG A J A J
CC
DRV
+25°C). (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Undervoltage-Lockout
CC
300
mV
Hysteresis
V
V
rising
100
2
V
Undervoltage Lockout to
CC
CC
CC
µs
Output Delay
falling
REG REGULATOR (V
Output Voltage
= 12V, V
= V
, C = 1µF, FB/SET = GND)
L
CC
REG
DRV
V
12V < V
< 28V, 0 < I
< 10mA
9
10
0.4
0.2
1
11
0.9
0.5
V
V
REG
CC
LOAD
V
V
V
= 6.5V, I
= 4.5V, I
= 100mA
CC
CC
CC
LOAD
LOAD
Dropout Voltage
V _
R DO
= 50mA
Load Regulation
Line Regulation
= 12V, I
= 0 to 100mA
%
LOAD
12V < V
< 28V
10
mV
CC
External resistive divider connected at
FB/SET
FB/SET Reference Voltage
1.10
-125
1.23
220
1.35
V
FB/SET Threshold
V
V
rising
mV
nA
FB
FB
FB/SET Input Leakage Current
DRIVER OUTPUT SINK
= 4.5V
+125
T
T
= +25°C
1.0
1.6
V
= V
= V
= 10V,
= 4.5V,
A
CC
REG
DRV
sinking 100mA
= +125°C
1.25
2.10
A
Driver Output Resistance
R
Ω
ON-N
V
= V = V
CC
REG
DRV
T
= +25°C
1.10
1.65
2.2
A
A
sinking 100mA
(MAX15025A/C)
T
= +125°C
1.5
4
Peak Output Current
I
V
= 10V
A
PK-N
OUT_
2
SOA condition: C x V
≤ 20µJ,
L
DRV
Maximum Load Capacitance
100
500
nF
for V
= 10V
DRV
Latchup Robustness
mA
DRIVER OUTPUT SOURCE
T
T
= +25°C
1.75
2.25
2.50
3.50
A
V
= V
= V
= 10V,
= 4.5V,
CC
REG
DRV
sourcing 100mA
= +125°C
A
Driver Output Resistance
R
Ω
ON-P
V
= V = V
CC
REG
DRV
T
= +25°C
1.85
2.50
2.60
3.75
A
A
sourcing 100mA
(MAX15025A/C)
T
= +125°C
Peak Output Current
Latchup Robustness
LOGIC INPUTS
I
V
= 0V
2
A
PK-P
OUT_
500
mA
MAX15025A/C
MAX15025B/D
MAX15025A/C
MAX15025B/D
MAX15025A/C
MAX15025B/D
2.0
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic Input Hysteresis
V
V
V
V
IH
4.25
0.8
2
V
IL
0.4
1
Logic Input Current Leakage
Input Capacitance
V
= 18V or V
-75
+0.01
10
+75
µA
pF
IN
GND
_______________________________________________________________________________________
5
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
MAX15025 ELECTRICAL CHARACTERISTICS (continued)
(V
= V
= V
= 10V, FB/SET = GND, T = T = -40°C to +125°C, unless otherwise noted. Typical values are at T = T =
CC
DRV
REG
A
J
A
J
+25°C). (Note 2)
PARAMETER
SWITCHING CHARACTERISTICS FOR V
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
= V
= V = 10V (see Figure 1)
REG
CC
DRV
C
C
C
C
C
C
C
C
= 1nF
6
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
Rise Time
Fall Time
t
= 5nF
24
48
5
ns
R
= 10nF
= 1nF
t
ns
= 5nF
16
32
16
16
F
= 10nF
Turn-On Delay Time
Turn-Off Delay Time
t
= 1nF (Note 3)
= 1nF (Note 3)
8
8
32
32
ns
ns
D-ON
t
D-OFF
Mismatch Propagation Delays
Between 2 Channels
C
= 1nF (Note 3)
-9
1
+9
ns
LOAD
SWITCHING CHARACTERISTICS FOR V
= V
= V
= 4.5V (see Figure 1) (MAX15025A/C)
CC
DRV
REG
C
C
C
C
C
C
C
C
= 1nF
= 5nF
= 10nF
= 1nF
= 5nF
= 10nF
= 1nF
= 1nF
5
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
4/MAX1025
Rise Time
Fall Time
t
20
42
4
ns
ns
R
t
15
30
18
18
F
Turn-On Delay Time
Turn-Off Delay Time
t
ns
ns
D-ON
t
D-OFF
Mismatch Propagation Delays
Between 2 Channels
C
= 1nF
2
ns
ns
LOAD
Minimum Input Pulse Width that
Changes the Output
t
15
PW
THERMAL CHARACTERISTICS
Thermal-Shutdown Temperature
Temperature rising
+160
15
°C
°C
Thermal-Shutdown Temperature
Hysteresis
Note 2: All devices are 100% production tested at T = +25°C. Limits over temperature are guaranteed by design.
A
Note 3: Design guaranteed by bench characterization. Limits are not production tested.
6
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
FALL TIME vs. SUPPLY VOLTAGE
(WITH 5nF LOAD)
RISE TIME vs. SUPPLY VOLTAGE
(DUAL DRIVER WITH 5nF LOAD)
PROPAGATION DELAY TIME
vs. TEMPERATURE (1nF LOAD)
30
25
20
15
10
40
30
20
10
0
18
16
14
12
10
8
MAX15025
MAX15025
T
= +125°C
A
RISING
T
= +85°C
A
T
= +125°C
A
T
= +85°C
= +25°C
A
T
FALLING
T
= +25°C
A
T
= 0°C
A
A
T
= -40°C
A
T
= 0°C
A
T
= -40°C
A
6
10
12
14
16
18
20
10 11 12 13 14 15 16 17 18 19 20
SUPPLY VOLTAGE (V)
-60 -40 -20
0
20 40 60 80 100 120 140
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(PROGRAMMED EXTERNALLY TO 5V)
SUPPLY CURRENT
vs. LOAD CAPACITANCE
SUPPLY CURRENT
vs. TEMPERATURE
2500
2000
1500
1000
500
1800
1600
1400
1200
1000
800
30
24
18
12
6
V
= V = V = 10V
REG DRV
V
= V = V = 10V
DRV
CC
CC
REG
1MHz
500kHz
SWITCHING
250kHz
SWITCHING
250kHz
75kHz
100kHz
600
NOT SWITCHING
NOT SWITCHING
400
40kHz
200
0
0
0
0
2
4
6
8
10 12 14 16 18 20
-40
0
40
TEMPERATURE (°C)
80
120
0
2000
4000
6000
8000 10,000
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (nF)
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE (TTL)
SUPPLY CURRENT
vs. LOGIC IN
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF RISING)
MAX15024/25 toc09
3.0
2.5
2.0
1.5
1.0
0.5
0
1600
1400
1200
1000
800
MAX15025
INPUT
LOW TO HIGH
IN_
1V/div
RISING
OUT_
5V/div
INPUT
HIGH TO LOW
600
FALLING
400
200
00
4
8
12
16
20
0
1
2
3
4
5
6
20ns/div
SUPPLY VOLTAGE (V)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
7
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
LOGIC INPUT VOLTAGE vs. OUTPUT VOLTAGE
(5nF FALLING)
(10nF RISING)
(10nF FALLING)
MAX15024/25 toc10
MAX15024/25 toc11
MAX15024/25 toc12
MAX15025
MAX15025
MAX15025
IN_
1V/div
IN_
1V/div
IN_
1V/div
OUT_
5V/div
OUT_
5V/div
OUT_
5V/div
20ns/div
20ns/div
20ns/div
4/MAX1025
PROPAGATION DELAY MISMATCH
vs. TEMPERATURE
LINE REGULATION OF V
(PROGRAMMED EXTERNALLY TO 5.04V)
REG
LOAD REGULATION OF V
REG
11.0
10.5
10.0
9.5
3.0
2.5
2.0
1.5
1.0
0.5
0
5.3
5.2
5.1
5.0
4.9
4.8
4.7
9.0
0
20 40 60 80 100 120 140 160 180 200
LOAD CURRENT (mA)
-40
0
40
80
120
5
10
15
20
25
30
TEMPERATURE (°C)
SUPPLY VOLTAGE
FB/SET CURRENT
vs. TEMPERATURE
FB/SET VOLTAGE
vs. TEMPERATURE
20
15
10
5
1.240
1.238
1.236
1.234
1.232
1.230
0
0
20
40
60
80
100
120
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
8
_______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
Pin Description
PIN
NAME
FUNCTION
MAX15025A MAX15025C
MAX15025B MAX15025D
MAX15024
LDO Regulator Output Set. Feedback for V
adjustment (V > 200mV).
FB
REG
1
1
2
1
2
FB/SET Connect FB/SET to GND for a fixed 10V output REG. Connect FB/SET to a
resistor ladder to set V
.
REG
Power-Supply Input. Bypass to GND with a low-ESR ceramic capacitor of
1µF. Input of the internal housekeeping regulator and of the main REG
regulator.
2
V
CC
3
4
3
—
4
3
—
4
GND
IN+
IN1
IN-
Signal Ground
Driver Noninverting Logic Input. Connect to V when not used.
CC
—
5
Driver 1 Noninverting Logic Input
—
5
—
—
5
Driver Inverting Logic Input. Connect to GND when not used.
Driver 2 Noninverting Logic Input
—
—
IN2
IN2
—
Driver 2 Inverting Logic Input
Power Ground. Sink current return. Source of the internal pulldown
n-channel transistor.
6
6
6
PGND
Sink Output. Open-drain n-channel output. N_OUT sinks current for power
MOSFET turn-off.
7
—
8
—
7
—
7
N_OUT
OUT2
Driver 2 Output
Source Output. Pullup p-channel output (open drain). Sources current for
power MOSFET turn-on.
—
8
—
8
P_OUT
OUT1
—
Driver 1 Output
Output Driver Supply Voltage. Decouple DRV with a low ESR > 0.1µF
ceramic capacitor to PGND placed in close proximity to the device. DRV
9
9
9
DRV
can be powered independently from REG. Connect DRV, REG, and V
CC
together when there is no need for special DRV supply sequencing and
the power-MOSFET gate voltage does not need to be regulated or limited.
Voltage Regulator Output. Connect to DRV for driving the power MOSFET
with regulated V amplitude. Bypass with a low-ESR 1µF (minimum)
GS
ceramic capacitor to GND placed in close proximity to the device to
ensure regulator stability.
10
—
10
—
10
—
REG
EP
Exposed Pad. Internally connected to GND. Connect to GND plane or
thermal pad and use multiple vias to a solid copper area on the bottom of
the PCB.
_______________________________________________________________________________________
9
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Input Control
Detailed Description
The MAX15024 features inverting and noninverting
input terminals. These inputs provide for flexibility of
The MAX15024 single gate driver’s internal source and
sink transistor outputs are brought out of the IC to inde-
pendent outputs allowing control of the external
MOSFET’s rise and fall time. The MAX15024 single
gate driver is capable of sinking an 8A peak current
and sourcing a 4A peak current. The MAX15025 dual
gate drivers are capable of sinking a 4A peak current
and sourcing a 2A peak current.
design and use. Connect IN+ to V
when using IN- as
an inverting input. Connect IN- to GND when using IN+
as a noninverting input.
CC
Shoot-Through Protection
The MAX15024/MAX15025 provide protection that
avoids any cross-conduction between the internal p-
channel and n-channel devices. It also eliminates shoot-
through, thus reducing the quiescent supply current.
An integrated adjustable low-dropout linear voltage
regulator (LDO) provides gate drive amplitude control
and optimization. The single gate-driver propagation
delay time is minimized and matched between the
inverting and noninverting inputs. The dual gate-driver
propagation delay is matched between channels.
Exposed Pad (EP)
The MAX15024/MAX15025 include an exposed pad
allowing greater heat dissipation from the internal die to
the outside environment. Solder the exposed pad care-
fully to GND or thermal pad to enhance the thermal
performance.
The MAX15024 has a dual input (IN+ and IN-), allows
the use of an inverting or noninverting input, and is
offered in TTL or CMOS-logic standards. The
MAX15025 is offered with configurations of inverting
and noninverting inputs with TTL or CMOS standards
(see the Selector Guide).
Applications Information
Supply Bypassing, Device Grounding,
and Placement
4/MAX1025
LDO Voltage Regulator Feedback Control
The MAX15024/MAX15025 include an internal LDO
designed to deliver a stable reference voltage for use
as a supply voltage for the internal MOSFET gate dri-
vers. Connect the LDO feedback FB/SET to GND to set
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the
V
DRV
pin can approach 4A, while at the PGND pin, the
peak current can approach 8A. V
drops and
DRV
V
to a stable 10V. Connect FB/SET to a resistor-
ground shifts are forms of negative feedback for invert-
ers and, if excessive, can cause multiple switching
when the inverting input is used and the input slew rate
is low. The device driving the input should be refer-
enced to the MAX15024/MAX15025 GND. Ground
shifts due to insufficient device grounding can disturb
other circuits sharing the same AC ground return path.
REG
divider between V
and GND to set V
:
REG
REG
V
= V
x (1 + R2 / R1) (see Figure 2)
REG
FB/SET
V
Undervoltage Lockout
CC
When V
is below the UVLO threshold, the internal n-
CC
channel transistor is ON and the internal p-channel tran-
sistor is OFF, holding the output at GND independent of
the state of the inputs so that the external MOSFETs
remain OFF in the UVLO condition. The UVLO threshold is
3.5V (typ) with 200mV (typ) hysteresis to avoid chattering.
Any series inductance in the V
, OUT_, and/or PGND
DRV
paths can cause oscillations due to the very high di/dt
that results when the MAX15024/MAX15025 are
switched with any capacitive load. A 0.1µF or larger
value ceramic capacitor is recommended for bypass-
When the device is operated at very low temperatures
and below the UVLO threshold, the driver output could
go high impedance. In this case, it is recommended
adding a 10kΩ resistor to PGND to discharge the gate
of the external MOSFET (see Figures 4 and 5).
ing V
to GND and should be placed as close to the
DRV
pins as possible. When driving very large loads
(> 10nF) at minimum rise time, 10µF or more of parallel
storage capacitance is recommended. A ground plane
is highly recommended to minimize ground return resis-
tance and series inductance. Care should be taken to
place the MAX15024/MAX15025 as close as possible to
the external MOSFET being driven to further minimize
board inductance and AC path resistance.
10 ______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
printed-circuit board (PCB) layout guidelines are recom-
mended when designing with the MAX15024/MAX15025:
Power Dissipation
Power dissipation of the MAX15024/MAX15025 con-
sists of three components: the quiescent current,
capacitive charge and discharge of internal nodes, and
the output current (either capacitive or resistive load).
The sum of these components must be kept below the
maximum power-dissipation limit. The quiescent cur-
rent is 700µA typ. The current required to charge and
discharge the internal nodes is frequency dependent
(see the Typical Operating Characteristics). The
MAX15024/MAX15025 power dissipation when driving
a ground-referenced resistive load is:
• Place one or more 1µF decoupling ceramic capaci-
tor(s) from V
to PGND as close to the device as
DRV
possible. At least one storage capacitor of 10µF (min)
should be located on the PCB with a low resistance
path to the V
pin of the MAX15024/MAX15025.
CC
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from MOSFET gate to
OUT_ of the MAX15024/MAX15025 to PGND of the
MAX15024/MAX15025, and to the source of the
MOSFET. When the gate of the MOSFET is being
2
P = D x R
x I
ON(MAX) LOAD
where D is the fraction of the period the MAX15024/
MAX15025s’ output pulls high, R is the maxi-
ON(MAX)
pulled high, the active current loop is from the V
DD
mum on-resistance of the device with the output high
terminal of the V
terminal of decoupling capaci-
(p-channel), and I
is the output load current of the
DRV
LOAD
tor, to the V
DRV
of the MAX15024/MAX15025, to the
MAX15024/MAX15025. For capacitive loads, the power
OUT_ of the MAX15024/MAX15025, to the MOSFET
gate, to the MOSFET source, and to the negative ter-
minal of the decoupling capacitor. Both charging
current loop and discharging current loop are impor-
tant. It is important to minimize the physical distance
and the impedance in these AC current paths.
dissipation for each driver is:
2
P = C
x V
x FREQ
DRV
LOAD
where C
is the capacitive load, V
is the driver
LOAD
DRV
supply voltage, and FREQ is the switching frequency.
Layout Information
The MAX15024/MAX15025 MOSFET drivers source and
sink large currents to create very fast rise and fall edges
at the gate of the switching MOSFET. The high di/dt can
cause unacceptable ringing if the trace lengths and
impedances are not well controlled. The following
• Keep the device as close as possible to the MOSFET.
• In the multilayer PCB, the inner layers should consist
of a GND plane containing the discharging and
charging current loops.
IN+
V
IH
V
IL
P_OUT AND
N_OUT CONNECTED
TOGETHER
90%
10%
OR OUT1/OUT2
t
t
t
t
R
D-OFF
F
D-ON
Figure 1. Timing Diagram
______________________________________________________________________________________ 11
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Typical Operating Circuits
V
CC
REG
DRV
V
< 18V
C1
DRV
(UP TO 18V)
DRV
V
CC
R2
R1
MAX15024
REG
FB/SET
P_OUT
MAX15024
P_OUT
FB/SET
GND
N_OUT
PGND
V
CC
(UP TO 28V)
N_OUT
PGND
V
CC
GND
IN-
IN+
IN-
IN+
4/MAX1025
Figure 2. Use R1, R2 to program V
< 18V, OR. Connect
Figure 3. Operation Using a Different Supply Rail for DRV
(Connect EP to GND)
REG
FB/SET to GND for V
= 10V (Connect EP to GND)
REG
REG
DRV
V
CC
(UP TO 18V)
V
CC
DRV
R2
MAX15025
OUT1
REG
FB/SET
MAX15024
R1
P_OUT
FB/SET
GND
OUT2
PGND
V
CC
(UP TO 28V)
V
N_OUT
PGND
CC
GND
IN-
IN+
IN1
IN2
Figure 4. Operation Using a V
to GND)
= DRV = REG (Connect EP
Figure 5. Use R1, R2 to program V
< 18V, OR. Connect
CC
REG
FB/SET to GND for V
= 10V (Connect EP to GND)
REG
12 ______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
Block Diagrams
REG
V
CC
LDO
UVLO
FB/SET
DRV
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
PREDRIVER
P
IN+
IN-
P_OUT
N_OUT
IN_ LOGIC
LEVEL SHIFT-UP
N
GND
PGND
MAX15024A
MAX15024B
V
CC
REG
DRV
LDO
UVLO
FB/SET
IN1
P
PREDRIVER
PREDRIVER
IN_ LOGIC
LEVEL SHIFT-UP
OUT1
IN_ LOGIC
LEVEL SHIFT-UP
N
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
P
IN2
OUT2
PGND
IN_ LOGIC
LEVEL SHIFT-UP
PREDRIVER
N
GND
MAX15025
______________________________________________________________________________________ 13
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Selector Guide
NO. OF
CHANNELS
PEAK CURRENTS
(SINK/SOURCE)
LOGIC
LEVELS
TOP
MARK
PART
INPUTS
MAX15024AATB+
MAX15024BATB+
MAX15025AATB+
MAX15025BATB+
1
1
2
2
8A/4A
8A/4A
4A/2A
4A/2A
Complementary
Complementary
Noninverting
TTL
CMOS
TTL
ATX
ATY
ATZ
AUA
Noninverting
CMOS
Noninverting (1)/
Inverting (2)
MAX15025CATB+
MAX15025DATB+
2
2
4A/2A
4A/2A
TTL
AUB
AUC
Noninverting (1)/
Inverting (2)
CMOS
Note: All devices operate in a -40°C to +125°C temperature range and come in a 10-pin TDFN package.
4/MAX1025
Pin Configurations (continued)
TOP VIEW
10
9
8
7
6
10
9
8
7
6
MAX15025C
MAX15025D
MAX15025A
MAX15025B
EP
EP
1
2
3
4
5
1
2
3
4
5
TDFN
TDFN
14 ______________________________________________________________________________________
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
4/MAX1025
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 TDFN
T1033-1
21-0137
______________________________________________________________________________________ 15
Single/Dual, 16ns, High Sink/Source
Current Gate Drivers
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
10/07
3/08
Initial release
Released MAX15024A/MAX15025B/C/D versions
—
1–6, 9, 13
Removed future product (MAX15024C/D, MAX15025E-H); minimum and
maximum specifications added to the EC table
2
4/10
1–6, 9, 10, 12–15
4/MAX1025
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明