MAX15034BAUI/V+ [MAXIM]
Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, BICMOS, PDSO28,;
| 型号： | MAX15034BAUI/V+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual Switching Controller, Current-mode, 1000kHz Switching Freq-Max, BICMOS, PDSO28, 控制器 |
| 文件： | 总26页 (文件大小：324K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4218; Rev 1; 10/11
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
General Description
Features
The MAX15034 two-phase, configurable single- or dual-
output buck controller has an input voltage range of
4.75V to 5.5V or 5V to 28V. A mode select input allows
for a dual-output supply or connecting two phases
together for a single-output, high-current supply. Each
output channel of the MAX15034 drives n-channel
MOSFETs and is capable of providing more than 25A of
load current. The MAX15034 uses average current-
mode control with a switching frequency up to 1MHz
per phase where each phase is 180° out of phase with
respect to the other. Out-of-phase operation results in
significantly reduced input capacitor ripple current and
output voltage ripple in dual-phase, single-output volt-
age applications. Each controller has its own high-per-
formance current and voltage-error amplifier that can
be compensated for optimum output filter L-C values
and transient response.
o 4.75V to 5.5V or 5V to 28V Input
o Dual-Output Synchronous Buck Controller
o Configurable for Two Separate Outputs (25A) or
One Single Output (50A)
o Average Current-Mode Control with Accurate
Adjustable Current Limit
o 180° Interleaved Operation Reduces Size of Input
Filter Capacitors
o Limits Reverse Current Sinking When Operated in
Parallel Mode
o Each Output is Adjustable from 0.61V to 5.5V
o Independently Programmable Adaptive Voltage
Positioning
o Monotonic Startup into Prebiased Outputs
o Independent Shutdown for Each Output
The MAX15034 offers two enable inputs with accurate
turn-on thresholds to allow for output voltage sequencing
of the two outputs. The device’s switching frequency can
be programmed from 100kHz to 1MHz with an external
resistor. The MAX15034 can be synchronized to an
external clock. Each output voltage is adjustable from
0.61V to 5.5V. Additional features include thermal shut-
down and hiccup-mode, short-circuit protection. Use the
MAX15034 with adaptive voltage positioning for applica-
tions that require a fast transient response or accurate
output voltage regulation.
o 100kHz to 1MHz per Phase Programmable
Switching Frequency
o Oscillator Frequency Synchronization from
200kHz to 2MHz
o Digital Soft-Start on Outputs
o Hiccup-Mode Overcurrent Protection
o Overtemperature Shutdown
The MAX15034 is available in a thermally enhanced 28-
pin TSSOP package capable of dissipating 2.1W. The
device is rated for operation over the -40°C to +125°C
automotive temperature range.
o Thermally Enhanced 28-Pin TSSOP Package
Capable of Dissipating 2.1W
Applications
Ordering Information
High-End Computers/Workstations/Servers
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
28 TSSOP
Graphics Cards
MAX15034AAUI+
MAX15034BAUI+
MAX15034BAUI/V+
Networking Systems
28 TSSOP-EP*
28 TSSOP-EP*
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
RAID Systems
/V Denotes an automotive qualified part.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ABSOLUTE MAXIMUM RATINGS
IN, LX_ to AGND.....................................................-0.3V to +30V
BST_ to AGND........................................................-0.3V to +35V
REG Continuous Output Current
(limited by power dissipation, no thermal or short-circuit
protection).........................................................................67mA
DH_ to LX_ ....................................-0.3V to (V
- V ) + 0.3V
BST_
LX_
DL_ to PGND..............................................-0.3V to (V
+ 0.3V)
Continuous Power Dissipation (T = +70°C) (Note 1)
A
DD
BST_ to LX_ ..............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
28-Pin TSSOP (derate 14mW/°C above +70°C) ..........1117mW
28-Pin TSSOP-EP (derate 27mW/°C above +70°C)........2162mW
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
V
DD
AGND to PGND.....................................................-0.3V to +0.3V
AVGLIMIT, REG, RT/CLKIN, CSP_,
CSN_ to AGND ......................................................-0.3V to +6V
All Other Pins to AGND ............................-0.3V to (V
+ 0.3V)
REG
MAX15034
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
TSSOP-EP
Junction-to-Ambient Thermal Resistance (θ )..................37°C/W
Junction-to-Ambient Thermal Resistance (θ )..................71.6°C/W
Junction-to-Case Thermal Resistance (θ )......................13°C/W
JA
JC
JA
Junction-to-Case Thermal Resistance (θ )......................2°C/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V = V
IN
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
REG
DD
EN_
A
J
MIN
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
5
28
5.50
17
Input Voltage Range
V
V
IN
IN and REG shorted together for +5V
operation
4.75
Quiescent Supply Current
I
f
= 500kHz, DH_ or DL_ = open
7
mA
IN
OSC
STARTUP/INTERNAL REGULATOR OUTPUT (REG)
REG Undervoltage Lockout
Hysteresis
UVLO
V
rising
4.0
4.15
200
4.5
V
mV
V
REG
V
HYST
REG Output Accuracy
REG Dropout
V
V
= 5.8V to 28V, I
= 0 to 65mA
4.75
5.10
5.30
0.5
IN
IN
SOURCE
< 5.8V, I
= 60mA
V
SOURCE
INTERNAL REFERENCE
EAN_ connected to
EAOUT_
Internal Reference Voltage
V
T
A
= -40°C to +125°C 0.605 0.6125 0.620
V
EAN_
(Note 3)
Clock
cycles
Digital Ramp Period for Soft-Start
1024
64
Soft-Start Voltage Steps
Steps
MOSFET DRIVERS
p-Channel Output Driver
Impedance
R
ON_P
1.35
3
Ω
2
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
IN
REG
DD
EN_
A
J
MIN
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
n-Channel Output Driver
Impedance
R
ON_N
0.45
1.35
Ω
Output Driver Source Current
Output Driver Sink Current
I
I
, I
2.5
5
A
A
DH_ DL_
, I
DH_ DL_
C
or C
= 5nF
DL_
-7.5
-10
+7.5
+10
DH_
Nonoverlap Time (Dead Time)
t
%
V
NO
f
= 1MHz nominal, R = 12.4kΩ
RT
SW
RT/CLKIN Output Voltage
V
1.225
0.5
RT/CLKIN
RT/CLKIN
RT/CLKIN Current Sourcing
Capability
I
mA
RT/CLKIN Logic-High Threshold
RT/CLKIN Logic-Low Threshold
RT/CLKIN High Pulse Width
V
V
2.4
V
V
RT/CLKIN_H
RT/CLKIN_L
0.8
t
30
ns
RT/CLKIN
RT/CLKIN Synchronization
Frequency Range
f
200
2000
kHz
RT/CLKIN
CURRENT LIMIT
Internal Average Current-Limit
Threshold
V
V
V
- V
- V
20.4
-3.0
22.5
24.75
-0.1
mV
mV
V
CL_
CSP_
CSP_
CSN_
Reverse Average Current-Limit
Threshold
V
-1.53
RCL_
CSN_
External Average Current-Limit
Threshold Adjustment
Resistor-divider connected from REG
to AVGLIMIT to AGND
V
-
AVGLIMIT
0.6/36
V
CL_ADJ
AVGLIMIT Ground Threshold
Voltage
V
550
mV
nA
AVGLIMIT_GND
Leakage Current at AVGLIMIT
I
V
= 3V
AVGLIMIT
100
AVGLIMIT
DIGITAL FAULT INTEGRATION (DF_)
Number of Switching Cycles to
Shutdown in Current Limit
Clock
cycles
NS
NR
32,768
DF_
Number of Switching Cycles to
Recover from Shutdown
Clock
cycles
524,288
3.8
DF_
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
R
kΩ
CS_
V
V
= V
= 5V to 10V
= 4.75V to 5.5V or
REG
IN
IN
-0.3
-0.3
+3.6
+5.5
V
Common-Mode Range
V
CMR(CS)
V
= 7V to 28V
V
IN
Input Offset Voltage
Amplifier Gain
V
100
36
µV
V/V
OS(CS)
A
V(CS)
_______________________________________________________________________________________
3
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= V = V
= +5V, T = T = T
to T , unless otherwise noted, circuit of Figure 6. Typical values are at T = +25°C.)
MAX A
IN
REG
DD
EN_
A
J
MIN
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-3dB Bandwidth
f
4
MHz
-3dB
V
V
= 5.5V, sinking
120
30
CSP_
CSP_
CSP_ Input Bias Current
I
µA
CSA(IN)
= 0V, sourcing
CURRENT-ERROR AMPLIFIER (CEA_)
MAX15034
Transconductance
g
550
50
µS
dB
m
Open-Loop Gain
A
No load
VOL(CEA)
VOLTAGE-ERROR AMPLIFIER (EAOUT_)
Open-Loop Gain
A
70
3
dB
MHz
nA
VOL(EA)
Unity-Gain Bandwidth
EAN_ Input Bias Current
f
UGEA
I
V
= 2.0V
EAN_
100
BIAS(EA)
Error-Amplifier Output Clamping
High Voltage
VCLMP_HI (EA)
With respect to V
With respect to V
1
V
V
CM
CM
Error-Amplifier Output Clamping
Low Voltage
VCLMP_LO (EA)
-0.234
EN_ INPUTS
EN_ Input High Voltage
EN_ Hysteresis
V
EN rising
1.2
1.222
0.05
1.245
+200
ENH
V
EN_ Input Leakage Current
Startup Delay Time to OUT_
MODE INPUT
I
-200
nA
ms
EN
tSTART_DELAY
From EN_ rising to V
rising
1
OUT_
MODE Logic-High Threshold
MODE Logic-Low Threshold
MODE Input Pulldown
PREBIASED OUTPUT
V
2.4
V
V
MODE_H
V
0.8
MODE_L
I
5
µA
PULLDWN
Peak Sink Current-Limit
Threshold during Reference
Soft-Start
V
- V
-2.1
448
mV
CSP_
CSN_
Digital Ramp Period for
Stepping Peak Sink Current
Limit after Reference Soft-Start
Clock
cycles
THERMAL SHUTDOWN
Thermal Shutdown
T
160
10
SHDN
°C
Thermal Shutdown Hysteresis
T
HYST
Note 2: The device is 100% production tested at T = T = +125°C. Limits at T = -40°C and T = +25°C are guaranteed by design.
A
A
A
J
Note 3: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage
accuracy must include external resistor-divider tolerances.
4
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Typical Operating Characteristics
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f = 500kHz per phase.)
SW
A
IN
OUT1
OUT2
SUPPLY CURRENT
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
vs. TEMPERATURE AND FREQUENCY
OSCILLATOR FREQUENCY vs. R
T
(V = 5V)
IN
(V = 12V)
IN
10,000
1000
100
16
14
12
10
8
16
14
12
10
8
C
= C = 0
DL_
DH_
f
= 1MHz
C
= C = 0
DL_
SW
C
= C = 0
f
= 1MHz
SW
DH_
DH_
DL_
f
= 500kHz
SW
f
= 500kHz
SW
f
= 250kHz
SW
f
= 250kHz
SW
6
6
f
= 125kHz
SW
f
= 125kHz
SW
4
4
2
2
10
0
0
0
100 200 300 400 500 600 700 800 900 1000
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5 20 35 50 65 80 95 110 125
R (kΩ)
T
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. OSCILLATOR FREQUENCY
SUPPLY CURRENT
vs. DRIVER LOAD CAPACITANCE
(V = 24V)
IN
14
13
12
11
10
9
100
90
80
70
60
50
40
30
20
10
0
16
14
12
10
8
C
= C
= C
DH_ DL_
C
= C = 0
C
= C = 0
f
= 1MHz
SW
LOAD
DH_
DL_
DH_
DL_
f
= 500kHz
SW
V
= 12V
IN
V
= 24V
IN
f
= 250kHz
SW
6
f
= 125kHz
SW
8
4
V
= 5V
IN
7
2
6
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
0
5
10
15
20
25
30
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
C
(nF)
LOAD
REG LINE REGULATION
REG LOAD REGULATION
OUTPUT LOAD-TRANSIENT RESPONSE
MAX15034 toc07
5.10
5.08
5.06
5.04
5.02
5.00
4.98
4.96
5.10
5.05
5.00
4.95
4.90
I
OUT
20A
I
= 0
REG
V
= 24V
IN
10A/div
V
OUT
V
= 12V
IN
100mV/div
AC-COUPLED
V
= 5.5V
IN
I
= 60mA
REG
5
7
9
11 13 15 17 19 21 23
(V)
0
10 20 30 40 50 60 70 80 90 100
(mA)
2ms/div
V
I
IN
REG
_______________________________________________________________________________________
5
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f
= 500kHz per phase.)
A
IN
OUT1
OUT2
SW
DRIVER RISE TIME
vs. LOAD CAPACITANCE
DRIVER FALL TIME
vs. LOAD CAPACITANCE
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
DH_
DH_
MAX15034
DL_
DL_
0
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10 12 14 16 18 20 22
C
(nF)
C
(nF)
LOAD
LOAD
HIGH-SIDE DRIVER FALL TIME
(V = 12V, C = 10nF)
HIGH-SIDE DRIVER RISE TIME
(V = 12V, C = 10nF)
IN
LOAD
IN
LOAD
MAX15034 toc11
MAX15034 toc10
DH_
DH_
2V/div
2V/div
20ns/div
20ns/div
LOW-SIDE DRIVER RISE TIME
(V = 12V, C = 10nF)
LOW-SIDE DRIVER FALL TIME
(V = 12V, C = 10nF)
IN
LOAD
IN
LOAD
MAX15034 toc12
MAX15034 toc13
DL_
2V/div
DL_
2V/div
20ns/div
20ns/div
6
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Typical Operating Characteristics (continued)
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f
= 500kHz per phase.)
A
IN
OUT1
OUT2
SW
OUT1/OUT2 OUT-OF-PHASE WAVEFORMS
TURN-ON/TURN-OFF WAVEFORM
(V
OUT1
= 0.8V, V
= 1.3V)
OUT2
MAX15034 toc14
MAX15034 toc15
LX1
10V/div
V
OUT1
1V/div
OUT1
100mV/div
EN1
5V/div
LX2
10V/div
V
OUT2
1V/div
EN2
5V/div
OUT2
100mV/div
10µs/div
1ms/div
AVERAGE CURRENT LIMIT
SHORT-CIRCUIT CURRENT WAVEFORMS
vs. V
(V = 5V)
AVGLIMIT
IN
MAX15034 toc16
75
60
45
30
15
I
OUT1
10A/div
I
OUT2
10A/div
0
0
0.5
1.0
1.5
2.0
2.5
3.0
200ms/div
V
(V)
AVGLIMIT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. TEMPERATURE
0.620
0.615
0.610
0.605
550
525
500
475
450
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 6, T = +25°C, unless otherwise noted. V = 12V, V
= 0.8V, V
= 1.3V, f
= 500kHz per phase.)
A
IN
OUT1
OUT2
SW
INTERNAL AVERAGE CURRENT LIMIT
vs. TEMPERATURE
INTERNAL AVERAGE REVERSE
CURRENT LIMIT vs. TEMPERATURE
25
24
23
22
21
20
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
MAX15034
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SOFT-START WAVEFORM
PREBIASED OUTPUT CONDITION
MAX15034 toc22
MAX15034 toc23
EN2
5V/div
EN2
5V/div
V
OUT2
V
500mV/div
OUT2
500mV/div
DH2
5V/div
V
EAN2
200mV/div
DL2
5V/div
EAOUT2
1V/div
0V
400µs/div
400µs/div
PEAK PULLUP AND PULLDOWN CURRENT
OR DRIVER AT DH_ AND DL_
MAX15034 toc24
C
= 10nF
LOAD
DH_
500mV/div
DL_
500mV/div
200ns/div
8
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Pin Description
PIN
NAME
FUNCTION
Current-Sense Differential Amplifier Negative Input for Output 2. Connect CSN2 to the negative terminal of
the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-
1
CSN2
sense amplifier (A
= 36V/V).
V(CS)
Current-Sense Differential Amplifier Positive Input for Output 2. Connect CSP2 to the positive terminal of the
sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-sense
2
3
CSP2
amplifier (A
= 36V/V).
V(CS)
Voltage Error-Amplifier Output 2. Connect to an external gain-setting feedback resistor. The error-amplifier
gain determines the output voltage load regulation for adaptive voltage positioning. This output also serves
EAOUT2 as the compensation network connection from EAOUT2 to EAN2. A resistive network results in a drooped
output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage
regulation (see the Adaptive Voltage Positioning section).
Voltage Error-Amplifier Inverting Input for Output 2. Connect a resistive divider from V
to EAN2 to
OUT2
AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in
very tight output-voltage regulation (see the Adaptive Voltage Positioning section).
4
EAN2
Current-Error Amplifier Output 2. Compensate the current loop by connecting an R-C network from CLP2 to
AGND.
5
6
CLP2
Average Current-Limit Programming. Connect a resistor-divider between REG, AVGLIMIT, and AGND to set
the average current-limit value (see the Programming Average the Current Limit section).
AVGLIMIT
External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to AGND
to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency
synchronization.
7
8
RT/CLKIN
AGND
Analog Ground
Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck regulator.
When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see Figure 1) and the
device operates as a two-output, out-of-phase buck regulator. When MODE is connected to REG (logic
high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.
9
MODE
CLP1
EAN1
Current-Error Amplifier Output 1. Compensate the current loop by connecting an R-C network from CLP1 to
AGND.
10
11
Voltage Error-Amplifier Inverting Input for Output 1. Connect a resistive divider from V
to EAN1 to
OUT1
regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive network
results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight
output-voltage regulation (see the Adaptive Voltage Positioning section).
Voltage Error-Amplifier Output 1. Connect to an external gain-setting feedback resistor. The error-amplifier
gain determines the output-voltage-load regulation for adaptive voltage positioning. This output also serves
12
EAOUT1 as the compensation network connection from EAOUT1 to EAN1. A resistive network results in a drooped
output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage
regulation (see the Adaptive Voltage Positioning section).
Current-Sense Differential Amplifier Positive Input for Output 1. Connect CSP1 to the positive terminal of the
13
14
CSP1
CSN1
sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-sense
amplifier (A = 36V/V).
V(CS)
Current-Sense Differential Amplifier Negative Input for Output 1. Connect CSN1 to the negative terminal of
the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-
sense amplifier (A
= 36V/V).
V(CS)
_______________________________________________________________________________________
9
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Pin Description (continued)
PIN
NAME
FUNCTION
Output 1 Enable. A logic-low shuts down channel 1’s MOSFET drivers. EN1 can be used for output
sequencing.
15
EN1
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST1 and LX1.
16
17
18
19
BST1
DH1
LX1
High-Side Gate Driver Output 1. DH1 drives the gate of the high-side MOSFET.
External Inductor Connection and Source Connection for the High-Side MOSFET for Output 1. LX1 also
serves as the return terminal for the high-side MOSFET driver.
MAX15034
DL1
Low-Side Gate Driver Output 1. Gate driver output for the synchronous MOSFET.
Supply Voltage for Low-Side Drivers. REG powers V . Connect a parallel combination of 0.1µF and 1µF
DD
20
V
ceramic capacitors from V
to PGND and a 1Ω resistor from V to REG to filter out the high-peak
DD
DD
DD
currents of the driver from the internal circuitry.
Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias
circuitry. Bypass REG to AGND with a 4.7µF ceramic capacitor.
21
22
23
24
25
26
27
REG
IN
Supply Voltage Connection. Connect IN to a 5V to 28V input supply.
Power Ground. Source connection for the low-side MOSFET. Connect V ’s bypass capacitor returns to
DD
PGND.
PGND
DL2
Low-Side Gate Driver Output 2. Gate driver for the synchronous MOSFET.
External Inductor Connection and Source Connection for the High-Side MOSFET for Output 2. Also serves
as the return terminal for the high-side MOSFET driver.
LX2
DH2
BST2
High-Side Gate Driver Output 2. DH2 drives the gate of the high-side MOSFET.
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST2 and LX2.
Output 2 Enable. A logic-low shuts down channel 2’s MOSFET drivers. EN2 can be used for output
sequencing.
28
—
EN2
EP
Exposed Pad. Connect exposed pad to ground plane (MAX15034BAUI only).
input of the transconductance amplifier (CA1 or CA2) is
clamped, thus limiting the output current.
Detailed Description
The MAX15034 switching power-supply controller can
be configured two ways. With the MODE input high, this
device operates as single-output, dual-phase, step-
down switching regulators where each output is 180°
out of phase. With MODE connected low, the
MAX15034 operates as a dual-output, step-down
switching regulator. The average current-mode control
topology of the MAX15034 offers high-noise immunity
while having benefits similar to those of peak current-
mode control. Average current-mode control has the
intrinsic ability to accurately limit the average current
sourced by the converter during a fault condition. When
a fault condition occurs, the error-amplifier output volt-
age (EAOUT1 or EAOUT2) that connects to the positive
The MAX15034 has internal logic to ensure each output’s
monotonic startup under prebias load conditions. This
facilitates glitch-free output voltage power-up in the pres-
ence of another redundant/parallel voltage regulator.
The MAX15034 contains all blocks necessary for two
independently regulated average current-mode PWM
regulators. This device has two voltage error amplifiers
(VEA1 and VEA2), two current-error amplifiers (CEA1
and CEA2), two current-sensing amplifiers (CA1 and
CA2), two PWM comparators (CPWM1 and CPWM2),
and drivers for both low- and high-side power MOSFETs
(see Figure 1). Each PWM section is also equipped with
a pulse-by-pulse, current-limit protection and a fault
integration block for hiccup protection.
10 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
CLP1
10
13 CSP1
CA1
CSN1
14
DF1 AND
HICCUP
LOGIC
EAOUT1 12
EAN1
11
CEA1
BST1
16
VEA1
CPWM1
17 DH1
UVLO
2V
P-P
RAMP
22
V
= 5V
IN
REG
CONTROL
AND DRIVER
LOGIC 1
LX1
18
V
20
19
DD
FOR INTERNAL
BIASING
21
REG
DL1
CEN1
0°
EN1 15
1.225V
THERMAL
SHUTDOWN
6
AVGLIMIT
OSCILLATOR
AND PHASE
SPLITTER
EXTERNAL FREQUENCY SYNC
RT/CLKIN
7
V
= 0.61V
INTREF
27 BST2
1.225V
180°
CEN2
DH2
LX2
26
25
EN2
28
8
CONTROL
AND DRIVER
LOGIC 2
2V
RAMP
P-P
V
DD
AGND
24 DL2
VEA2
MUX
CPWM2
23
PGND
EAN2
4
CEA2
DF2 AND
HICCUP
LOGIC
3
9
EAOUT2
MODE
2
1
CSP2
CSN2
CA2
5
CLP2
Figure 1. Block Diagram
Two enable comparators (CEN1 and CEN2) are avail-
able to control and sequence the two PWM sections
through the enable (EN1 or EN2) inputs. An oscillator,
with an externally programmable frequency generates
two clock pulse trains and two ramps for both PWM
sections. The two clocks and the two ramps are 180°
out of phase with each other.
circuitry and the power for the external MOSFET’s gate
drivers. Internal UVLO circuitry ensures that the
MAX15034 starts up when V
is at the correct volt-
REG
age levels to guarantee safe operation of the IC and of
the power MOSFETs.
Finally, a thermal-shutdown feature protects the device
during thermal faults and shuts down the MAX15034
when the die temperature exceeds +160°C.
A linear regulator (REG) generates the 5V to supply the
device. This regulator has the output-current capability
necessary to provide for the MAX15034’s internal
______________________________________________________________________________________ 11
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Minimize the trace inductance from BST_ and V
to
Dual-Output/Dual-Phase Select (MODE)
The MAX15034 can operate as a dual-output, indepen-
dently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic-low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1), and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic-high), VEA2 is dis-
connected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
DD
the rectifier diodes, D1 and D2, and from BST_ and LX_
to the boost capacitors, C8 and C9 (see Figure 6). This
is accomplished by using short, wide trace lengths.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX15034 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold monitors V
and is inter-
MAX15034
REG
nally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates chattering during
startup. Most of the internal circuitry, including the
Supply Voltage Connections (V /V
)
oscillator, turns on when V
reaches 4.5V. The
IN REG
REG
The MAX15034 accepts a wide input voltage range at
IN of 5V to 28V. An internal linear regulator steps down
IN
MAX15034 draws up to 4mA (typ) of current before
reaches the UVLO threshold.
V
REG
V
to 5.1V (typ) and provides power to the MAX15034.
The output of this regulator is available at REG. For V
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the current-
error amplifier output limits the maximum current avail-
able to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus, the output voltage.
IN
= 4.75V to 5.5V, connect IN and REG together external-
ly. REG can supply up to 65mA for external loads.
Bypass REG to AGND with a 4.7µF ceramic capacitor
for high-frequency noise rejection and stable operation.
REG supplies the current for the MAX15034’s internal
circuitry and for the MOSFET gate drivers (when con-
nected externally to V ), and can source up to 65mA.
DD
Calculate the maximum bias current (I
MAX15034:
) for the
BIAS
Setting the Switching Frequency (f
)
SW
An internal oscillator generates the 180o out-of-phase
clock signals required for both PWM modulators. The
I
= I + f
× Q
(
+ Q
+ Q
+ Q
GQ4
)
BIAS IN SW
GQ1
GQ2
GQ3
oscillator also generates the 2V
voltage ramps nec-
P-P
where I is the quiescent supply current into IN (4mA,
IN
essary for the PWM comparators. The oscillator fre-
quency can be set from 200kHz to 2MHz by an external
typ), Q
, Q
, Q
, Q
are the total gate
GQ4
GQ1
GQ2
GQ3
charges of MOSFETs Q1 through Q4 at V
= 5V (see
GS
resistor (R ) connected from RT/CLKIN to AGND (see
T
Figure 6), and f
individual phase.
is the switching frequency of each
SW
Figure 6). The equation below shows the relationship
between R and the switching frequency:
T
Low-Side MOSFET Driver Supply (V
)
DD
10
V
is the power input for the low-side MOSFET dri-
DD
2.5 ×10
f
=
Hz
vers. Connect the regulator output REG externally to
OSC
R
RT
V
through an R-C lowpass filter. Use a 1Ω resistor
DD
and a parallel combination of 1µF and 0.1µF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
where R is in ohms and the per-phase switching fre-
RT
quency is f
= f
/2.
SW
OSC
Use RT/CLKIN as a clock input to synchronize the
MAX15034 to an external frequency (f ).
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
RT/CLKIN
Applying an external clock to RT/CLKIN allows each
PWM section to work at a frequency equal to
f
/2. An internal comparator with a 1.6V thresh-
Connect BST1 and BST2 to V
through rectifier
RT/CLKIN
old detects f
DD
. If f
is present, internal
RT/CLKIN
diodes D1 and D2 (see Figure 6). Connect a 0.1µF
ceramic capacitor between BST_ and LX_.
RT/CLKIN
logic switches from the internal oscillator clock, to the
clock present at RT/CLKIN.
12 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
current, while the outer voltage loop controls the output
voltage. The inner current loop absorbs the inductor
pole, reducing the order of the outer voltage loop to
that of a single-pole system. Figure 2 is the block dia-
gram of OUT1’s control loop.
Hiccup Fault Protection
The MAX15034 includes overload fault protection circuitry
that prevents damage to the power MOSFETs. The fault
protection consists of two digital fault integration blocks
that enable hiccuping under overcurrent conditions. This
circuit works as follows: for every clock cycle the current-
limit threshold is exceeded, the fault integration counter
increments by one count. Thus, if the current-limit condi-
tion persists, the counter reaches its shutdown threshold
in 32,768 counts and shuts down the external MOSFETs.
When the MAX15034 shuts down due to a fault, the
counter begins to count down (since the current-limit con-
dition has ended), once every 16 clock cycles. Thus, the
device counts down for 524,288 clock cycles. At this
point, switching resumes. This produces an effective duty
cycle of 6.25% power-up and 93.75% power-down under
fault conditions. With a switching frequency set to
250kHz, power-up and power-down times are approxi-
mately 131ms and 2.09s, respectively.
The current loop consists of a current-sense resistor,
R
, a current-sense amplifier (CA1), a current-
SENSE
error amplifier (CEA1), an oscillator providing the carri-
er ramp, and a PWM comparator (CPWM1). The
precision current-sense amplifier (CA1) amplifies the
sense voltage across R
by a factor of 36. The
SENSE
inverting input to CEA1 senses the output of CA1. The
output of CEA1 is the difference between the voltage-
error amplifier output (EAOUT1) and the gained-up volt-
age from CA1. The RC compensation network
connected to CLP1 provides external frequency com-
pensation for the respective CEA1 (see the
Compensation section). The start of every clock cycle
enables the high-side driver and initiates a PWM on-
cycle. Comparator CPWM1 compares the output volt-
age from CEA1 against a 0 to 2V ramp from the
oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
Control Loop
The MAX15034 uses an average current-mode control
topology to regulate the output voltage. The control
loop consists of an inner current loop and an outer volt-
age loop. The inner current loop controls the output
R
CF
C
CF
CSN1
CSP1
CA 1
CLP1
C
CFF
V
IN
I
L
CEA1
R
F
R
SENSE
V
OUT1
CPWM1
DRIVE
2V
P-P
R1
R2
VEA1
LOAD
C
OUT
V
REF
= 0.61V
Figure 2. Current and Voltage Loops
______________________________________________________________________________________ 13
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
The outer voltage control loop consists of the voltage-
error amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive volt-
age-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
The voltage at full load is given by:
⎛
⎞
⎟
⎠
R
1
V
= 0.6125 × 1+
− ∆V
OUT
OUT(FL)
⎜
⎝
R
2
where ∆V
is the voltage-positioning window
OUT
described in the Adaptive Voltage Positioning section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of out-
put capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
Current-Error Amplifier
The MAX15034 features two dedicated transconduc-
tance current-error amplifiers CEA1 and CEA2 with a
MAX15034
typical g of 550µS and 320µA output sink and source
m
capability. The current-error amplifier outputs (CLP1 and
CLP2) serve as the inverting input to the PWM compara-
tors. CLP1 and CLP2 are externally accessible to pro-
vide frequency compensation for the inner current loops
(see C , C , and R in Figure 2). Compensate the
CFF CF CF
current-error amplifier so that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
The MAX15034 internal 0.6125V reference provides a
tolerance of 1.25%. Using 0.1% resistors for R1 and
R2 allows a 4% variation from the nominal output volt-
age. This available voltage range allows the reduction
of the total number of output capacitors to meet a given
transient response requirement resulting in a voltage-
positioning window as shown in Figure 5.
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the current-
error amplifier output to a 2V
ramp. At the start of
P-P
each clock cycle an R-S flip-flop resets and the high-
side drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminat-
ing the on-cycle.
From the allowable voltage-positioning window calcu-
late the value of R from the equation below.
F
Voltage-Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
I
× R
× 36 × R
SENSE 1
OUT
R
=
F
∆V
OUT
-0.234V relative to V
= 0.61V. Set the MAX15034 out-
CM
where ∆V
is the allowable voltage-positioning win-
is the sense resistor, 36 is the current-
sense amplifier gain, and R is as shown in Figure 4.
put voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load, the
output of the voltage error amplifier is zero.
OUT
SENSE
dow, R
1
Use the equation below to calculate the no load voltage:
⎛
⎞
⎟
⎠
R
1
V
= 0.6125 × 1+
OUT(NL)
⎜
⎝
R
2
14 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
V
DD
CLP_
CSP_
CSN_
A = 36V/V
V
g
m
= 500µS
PWM
COMPARATOR
BST_
DH_
LX_
GM
IN
S
R
Q
Q
RAMP
CLK
2 x f (V/S)
SW
DL_
1.225V
PGND
EN_
Figure 3. Current Comparator and MOSFET Driver Logic
V
OUT
V
+ ∆V /2
CNTR
OUT
R
F
V
CNTR
R
R
1
EAN_
V
- ∆V /2
CNTR
OUT
C
OUT
LOAD
EAOUT_
2
V
REF
= 0.61V
NO LOAD
1/2 LOAD
LOAD (A)
FULL LOAD
Figure 4. Voltage Error Amplifier
Figure 5. Defining the Voltage-Positioning Window
cycle is less than 50%, choose high-side MOSFETs (Q2
and Q4, Figure 6) with a moderate R and a very
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side dri-
vers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capa-
bility of these drivers provides ample drive for the fast
rise and fall times of the switching MOSFETs. Faster rise
and fall times result in reduced switching losses. For low-
output, voltage-regulating applications where the duty
DS(ON)
low gate charge. Choose low-side MOSFETs (Q1 and
Q3, Figure 6) with very low R and moderate gate
DS(ON)
charge. The driver block also includes a logic circuit that
provides an adaptive nonoverlap time (30ns typ) to pre-
vent shoot-through currents during transition. Figure 7
shows the dual-phase, single-output buck regulator.
______________________________________________________________________________________ 15
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
V
IN
C5
10µF
IN
REG
V
DD
R3
D1
1Ω
(100mA, 30V)
22Ω
C2
1µF
C3
C4
4.7µF
BST1
D2
22Ω
0.1µF
(100mA, 30V)
MAX15034
Q2
IRF7821
BST2
C8
0.1µF
Q4
IRF7821
C9
0.1µF
DH1
LX1
L1
0.5µH
R1
DH2
LX2
L2
0.8µH
2mΩ
0.8V/10A
Q1
IRF7832
R2
2mΩ
1.3V/10A
Q3
IRF7832
MAX15034
DL1
C6
680µF
DL2
C7
680µF
PGND
R4
1.74kΩ
CSP1
CSN1
R6
5.11kΩ
CSP2
CSN2
EAN1
EAN2
EAOUT1
R5
4.64kΩ
EAOUT2
R8
29.4kΩ
R7
4.75kΩ
R9
60.4kΩ
MODE
CLP1
V
REG
R16
100kΩ
C10
15nF
R14
1kΩ
EN1
EN2
C14
0.1µF
C11
120pF
R17
100kΩ
C12
15nF
R15
1kΩ
C15
0.1µF
CLP2
PGND
C13
120pF
RT/CLKIN
AVGLIMIT
AGND
V
REG
R18
19.6kΩ
R19
10kΩ
R
T
24.9kΩ
EXTERNAL FREQUENCY SYNC
Figure 6. Dual-Output Buck Regulator
16 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
V
IN
C5
10µF
IN
REG
V
R3
DD
1Ω
D1
(100mA, 30V)
22Ω
C3
C4
4.7µF
C2
1µF
BST1
D2
0.1µF
22Ω
(100mA, 30V)
Q2
IRF7821
BST2
C8
0.1µF
Q4
IRF7821
DH1
LX1
C9
0.1µF
L1
0.8µH
R1
DH2
LX2
L2
0.8µH
2mΩ
1.3V/20A
Q1
IRF7832
R2
2mΩ
Q3
IRF7832
MAX15034
DL1
C6
680µF
DL2
PGND
R4
5.11kΩ
CSP1
CSN1
CSP2
CSN2
EAN1
EAN2
EAOUT1
R5
4.75kΩ
EAOUT2
R8
60.4kΩ
MODE
CLP1
TO REG
V
REG
R16
100kΩ
C10
15nF
R14
1kΩ
EN1
C14
C11
120pF
0.1µF
R17
100kΩ
EN2
C12
15nF
R15
1kΩ
C15
0.1µF
CLP2
PGND
C13
120pF
RT/CLKIN
AVGLIMIT
AGND
R
T
24.9kΩ
EXTERNAL FREQUENCY SYNC
Figure 7. Dual-Phase, Single-Output Buck Regulator
______________________________________________________________________________________ 17
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
where 24.75mV is the maximum average current-limit
Design Procedures
threshold for the current-sense amplifier and R
the sense resistor.
is
SENSE
Inductor Selection
The switching frequency per phase, peak-to-peak ripple
current in each phase, and allowable voltage ripple at
the output, determine the inductance value. Selecting
higher switching frequencies reduces the inductance
requirement, but at the cost of lower efficiency due to
the charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs. The situation
worsens at higher input voltages, since capacitive
switching losses are proportional to the square of the
input voltage. Lower switching frequencies on the other
hand increase the peak-to-peak inductor ripple current
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, R
, power dissipation, the maximum
DS(ON)
drain-to-source voltage, and package thermal imped-
ance. The product of the MOSFET gate charge and on-
resistance is a figure of merit, with a lower number
signifying better performance. Choose MOSFETs opti-
mized for high-frequency switching applications. The
average gate-drive current from the MAX15034’s output
is proportional to the total capacitance it drives at DH1,
DH2, DL1, and DL2. The power dissipated in the
MAX15034 is proportional to the input voltage and the
average drive current. See the Supply Voltage
MAX15034
(∆I ), and therefore, increase the MOSFET conduction
losses (see the Power MOSFET Selection section for a
detailed description of MOSFET power loss).
L
Connections (V /V
) and the Low-Side MOSFET
IN REG
When using higher inductor ripple current, the ripple can-
cellation in the multiphase topology, reduces the input
and output capacitor RMS ripple current. Use the follow-
ing equation to determine the minimum inductance value:
Drives Supply (V ) sections to determine the maxi-
DD
mum total gate charge allowed from all driver outputs
together.
The losses may be broken into four categories: conduc-
tion loss, gate drive loss, switching loss, and output loss.
The following simplified power loss equation is true for
both MOSFETs in the synchronous buck-converter:
V
(V
− V
)
OUT IN(MAX)
OUT
L =
V
× f
× ∆I
IN SW L
Choose ∆I to be equal to approximately 30% of the out-
L
put current per channel. Since ∆I affects the output-rip-
P
= P
+ P
L
LOSS
CONDUCTION
GATEDRIVE
+ P
OUTPUT
ple voltage, the inductance value may need minor
adjustment after choosing the output capacitors for full-
rated efficiency. Choose inductors from the standard
high-current, surface-mount inductor series available
from various manufacturers. Particular applications may
require custom-made inductors. Use high-frequency core
+ P
SWITCH
For the low-side MOSFET, the P
virtually zero because the body diode of the MOSFET is
conducting before the MOSFET is turned on.
term becomes
SWITCH
Tables 1 and 2 describe the different losses and shows
an approximation of the losses during that period.
material for custom inductors. High ∆I causes large
L
peak-to-peak flux excursion increasing the core losses at
higher frequencies. The high-frequency operation cou-
Input Capacitance
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source, dictate the capacitance
requirement. Increasing the number of phases increas-
es the effective switching frequency and lowers the
peak-to-average current ratio, yielding lower input
capacitance requirement. It can be shown that the
worst-case RMS current occurs when only one con-
troller section is operating. The controller section with
the highest output power needs to be used in determin-
ing the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other out-
of-phase controller section results in reducing the input
pled with high ∆I , reduces the required minimum induc-
L
tance and even makes the use of planar inductors
possible. The advantages of using planar magnetics
include low-profile design, excellent current sharing
between phases due to the tight control of parasitics, and
low cost. For example, the minimum inductance at V
=
IN
12V, V
= 0.8V, ∆I = 3A, and f
= 500kHz is 0.5µH.
OUT
L
SW
The average current-mode control feature of the
MAX15034 limits the maximum inductor current, which
prevents the inductor from saturating. Choose an
inductor with a saturating current greater than the
worst-case peak inductor current:
−3
∆I
2
24.75 × 10
L
I
=
+
L_PEAK
R
SENSE
18 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
SEGMENT LOSS
P
= I
2 × R
×I
CONDUCTION RMS
DS(ON)
Losses associated with MOSFET on-time and
Conduction Loss on-resistance. I
and duty cycle.
is a function of load current
RMS
V
OUT
where I
≈
RMS
LOAD
V
IN
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q )
G
P
= V × Q − Q
× f
GD SW
(
)
Gate Drive Loss
GATEDRIVE
DD
G
specification.
Losses during the drain voltage and drain
current transitions for every switching cycle.
(Q
+ Q
)
GS2
I
GD
P
= V ×I
× f
×
Losses occur only during the Q
time period and not during the initial Q
period. The initial Q period is the rise in the
and Q
SWITCH
IN LOAD SW
GS2
GD
GS1
GATE
GS1
Switching Loss
gate voltage from zero to V
R
is the high-
TH. DH_
V
side MOSFET driver’s on-resistance and R
GATE
DD
+ R
where I
=
GATE
is the internal gate resistance of the high-side
MOSFET (Q and Q are found in the
2 × (R
)
DH_
GATE
GD
GS2
MOSFET data sheet).
Losses associated with Q
of the MOSFET
OSS
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs, but are dissipated in the high-side
MOSFET.
Q
+ Q
OSS(HS)
OSS(LS)
Output Loss
P
=
× V × f
IN SW
OUTPUT
2
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R
).
ESR_OUT
The peak-to-peak inductor current ripple is given by:
V
(V − V
)
OUT IN
OUT
V
(1− D)
I
≈I
OUT
CIN(RMS) MAX
∆I =
V
L
IN
L × f
SW
where I
is the full load current of the regulator. V
OUT
MAX
During a load step, the allowable deviation of the output
voltage during the fast transient load dictates the output
capacitance and ESR. The output capacitors supply the
load step until the controller responds with a greater duty
is the output voltage of the same regulator and C is C5
IN
in Figure 6. The ESR of the input capacitors wastes
power from the input and heats up the capacitor.
Reducing the ESR is important to maintain a high overall
efficiency and in reducing the heating of the capacitors.
cycle. The response time (t
) depends on the
RESPONSE
closed-loop bandwidth of the regulator. The resistive
drop across the capacitor’s ESR and capacitor discharge
causes a voltage drop during a load step. Use a combi-
nation of SP polymer and ceramic capacitors for better
transient load and ripple/noise performance.
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
______________________________________________________________________________________ 19
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 2. Low-Side MOSFET Losses
LOSS
DESCRIPTION
SEGMENT LOSSES
P
= I
2 ×R
CONDUCTION RMS
DS(ON)
− V
OUT
Losses associated with MOSFET on-time, I
is a function of load current and duty cycle.
RMS
Conduction Loss
V
IN
where I
≈
×I
LOAD
RMS
V
IN
Losses associated with charging and
MAX15034
discharging the gate of the MOSFET every
Gate Drive Loss
cycle. There is no Q
MOSFET due to the zero-voltage turn-on. The
charge involved is (Q - Q ).
charging involved in this
P
= V × Q − Q
× f
GD SW
GD
(
)
GATEDRIVE
DD
G
G
GD
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
The minimum average voltage, at which the voltage
across the current-sense resistor is clamped, is either
internally set to 20.4mV or is controlled by the voltage
at AVGLIMIT. The AVGLIMIT ground threshold of
550mV (typ) is the threshold above which the control of
the average current-limit voltage is transferred from the
internal 20.4mV (min) reference to the externally set
(∆V
). During a load step, assume a 50% contribu-
OUT
tion each from the output capacitance discharge and
the voltage drop across the ESR (∆V = ∆V
OUT
ESR_OUT
+ ∆V
). Use the following equations to calculate
the required ESR and capacitance value:
Q_OUT
V
. For using the internal average current-limit
AVGLIMIT
∆V
value, short AVGLIMIT to AGND. The minimum (inter-
nally set) average current limit is set at:
ESR_OUT
R
=
ESR_OUT
I
LOAD_STEP
I
× t
LOAD_STEP RESPONSE
20.4mV
C
=
OUT
I
=
LIMIT(MIN)
∆V
Q_OUT
R
SENSE
where I
RESPONSE
is the step in load current and
is the response time of the controller.
LOAD_STEP
For example, the current-sense resistor:
t
Controller response time depends on the control-loop
bandwidth. C is C6 and C7 in Figure 6.
20.4mV
10A
OUT
R
=
= 2.04mΩ
SENSE
Current Limit
for a maximum output current limit of 10A. A standard
value is 2mΩ. Also, adjust the value of the current-
sense resistor to compensate for parasitics associated
with the PCB. Select a noninductive resistor with an
appropriate wattage rating.
The MAX15034 incorporates two forward current-limit
protection mechanisms, average current limit and hic-
cup fault current limit, which accurately limit the output
current per phase. The average current-mode control
technique of the MAX15034 accurately limits the maxi-
mum average output current per phase. The
MAX15034 senses the voltage across either a sense
resistor or can implement lossless inductor sense,
sensing the voltage across the parasitic resistance of
the inductor (DCR). Use either mechanism to limit the
maximum inductor current.
The implementation is shown in Figure 8.
When sensing directly across the inductor, connect an
RC circuit directly across the shunt or inductor (see
Figure 9).
20 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
L
OUT
R
SENSE
V
OUT
LX_
MAX15034
CSP_
CSN_
Figure 8. Noninductive Resistive Sense
INDUCTOR
L
DCR
C1
V
OUT
LX_
R1
MAX15034
CSP_
CSN_
R2*
C3*
C2*
*OPTIONAL.
Figure 9. Lossless Inductor Sense
Set the RC time constant to be 1.1 to 1.2 times the
inductor time constant (L/DCR). Select C1 to be in the
0.1µF to 0.47µF range, and then calculate R1 from:
parallel with R2 to aid in short-circuit recovery. Set C3
equal to C1. Finally, it may be helpful to add a 100pF
(C2) capacitor immediately across the CSP_ and CSN_
inputs to minimize high-frequency noise pick-up at the
IC in some applications.
1.2 × L[µH]
R1[kΩ] =
For current-sense resistors that have a noticeable
inductance component, use lossless inductor sense
implementation (and design procedure). See Figure 10.
DCR[mΩ]× C1[µF]
In some applications, it may be useful to add a resistor
(R2 in Figure 9) in series with the CSN_ connection to
minimize input offset error. Set R2 equal to R1. It may
also prove useful to add capacitor C3 (Figure 9) in
Table 3 highlights the tradeoffs of each current-sense
method.
Table 3. Current-Sense Configurations
CURRENT-SENSE
INDUCTOR-SATURATION
PROTECTION
CURRENT-SENSE POWER
LOSS (EFFICIENCY)
METHOD
ACCURACY
2
Output Current-Sense Resistor
High
Low
Allowed (highest accuracy)
Allowed
R
x I
SENSE OUT
Equivalent Inductor DC Resistance
No additional loss
______________________________________________________________________________________ 21
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
SENSE RESISTOR (INDUCTIVE)
L
OUT
ESL
R1
R
SENSE
V
OUT
LX_
C1
MAX15034
MAX15034
CSP_
CSN_
R2
C3
C2
Figure 10. Inductive Sense Resistor
The MAX15034 provides precision average current-limit
programmability while using standard sense resistors
or shunts. Use the equation below to determine the
Programming the Average Current Limit
The MAX15034 average current-limit reference voltage
is set by connecting a resistor-divider network from
REG to AGND, the center node is connected to
AVGLIMIT. The resistive divider’s upper resistor, R1, is
connected between REG and the AVGLIMIT. The resis-
tive divider’s lower resistor, R2, is connected between
the AVGLIMIT and AGND.
appropriate V
AVGLIMIT:
external reference voltage at
AVGLIMIT
V
= 56 × R
(
[mΩ] × I
[A] + 612.5mV
)
AVGLIMIT
SENSE
LOAD(MAX)
The resistor-divider values are determined by first,
choosing R2. To minimize reference noise select R2
such that (R1 + R2) < 100kΩ; a typical value is 10kΩ.
Next, determine R1 from:
For example, assuming the desired average current
limit is 18A, and R
= 2mΩ.
SENSE
V
= 2mΩ × 36 ×18A + 612.5mV
(
)
AVGLIMIT
= 1910mV = 1.91V
⎛
⎞
V
REG
R1= R2 ×
−1
⎜
⎟
V
⎝
⎠
AVGLIMIT
where R
is determined from maximum load cur-
SENSE
rent, wattage rating, and circuit parasitics (see above)
and I from circuit requirements. V is
⎛
⎜
⎞
5V
LOAD(MAX)
AVGLIMIT
= 10kΩ ×
−1
⎟
V
[V]
the average current-limit reference voltage selected for
a desired I and is set by a resistive voltage-
⎝
⎠
AVGLIMT(MAX)
LOAD(MAX)
From the example above, assuming V
= 1.91V:
AVGLIMIT
divider from REG to AGND. See the Programming the
Average Current Limit section.
5V
⎛
⎞
The second current-protection circuit is the hiccup fault
protection as explained in the Hiccup Fault Protection
section. The average current during a short at the out-
put is given by:
R1= 10kΩ ×
−1 = 16.18kΩ
⎟
⎜
⎝
⎠
1.91V
A standard value for R1 is 16.2kΩ. Connect AVGLIMIT
to AGND for default current limit
⎛
⎝
⎞
⎠
20.4mV
I
= 0.0625 × I
LOAD(MAX)
AVG(SHORT)
.
⎜
⎟
R
SENSE
22 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
1) The average current tracks the programmed cur-
rent with a high degree of accuracy.
Reverse Current Limit
The MAX15034 limits the reverse current when the out-
put capacitor voltage is higher than the preset output
voltage. Calculate the maximum reverse current limit
2) Slope compensation is not required, but there is a
limit to the loop gain at the switching frequency to
achieve stability.
based on V
and the current-sense resistor
CLMP_LO
R
.
SENSE
3) Noise immunity is excellent.
−3
4) The average current-mode method can be used to
sense and control the current in any circuit branch.
1.55 ×10
R
I
=
REVERSE
SENSE
For stability of the current loop, the amplified inductor-
current downslope at the negative input of the PWM
comparator (CPWM1 and CPWM2) must not exceed
the ramp slope at the comparator’s positive input. This
puts an upper limit on the current-error amplifier gain at
the switching frequency. The inductor current downs-
Output-Voltage Setting
The output voltage is set by the combination of resistors
R1, R2, and R as described in the Voltage-Error
F
Amplifier section. First select a value for resistor R2. Then
calculate the value of R1 from the following equation:
lope is given by V
/L where L is the value of the
OUT
inductor (L1 and L2 in Figure 6) and V
is the output
OUT
(V
− 0.6125)
OUT(NL)
voltage. The amplified inductor current downslope at
the negative input of the PWM comparator is given by:
R1=
× R2
0.6125
where V
is the voltage at no load. Then find the
OUT(NL)
∆V
∆t
V
OUT
L
L
value of R from the following equation:
F
=
× R
× 36 × g × R
SENSE m CF
I
× R
× 36 × R
SENSE 1
OUT
where R
is the current-sense resistor (R1 and R2
SENSE
R
=
F
∆V
in Figure 6) and g x R is the gain of the current-error
OUT
M
CF
amplifier (CEA_) at the switching frequency. The slope
of the ramp at the positive input of the PWM comparator
where ∆V
is the allowable drop in voltage from no
OUT
load to full load. R is R8 and R9, R1 is R4 and R6, R2
F
is 2V x f . Use the following equation to calculate the
SW
is R5 and R7 in Figure 6.
maximum value of R (R14 or R15 in Figure 6).
CF
Compensation
The MAX15034 uses an average current-mode control
scheme to regulate the output voltage (see Figure 2).
The main control loop consists of an inner current loop
and an outer voltage loop. The voltage error amplifier
(VEA1 and VEA2) provides the controlling voltage for
the current loop in each phase. The output inductor is
hidden inside the inner current loop. This simplifies the
design of the outer voltage control loop and also
improves the power-supply dynamics. The objective of
the inner current loop is to control the average inductor
current. The gain-bandwidth characteristic of the cur-
rent loop can be tailored for optimum performance by
the compensation network at the output of the current-
error amplifier (CEA1 or CEA2). Compared with peak
current-mode control, the current-loop gain crossover
2 × f
× L
× 36 × g
SW
R
≤
(1)
CF
V
× R
OUT
SENSE m
The highest crossover frequency f
is given by:
CMAX
f
× V
IN
SW
f
=
CMAX
2π × V
OUT
or alternatively:
f
× 2π × V
OUT
CMAX
f
=
SW
V
IN
Equation (1) can now be rewritten as:
frequency, f , can be made approximately the same,
C
π × f × L
but the gain at low frequencies is much higher. This
results in the following advantages over peak current-
mode control.
C
R
=
(2)
CF
V
× R × 9 × g
S m
IN
______________________________________________________________________________________ 23
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
In practical applications, pick the crossover frequency
(f ) in the range of:
especially true for dual-phase converters where one
channel can affect the other. Use the following guide-
lines for PCB layout:
C
f
f
SW
2
SW
< f
<
C
1) Place the V , REG, and the BST1 and BST2 bypass
DD
10
capacitors close to the MAX15034.
First calculate R in equation 2 above. Calculate C
CF
CF
2) Minimize all high-current switching loops.
so that:
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs (2oz or higher) to enhance effi-
ciency and minimize trace inductance and resis-
tance.
10
2 × π × f × R
C
=
CF
C
CF
MAX15034
where C is C10 and C12 in Figure 6.
CF
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
Calculate C
so that:
CFF
1
C
=
CFF
2 × π × f ×10 × R
C
CF
where C
is C11 and C13 in Figure 6.
CFF
5) Place the bank of output capacitors close to the
load.
Applications Information
Independent Turn-On and Turn-Off
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
The MAX15034 can be used to regulate two outputs
from one controller. Each of the two outputs can be
turned on and off independently of one another by con-
trolling the enable input of each phase (EN1 and EN2).
A logic-low on each enable pin shuts down the
MOSFET drivers for that phase. When the voltage on the
enable pin exceeds 1.2V, the drivers are turned on and
the output can come up to regulation. This method of
turning on the outputs allows the MAX15034 to be used
for power sequencing.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
8) Distribute the power components evenly across the
top side for proper heat dissipation.
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
10) Place all input bypass capacitors for each input as
close to each other as is practical.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low losses, low
output noise, and clean and stable operation. This is
24 ______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Pin Configuration
Chip Information
PROCESS: BiCMOS
TOP VIEW
+
CSN2
CSP2
1
2
3
4
5
6
7
8
9
28 EN2
27 BST2
26 DH2
25 LX2
24 DL2
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
EAOUT2
EAN2
CLP2
MAX15034
AVGLIMIT
RT/CLKIN
AGND
23 PGND
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
22 IN
21 REG
28 TSSOP
U28+2
21-0066
21-0108
90-0171
90-0146
MODE
20 V
DD
28 TSSOP-EP
U28E+4
CLP1 10
EAN1 11
19 DL1
18 LX1
17 DH1
16 BST1
15 EN1
EAOUT1 12
CSP1 13
*EXPOSED PAD
CSN1 14
TSSOP
*CONNECT EXPOSED PAD TO GROUND PLANE.
MAX15034A DOES NOT HAVE AN EXPOSED PAD.
______________________________________________________________________________________ 25
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
7/08
Initial release
—
1
10/11
Updated Ordering Information.
MAX15034
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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