MAX15037 [MAXIM]
2.2MHz, 3A Buck or Boost Converters with an Integrated High-Side Switch;
| 型号： | MAX15037 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 2.2MHz, 3A Buck or Boost Converters with an Integrated High-Side Switch |
| 文件： | 总25页 (文件大小：396K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4222; Rev 0; 7/08
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
General Description
Features
o 4.5V to 5.5V or 5.5V to 23V Input Voltage Range
The MAX15036/MAX15037 high-frequency, DC-DC con-
verters with an integrated n-channel power MOSFET
provide up to 3A of load current. The MAX15036
includes an internal power MOSFET to enable the
design of a nonsynchronous buck or boost topology
power supply. The MAX15037 is for the design of a
synchronous buck topology power supply. These
devices operate from a 4.5V to 5.5V or 5.5V to 23V
input voltage and offer the ability to set the switching
frequency from 200kHz to 2.2MHz with an external
resistor. The voltage-mode architecture with a peak
switch current-limit scheme provides stable operation
up to a 2.2MHz switching frequency. The MAX15036
includes a clock output for driving a second DC-DC
converter 180° out-of-phase and a power-on-reset
(RESET) output. The MAX15037 includes a power-good
output and a synchronous rectifier driver to drive an
external low-side MOSFET in the buck converter config-
uration for high efficiency.
o Output Voltage Adjustable Down to 0.6V (Buck) or
Up to 28V (Boost)
o 3A Output Current
o Synchronous Rectifier Driver Output (MAX15037)
for Higher Efficiency
o Resistor-Programmable Switching Frequency
from 200kHz to 2.2MHz
o External Synchronization and Enable (On/Off)
Inputs
o Clock Output for Driving Second Converter 180°
Out-Of-Phase (MAX15036)
o Integrated 150mΩ High-Side n-Channel Power
MOSFET
o Power-On-Reset Output (MAX15036)/Power-Good
Output (MAX15037)
o Short-Circuit Protection (Buck)/Maximum Duty-
Cycle Limit (Boost)
o Thermal-Shutdown Protection
The MAX15036/MAX15037 protect against overcurrent
conditions by utilizing a peak current limit as well as
overtemperature shutdown providing a very reliable
and compact power source for point-of-load regulation
applications. Additional features include synchroniza-
tion, internal digital soft-start, and an enable input. The
MAX15036/MAX15037 are available in a thermally
enhanced, space-saving 16-pin TQFN (5mm x 5mm)
package and operate over the -40°C to +125°C tem-
perature range.
o Thermally Enhanced 16-Pin TQFN Package
Dissipates 2.7W
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
MAX15036ATE+
MAX15037ATE+
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Applications
Pin Configurations
xDSL Modem Power Supplies
Automotive Radio Power Supplies
Servers and Networks
TOP VIEW
12
11
10
9
IP Phones/WLAN Access Points
V
8
7
6
5
SYNC
13
L
Selector Guide
RESET 14
V+
PART
CONFIGURATION
FEATURES
MAX15036
Nonsynchronous
Buck or Boost
RESET Output,
Clock Output
BST/VDD 15
BYPASS
OSC
MAX15036ATE
16
EN
EP*
PGOOD Output,
Synchronous FET
Driver
+
MAX15037ATE
Synchronous Buck
1
2
3
4
Pin Configurations continued at end of data sheet.
THIN QFN
5mm x 5mm
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
1
For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
ABSOLUTE MAXIMUM RATINGS
V+ to PGND............................................................-0.3V to +25V
BST/VDD, DRAIN to SGND ....................................-0.3V to +30V
SGND to PGND .....................................................-0.3V to +0.3V
BST/VDD to SOURCE...............................................-0.3V to +6V
SOURCE to SGND..................................................-0.6V to +25V
SOURCE or DRAIN Maximum Peak Current...............5A for 1ms
BYPASS to SGND..................................................-0.3V to +2.2V
V and BYPASS Short-Circuit Duration to SGND ......Continuous
L
Continuous Power Dissipation (T = +70°C)
A
16-Pin TQFN (derate 33mW/°C above +70°C) ..........2666mW
Junction-to-Case Thermal Resistance (θ ) (Note 1)
JC
16-Pin TQFN................................................................1.7°C/W
V to SGND ................-0.3V to the lower of +6V and (V+ + 0.3V)
SYNC, EN, DL, CKO, OSC, COMP,
Junction-to-Ambient Thermal Resistance (θ ) (Note 1)
JA
L
16-Pin TQFN.................................................................30°C/W
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature Range............................-65°C to +150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
FB to SGND...............................................-0.3V to (V + 0.3V)
L
BYPASS, CKO, OSC, COMP, FB, EN, SYNC, RESET,
PGOOD Maximum Input Current ................................. 50mA
RESET, PGOOD to SGND ........................................-0.3V to +6V
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = V = 5V or V+ = 5.5V to 23V, V = 5V, T = T = -40°C to +125°C, unless otherwise noted. Circuits of Figures 5 and 6. Typical
L
EN
A
J
values are at T = T = +25°C.) (Note 2)
6/MAX15037
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
5.5
4.5
23.0
5.5
Input Voltage Range
V+
V
V+ = V
L
V+ = 12V, V = 0.8V
FB
V+ Operating Supply Current
I
1.8
1
2.5
mA
Q
R
OSC
= 10kΩ, no switching
V+ = 12V, V = 0V, PGOOD
EN
(MAX15037), RESET, CKO unconnected
V+ Standby Supply Current
I
1.4
mA
%
STBY
(MAX15036), R
= 10kΩ
OSC
Nonsynchronous (MAX15036),
= 1.25MHz, V+ = 12V, I
f
= 1.5A,
OUT
79
90
SW
V
= 3.3V
OUT
Efficiency
η
Synchronous (MAX15037),
= 300kHz, V+ = 12V, I
f
= 1.5A,
OUT
SW
V
= 3.3V
OUT
V REGULATOR (V )/BYPASS OUTPUT (BYPASS)
L
L
V Undervoltage Lockout
V
V falling
4.1
137
5.2
110
2
4.3
5.5
V
mV
V
L
UVLO
L
V Undervoltage Lockout
L
Hysteresis
V
HYST
V Output Voltage
L
V
V+ = 5.5V to 23V, I = 0 to 40mA
5.0
L
VL
V Regulator Short-Circuit
L
Current
I
V
= 5.5V
IN
mA
V
VLSHORT
BYPASS Output Voltage
V
V+ = V = 5.2V, I = 0
BYPASS
1.98
0
2.02
5
BYPASS
L
I
steps from 0 to 50μA,
BYPASS
BYPASS Load Regulation
ΔV
1.2
mV
BYPASS
V+ = V = 5.2V
L
2
_______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
ELECTRICAL CHARACTERISTICS (continued)
(V+ = V = 5V or V+ = 5.5V to 23V, V = 5V, T = T = -40°C to +125°C, unless otherwise noted. Circuits of Figures 5 and 6. Typical
L
EN
A
J
values are at T = T = +25°C.) (Note 2)
A
J
PARAMETER
SOFT-START
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Clock
periods
Digital Soft-Start Period
Internal 6-bit DAC
4096
64
Soft-Start Steps
Steps
ERROR AMPLIFIER (FB and COMP)
FB to COMP Transconductance
FB Input Bias Current
g
1.20
1.8
2.75
250
mS
nA
V
M
I
FB
FB Input Voltage Set Point
V
0.591
100
0.600
150
0.609
FB
COMP Sink-and-Source Current
Capability
I
μA
COMP
INTERNAL MOSFETs
On-Resistance n-Channel Power
MOSFET
R
V+ = V = 5.2V, I = 100mA
SINK
0.150
0.302
20
Ω
ON
L
V
= 0V, V
= 23V,
DRAIN
EN
Leakage Current
I
μA
LEAK
SOURCE = PGND
Minimum Output Current
Peak Current Limit
I
V
= 3.3V, V+ = 12V (Note 3)
3
A
A
OUT
OUT
I
3.56
4.6
5.6
40
LIMIT
On-Resistance Internal Low-Side
Switch
R
I
= 50mA, V+ = V = 5.2V
20
Ω
ONLSW
SWITCH
L
SYNCHRONOUS RECTIFIER DRIVER (DL) (MAX15037 Only)
On-Resistance nMOS
On-Resistance pMOS
Peak Sink Current
R
R
I
I
= 10mA
1
1.9
1
4
5
Ω
Ω
A
A
ONDLN
ONDLP
SINK
= 10mA
SOURCE
I
IDL_SINK
Peak Source Current
I
0.75
IDL_SOURCE
CLOCK OUTPUT (CKO) (MAX15036 Only)
Clock Output-High Level
Clock Output-Low Level
V
V = 5.2V, I = 5mA
SOURCE
3.54
V
V
CKOH
L
V
V = 5.2V, I = 5mA
L SINK
0.4
CKOL
Clock Output Phase Delay With
Respect to SOURCE Waveform
R
= 10kΩ, SYNC = GND
OSC
CKO
115
Degrees
PHASE
(Note 4)
OSCILLATOR (OSC)/SYNCHRONIZATION (SYNC)
R
OSC
R
OSC
R
OSC
= 5.62kΩ
= 41.2kΩ
= 10kΩ
2100
312
Switching Frequency
f
V+ = V = 5.2V
L
kHz
SW
1130
82
1250
120
1380
Minimum Controllable On-Time
Maximum Duty Cycle
t
ns
%
ON_MIN
D
f
= 2.2MHz
87.5
MAX
SW
_______________________________________________________________________________________
3
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
ELECTRICAL CHARACTERISTICS (continued)
(V+ = V = 5V or V+ = 5.5V to 23V, V = 5V, T = T = -40°C to +125°C, unless otherwise noted. Circuits of Figures 5 and 6. Typical
L
EN
A
J
values are at T = T = +25°C.) (Note 2)
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYNC Frequency Range
(Note 5)
200
2200
kHz
SYNC Input to SOURCE Rising-
Edge Phase Delay
R
= 10kΩ, f
= 1.2MHz
OSC
SYNC
SYNC
65
Degrees
PHASE
(Note 6)
SYNC High Threshold
V
2.0
2.0
V
V
SYNCH
SYNC Low Threshold
V
0.8
SYNCL
SYNC Input Bias Current
Minimum SYNC High Pulse Width
I
250
nA
ns
SYNC
t
100
SYNC_H
EN, RESET (MAX15036)/PGOOD (MAX15037)
V
IH
EN Threshold
V
V
0.8
250
95
IL
EN Input Bias Current
RESET Threshold
I
nA
EN
V
V
V
V
= V
= V
(Note 7)
(Note 7)
90
90
92.5
92.5
% V
TH
TH
FB
FB
OUT
OUT
OUT
OUT
PGOOD Threshold
95
% V
6/MAX15037
FB to RESET or FB to PGOOD
Propagation Delay
t
t
3
μs
FD
RP
ms
V
RESET Active Timeout Period
140
200
254
0.4
RESET, PGOOD Output Voltage
Low
V
I
= 3mA
OL
SINK
RESET, PGOOD Output Leakage
Current
V+ = V = 5.2V, V
or
R ESET
L
I
2
μA
LEAK
V
= 6V, V = 0.8V
PGOOD FB
THERMAL SHUTDOWN
Thermal Shutdown
T
Temperature rising
+170
25
°C
°C
SHDN
Thermal-Shutdown Hysteresis
Note 2: 100% tested at T = +25°C and T = +125°C. Limits from T = -40°C to +25°C are guaranteed by design.
A
A
A
Note 3: Output current may be limited by the power dissipation of the package. See the Power Dissipation section in the Applications
Information section.
Note 4: From the rising edge of the SOURCE waveform to the rising edge of the CKO waveform.
Note 5: SYNC input frequency is equal to the switching frequency.
Note 6: From the SYNC rising edge to SOURCE rising edge.
Note 7: RESET goes high 200ms after V
crosses this threshold, PGOOD goes high after V
crosses this threshold.
OUT
OUT
4
_______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
Typical Operating Characteristics
(V+ = V = 5.2V, T = +25°C, Figures 5 and 6, unless otherwise noted.)
L
A
MAX15036 BUCK EFFICIENCY vs. OUTPUT
MAX15036 BUCK EFFICIENCY vs. OUTPUT
CURRENT (V = 12V, f = 2.2MHz)
MAX15036 BUCK EFFICIENCY vs. OUTPUT
CURRENT (V = 5.5V, f = 2.2MHz)
CURRENT (V = 16V, f = 2.2MHz)
IN
SW
IN
SW
IN SW
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
V = 3.3V
OUT
V
= 3.3V
= 2.5V
V
= 3.3V
OUT
OUT
V
OUT
V
= 2.5V
V
= 2.5V
OUT
OUT
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
MAX15037 SYNCHRONOUS
EFFICIENCY vs. OUTPUT CURRENT
MAX15037 SYNCHRONOUS EFFICIENCY vs. OUTPUT
(V = 12V, f = 330kHz, L = 15μH)
CURRENT (V = 12V, f = 2.2MHz, L = 4.7μH)
IN
SW
IN SW
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
60
55
50
V
= 3.3V
OUT
V
= 3.3V
OUT
V
V
= 2.5V
= 1.2V
OUT
OUT
L = TOKO DS126C2-150M
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
MAX15037 OUTPUT VOLTAGE vs. OUTPUT
V OUTPUT VOLTAGE
L
CURRENT (V = 12V, V
= 3.3V, f = 2.2MHz)
vs. SWITCHING FREQUENCY
IN
OUT
SW
5.190
5.185
5.180
5.175
5.170
5.165
5.160
5.155
5.150
3.301
3.300
3.299
3.298
3.297
3.296
3.295
3.294
3.293
3.292
V
= 23V
IN
V
= 5.5V
IN
600
1100
100
1600
2100
0.5
1.0
2.5
0
1.5
2.0
3.0
SWITCHING FREQUENCY (kHz)
OUTPUT CURRENT (A)
_______________________________________________________________________________________
5
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
Typical Operating Characteristics (continued)
(V+ = V = 5.2V, T = +25°C, Figures 5 and 6, unless otherwise noted.)
L
A
SWITCHING FREQUENCY
vs. TEMPERATURE
MAX15037 V DROPOUT VOLTAGE
L
vs. SWITCHING FREQUENCY
SWITCHING FREQUENCY
vs. R
OSC
2350
2100
1850
1600
1350
1100
850
10,000
1000
100
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V+ = 5.5V
R
= 6.04kΩ
= 10kΩ
OSC
V+ = 5.25V
V+ = 5V
R
R
OSC
= 20kΩ
= 40kΩ
OSC
600
R
OSC
350
100
10
60
110
-40
600
1100
0
10
20
30
40
50
60
70
100
1600
2100
TEMPERATURE (°C)
RESISTANCE (kΩ)
SWITCHING FREQUENCY (kHz)
MAX15037 LOAD-TRANSIENT RESPONSE
MAX15037 LINE-TRANSIENT RESPONSE
(I = 1A, V STEP = 14V TO 21V)
6/MAX15037
(I
= 0.2A TO 1A)
OUT
OUT
IN
MAX15036 toc11
MAX15036 toc12
V
= 3.3V
OUT
V
V
= 12V
IN
= 3.3V
OUT
V
OUT
100mV/div
V
5V/div
0V
IN
500mA/div
0A
V
200mV/div
OUT
I
OUT
100μs/div
20μs/div
MAX15037 LOAD-TRANSIENT RESPONSE
MAX15037 SOFT-START AND SHUTDOWN
(I
= 0.5A TO 3A)
(NO LOAD)
OUT
MAX15036 toc13
MAX15036 toc14
V
V
= 12V
IN
V
= 12V
IN
= 3.3V
OUT
V
OUT
200mV/div
V
1V/div
0V
OUT
I
1A/div
0A
OUT
5V/div
0V
V
EN
20μs/div
1ms/div
6
_______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
Typical Operating Characteristics (continued)
(V+ = V = 5.2V, T = +25°C, Figures 5 and 6, unless otherwise noted.)
L
A
RESET TIMEOUT
(MAX15036)
MAX15037 SOFT-START AND SHUTDOWN
(I = 2A)
V
STARTUP WAVEFORM
IN
(EN CONNECTED TO V ) (MAX15037)
OUT
L
MAX15036 toc17
MAX15036 toc15
MAX15036 toc16
V
EN
V
= 12V
IN
5V/div
V
IN
10V/div
V
OUT
2V/div
V
1V/div
0V
OUT
V
EN
5V/div
2V/div
V
V
OUT
PGOOD
5V/div
5V/div
0V
V
EN
V
RESET
5V/div
V
IN
10V/div
40ms/div
1ms/div
1ms/div
MAX15036 EXTERNALLY SYNCHRONIZED
STANDBY CURRENT
vs. TEMPERATURE
SWITCHING WAVEFORM
MAX15036 toc18
1.60
1.55
1.50
1.45
1.40
f
R
= 2.2MHz
SW
5V/div
V
SYNC
= 5.62kΩ
OSC
0V
5V/div
V
CKO
0V
5V/div
V
SOURCE_MASTER
0V
5V/div
V
SOURCE_SLAVE
0V
0
20 40
-40 -20
60
80 100 120
100ns/div
TEMPERATURE (°C)
SWITCHING SUPPLY CURRENT (I
vs. TEMPERATURE
)
MAXIMUM OUTPUT CURRENT
vs. TEMPERATURE
SW
80
70
60
50
40
30
20
10
0
3.75
3.70
3.65
3.60
3.55
3.50
3.45
3.40
3.35
3.30
3.25
V
V
f
= 12V
IN
MAX15036
= 3.3V
OUT
V
I
= 3.3V
= 1A
OUT
OUT
= 1MHz
SW
f
= 2.2MHz
SYNC
f
f
= 1.2MHz
= 600kHz
SYNC
SYNC
f
= 300kHz
0
SYNC
-50 -25
25
50
75 100 125
-40
10
60
110
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
Pin Description
PIN
NAME
FUNCTION
Internal Power MOSFET Drain Connection. Buck converter operation—use the MOSFET as a high-side switch
and connect DRAIN to the input supply. Boost converter operation (MAX15036 only)—use the MOSFET as a
low-side switch and connect DRAIN to the inductor and diode junction.
1, 2
DRAIN
Transconductance Error Amplifier Output. Connect a compensation network from COMP to SGND or from
COMP to FB to SGND (see the Compensation section).
3
4
COMP
FB
Feedback Input. Connect a resistive divider from the output to FB to SGND to set the output voltage.
Switching Frequency Set Input. Connect a resistor R
from OSC to SGND to set the switching frequency.
OSC
5
OSC
When using external synchronization, program R
required when external synchronization is used.
so that (0.8 x f
) ≤ f
≤ (1.2 x f
). R
is still
OSC
SYNC
SW
SYNC
OSC
6
7
BYPASS Reference Bypass Connection. Bypass to SGND with a 0.22μF or greater ceramic capacitor.
Input Supply Voltage. V+ can range from 5.5V to 23V. Connect V+ and V together for 4.5V to 5.5V input
L
V+
operation. Bypass V+ to SGND with a minimum of 0.1μF ceramic capacitor.
Internal Regulator Output. Bypass V to SGND with a 4.7μF ceramic capacitor and to PGND with a 0.1μF
ceramic capacitor. Connect V+ to V for 4.5V to 5.5V operation.
L
L
8
9
V
L
6/MAX15037
Clock Output (MAX15036 Only). CKO is an output with the same frequency as the converter’s switching
frequency and 115° out-of-phase. CKO is used to synchronize the MAX15036 to other MAX15036/MAX15037s.
CKO
Low-Side Synchronous Rectifier Driver (MAX15037 Only). DL sources 0.7A and sinks 1A to quickly turn on and
off the external synchronous rectifier MOSFET.
DL
10
11
SGND
PGND
Signal Ground
Power Ground. Connect the rectifier diode’s anode, the input capacitor negative terminal, the output capacitor
negative terminal, and V bypass capacitor negative terminal to PGND.
L
Internal Power MOSFET Source Connection. Buck converter operation—connect SOURCE to the switched side
of the inductor as shown in Figure 5. Boost converter operation (MAX15036 only)—connect SOURCE to PGND.
12
13
SOURCE
SYNC
External Synchronization Input. Connect SYNC to an external logic-level clock to synchronize the MAX15036/
MAX15037. Connect SYNC to SGND when not used.
Open-Drain Active-Low Reset Output (MAX15036 Only). RESET remains low while the converter’s output is
RESET
below 92.5% of V
’s nominal set point. When V
rises above 92.5% of its nominal set point, RESET goes
OUT
OUT
high after the reset timeout period of 200ms (typ).
14
15
Open-Drain Power-Good Output (MAX15037 Only). PGOOD remains low while the output is below 92.5% of its
nominal set point.
PGOOD
Internal MOSFET Driver Supply Input. Buck converter operation—bootstrap flying capacitor connection.
Connect BST/VDD to an external ceramic capacitor and diode (see Figure 5). Boost converter operation
(MAX15036 only)—driver bypass capacitor connection. Connect a low-ESR 0.1μF ceramic capacitor from
BST/VDD to PGND.
BST/VDD
Enable Input. A logic-low turns off the converter. A logic-high turns on the device. Connect EN to V for an
L
always-on application.
16
—
EN
EP
Exposed Pad. Connect to SGND. Solder EP to SGND to enhance thermal dissipation.
8
_______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
V+
V
L
DRAIN
LDO
V = 5.2V
L
SYNC
CKO
R
SENSE
CURRENT-LIMIT
COMPARATOR
OSCILLATOR
2V
OSC
4-PULSE
SKIP
BST/VDD
R
150mΩ
1V
Q
N2
BYPASS
PWM
COMPARATOR
SOURCE
Q
20Ω
ADAPTIVE
BBM
N3
V
f
/4
SW
REF
PGND
V
= 0.6V
REF
EN
DIGITAL
SOFT-START
g
m
FB
COMP
SGND
RESET
200mV
N1
0.925 x V
REF
200ms
DELAY
MAX15036
Figure 1. MAX15036 Block Diagram
_______________________________________________________________________________________
9
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
V+
DRAIN
V
L
LDO
V = 5.2V
L
SYNC
R
SENSE
CURRENT-LIMIT
COMPARATOR
OSCILLATOR
OSC
4-PULSE
SKIP
BST/VDD
2V
R
150mΩ
1V
Q
N2
BYPASS
PWM
COMPARATOR
SOURCE
6/MAX15037
Q
20Ω
ADAPTIVE
BBM
N3
f
/4
SW
VL
V
REF
DL
PGND
EN
DIGITAL
SOFT-START
V
= 0.6V
g
REF
m
FB
COMP
SGND
200mV
PGOOD
N1
0.925 x V
REF
MAX15037
Figure 2. MAX15037 Block Diagram
10 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
when the inductor current exceeds the peak current limit
Detailed Description
of the internal switch, the high-side MOSFET turns off
PWM Controller
The MAX15036/MAX15037 use a pulse-width modula-
tion (PWM) voltage-mode control scheme. The
MAX15036 is a nonsynchronous converter and uses an
external low-forward-drop Schottky diode for rectifica-
tion. The MAX15037 is a synchronous converter and
drives a low-side, low-gate-charge MOSFET for higher
efficiency. The controller generates the clock signal
from an internal oscillator or the SYNC input when dri-
ven by an external clock. An internal transconductance
error amplifier produces an integrated error voltage at
COMP, providing high DC accuracy. The voltage at
COMP sets the duty cycle using a PWM comparator
quickly and waits until the next clock cycle.
MAX15037
The MAX15037 is intended for synchronous buck oper-
ation only. During the high-side MOSFET on-time, the
inductor current ramps up. When the MOSFET turns off,
the inductor reverses polarity and forward biases the
Schottky rectifier in parallel with the low-side synchro-
nous MOSFET. The SOURCE voltage is clamped to
0.5V below ground until the break-before-make time
(t
BBM
) of 25ns is over. After t
the synchronous rec-
BBM,
tifier MOSFET turns on. The inductor releases the
stored energy as its current ramps down, and contin-
ues providing current to the output. The bootstrap
and an internal 1V
voltage ramp. At each rising
P-P
capacitor is also recharged from the V output when
L
edge of the clock, the converter’s high-side n-channel
MOSFET turns on and remains on until either the
appropriate or maximum duty cycle is reached or the
maximum current limit for the switch is detected.
the MOSFET turns off. The synchronous rectifier keeps
the circuit in continuous conduction mode operation
even at light load. Under overload conditions, when the
inductor current exceeds the peak current limit of the
internal switch, the high-side MOSFET turns off and
waits until the next clock cycle.
In the case of the MAX15036 boost operation, the
MOSFET is a low-side switch. During each on-time, the
inductor current ramps up. During the second half of
the switching cycle, the low-side switch turns off and
forward biases the Schottky diode. During this time, the
The MAX15037, with the synchronous rectifier driver out-
put (DL), has an adaptive break-before-make circuit to
avoid cross conduction between the internal power
MOSFET and the external synchronous rectifier MOSFET.
When the synchronous rectifier MOSFET is turning off, the
DRAIN voltage is clamped to 0.4V (V ) above V
D
OUT
and the inductor provides energy to the output as well
as replenishes the output capacitor charge.
internal high-side power MOSFET is kept off until V falls
DL
MAX15036
During each high-side MOSFET on-time (Figure 5), the
inductor current ramps up. During the second half of the
switching cycle, the high-side MOSFET turns off and for-
ward biases the Schottky rectifier (D2 in Figure 5). During
this time, the SOURCE voltage is clamped to 0.5V below
ground. The inductor releases the stored energy as its
current ramps down, and provides current to the output.
During the MOSFET off-time, when the Schottky rectifier is
conducting, the bootstrap capacitor (C10 in Figure 5) is
below 0.97V. Similarly, DL does not go high until the inter-
nal power MOSFET gate voltage falls below 1.24V.
Input Voltage (V+)/Internal Linear
Regulator (V )
L
All internal control circuitry operates from an internally reg-
ulated nominal voltage of 5.2V (V ). At higher input volt-
L
ages (V+) of 5.5V to 23V, V is regulated to 5.2V. At 5.5V
L
or below, the internal linear regulator operates in dropout
mode, where V follows V+. Depending on the load on V ,
L
L
the dropout voltage can be high enough to reduce V to
L
recharged from the V output. At light loads, the
L
below the undervoltage lockout (UVLO) threshold.
MAX15036 goes in to discontinuous conduction mode
operation when the inductor current completely dis-
charges before the next switching cycle commences.
When the MAX15036 operates in discontinuous conduc-
tion, the bootstrap capacitor can become undercharged.
To prevent this, an internal low-side 20Ω switch (see N3 in
Figure 1) turns on, during the off-time, once every 4 clock
cycles. This ensures that the negative terminal of the boot-
strap capacitor is pulled to PGND often enough to allow it
For input voltages of lower than 5.5V, connect V+ and
V
together. The load on V is proportional to the
L
L
switching frequency of the converter. See the V
L
Output Voltage vs. Switching Frequency graph in the
Typical Operating Characteristics. For an input voltage
higher than 5.5V, use the internal regulator.
Bypass V+ to SGND with a low-ESR 0.1μF or greater
ceramic capacitor placed as close as possible to the
to fully charge to V , ensuring the internal power switch
L
MAX15036/MAX15037. Current spikes from V disturb
L
properly turns on. The operation of the bootstrap capaci-
tor wake-up switch causes a small increase in the output
voltage ripple at light loads. Under overload conditions,
the internal circuitry powered by V . Bypass V with a
L
L
low-ESR 0.1μF ceramic capacitor to PGND and a low-
ESR 4.7μF ceramic capacitor to SGND.
______________________________________________________________________________________ 11
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
the turn-on edge of the internal n-channel power MOSFET
with a fixed propagation delay. When operating the
MAX15036/MAX15037 with an external SYNC clock,
Enable
EN is an active-high input that turns the MAX15036/
MAX15037 on and off. EN is a TTL-logic input with 2.0V
and 0.8V logic-high and low levels, respectively. When
EN is asserted high, the internal digital soft-start cycle
slowly ramps up the internal reference and provides
some soft-start at the output. Hysteresis provides immu-
nity to the glitches during logic turn-on of the converter.
Large voltage variations at EN can interrupt the soft-start
sequence and can cause a latch-up. Ensure that EN
remains high for at least 5ms once it is asserted. Force
EN low to turn off the internal power MOSFET and cause
RESET to go low (MAX15036) or cause PGOOD to go
R
must be installed. Program the internal switching
OSC
frequency so that (0.8 x f
) ≤ f
≤ (1.2 x f
). The
SYNC
SW
SYNC
minimum pulse width for f
to SGND if synchronization is not used.
is 100ns. Connect SYNC
SYNC
The CKO output (MAX15036 only) is a logic-level clock
with the same frequency as f
and with 115° phase
SW
shift with respect to SYNC clock. Two MAX15036s can
be connected in a master/slave configuration for two-
phase (180°) interleaved operation. The CKO output of
the master drives the SYNC input of the slave to form a
dual-phase converter. To achieve the 180° out-of-phase
operation, program the internal switching frequency of
both converters close to each other by using the same
low (MAX15037). Connect EN to V when not used.
L
Soft-Start/Soft-Stop
The MAX15036/MAX15037 include UVLO with hystere-
sis to prevent chattering during startup. The UVLO cir-
cuit holds the MAX15036/MAX15037 off until V+
reaches 4.5V and turns the devices off when V+ falls
below 4.3V. The MAX15036/MAX15037 also offer a
soft-start feature that reduces surge currents and
glitches on the input during turn-on. During turn-on
when the UVLO threshold is reached or EN goes from
low to high, the digital soft-start ramps up the reference
R
value. When synchronizing the master-slave con-
OSC
figuration using external clock, program the internal
switching frequency using R close to the external
OSC
clock frequency (f
) for 180° ripple phase operation
SYNC
(see Figure 8). Any difference in the internal switching
frequency and f changes the phase delay. If both
6/MAX15037
SYNC
master and slave converters use the same power
source, and share input bypass capacitors, the effec-
tive switching frequency at the input is twice the switch-
ing frequency of the individual converter. Higher ripple
frequency at the input capacitor means a lower RMS
ripple current into the capacitor.
(V
) in 64 steps. During a turn-off (by driving EN
BYPASS
or V+ low), the reference is reduced to zero slowly. The
soft-start and soft-stop periods (t ) are 4096 cycles of
SS
the internal oscillator. To calculate the soft-start/soft-stop
period use the following equation:
Current Limit
The MAX15036/MAX15037 protect against output over-
load and short-circuit conditions when operated in a
buck configuration. An internal current-sensing stage
develops a voltage proportional to the instantaneous
switch current. When the switch current reaches 4.6A
(typ), the power MOSFET turns off and remains off until
the next on cycle.
4096
t
=
SS
f
SW
f
is the switching frequency of the converter.
SW
Oscillator/Synchronization
(SYNC)/Clock Output (CLKOUT)
During a severe overload or short-circuit condition when
the output voltage is pulled to ground, the discharging
The clock frequency (or switching frequency) is gener-
ated internally and is adjustable through an external
resistor connected from OSC to SGND. The relationship
slope of the inductor is V (the voltage across the syn-
DS
chronous FET), or V (the voltage across the rectifying
F
between R
and f
is:
SW
OSC
diode) divided by L. The short off-time does not allow
the current to properly ramp down in the inductor, caus-
ing a dangerous current runaway and possibly destruc-
tion of the device. To prevent this, the MAX15036/
MAX15037 include a frequency foldback feature. When
the current limit is detected the frequency is reduced to
1/4th of the programmed switching frequency. When the
output voltage falls below 1/3rd of its nominal set point
8
125 ×10 Ω /s
R
=
OSC
f
SW
The adjustment range for f
2.2MHz.
is from 200kHz to
SW
Connect a logic-level clock between 200kHz to 2.2MHz
at SYNC to externally synchronize the MAX15036/
MAX15037’s oscillator (see Figure 8). The MAX15036/
MAX15037 synchronize to the rising edge of the SYNC
clock. The rising edge of the SYNC clock corresponds to
(V = 0.2V), the converter is turned off and soft-start
FB
cycle is initiated. This reduces the RMS current sourced
by the converter during the fault condition.
12 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
At high input-to-output differential, and high switching
reaches +170°C. A thermal sensor monitors the die
temperature and turns the device on again when the
temperature reduces by +25°C. During thermal shut-
down, the internal power MOSFET shuts off, DL pulls to
frequency, the on-time drops to the order of 100ns.
Even though the MAX15036/MAX15037 can control the
on-time as low as 100ns, the internal current-limit circuit
may not detect the overcurrent within this time. In that
case, the output current during the fault may exceed the
current limit specified in the Electrical Characteristics
table. The MAX15036/MAX15037 may still be protected
against the output short-circuit fault through the
overtemperature shutdown. However, the output switch
current may be as high as 5.6A. If the minimum on-time
for a given frequency and duty cycle is less than
200ns, choose the inductor with a saturation current of
greater than 5.6A.
SGND, V shuts down, RESET (MAX15036)/PGOOD
L
(MAX15037) goes low, and soft-start resets.
Applications Information
Setting the Switching Frequency
The controller generates the switching frequency (f
)
SW
through the internal oscillator or the signal at SYNC
(f ), when driven by an external oscillator. The
SYNC
switching frequency is equal to f
or f
.
SW
SYNC
A resistor, R
, from OSC to SGND sets the internal
OSC
Power-On Reset (RESET)
(MAX15036 Only)
RESET is an active-low open-drain output that goes low
oscillator. The relationship between f
and R
is:
SW
OSC
8
125×10
R
=
OSC
when V
falls below 92.5% of its nominal set point.
OUT
f
SW
RESET goes high impedance when V
rises above
OUT
92.5% of its nominal set point, the soft-start period is
complete, and the 200ms (typ) timeout period has
elapsed. Connect a pullup resistor from RESET to a
where f
is in Hertz, and R
is in ohms. For exam-
SW
OSC
ple, a 1.25MHz switching frequency is set with R
=
OSC
10kΩ. Higher frequencies allow designs with lower
logic voltage or to V . The internal open-drain MOSFET
L
inductor values and less output capacitance.
at RESET can sink 3mA while providing a TTL-compati-
ble logic-low signal. Connect RESET to SGND or leave
unconnected when not used.
2
Consequently, peak currents and I R losses are lower
at higher switching frequencies, but core losses, gate-
charge currents, and switching losses increase.
Rising clock edges on SYNC are interpreted as a syn-
chronization input. If the SYNC signal is lost, the internal
oscillator takes control of the switching rate, returning
Power-Good (PGOOD)
(MAX15037 Only)
PGOOD is an open-drain, active-high output that goes
the switching frequency to that set by R
. This main-
OSC
low when V
is below 92.5% of its nominal set point
OUT
tains output regulation even with intermittent SYNC sig-
nals. When using an external synchronization signal, set
and goes high impedance when V
goes above
OUT
92.5% its nominal set point. Connect a pullup resistor
R
OSC
so that (0.8 x f
) ≤ f
≤ (1.2 x f ).
SYNC
SYNC
SW
from PGOOD to a logic voltage or to V . PGOOD can sink
L
up to 3mA while still providing a TTL-compatible logic-low
output. Pulling EN low forces PGOOD low. Connect
PGOOD to SGND or leave unconnected when not used.
Buck Converter
Use the internal n-channel power MOSFET as a high-
side switch to configure the MAX15036/MAX15037 as a
buck converter. In this configuration, SOURCE is con-
nected to the inductor, DRAIN is connected to the
input, and BST/VDD connects to the cathode of the
bootstrap diode and capacitor. Figures 5 and 6 show
the typical application circuits for MAX15036/
MAX15037, respectively, in a buck configuration.
Thermal-Overload Protection
During a continuous output short-circuit or overload
condition, the die junction temperature in the
MAX15036/MAX15037 can exceed its limit. The
MAX15036/MAX15037 provide an internal thermal shut-
down to turn off the device when the die temperature
______________________________________________________________________________________ 13
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
Effective Input Voltage Range
The MAX15036/MAX15037 can operate with input sup-
plies ranging from 4.5V to 5.5V or 5.5V to 23V. The
input voltage range (V+) can be constrained to a mini-
mum by the duty-cycle limitations and to a maximum by
the on-time limitation. The minimum input voltage is
determined by:
tance is a function of operating frequency, input-to-out-
put voltage differential, and the peak-to-peak inductor
current (ΔI ). Higher ΔI
allows for a lower inductor
requires a higher inductor
P-P
P-P
P-P
value, while a lower ΔI
value. A lower inductor value minimizes size and cost,
improves large-signal and transient response, but
reduces efficiency due to higher peak currents and
higher peak-to-peak output voltage ripple for the same
output capacitor. On the other hand, higher inductance
increases efficiency by reducing the ripple current.
Resistive losses due to extra wire turns can exceed the
benefit gained from lower ripple current levels especial-
ly when the inductance is increased without also allow-
ing for larger inductor dimensions. A good compromise
V
+ V
DROP1
OUT
V
=
+ V
− V
IN_MIN
DROP2 DROP1
D
MAX
D
is the maximum duty cycle of 87.5% (typ).
MAX
V
is the total drop in the inductor discharge path
DROP1
that includes the diode’s forward voltage drop (or the
drop across the synchronous rectifier MOSFET), and
the drops across the series resistance of the inductor
is to choose ΔI
equal to 30% of the full load current.
P-P
Use the following equation to calculate the inductance:
and PCB traces. V
is the total drop in the induc-
DROP2
V
V
(V − V
)
OUT
OUT IN
tors charging path, which includes the drop across the
internal power MOSFET, and the drops across the
series resistance of the inductor and PCB traces.
L =
× f × ΔI
IN SW
P−P
V
and V
are typical values so that efficiency is
OUT
IN
The maximum input voltage can be determined by:
6/MAX15037
optimum for typical conditions. The switching frequency
is set by R (see the Setting the Switching Frequency
OSC
V
OUT
V
=
section). The peak-to-peak inductor current, which
reflects the peak-to-peak output ripple, is worse at the
maximum input voltage. See the Output Capacitor
Selection section to verify that the worst-case output rip-
ple is acceptable. The inductor saturation current is also
important to avoid runaway current during continuous
output short-circuit. At high input-to-output differential,
and high switching frequency, the on-time drops to the
order of 100ns. Though the MAX15036/MAX15037 can
control the on-time as low as 100ns, the internal current-
limit circuit may not detect the overcurrent within this
time. In that case, the output current during the fault
may exceed the current limit specified in the Electrical
Characteristics table. The overtemperature shutdown
protects the MAX15036/MAX15037 against the output
short-circuit fault. However, the output current may
reach 5.6A. Choose an inductor with a saturation current
of greater than 5.6A when the minimum on-time for a
given frequency and duty cycle is less than 200ns.
IN_MAX
t
× f
ON_MIN SW
where t
= 100ns and f is the switching frequency.
SW
ON_MIN
Setting the Output Voltage
For 0.6V or greater output voltages, connect a resistive
divider from V
to FB to SGND. Select the FB to
OUT
SGND resistor (R2) from 1kΩ to 10kΩ and calculate the
resistor from OUT to FB (R1) by the following equation:
⎡
⎢
⎣
⎤
V
V
OUT
R1=R2×
−1
⎥
⎦
FB
where V = 0.6V, see Figure 3.
FB
For designs that use a Type III compensation scheme,
first calculate R1 for stability requirements (see the
Compensation section) then choose R2 so that:
R1 × V
FB
R2 =
Input Capacitors
The discontinuous input current of the buck converter
causes large input ripple current. The switching frequen-
cy, peak inductor current, and the allowable peak-to-
peak input voltage ripple dictate the input capacitance
requirement. Increasing the switching frequency or the
inductor value lowers the peak-to-average current ratio
yielding a lower input capacitance requirement.
V
− V
OUT
FB
See Figure 4.
Inductor Selection
Three key inductor parameters must be specified for
operation with the MAX15036/MAX15037: inductance
value (L), peak inductor current (I
), and inductor
PEAK
saturation current (I
). The minimum required induc-
SAT
14 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
The input ripple comprises mainly of ΔV (caused by the
where:
Q
capacitor discharge) and ΔV
(caused by the ESR of
ESR
V
− V
× V
×L
the input capacitor). The total voltage ripple is the sum of
. Assume the input voltage ripple from
(
=
)
IN
OUT OUT
ΔI
P−P
ΔV and ΔV
Q
ESR
V
× f
IN SW
the ESR and the capacitor discharge is equal to 50%
each. The following equations show the ESR and capaci-
tor requirement for a target voltage ripple at the input:
V
≅ ΔV
+ ΔV
OUT_RIPPLE
ESR Q
ΔI
P-P
is the peak-to-peak inductor current as calculated
above and f
frequency.
is the individual converter’s switching
SW
ΔV
ESR
ESR =
ΔI
⎛
⎞
P−P
The allowable deviation of the output voltage during
fast transient loads also determines the output capaci-
tance and its ESR. The output capacitor supplies the
step load current until the controller responds with a
I
+
⎜
⎝
⎟
⎠
OUT
2
I
×D 1−D
(
)
OUT
C
=
IN
ΔV ×f
Q
SW
greater duty cycle. The response time (t
)
RESPONSE
depends on the closed-loop bandwidth of the convert-
er. The high switching frequency of the MAX15036/
MAX15037 allows for a higher closed-loop bandwidth,
where
V
− V
× V
(
)
IN
OUT OUT
ΔI
=
and
P−P
thus reducing t
and the output capacitance
RESPONSE
V
×f
×L
IN SW
requirement. The resistive drop across the output
capacitor’s ESR and the capacitor discharge causes a
voltage droop during a step load. Use a combination of
low-ESR tantalum and ceramic capacitors for better
transient load and ripple/noise performance. Keep the
maximum output voltage deviation below the tolerable
limits of the electronics being powered. When using a
ceramic capacitor, assume an 80% and 20% contribu-
tion from the output capacitance discharge and the
ESR drop, respectively. Use the following equations to
calculate the required ESR and capacitance value:
V
V
OUT
D =
IN
where I
is the output current, D is the duty cycle,
is the switching frequency. Use additional
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during
transient loading.
OUT
and f
SW
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during step load cur-
rents determine the output capacitance and its ESR.
ΔV
ESR
ESR
I
=
OUT
I
STEP
The output ripple comprises of ΔV (caused by the
Q
× t
capacitor discharge) and ΔV
(caused by the ESR of
STEP RESPONSE
ESR
C
=
OUT
the output capacitor). Use low-ESR ceramic or alu-
minum electrolytic capacitors at the output. For alu-
minum electrolytic capacitors, the entire output ripple is
ΔV
Q
where I
is the load step and t
is the
RESPONSE
STEP
response time of the controller. The controller response
time depends on the control-loop bandwidth.
contributed by ΔV
. Use the ESR
equation to cal-
ESR
OUT
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge to be equal. The following
equations show the output capacitance and ESR
requirement for a specified output voltage ripple.
Boost Converter
The MAX15036 can be configured for step-up conver-
sion since the internal MOSFET can be used as a low-
side switch. Use the following equations to calculate
the inductor (L
), input capacitor (C ), and output
IN
MIN
capacitor (C
operation.
) when using the converter in boost
OUT
ΔV
ΔI
ESR
ESR =
P-P
ΔI
P-P
C
=
OUT
8× ΔV ×f
Q
SW
______________________________________________________________________________________ 15
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
Inductor
Output Capacitor
Choose the minimum inductor value so the converter
remains in continuous mode operation at minimum out-
For the boost converter, the output capacitor supplies
the load current when the main switch is on. The
required output capacitance is high, especially at high-
er duty cycles. Also, the output capacitor ESR needs to
be low enough to minimize the voltage drop due to the
ESR while supporting the load current. Use the follow-
ing equation to calculate the output capacitor for a
specified output ripple tolerance.
put current (I
).
OUTMIN
2
V
× D × η
IN
L
=
MIN
2 × f
× V
× I
SW
OUT OUTMIN
where
ΔV
ESR
V
+ V − V
IN
+ V − V
D DS
ESR =
OUT
D
D =
I
OUT
V
OUT
and I
= 0.25 x I
.
OUTMIN
OUT
I
× D
OUT
MAX
SW
C
=
OUT
The V is the forward voltage drop of the external
D
ΔV × f
Q
Schottky diode, D is the duty cycle, and V is the volt-
DS
age drop across the internal switch. Select the inductor
I
is the load current, ΔV is the portion of the ripple
Q
OUT
with low DC resistance and with a saturation current (I
)
SAT
due to the capacitor discharge, and ΔV
is the con-
MAX
ESR
rating higher than the peak switch current limit of 5.6A.
tribution due to the ESR of the capacitor. D
is the
maximum duty cycle at minimum input voltage.
0
Input Capacitor
The input current for the boost converter is continuous
and the RMS ripple current at the input is low. Calculate
the capacitor value and ESR of the input capacitor
using the following equations.
Power Dissipation
The MAX15036/MAX15037 are available in thermally
enhanced 16-pin, 5mm x 5mm TQFN packages that
dissipate up to 2.7W at T = +70°C. When the die tem-
A
perature reaches +170°C, the MAX15036/MAX15037
shut down (see the Thermal-Overload Protection sec-
tion). The power dissipated in the device is the sum of
ΔI
4 × f
× D
× ΔV
Q
P−P
C
=
IN
SW
the power dissipated from supply current (P ), power
Q
dissipated due to switching the internal power MOSFET
ΔV
ΔI
ESR
ESR =
(P ), and the power dissipated due to the RMS cur-
SW
P−P
rent through the internal power MOSFET (P
).
MOSFET
The total power dissipated in the package must be lim-
ited so the junction temperature does not exceed its
absolute maximum rating of +150°C at maximum ambi-
ent temperature.
where
V
− V
L × f
× D
(
)
IN
DROP
ΔI
=
P−P
SW
The power dissipated in the switch is:
where V
is the total voltage drop across the inter-
P
= I
x R
DROP
MOSFET
RMS_MOSFET
ON
nal MOSFET plus the voltage drop across the inductor
For the buck converter:
ESR. ΔI
is the peak-to-peak inductor ripple current
P-P
as calculated above. ΔV is the portion of input ripple
Q
2
due to the capacitor discharge and ΔV
is the contri-
⎛
⎞
ESR
ΔI
×D
2
P−P
I
= (I
×D)+
bution due to ESR of the capacitor.
⎜
⎟
RMS_MOSFET
OUT
⎜
⎟
12
⎝
⎠
ΔI
P-P
is the peak-to-peak inductor current ripple.
16 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
For the boost converter:
T = T + (P
x θ
)
J
C
TOTAL
JC
θ
is the junction-to-case thermal resistance equal to
JC
D
1.7°C/W. T is the temperature of the case and T is
C
J
MAX
3
I
= (I2 +I2 +(I ×I ))×
RMS_MOSFET
DC
PK
DC PK
the junction temperature, or die temperature. The case-
to-ambient thermal resistance is dependent on how
well heat can be transferred from the PCB to the air.
Solder the underside exposed pad to a large copper
GND plane. If the die temperature reaches +170°C the
MAX15036/MAX15037 shut down and do not restart
again until the die temperature cools by 25°C.
V
×I
× η
OUT OUT
I
=
(
IN
V
IN
V
− V
× D
)
IN
DROP
ΔI
=
Compensation
The MAX15036/MAX15037 have an internal transcon-
ductance error amplifier with an inverting input (FB)
and output (COMP) available for external frequency
compensation. The flexibility of external compensation
and high switching frequencies for the MAX15036/
MAX15037 allow a wide selection of output filtering
components, especially the output capacitor. For cost-
sensitive applications, use high-ESR aluminum elec-
trolytic capacitors. For size-sensitive applications, use
low-ESR tantalum or ceramic capacitors at the output.
P−P
L × f
SW
ΔI
P−P
2
I
= I
−
+
DC IN
ΔI
P−P
I
= I
PK IN
2
The power lost due to switching the internal power
MOSFET is:
Before designing the compensation components, first
choose all the passive power components that meet
the output ripple, component size, and component cost
requirements. Secondly, choose the compensation
components to achieve the desired closed-loop band-
width and phase margin. Use a simple 1-zero, 2-pole
pair (Type II) compensation if the output capacitor ESR
V
×I
× t + t × f
4
(
)
IN OUT
R
F
SW
P
=
SW
t and t are the rise and fall times of the internal power
R
F
MOSFET measured at SOURCE.
zero frequency (f
) is below the unity-gain
ZESR
The power lost due to the switching quiescent current
of the device is:
crossover frequency (f ). Use a 2-zero, 2-pole (Type
C
III) compensation when the f
is higher than f .
C
ZESR
P
Q
= V x I
SW
(MAX15036)
) of the
IN
Buck Converter Compensation
The switching quiescent current (I
SW
Use procedure 1 to calculate the compensation net-
work components when f
MAX15036/MAX15037 is dependent on switching fre-
quency. See the Typical Operating Characteristics sec-
< f .
C
ZESR
tion for the value of I
at a given frequency.
Procedure 1 (see Figure 3)
Calculate the f
SW
In the case of the MAX15037, the switching current
includes the synchronous rectifier MOSFET gate-drive
and f double pole:
LC
ZESR
current (I
charge (Q
and the switching frequency.
). The I
depends on the total gate
SW-DL
) of the synchronous rectifier MOSFET
SW-DL
g-DL
1
f
=
ZESR
2π ×ESR× C
OUT
1
P
Q
= V x (I
+ I
SW-DL
)
(MAX15037)
IN
SW
f
=
LC
2π × L × C
OUT
I
= Q
x f
SW-DL
g-DL SW
where the Q
is the total gate charge of the synchro-
Calculate the unity-gain crossover frequency as:
g-DL
nous rectifier MOSFET at V = 5V.
GS
f
SW
The total power dissipated in the device is:
f
=
C
20
P
= P
+ P + P
SW Q
TOTAL
MOSFET
Calculate the temperature rise of the die using the fol-
lowing equation:
______________________________________________________________________________________ 17
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
If f
is lower than f and close to f , use a Type II
First, select the crossover frequency so that:
ZESR
C
LC
compensation network where R C provides a midband
F
F
f
20
SW
f
≤
C
zero (f
) and R C provides a high-frequency pole.
mid,zero
F CF
Calculate the modulator gain (G ) at the crossover
M
frequency.
Calculate the LC double-pole frequency, f
1
:
LC
f
=
LC
V
V
FB
ESR
ESR+(2π ×f ×L)
IN
2π × L × C
G
=
×
×
OUT
M
V
V
OSC
C
OUT
1
where V
is the 1V
P-P
ramp amplitude and V = 0.6V.
OSC
FB
Place a zero f
where:
=
at 0.75 × f
LC
Z
2π × R × C
F
The transconductance error amplifier gain at f is:
F
C
G
E/A
= g x R
m F
1
The total loop gain at f should be equal to 1:
C
C
=
F
2π ×0.75 ×f ×R
LC
F
G
M
= G
= 1
E/A
with R ≥ 10kΩ.
or
F
Calculate C for a target unity crossover frequency, f :
A
C
V
(ESR + 2π × f × L)V
C OUT
OSC
R
=
F
V
× V × g ×ESR
IN m
2π× f ×L×C
×V
OSC
FB
C
OUT
C
=
A
6/MAX15037
V
× R
F
IN
Place a zero at or below the LC double pole:
1
1
Place a pole (f
=
) at f
.
P1
ZESR
2π ×R × C
C
=
A
A
F
2π ×R × f
F
LC
1
Place a high-frequency pole at f = 0.5 x f . Therefore
CF
P
SW
R
=
A
2π × f
× C
A
C
is:
ZESR
Place a second zero, f , at 0.2 x f or at f , whichev-
Z2
C
LC
1
C
=
CF
er is lower.
π ×R × f
F
SW
1
R
=
− R
Procedure 2 (see Figure 4)
1
A
2π × f × C
Z2
A
When using a low-ESR ceramic-type capacitor as the
output capacitor, the ESR frequency is much higher
1
than the targeted unity-gain crossover frequency (f ).
C
Place a second pole (f
=
)
P2
2π ×R × C
In this case, Type III compensation is recommended.
Type III compensation provides a low-frequency pole
(≈DC) and two pole-zero pairs. The locations of the
zero and poles should be such that the phase margin
F
CF
at 1/2 the switching frequency.
C
F
C
=
CF
(2π × 0.5× f ×R ×C )-1
peaks at f .
C
SW
F
F
f
f
f
C
C
P
=
= 5
f
Z
The
is a good number to get approximate-
ly 60° of phase margin at f . However, it is important to
C
place the two zeros at or below the double pole to
avoid conditional stability.
18 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
V
OUT
R1
COMP
g
m
R2
V
REF
C
CF
R
F
C
F
Figure 3. Type II Compensation Network
V
OUT
C
CF
R1
R
A
C
F
R
F
C
A
g
m
COMP
R2
V
REF
Figure 4. Type III Compensation Network
______________________________________________________________________________________ 19
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
where ω = 2π f
Boost Converter Compensation
C
C.
The boost converter compensation gets complicated
1
(f
=
)
P1
due to the presence of a right-half-plane zero f
.
ZERO,RHP
2π × R × C
A
A
4) Place a pole
R
at f
.
The right-half-plane zero causes a drop in-phase while
adding positive (+1) slope to the gain curve. It is impor-
tant to drop the gain significantly below unity before the
RHP frequency. Use the following procedure to calculate
the compensation components. (See Figure 4.)
ZERO,RHP
1
=
A
2π × f
,R × C
A
ZERO HP
1) Calculate the LC double-pole frequency, f , and
LC
1
the right half plane zero frequency.
(f
=
)
Z2
2π × R1 × C
A
1 − D
2π × LC
5) Place the second zero
at f
.
LC
f
=
LC
OUT
1
R1=
− R
A
2
(1 − D) R
2π × f × C
(MIN)
LC
A
f
=
ZERO, RHP
2π × L
1
(f
=
)
P2
2π × R × C
where:
F
CF
6) Place the second pole
the switching frequency.
at 1/2
V
IN
D =1−
6/MAX15037
V
C
OUT
V
F
C
=
CF
(2π × 0.5× f
× R × C
OUT
SW
F F) − 1
R
=
(MIN)
I
OUT(MAX)
Target the unity-gain crossover frequency for:
Improving Noise Immunity
f
ZERO,RHP
When using the MAX15036/MAX15037 in noisy environ-
ments, adjust the controller’s compensation to improve
the system’s noise immunity. In particular, high-fre-
quency noise coupled into the feedback loop causes
duty-cycle jitter. One solution is to lower the crossover
frequency (see the Compensation section).
f
≤
=
C
5
1
(f
)
Z1
2π ×R × C
F
F
2) Place a zero
C
at 0.75 x f
.
LC
1
=
F
PCB Layout Guidelines
Careful PCB layout is critical to achieve low-switching
power losses and clean stable operation. Use a multi-
layer board whenever possible for better noise immuni-
ty. Follow these guidelines for good PCB layout:
2π × 0.75 × f
× R
F
LC
where R ≥ 10kΩ.
F
3) Calculate C for a target crossover frequency, f :
A
C
1) Solder the exposed pad to a large copper plane
under the IC. To effectively use this copper area as
a heat exchanger between the PCB and the ambi-
ent, expose this copper area on the top and bottom
2
2
⎡
⎣
⎤
⎦
V
1− D + ω LC
C OUT
(
)
OSC
C
=
A
ω R V
C F IN
20 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
side of the PCB. Do not make a direct connection of
Layout Procedure
1) Place the power components (inductor, C , and
the exposed pad copper plane to the SGND (pin 10)
underneath the IC. Connect this plane and SGND
together at the return terminal of the V+ bypass
capacitor
IN
C
) first, with ground terminals close to each
OUT
other. Make all these connections on the top layer
with wide, copper-filled areas (2oz copper recom-
mended).
2) Isolate the power components and high-current
paths from sensitive analog circuitry.
2) Group the gate-drive components (boost diodes
and capacitors, and V bypass capacitor) together
L
3) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
near the controller IC.
3) Make the ground connections as follows:
4) Connect SGND and PGND together close to the
a) Create a small-signal ground plane underneath
the IC.
return terminals of the V and V+ high-frequency
L
bypass capacitors near the IC. Do not connect them
together anywhere else.
b) Connect this plane to SGND and use this plane
for the ground connection for BYPASS, COMP,
FB, and OSC.
5) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs to enhance full-load efficiency
and power dissipation capability.
c) Connect SGND and PGND together at the
return terminal of V+ and V bypass capacitors
L
near the IC. Make this the only connection
between SGND and PGND.
6) Ensure that the feedback connection from FB to
C
OUT
is short and direct.
7) Route high-speed switching nodes (BST/VDD,
SOURCE) away from the sensitive analog areas
(BYPASS, COMP, FB, and OSC). Use internal PCB
layers for SGND as EMI shields to keep radiated
noise away from the IC, feedback dividers, and the
analog bypass capacitors.
______________________________________________________________________________________ 21
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
Figure 5. MAX15036 Buck Configuration
22 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
Figure 6. MAX15037 Buck Configuration
______________________________________________________________________________________ 23
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
V
L
VOUT
R8
10kΩ
VOUT
PGND
VIN
SGND
JU1
C12
0.1μF
C11
22μF
16
V
L
EN
D2
R9
VIN
L1
4.7μH
10kΩ
PGOOD
SYNC
14
13
1
2
RESET
SYNC
DRAIN
DRAIN
C1
47μF
35V
C2
10μF
PGND
R10
10kΩ
V
L
VOUT
MAX15036
3
4
15
12
COMP
BST/VDD
C10
0.1μF
R3
1kΩ
1%
R4
R1
22.1kΩ
C4
22pF
27.4kΩ
1%
1%
C5
560pF
C3
2200pF
SOURCE
6/MAX15037
FB
9
5
CKO
OSC
R2
6.04kΩ
1%
VIN
7
SGND PGND
R5
6.04kΩ
1%
V+
C6
0.1μF
11
PGND
V
L
6
8
BYPASS
V
L
C7
0.22μF
C9
4.7μF
C8
0.1μF
10
SGND
Figure 7. MAX15036 Boost Configuration
24 ______________________________________________________________________________________
2.2MHz, 3A Buck or Boost Converters
with an Integrated High-Side Switch
6/MAX15037
V
IN
C
IN
V+
V+
DRAIN
DRAIN
OUTPUT1
OUTPUT2
SOURCE
SOURCE
DUTY CYCLE = 50%
SYNC
SYNC
CLKOUT
CLKIN
SLAVE
MASTER
SYNC
CLKOUT
(MASTER)
SOURCE
(MASTER)
SYNC
PHASE
SOURCE
(SLAVE)
CLKOUT
PHASE
Figure 8. Synchronized Converters
Chip Information
Pin Configurations (continued)
PROCESS: BiCMOS
TOP VIEW
12
11
10
9
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
V
8
7
6
5
SYNC
13
L
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
PGOOD 14
V+
MAX15037
16 TQFN
T1655-2
21-0140
BST/VDD 15
BYPASS
OSC
16
EN
EP*
+
1
2
3
4
THIN QFN
5mm x 5mm
*EXPOSED PAD.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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