MAX15039ETG+ [MAXIM]
6A, 2MHz Step-Down Regulator with Integrated Switches; 6A ， 2MHz降压型稳压器，内置开关
| 型号： | MAX15039ETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 6A, 2MHz Step-Down Regulator with Integrated Switches |
| 文件： | 总19页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4321; Rev 1; 12/09
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
General Description
Features
o Internal 26mΩ R
High-Side and 20mΩ
The MAX15039 high-efficiency switching regulator
delivers up to 6A load current at output voltages from
DS(ON)
R
Low-Side MOSFETs
DS(ON)
o Continuous 6A Output Current Over Temperature
o ±±1 Output Aꢀꢀuraꢀc Over Loadꢁ Lineꢁ and
Temperature
0.6V to 90% of V . The IC operates from 2.9V to 5.5V,
IN
making it ideal for on-board point-of-load and postregu-
lation applications. Total output error is less than 1%
over load, line, and temperature ranges.
o Operates from 2.9V to 5.5V V Supplc
IN
o Adjustable Output from 0.6V to (0.9 x V )
IN
The MAX15039 features fixed-frequency PWM mode
operation with a switching frequency range of 500kHz
to 2MHz set by an external resistor. The MAX15039
provides the option of operating in a skip mode to
improve light-load efficiency. High-frequency operation
allows for an all-ceramic capacitor design. The high
operating frequency also allows for small-size external
components.
o Soft-Start Reduꢀes Inrush Supplc Current
o 500kHz to 2MHz Adjustable Switꢀhing Frequenꢀc
o Compatible with Ceramiꢀꢁ Polcmerꢁ and
Eleꢀtrolctiꢀ Output Capaꢀitors
o Nine Preset and Adjustable Output Voltages
0.6Vꢁ 0.7Vꢁ 0.8Vꢁ ±.0Vꢁ ±.2Vꢁ ±.5Vꢁ ±.8Vꢁ 2.0Vꢁ
2.5Vꢁ and Adjustable
o Monotoniꢀ Startup for Safe-Start Into Prebiased
The low-resistance on-chip nMOS switches ensure high
efficiency at heavy loads while minimizing critical induc-
tances, making the layout a much simpler task with
respect to discrete solutions. Following a simple layout
and footprint ensures first-pass success in new designs.
Outputs
o Seleꢀtable Forꢀed PWM or Skip Mode for Light
Load Effiꢀienꢀc
o Overꢀurrent and Overtemperature Proteꢀtion
o Output Current Sink/Sourꢀe Capable with Ccꢀle-
bc-Ccꢀle Proteꢀtion
o Open-Drainꢁ Power-Good Output
o Lead-Freeꢁ 4mm x 4mmꢁ 24-Pin Thin QFN Paꢀkage
The MAX15039 comes with a high bandwidth (28MHz)
voltage-error amplifier. The voltage-mode control archi-
tecture and the voltage-error amplifier permit a type III
compensation scheme to be utilized to achieve maxi-
mum loop bandwidth, up to 20% of the switching fre-
quency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance
and allowing for all-ceramic-capacitor designs.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX15039ETG+
-40°C to +85°C
24 Thin QFN-EP*
The MAX15039 provides two three-state logic inputs to
select one of nine preset output voltages. The preset
output voltages allow customers to achieve 1% out-
put-voltage accuracy without using expensive 0.1%
resistors. In addition, the output voltage can be set to
any customer value by either using two external resis-
tors at the feedback with a 0.6V internal reference or
applying an external reference voltage to the REFIN
input. The MAX15039 offers programmable soft-start
time using one capacitor to reduce input inrush current.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
INPUT
2.9V TO 5.5V
IN
BST
OUTPUT
1.8V, 6A
MAX15039
EN
LX
V
DD
OUT
Applications
PGND
FB
Server Power Supplies
POLs
CTL2
CTL1
FREQ
ASIC/CPU/DSP Core and I/O Voltages
DDR Power Supplies
Base-Station Power Supplies
Telecom and Networking Power Supplies
RAID Control Power Supplies
REFIN
SS
V
DD
COMP
MODE
PWRGD
GND
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Produꢀts
±
For priꢀingꢁ delivercꢁ and ordering informationꢁ please ꢀontaꢀt Maxim Direꢀt at ±-888-629-4642ꢁ
or visit Maxim’s website at www.maxim-iꢀ.ꢀom.
6A, 2MHz Step-Down Regulator
with Integrated Switches
ABSOLUTE MAXIMUM RATINGS
IN, PWRGD to GND..................................................-0.3V to +6V
V
DD
Output Short-Circuit Duration.............................Continuous
V
to GND..................-0.3V to the lower of +4V or (V + 0.3V)
Converter Output Short-Circuit Duration....................Continuous
DD
IN
COMP, FB, MODE, REFIN, CTL1, CTL2, SS,
Continuous Power Dissipation (T = +70°C)
A
FREQ to GND ..........................................-0.3V to (V
+ 0.3V)
24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
Thermal Resistance (Note 2)
DD
OUT, EN to GND ......................................................-0.3V to +6V
BST to LX..................................................................-0.3V to +6V
BST to GND............................................................-0.3V to +12V
PGND to GND .......................................................-0.3V to +0.3V
θJA.................................................................................36°C/W
θJC ..................................................................................6°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
LX to PGND ..................-0.3V to the lower of +6V or (V + 0.3V)
IN
LX to PGND ..........-1V to the lower of +6V or (V + 1V) for 50ns
IN
MAX15039
I
(Note 1)......................................................................6A
LX(RMS)
Note ±: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-iꢀ.ꢀom/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V
IN
= 5V, C
= 2.2µF, T = T = -40°C to +85°C, typical values are at T = +25°C, circuit of Figure 1, unless otherwise
VDD A J A
EN
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN
IN Voltage Range
2.9
5.5
8
V
V
= 3.3V
= 5V
4.9
5.2
10
IN
IN
IN Supply Current
f = 1MHz, no load
mA
S
V
8.5
20
V
V
= 5V, V = 0V
EN
IN
IN
Total Shutdown Current from IN
µA
= V
= 3.3V, V = 0V
45
DD
EN
3.3V LDO (V )
DD
V
V
rising
falling
2.6
2.8
DD
DD
V
2.35
2.55
V
Undervoltage Lockout
DD
LX starts/stops switching
Threshold
Minimum glitch-width
rejection
10
µs
V
V
V
Output Voltage
Dropout
V
V
V
= 5V, I = 0 to 10mA
VDD
3.1
25
3.3
3.5
V
V
DD
DD
DD
IN
IN
IN
= 2.9V, I
= 10mA
0.08
VDD
Current Limit
= 5V, V
= 0V
40
mA
DD
BST
BST Supply Current
V
= V = 5V, V = 0 or 5V, V = 0V
0.025
µA
ns
BST
IN
LX
EN
PWM COMPARATOR
PWM Comparator Propagation
Delay
10mV overdrive
20
PWM Peak-to-Peak Ramp
Amplitude
1
V
V
PWM Valley Amplitude
0.8
2
_______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V = V
IN
= 5V, C
= 2.2µF, T = T = -40°C to +85°C, typical values are at T = +25°C, circuit of Figure 1, unless otherwise
VDD A J A
EN
noted.) (Note 3)
PARAMETER
ERROR AMPLIFIER
CONDITIONS
MIN
TYP
MAX
UNITS
COMP Clamp Voltage, High
COMP Clamp Voltage, Low
COMP Slew Rate
V
V
V
= 2.9V to 5V, V = 0.5V, V
= 0.6V
= 0.6V
2
V
V
IN
IN
FB
FB
REFIN
REFIN
= 2.9V to 5V, V = 0.7V, V
0.7
1.6
FB
step from 0.5V to 0.7V in 10ns
V/µs
From COMP to GND, V = 3.3V, V
= 100mV,
COMP
IN
COMP Shutdown Resistance
6
Ω
V
= V = 0V
SS
EN
Internally Preset Output Voltage
Accuracy
V
= V , MODE = GND
-1
+1
%
REFIN
SS
FB Set-Point Value
CTL1 = CTL2 = GND, MODE = GND
All VID settings except CTL1 = CTL2 = GND
0.594
5.5
0.6
8
0.606
10.5
V
FB to OUT Resistor
Open-Loop Voltage Gain
kΩ
dB
115
Error-Amplifier Unity-Gain
Bandwidth
28
MHz
V
Error-Amplifier Common-Mode
Input Range
V
= 2.9V to 3.5V
0
V
- 2
DD
DD
V
V
= 0.7V, sinking
1
FB
FB
Error-Amplifier Maximum Output
Current
V
V
= 1V,
= 0.6V
COMP
REFIN
mA
nA
= 0.5V, sourcing
-1
FB Input Bias Current
CTL1 = CTL2 = GND
-125
CTL_
V
V
= 0V
-7.2
7.2
0.8
CTL_
CTL_
CTL_ Input Bias Current
CTL_ Input Threshold
µA
= V
DD
Low, falling
Open
V
/2
DD
V
V
-
DD
High, rising
0.8
Hysteresis
All VID transitions
50
mV
REFIN
REFIN Input Bias Current
REFIN Offset Voltage
LX (All Pins Combined)
V
V
= 0.6V
-185
nA
REFIN
REFIN
= 0.9V, FB shorted to COMP
-4.5
+4.5
mV
V
V
V
V
= V
= V
- V = 3.3V
35
26
IN
IN
IN
IN
BST
BST
LX
LX On-Resistance, High Side
LX On-Resistance, Low Side
I
I
= -2A
mΩ
mΩ
LX
LX
- V = 5V
45
35
LX
= 3.3V
= 5V
25
= 2A
20
High-side sourcing
Low-side sinking
9
11
LX Current-Limit Threshold
LX Leakage Current
11
A
Zero-crossing current threshold, MODE = V
0.2
-0.01
-0.01
DD
V
V
= 0V
= 5V
LX
LX
V
= 5V, V = 0V
µA
IN
EN
_______________________________________________________________________________________
3
6A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V = V
= 5V, C
= 2.2µF, T = T = -40°C to +85°C, typical values are at T = +25°C, circuit of Figure 1, unless otherwise
EN
VDD
A
J
A
IN
noted.) (Note 3)
PARAMETER
CONDITIONS
MIN
0.9
TYP
1
MAX
1.1
UNITS
R
R
= 49.9kΩ
= 23.6kΩ
FREQ
LX Switching Frequency
V
= 2.9V to 5.5V
MHz
IN
1.8
2
2.2
FREQ
Switching Frequency Range
LX Minimum Off-Time
500
2000
78
kHz
ns
%
MAX15039
LX Maximum Duty Cycle
LX Minimum Duty Cycle
R
R
= 49.9kΩ
= 49.9kΩ
92
95
5
FREQ
15
%
FREQ
Average Short-Circuit IN Supply
Current
OUT connected to GND, V = 5V
IN
0.35
A
A
RMS LX Output Current
ENABLE
6
EN Input Logic-Low Threshold
EN Input Logic-High Threshold
EN Input Current
EN falling
EN rising
0.9
V
V
1.5
V
= 0 or 5V, V = 5V
0.01
µA
EN
IN
MODE
Logic-low, falling
26
50
74
5
MODE Input-Logic Threshold
Logic V /2 or open, rising
DD
%V
%V
DD
Logic-high, rising
MODE falling
MODE Input-Logic Hysteresis
MODE Input Bias Current
DD
MODE = GND
-5
5
µA
MODE = V
DD
SS
SS Current
V
= 0.45V, V
= 0.6V, sourcing
6.7
88
8
9.3
µA
SS
REFIN
THERMAL SHUTDOWN
Thermal-Shutdown Threshold
Thermal-Shutdown Hysteresis
POWER GOOD (PWRGD)
Rising
165
25
°C
°C
V
V
falling, V
= 0.6V
90
92
FB
FB
REFIN
%
REFIN
Power-Good Threshold Voltage
Power-Good Edge Deglitch
V
rising, V
= 0.6V
92.5
REFIN
Clock
Cycles
V
rising or falling
48
FB
PWRGD Output-Voltage Low
PWRGD Leakage Current
I
= 4mA
PWRGD
0.03
0.01
0.1
V
PWRGD
V
= V
= 5V, V = 0.7V, V = 0.6V
REFIN
µA
IN
FB
HICCUP OVERCURRENT LIMIT
Clock
Cycles
Current-Limit Startup Blanking
Autoretry Restart Time
112
896
Clock
Cycles
4
_______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
ELECTRICAL CHARACTERISTICS (ꢀontinued)
(V = V
= 5V, C
= 2.2µF, T = T = -40°C to +85°C, typical values are at T = +25°C, circuit of Figure 1, unless otherwise
EN
VDD
A
J
A
IN
noted.) (Note 3)
PARAMETER
FB Hiccup Threshold
CONDITIONS
MIN
TYP
70
MAX
UNITS
%
V
V
falling
falling
FB
FB
V
REFIN
Hiccup Threshold Blanking Time
28
µs
Note 3: Specifications are 100% production tested at T = +25°C. Limits over the operating temperature range are guaranteed by design.
A
Typical Operating Characteristics
(Typical values are V = V = 5V, V
= 1.8V, R
= 49.9kΩ, I
= 6A, T = +25°C, circuit of Figure 1, unless otherwise noted.)
IN
EN
OUT
FREQ
OUT A
EFFICIENCY
vs. OUTPUT CURRENT
EFFICIENCY
vs. OUTPUT CURRENT
FREQUENCY
vs. INPUT VOLTAGE
100
90
80
70
60
50
40
100
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
1.80
90
80
70
60
50
40
V
= 2.5V
OUT
V
= 2.5V
OUT
V
= 1.8V
OUT
V
= 1.8V
OUT
T
= +85°C
A
V
= 1.2V
OUT
V
= 1.2V
1.0
OUT
T
= +25°C
A
T
= -40°C
A
PWM
SKIP
PWM
SKIP
V
= 3.3V
R
= 23.2kΩ
IN
FREQ
0.1
10.0
0.1
1.0
10.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FREQUENCY
vs. INPUT VOLTAGE
LOAD REGULATION
LINE REGULATION (LOAD = 6A)
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0
0
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.35
-0.40
-0.45
-0.50
V
= 1.8V
OUT
V
= 1.2V
OUT
T
= +85°C
A
V
= 1.8V
OUT
T
= +25°C
V
= 2.5V
A
OUT
V
= 1.2V
OUT
T
= -40°C
A
R
= 49.9kΩ
FREQ
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1
2
3
4
5
7
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6
INPUT VOLTAGE (V)
LOAD CURRENT (A)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
6A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
(Typical values are V = V = 5V, V
= 1.8V, R
= 49.9kΩ, I
= 6A, T = +25°C, circuit of Figure 1, unless otherwise noted.)
IN
EN
OUT
FREQ
OUT A
SWITCHING WAVEFORMS
(SKIP MODE, NO LOAD)
SWITCHING WAVEFORMS
(FORCED PWM, 2A LOAD)
LOAD TRANSIENT
MAX15039 toc08
MAX15039 toc07
MAX15039 toc06
AC-COUPLED
100mV/div
V
OUT
V
OUT
AC-COUPLED
V
OUT
AC-COUPLED
100mV/div
50mV/div
MAX15039
1A/div
0A
I
LX
2A/div
0A
I
LX
2A
5V/div
0V
I
OUT
V
5V/div
LX
V
LX
0A
2µs/div
400ns/div
40µs/div
SOFT-START WAVEFORM
SHUTDOWN WAVEFORM
(R
= 0.5Ω)
(R
= 0.5Ω)
LOAD
LOAD
MAX15039 toc09
MAX15039 toc10
V
EN
V
EN
5V/div
5V/div
V
OUT
V
OUT
1V/div
1V/div
0V
0V
400µs/div
10µs/div
INPUT SHUTDOWN CURRENT
vs. INPUT VOLTAGE
MAXIMUM OUTPUT CURRENT
vs. OUTPUT VOLTAGE
12
11
10
9
10
9
8
7
6
8
5
7
4
6
3
V
= 0V
EN
5
2
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.5
1.0
1.5
2.0
2.5
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
6
_______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
Typical Operating Characteristics (continued)
(Typical values are V = V = 5V, V
= 1.8V, R
= 49.9kΩ, I
= 6A, T = +25°C, circuit of Figure 1, unless otherwise noted.)
IN
EN
OUT
FREQ
OUT A
EXPOSED PAD TEMPERATURE
vs. AMBIENT TEMPERATURE
RMS INPUT CURRENT DURING
SHORT CIRCUIT vs. INPUT VOLTAGE
HICCUP CURRENT LIMIT
MAX15039 toc13
100
90
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
6A LOAD
1V/div
0V
V
I
OUT
5A/div
0A
OUT
1A/div
0A
I
IN
0.1
0
MEASURED ON A MAX15039EVKIT
V
= 0V
OUT
0
20
40
60
80
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
400µs/div
AMBIENT TEMPERATURE (°C)
INPUT VOLTAGE (V)
FEEDBACK VOLTAGE
vs. TEMPERATURE
SOFT-START WITH REFIN
MAX15039 toc17
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
1A/div
0A
I
IN
0.5V/div
0V
V
REFIN
1V/div
0V
V
OUT
V
2V/div
0V
PWRGD
-40
-15
10
35
60
85
200µs/div
TEMPERATURE (°C)
STARTING INTO PREBIASED OUTPUT
(MODE = V , V = 2.5V, 2A LOAD)
STARTING INTO PREBIASED OUTPUT
(MODE = V /2, V = 2.5V, 2A LOAD)
DD OUT
DD
OUT
MAX15039 toc18
MAX15039 toc19
5V/div
0V
5V/div
0V
V
V
EN
EN
1V/div
1V/div
V
V
OUT
OUT
OUT
0V
2A
0A
0V
2A
0A
I
I
OUT
5V/div
0V
5V/div
0V
V
V
PWRGD
PWRGD
200µs/div
200µs/div
_______________________________________________________________________________________
7
6A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
(Typical values are V = V = 5V, V
= 1.8V, R
= 49.9kΩ, I = 6A, T = +25°C, circuit of Figure 1, unless otherwise noted.)
OUT A
IN
EN
OUT
FREQ
STARTING INTO PREBIASED OUTPUT
STARTING INTO PREBIASED OUTPUT
(MODE = V , V = 2.5V, NO LOAD)
(MODE = V /2, V
= 2.5V, NO LOAD)
DD
OUT
DD OUT
MAX15039 toc21
MAX15039 toc20
V
V
EN
EN
2V/div
2V/div
0V
0V
MAX15039
V
V
OUT
OUT
1V/div
1V/div
0V
0V
V
PWRGD
V
PWRGD
2V/div
2V/div
0V
0V
200µs/div
200µs/div
STARTING INTO PREBIASED OUTPUT
ABOVE NOMINAL SET POINT (V = 1.5V)
STARTING INTO PREBIASED ABOVE
NOMINAL SET POINT (V
= 1.5V)
OUT
OUT
MAX15039 toc22
MAX15039 toc23
V
V
EN
EN
2V/div
2V/div
0V
0V
V
OUT
V
OUT
1V/div
1V/div
0V
0V
V
V
PWRGD
PWRGD
2V/div
2V/div
V
= 1.5V,
OUT
V
= V ,
DD
MODE
V
= V /2,
0V
0V
MODE
DD
NO LOAD
NO LOAD
1ms/div
1ms/div
TRANSITION FROM SKIP MODE
TO FORCED PWM MODE
TRANSITION FROM FORCED PWM
TO SKIP MODE
MAX15039 toc24
MAX15039 toc25
V
MODE
V
MODE
5V/div
5V/div
V
V
LX
LX
5V/div
5V/div
V
OUT
V
OUT
0.5V/div
0.5V/div
NO LOAD
NO LOAD
0V
0V
2ms/div
4ms/div
8
_______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
Pin Description
PIN
NAME
FUNCTION
1
MODE
Functional Mode Selection Input. See the MODE Selection section for more information.
3.3V LDO Output. Supply input for the internal analog core. Connect a low-ESR, ceramic capacitor with a
minimum value of 2.2µF from V to GND.
2
V
DD
DD
3
4
CTL1
CTL2
Preset Output-Voltage Selection Inputs. CTL1 and CTL2 set the output voltage to one of nine preset
voltages. See Table 1 and the Programming the Output Voltage (CTL1, CTL2) section for preset voltages.
External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
external voltage forces FB to regulate to the voltage applied to REFIN. REFIN is internally pulled to GND
when the IC is in shutdown/hiccup mode.
5
REFIN
Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. Use a capacitor with a 1nF
minimum value. See the Soft-Start and REFIN section for details on setting the soft-start time.
6
7
8
SS
Analog Ground Connection. Connect GND and PGND together at one point near the input bypass capacitor
return terminal.
GND
COMP
Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to FB and OUT.
COMP is internally pulled to GND when the IC is in shutdown/hiccup mode.
Feedback Input. Connect FB to the center tap of an external resistive divider from the output to GND to set
9
FB
the output voltage from 0.6V to 90% of V . Connect FB through an RC network to the output when using
IN
CTL1 and CTL2 to select any of nine preset voltages.
Output-Voltage Sense. Connect to the converter output. Leave OUT unconnected when an external resistive
divider is used.
10
11
OUT
Oscillator Frequency Select. Connect a precision resistor from FREQ to GND to select the switching
frequency. See the Frequency Select (FREQ) section.
FREQ
Open-Drain, Power-Good Output. PWRGD is high impedance when V rises above 92.5% (typ) of V
FB
REFIN
or
and V
is above 0.54V. PWRGD is internally pulled low when V falls below 90% (typ) of V
FB REFIN
REFIN
12
13
PWRGD
V
is below 0.54V. PWRGD is internally pulled low when the IC is in shutdown mode, V
is below the
DD
REFIN
internal UVLO threshold, or the IC is in thermal shutdown.
High-Side MOSFET Driver Supply. Internally connected to IN through a pMOS switch. Bypass BST to LX with
a 0.1µF capacitor.
BST
LX
14, 15,
16
Inductor Connection. All LX pins are internally shorted together. Connect all LX pins to the switched side of
the inductor. LX is high impedance when the IC is in shutdown mode.
Power Ground. Connect all PGND pins externally to the power ground plane. Connect all PGND pins
together near the IC.
17–20
PGND
21, 22,
23
Input Power Supply. Input supply range is from 2.9V to 5.5V. Bypass IN to PGND with a 22µF ceramic
capacitor.
IN
EN
EP
24
Enable Input. Logic input to enable/disable the MAX15039.
Exposed Pad. Solder EP to a large contiguous copper plane connected to PGND to optimize thermal
performance. Do not use EP as a ground connection for the device.
—
_______________________________________________________________________________________
9
6A, 2MHz Step-Down Regulator
with Integrated Switches
Block Diagram
V
DD
MAX15039
3.3V LDO
UVLO
CIRCUITRY
SHUTDOWN
CONTROL
EN
MAX15039
BST
CURRENT-LIMIT
COMPARATOR
BST SWITCH
IN
BIAS
GENERATOR
VOLTAGE
REFERENCE
THERMAL
SHUTDOWN
CONTROL
LOGIC
LX
IN
SS
SOFT-START
PGND
CURRENT-LIMIT
COMPARATOR
REFIN
OUT
ERROR
AMPLIFIER
PWM
COMPARATOR
8kΩ
MODE
FREQ
FB
CTL1
VID
VOLTAGE-
CONTROL
CIRCUITRY
CTL2
1V
P-P
OSCILLATOR
COMP
PWRGD
GND
SHDN
FB
COMP CLAMPS
0.9 x V
REFIN
±0 ______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
2.2Ω
INPUT
2.9V TO 5.5V
OPTIONAL
C15
1000pF
IN
BST
C10
0.1µF
C6
22µF
C7
0.1µF
L1
0.47µH
OUTPUT
1.8V, 6A
MAX15039
LX
V
DD
C5
2.2µF
OUT
C9
0.01µF
C8
22µF
C3
560pF
CTL2
CTL1
EN
R3
158Ω
PGND
FB
C2
1500pF
R2
2.67kΩ
FREQ
REFIN
R4
49.9kΩ
SS
C1
33pF
C4
0.022µF
COMP
V
DD
R1
20kΩ
MODE
PWRGD
GND
Figure 1. Typical Application Circuit: 1MHz, All-Ceramic-Capacitor Design with V = 2.9V to 5.5V and V
= 1.8V
IN
OUT
MOSFET and 26mΩ for the high-side n-channel
MOSFET) maintains high efficiency at both heavy-load
and high-switching frequencies.
Detailed Description
The MAX15039 high-efficiency, voltage-mode switching
regulator delivers up to 6A of output current. The
MAX15039 provides output voltages from 0.6V to 0.9 x
The MAX15039 employs voltage-mode control architec-
ture with a high bandwidth (28MHz) error amplifier. The
voltage-mode control architecture allows up to 2MHz
switching frequency, reducing board area. The op amp
voltage-error amplifier works with type III compensation
to fully utilize the bandwidth of the high-frequency
switching to obtain fast transient response. Adjustable
soft-start time provides flexibilities to minimize input
startup inrush current. An open-drain, power-good
V
from 2.9V to 5.5V input supplies, making it ideal for
IN
on-board point-of-load applications. The output-voltage
accuracy is better than 1% over load, line, and tem-
perature.
The MAX15039 features a wide switching frequency
range, allowing the user to achieve all-ceramic-capaci-
tor designs and fast transient responses (see Figure 1).
The high operating frequency minimizes the size of
external components. The MAX15039 is available in a
small (4mm x 4mm), lead-free, 24-pin thin QFN pack-
age. The REFIN function makes the MAX15039 an ideal
candidate for DDR and tracking power supplies. Using
(PWRGD) output goes high when V reaches 92.5% of
FB
V
and V
is greater than 0.54V.
REFIN
REFIN
The MAX15039 provides an option for three modes of
operation: regular PWM, PWM mode with monotonic
startup into prebiased output, or skip mode with monot-
onic startup into prebiased output.
internal low-R
(20mΩ for the low-side n-channel
DS(ON)
______________________________________________________________________________________ ±±
6A, 2MHz Step-Down Regulator
with Integrated Switches
Controller Function
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
8µA × t
SS
C =
0.6V
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The break-before-make logic and
the timing for charging the bootstrap capacitors are
calculated by the controller logic block. The error signal
from the voltage-error amplifier is compared with the
ramp signal generated by the oscillator at the PWM
comparator and, thus, the required PWM signal is pro-
duced. The high-side switch is turned on at the begin-
ning of the oscillator cycle and turns off when the ramp
where t is the required soft-start time in seconds. The
SS
MAX15039 also features an external reference input
(REFIN). The IC regulates FB to the voltage applied to
REFIN. The internal soft-start is not available when
using an external reference. A method of soft-start
when using an external reference is shown in Figure 2.
Connect REFIN to SS to use the internal 0.6V reference.
Use a capacitor of 1nF minimum value at SS.
MAX15039
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when V
is below
DD
2.55V (typ). Once V
rises above 2.6V (typ), UVLO
DD
clears and the soft-start function activates. A 50mV hys-
teresis is built in for glitch immunity.
voltage exceeds the V
signal or the current-limit
COMP
threshold is exceeded. The low-side switch is then
turned on for the remainder of the oscillator cycle.
BST
The gate-drive voltage for the high-side, n-channel
switch is generated by a flying-capacitor boost circuit.
The capacitor between BST and LX is charged from the
Current Limit
The internal, high-side MOSFET has a typical 11A peak
current-limit threshold. When current flowing out of LX
exceeds this limit, the high-side MOSFET turns off and
the synchronous rectifier turns on. The synchronous
rectifier remains on until the inductor current falls below
the low-side current limit. This lowers the duty cycle
and causes the output voltage to droop until the current
limit is no longer exceeded. The MAX15039 uses a hic-
cup mode to prevent overheating during short-circuit
output conditions.
V
supply while the low-side MOSFET is on. When the
IN
low-side MOSFET is switched off, the voltage of the
capacitor is stacked above LX to provide the necessary
turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency is resistor programmable from
500kHz to 2MHz. Set the switching frequency of the IC
with a resistor (R
FREQ
) connected from FREQ to GND.
FREQ
is calculated as:
During current limit, if V drops below 70% of V
FB
REFIN
R
and stays below this level for 12µs or more, the
MAX15039 enters hiccup mode. The high-side
MOSFET and the synchronous rectifier are turned off
and both COMP and REFIN are internally pulled low. If
REFIN and SS are connected together, both are pulled
low. The part remains in this state for 896 clock cycles
and then attempts to restart for 112 clock cycles. If the
fault causing current limit has cleared, the part resumes
normal operation. Otherwise, the part reenters hiccup
mode again.
50kΩ
0.95µs
1
f
S
R
=
× ( − 0.05µs)
FREQ
where f is the desired switching frequency in Hertz.
S
R1
REFIN
Soft-Start and REFIN
The MAX15039 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8µA (typ) cur-
rent source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the
external capacitor from SS to GND. The required
capacitance value is determined as:
C
R2
MAX15039
Figure 2. Typical Soft-Start Implementation with External
Reference
±2 ______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high imped-
ance when V is above 0.925 x V and V is
Table ±. CTL± and CTL2 Output Voltage
Seleꢀtion
FB
REFIN
REFIN
above 0.54V for at least 48 clock cycles. PWRGD pulls
low when V is below 90% of V or V is
CTL±
CTL2
V
(V)
OUT
0.6
0.7
0.8
1.0
1.2
1.5
1.8
2.0
2.5
FB
REFIN
REFIN
GND
GND
below 0.54V for at least 48 clock cycles. PWRGD is low
V
V
DD
DD
when the IC is in shutdown mode, V is below the
DD
GND
Unconnected
internal UVLO threshold, or the IC is in thermal shut-
down mode.
GND
V
DD
Unconnected
Unconnected
Unconnected
GND
Programming the Output Voltage
(CTL1, CTL2)
Unconnected
As shown in Table 1, the output voltage is pin program-
mable by the logic states of CTL1 and CTL2. CTL1 and
V
DD
V
V
GND
DD
DD
CTL2 are trilevel inputs: V , unconnected, and GND.
DD
Unconnected
An 8.06kΩ resistor must be connected between OUT
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro-
grammed only before power-up. Once the part is
enabled, CTL1 and CTL2 should not be changed. If the
output voltage needs to be reprogrammed, cycle
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from
L
V
OUT
LX
C
OUT
R2
C3
MAX15039
R3
R4
OUT
0.6V to 90% of V by using a resistor-divider network
IN
FB
COMP
from V
to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
OUT
CTL1
C1
R1
CTL2
Shutdown Mode
C2
Drive EN to GND to shut down the IC and reduce quies-
cent current to 10µA (typ). During shutdown, the LX is
high impedance. Drive EN high to enable the MAX15039.
a)
EXTERNAL RESISTIVE DIVIDER
Thermal Protection
Thermal-overload protection limits total power dissipation
in the device. When the junction temperature exceeds
L
V
OUT
R2
LX
C
OUT
T = +165°C, a thermal sensor forces the device into
J
MAX15039
shutdown, allowing the die to cool. The thermal sensor
turns the device on again after the junction temperature
cools by 20°C, causing a pulsed output during continu-
ous overload conditions. The soft-start sequence begins
after recovery from a thermal-shutdown condition.
OUT
R3
8kΩ
C3
Applications Information
FB
C1
R1
CTL1
CTL2
VOLTAGE
SELECT
COMP
IN and V
Decoupling
DD
To decrease the noise effects due to the high switching
frequency and maximize the output accuracy of
the MAX15039, decouple IN with a 22µF capacitor from
C2
IN to PGND. Also decouple V
with a 2.2µF low-ESR
DD
b)
INTERNAL PRESET VOLTAGES
ceramic capacitor from V
to GND. Place these
DD
capacitors as close as possible to the IC.
Figure 3. Type III Compensation Network
______________________________________________________________________________________ ±3
6A, 2MHz Step-Down Regulator
with Integrated Switches
evaluation circuit. A smaller ripple current results in less
Inductor Selection
Choose an inductor with the following equation:
output-voltage ripple. Since the inductor ripple current
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic
capacitors for low ESR and low ESL at the switching
frequency of the converter. The ripple voltage due to
ESL is negligible when using ceramic capacitors.
V
× (V − V
IN OUT
)
OUT
L =
f × V × LIR×I
S
IN
OUT(MAX)
where LIR is the ratio of the inductor ripple current to full
load current at the minimum duty cycle. Choose LIR
between 20% to 40% for best performance and stability.
Load-transient response depends on the selected out-
put capacitance. During a load transient, the output
Use an inductor with the lowest possible DC resistance
that fits in the allotted dimensions. Powdered iron ferrite
core types are often the best choice for performance.
With any core material, the core must be large enough
not to saturate at the current limit of the MAX15039.
instantly changes by ESR x ∆I
. Before the con-
LOAD
MAX15039
troller can respond, the output deviates further,
depending on the inductor and output capacitor val-
ues. After a short time, the controller responds by regu-
lating the output voltage back to its predetermined
value. The controller response time depends on the
closed-loop bandwidth. A higher bandwidth yields a
faster response time, preventing the output from deviat-
ing further from its regulating value. See the Compen-
sation Design section for more details.
Output-Capacitor Selection
The key selection parameters for the output capacitor are
capacitance, ESR, ESL, and voltage-rating requirements.
These affect the overall stability, output ripple voltage,
and transient response of the DC-DC converter. The out-
put ripple occurs due to variations in the charge stored
in the output capacitor, the voltage drop due to the
capacitor’s ESR, and the voltage drop due to the
capacitor’s ESL. Estimate the output-voltage ripple due
to the output capacitance, ESR, and ESL:
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching
noise in the IC. The total input capacitance must be
equal or greater than the value given by the following
equation to keep the input-ripple voltage within specifi-
cation and minimize the high-frequency ripple current
being fed back to the input source:
V
= V
+ V
+ V
RIPPLE
RIPPLE(C)
RIPPLE(ESR) RIPPLE(ESL)
where the output ripple due to output capacitance,
ESR, and ESL is:
D x T x I
S
OUT
C
=
IN_MIN
V
IN-RIPPLE
I
P−P
V
=
RIPPLE(C)
where V
is the maximum allowed input ripple
IN-RIPPLE
8 x C
x f
S
OUT
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage. D
V
= I
x ESR
x ESL
is the duty cycle (V
/V ) and T is the switching
S
OUT IN
RIPPLE(ESR)
P−P
period (1/f ).
S
The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
high-frequency switching currents do not pass through
the input source, but are instead shunted through the
input capacitor. The input capacitor must meet the ripple
current requirement imposed by the switching currents.
The RMS input ripple current is given by:
I
P−P
V
=
RIPPLE(ESL)
t
ON
or:
I
t
P−P
V
=
x ESL
RIPPLE(ESL)
OFF
or whichever is larger.
The peak-to-peak inductor current (I ) is:
P-P
V
× (V − V )
IN OUT
OUT
I
= I
×
V
− V
OUT
V
OUT
V
IN
RIPPLE
LOAD
IN
V
I
=
x
IN
P−P
f × L
S
where I
is the input RMS ripple current.
RIPPLE
Use these equations for initial output-capacitor selec-
tion. Determine final values by testing a prototype or an
±4 ______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
Compensation Design
1
f
=
The power transfer function consists of one double pole
and one zero. The double pole is introduced by the
inductor L and the output capacitor CO. The ESR of the
output capacitor determines the zero. The double pole
and zero frequencies are given as follows:
P3_EA
2π × R1 × C2
1
f
=
P2_EA
2π × R2 × C3
The above equations are based on the assumptions
that C1 >> C2 and R3 >> R2, which are true in most
applications. Placements of these poles and zeros are
determined by the frequencies of the double pole and
ESR zero of the power transfer function. It is also a
function of the desired close-loop bandwidth. The fol-
lowing section outlines the step-by-step design proce-
dure to calculate the required compensation
components for the MAX15039. When the output volt-
age of the MAX15039 is programmed to a preset volt-
age, R3 is internal to the IC and R4 does not exist
(Figure 3b).
1
f
= f
=
P1_LC
P2_LC
⎛
⎞
R
R
+ ESR
O
2π x L x C
x
O
⎜
⎟
+ R
⎝
⎠
O
L
1
f
=
Z _ESR
2π x ESR x C
O
where R is equal to the sum of the output inductor’s DCR
L
(DC resistance) and the internal switch resistance,
R
. A typical value for R
is 20mΩ (low-side
DS(ON)
DS(ON)
MOSFET) and 26mΩ (high-side MOSFET). R is the output
O
load resistance, which is equal to the rated output voltage
divided by the rated output current. ESR is the total equiv-
alent series resistance of the output capacitor. If there is
more than one output capacitor of the same type in paral-
lel, the value of the ESR in the above equation is equal to
that of the ESR of a single output capacitor divided by the
total number of output capacitors.
When externally programming the MAX15039 (Figure
3a), the output voltage is determined by:
0.6 × R3
R4 =
(for V
> 0.6V)
OUT
(V
− 0.6)
OUT
For a 0.6V output, connect an 8.06kΩ resistor from FB
The high switching frequency range of the MAX15039
allows the use of ceramic output capacitors. Since the
ESR of ceramic capacitors is typically very low, the fre-
quency of the associated transfer function zero is higher
to OUT. The zero-cross frequency of the close-loop, f ,
C
should be between 10% and 20% of the switching fre-
quency, f . A higher zero-cross frequency results in
S
faster transient response. Once f is chosen, C1 is cal-
C
than the unity-gain crossover frequency, f , and the zero
C
culated from the following equation:
cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
ble pole produces a gain drop of 40dB/decade and a
phase shift of 180°. The compensation network error
amplifier must compensate for this gain drop and phase
shift to achieve a stable high-bandwidth closed-loop sys-
tem. Therefore, use type III compensation as shown in
Figures 3 and 4. Type III compensation possesses three
V
IN
2.5 x
V
P−P
C1 =
R
L
2 x π x R3 x (1+
) × f
C
R
O
where V
is the ramp peak-to-peak voltage (1V typ).
P-P
Due to the underdamped nature of the output LC dou-
ble pole, set the two zero frequencies of the type III
compensation less than the LC double-pole frequency
to provide adequate phase boost. Set the two zero fre-
quencies to 80% of the LC double-pole frequency.
Hence:
poles and two zeros with the first pole, f
zero frequency (DC). Locations of other poles and zeros
of the type III compensation are given by:
, located at
P1_EA
1
f
=
Z1_EA
2π × R1 × C1
1
L x C x (R + ESR)
1
O
O
f
=
R1 =
x
Z2_EA
2π × R3 × C3
0.8 x C1
R + R
L O
______________________________________________________________________________________ ±5
6A, 2MHz Step-Down Regulator
with Integrated Switches
Table 2. Mode Seleꢀtion
L x C x (R + ESR)
1
O
O
C3 =
x
MODE CONNECTION
OPERATION MODE
Forced PWM
0.8 x R3
R + R
L O
GND
Setting the second compensation pole, f
, at
P2_EA
Unconnected or
Forced PWM. Soft-start up into a
prebiased output (monotonic startup).
f
yields:
Z_ESR
V
/2
DD
C
x ESR
C3
O
R2 =
Skip Mode. Soft-start into a prebiased
output (monotonic startup).
V
DD
Set the third compensation pole at 1/2 of the switching
frequency. Calculate C2 as follows:
MAX15039
1
C2 =
COMPENSATION
TRANSFER
FUNCTION
π × R1 × f
S
OPEN-LOOP
GAIN
The above equations provide application compensation
when the zero-cross frequency is significantly higher than
the double-pole frequency. When the zero-cross frequen-
cy is near the double-pole frequency, the actual zero-
cross frequency is higher than the calculated frequency.
In this case, lowering the value of R1 reduces the zero-
cross frequency. Also, set the third pole of the type III
compensation close to the switching frequency if the
zero-cross frequency is above 200kHz to boost the phase
margin. The recommended range for R3 is 2kΩ to 10kΩ.
Note that the loop compensation remains unchanged if
only R4’s resistance is altered to set different outputs.
THIRD
POLE
DOUBLE POLE
GAIN (dB)
SECOND
POLE
POWER-STAGE
TRANSFER
FUNCTION
FIRST AND SECOND ZEROS
Figure 4. Type III Compensation Illustration
MODE Selection
The MAX15039 features a mode selection input
(MODE) that users can select a functional mode for the
device (see Table 2).
Soft-Starting Into a Prebiased Output
Mode (Monotonic Startup)
When MODE is left unconnected or biased to V /2, the
DD
Forced-PWM Mode
Connect MODE to GND to select forced-PWM mode. In
forced-PWM mode, the MAX15039 operates at a con-
stant switching frequency (set by the resistor at FREQ
terminal) with no pulse skipping. PWM operation starts
after a brief settling time when EN goes high. The low-
side switch turns on first, charging the bootstrap
capacitor to provide the gate-drive voltage for the high-
side switch. The low-side switch turns off either at the
end of the clock period or once the low-side switch
sinks 1.35A current (typ), whichever occurs first. If the
low-side switch is turned off before the end of the clock
period, the high-side switch is turned on for the remain-
ing part of the time interval until the inductor current
reaches 0.9A, or the end of clock cycle is encountered.
MAX15039 soft-starts into a prebiased output without dis-
charging the output capacitor. This type of operation is
also termed monotonic startup. See the Starting Into
Prebiased Output waveforms in the Typical Operating
Characteristics section for an example.
In monotonic startup mode, both low-side and high-
side switches remain off to avoid discharging the prebi-
ased output. PWM operation starts when the FB voltage
crosses the SS voltage. As in forced-PWM mode, the
PWM activity starts with the low-side switch turning on
first to build the bootstrap capacitor charge.
The MAX15039 is also able to start into prebiased with
the output above the nominal set point without abruptly
discharging the output, thanks to the sink current con-
trol of the low-side switch through a 4-step DAC in 128
clock cycles. Monotonic startup mode automatically
switches to forced-PWM mode 4096 clock cycles delay
after the voltage at FB increases above 92.5% of
Starting from the first PWM activity, the sink current
threshold is increased through an internal 4-step DAC
to reach the current limit of 11A after 128 clock periods.
This is done to help a smooth recovery of the regulated
voltage even in case of accidental prebiased output in
spite of the initial forced-PWM mode selection.
V
. The additional delay prevents an early transi-
REFIN
±6 ______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
tion from monotonic startup to forced-PWM mode dur-
ing soft-start when a prolonged time constant external
REFIN voltage is applied.
PCB Layout Considerations and
Thermal Performance
Careful PCB layout is critical to achieve clean and sta-
ble operation. It is highly recommended to duplicate the
MAX15039 EV kit layout for optimum performance. If devi-
ation is necessary, follow these guidelines for good PCB
layout:
The maximum allowed soft-start time is 2ms when an
external reference is applied at REFIN in the case of
starting up into prebiased output.
Skip Mode
to select skip mode. In skip
1) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the sig-
nal ground plane.
Connect MODE to V
DD
mode, the MAX15039 switches only as necessary to
maintain the output at light loads (not capable of sinking
current from the output), but still operates with fixed-fre-
quency (set by the resistor at FREQ terminal) PWM at
medium and heavy loads. This maximizes light-load effi-
ciency and reduces the input quiescent current.
2) Place capacitors on V , IN, and SS as close as pos-
DD
sible to the IC and its corresponding pin using direct
traces. Keep power ground plane (connected to
PGND) and signal ground plane (connected to GND)
separate.
In case of prolonged high-side idle activity (beyond
eight clock cycles), the low-side switch is turned on
briefly to rebuild the charge lost in the bootstrap capac-
itor before the next on-cycle of the high-side switch.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the out-
put capacitors, and the input capacitors.
In skip mode, the low-side switch is turned off when the
inductor current decreases to 0.2A (typ) to ensure no
reverse current flowing from the output capacitor and
the best conversion efficiency/minimum supply current.
4) Connect IN, LX, and PGND separately to a large
copper area to help cool the IC to further improve
efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensa-
tion components as close as possible to the IC.
The high-side switch minimum on-time is controlled to
guarantee that 0.9A current is reached to avoid high
frequency bursts at no load conditions and that might
cause a rapid increase of the supply current caused by
additional switching losses.
6) Route high-speed switching nodes, such as LX,
away from sensitive analog areas (FB, COMP).
Even if skip mode is selected at the device turn-on, the
monotonic startup mode is internally selected during
soft-start. The transition to skip mode is automatically
achieved 4096 clock cycles after the voltage at FB
increases above 92.5% of V
.
REFIN
Changing from skip mode to forced-PWM mode and
vice-versa can be done at any time. The output capaci-
tor should be large enough to limit the output-voltage
overshoot/undershoot due to the settling times to reach
different duty-cycle set points corresponding to forced-
PWM mode and skip mode at light loads.
______________________________________________________________________________________ ±7
6A, 2MHz Step-Down Regulator
with Integrated Switches
Pin Configuration
Chip Information
PROCESS: BiCMOS
TOP VIEW
18 17 16 15 14 13
19
12
PGND
PWRGD
Package Information
For the latest package outline information and land patterns, go
PGND 20
11 FREQ
to www.maxim-iꢀ.ꢀom/paꢀkages.
21
22
23
24
10
9
IN
IN
OUT
FB
MAX15039
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
MAX15039
*EP
24 TQFN-EP
T2444-4
2±-0±39
IN
COMP
GND
8
EN
7
+
1
2
3
4
5
6
THIN QFN
*EXPOSED PAD
±8 ______________________________________________________________________________________
6A, 2MHz Step-Down Regulator
with Integrated Switches
MAX15039
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
DESCRIPTION
CHANGED
0
1
10/08
12/09
Initial release
Updated the Typical Operating Characteristics.
—
5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ ±9
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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