MAX15053 [MAXIM]
High-Efficiency, 2A, Current-Mode Synchronous, Step-Down Switching Regulator; 高效， 2A ，电流模式同步整流，降压型开关稳压器
| 型号： | MAX15053 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Efficiency, 2A, Current-Mode Synchronous, Step-Down Switching Regulator |
| 文件： | 总21页 (文件大小：2278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5240; Rev 2; 7/11
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
General Description
Features
High-Side and 18mI
The MAX15053 high-efficiency, current-mode, synchro-
nous step-down switching regulator with integrated
power switches delivers up to 2A of output current.
The device operates from 2.7V to 5.5V and provides an
output voltage from 0.6V up to 94% of the input voltage,
making the device ideal for distributed power systems,
portable devices, and preregulation applications.
S Internal 30mI (typ) R
DS(ON)
(typ) Low-Side MOSFETs at 5V
S Continuous 2A Output Current Over Temperature
S 96% Efficiency with 3.3V Output at 2A
S
1% Output Voltage Accuracy Over Load, Line,
and Temperature
S Operates from 2.7V to 5.5V Supply
S Cycle-by-Cycle Overcurrent Protection
S Adjustable Output from 0.6V to Up to 0.94 x V
S Programmable Soft-Start
The MAX15053 utilizes a current-mode control archi-
tecture with a high gain transconductance error ampli-
fier. The current-mode control architecture facilitates
easy compensation design and ensures cycle-by-cycle
current limit with fast response to line and load transients.
IN
S Factory-Trimmed, 1MHz Switching Frequency
The MAX15053 offers selectable skip-mode functionality
to reduce current consumption and achieve a higher effi-
S Stable with Low-ESR Ceramic Output Capacitors
S Safe-Startup Into Prebiased Output
S External Reference Input
ciency at light output load. The low R
integrated
DS(ON)
switches ensure high efficiency at heavy loads while min-
imizing critical inductances, making the layout design
a much simpler task with respect to discrete solutions.
Utilizing a simple layout and footprint assures first-pass
success in new designs.
S Skip-Mode Functionality
S Enable Input/Power-Good Output
S Fully Protected Against Overcurrent and
The MAX15053 features a 1MHz, factory-trimmed, fixed-
frequency PWM mode operation. The high switching fre-
quency, along with the PWM current-mode architecture,
allows for a compact, all-ceramic capacitor design.
Overtemperature
S Input Undervoltage Lockout
Ordering Information
The MAX15053 offers a capacitor-programmable soft-
start reducing inrush current, startup into PREBIAS
operations, and a PGOOD open-drain output that can be
used as an interrupt and for power sequencing.
PART
TEMP RANGE
PIN-PACKAGE
MAX15053EWL+
-40°C to +85°C
9 WLP
+Denotes a lead(Pb)-free/RoHS-compliant package.
The MAX15053 is available in a 9-bump (3 x 3 array),
1.5mm x 1.5mm WLP package and is specified over the
-40NC to +85NC temperature range.
Typical Operating Circuit
Applications
Distributed Power Systems
Preregulators for Linear Regulators
Portable Devices
INPUT
2.7V TO 5.5V
OUTPUT
1.8V/2A
IN
LX
MAX15053
GND
Notebook Power
PGOOD
FB
Server Power
ON
EN
ENABLE
OFF
COMP
IP Phones
SKIP
SS/REFIN
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
ABSOLUTE MAXIMUM RATINGS
IN, PGOOD to GND ................................................-0.3V to +6V
Continuous Power Dissipation (T = +70NC)
A
LX to GND ..................................................-0.3V to (V + 0.3V)
9-Bump WLP Multilayer Board
IN
LX to GND .......................................-1V to (V + 0.3V) for 50ns
IN
(derate 14.1mW/NC above T = +70NC)....................1127mW
A
EN, COMP, FB, SS/REFIN, SKIP to GND...-0.3V to (V + 0.3V)
IN
Operating Temperature Range.......................... -40NC to +85NC
Operating Junction Temperature (Note 2)......................+105NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
LX Current (Note 1)................................................... -5A to +5A
Output Short-Circuit Duration....................................Continuous
Note 1: LX has internal clamp diodes to GND and IN. Applications that forward bias these diodes should not exceed the IC’s pack-
age power dissipation limits.
Note 2: Limit the junction temperature to +105NC for continuous operation at maximum output current.
PACKAGE THERMAL CHARACTERISTICS (Note 3)
WLP
Junction-to-Case Thermal Resistance (B )...................26NC/W
JC
Junction-to-Ambient Thermal Resistance (B )..............71NC/W
JA
Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V = 5V, T = -40NC to +85NC, unless otherwise noted, typical values are at T = +25NC.) (Note 4)
IN
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5.5
2
UNITS
V
IN Voltage Range
V
IN
2.7
IN Shutdown Supply Current
IN Supply Current
V
V
= 0V
0.2
FA
EN
EN
I
IN
= 5V, V = 0.65V, no switching
1.56
2.3
mA
FB
V
Undervoltage Lockout
IN
LX starts switching, V rising
2.6
2.7
V
IN
Threshold
V
Undervoltage Lockout
IN
LX stops switching, V falling
IN
200
mV
Hysteresis
ERROR AMPLIFIER
Transconductance
Voltage Gain
g
1.5
90
mS
dB
mV
nA
MV
A
VEA
FB Set-Point Accuracy
FB Input Bias Current
V
Over line, load, and temperature
594
600
606
FB
I
V
FB
= 0.6V
-500
+500
FB
COMP to Current-Sense
Transconductance
g
18
A/V
V
MC
COMP Clamp Low
V
FB
= 0.65V, V = 0.6V
0.94
SS
POWER SWITCHES
LX On-Resistance, High-Side
pMOS
30
18
4
mI
mI
A
LX On-Resistance, Low-Side
nMOS
High-Side Switch Current-Limit
Threshold
I
HSCL
Low-Side Switch Sink Current-
Limit Threshold
4
A
2
______________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
ELECTRICAL CHARACTERISTICS (continued)
(V = 5V, T = -40NC to +85NC, unless otherwise noted, typical values are at T = +25NC.) (Note 4)
IN
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
10
UNITS
Low-Side Switch Source Current-
Limit Threshold
4
A
LX Leakage Current
RMS LX Output Current
OSCILLATOR
V
EN
= 0V
FA
2
A
Switching Frequency
Maximum Duty Cycle
Minimum Controllable On-Time
f
850
94
1000
95.8
70
1150
kHz
%
SW
D
MAX
ns
Slope Compensation Ramp
Valley
1.15
320
V
Slope Compensation Ramp
Amplitude
V
Extrapolated to 100% duty cycle
mV
SLOPE
ENABLE
EN Input High Threshold Voltage
EN Input Low Threshold Voltage
EN Input Leakage Current
SKIP Input Leakage Current
SOFT-START, PREBIAS, REFIN
Soft-Start Current
V
V
V
V
rising
falling
= 5V
1.45
V
V
EN
EN
EN
0.4
0.025
25
FA
FA
= V = 5V
SKIP
EN
I
V
= 0.45V, sourcing
= 10mA, sinking
10
FA
I
SS
SS/REFIN
SS/REFIN Discharge Resistance
R
I
8.3
SS
SS/REFIN
SS/REFIN Prebias Mode Stop
Voltage
V
rising
0.58
V
V
SS/REFIN
V
1.8
-
IN
External Reference Input Range
0
HICCUP
Number of Consecutive Current-
Limit Events to Hiccup
8
Events
Clock
Cycles
Timeout
1024
POWER-GOOD OUTPUT
PGOOD Threshold
V
V
rising
0.535
0.555
28
0.575
60
V
FB
PGOOD Threshold Hysteresis
falling
= 5mA, V = 0.5V
mV
mV
FA
FB
PGOOD V
I
20
OL
PGOOD
FB
PGOOD Leakage
V
= 5V, V = 0.65V
0.013
PGOOD
FB
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
20
NC
NC
Temperature falling
Note 4: Specifications are 100% production tested at T = +25NC. Limits over the operating temperature range are guaranteed by
A
design and characterization.
_______________________________________________________________________________________
3
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Typical Operating Characteristics
(V = 5V, V
= 1.8V, I
= 2A, Circuit of Figure 5, T = +25NC, unless otherwise noted.)
IN
OUT
LOAD A
EFFICIENCY vs. OUTPUT CURRENT
(PWM MODE)
EFFICIENCY vs. OUTPUT CURRENT
(PWM MODE)
EFFICIENCY vs. OUTPUT CURRENT
(SKIP MODE)
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
= 3.3V
OUT
V
= 3.3V
V
= 1.8V
V
= 1.2V
V
= 2.5V
V
= 1.8V
V
= 1.2V
OUT
OUT
OUT
OUT
OUT
OUT
V
= 2.5V
OUT
V
= 1.5V
OUT
V
= 1.5V
OUT
V
= 1.8V
V
= 1.2V
OUT
OUT
V
= 2.5V
V
= 1.5V
OUT
OUT
V
= 5V
V
= 3.3V
IN
IN
V
= 5V
IN
0
400
800 1200 1600 2000 2400
OUTPUT CURRENT (mA)
0
400
800 1200 1600 2000 2400
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
SWITCHING FREQUENCY
vs. INPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
(SKIP MODE)
1100
1080
1060
1040
1020
1000
980
100
95
90
85
80
75
70
65
60
55
50
V
= 2.5V
V
= 1.5V
OUT
OUT
V
= 1.8V
V
= 1.2V
OUT
OUT
960
940
920
V
= 3.3V
IN
900
2.7
3.2
3.7
4.2
4.7
5.2
INPUT VOLTAGE (V)
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs. OUTPUT CURRENT
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
1.89
1.87
1.85
1.83
1.81
1.79
1.77
1.75
V
= 3.3V
= 5V
OUT
V
OUT
I
= 0.5A
OUT
2.7
3.2
3.7
4.2
4.7
5.2
0
0.5
1.0
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
OUTPUT CURRENT (A)
4
______________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Typical Operating Characteristics (continued)
(V = 5V, V
= 1.8V, I
= 2A, Circuit of Figure 5, T = +25NC, unless otherwise noted.)
IN
OUT
LOAD A
SWITCHING WAVEFORMS
(I
= 2A)
OUT
LOAD-TRANSIENT RESPONSE
MAX15053 toc9a
MAX15053 toc08
V
OUT
V
OUT
50mV/div
AC-COUPLED
100mV/div
AC-COUPLED
I
LX
1A/div
I
OUT
0A
1A/div
0A
V
LX
5V/div
PWM MODE
V
= 5V
IN
400ns/div
40µs/div
SWITCHING WAVEFORM IN SKIP MODE
(I = 10mA)
SWITCHING WAVEFORMS
OUT
MAX15053 toc10
MAX15053 toc09b
V
OUT
50mV/div
AC-COUPLED
V
OUT
50mV/div
AC-COUPLED
I
LX
1A/div
I
LX
0A
1A/div
V
V
LX
LX
5V/div
5V/div
V
= 3.3V
IN
10µs/div
400ns/div
INPUT AND OUTPUT RIPPLE VOLTAGE
WAVEFORM (I = 2A)
SHUTDOWN WAVEFORM
OUT
MAX15053 toc11
MAX15053 toc12
V
ENABLE
5V/div
INPUT
20mV/div
AC-COUPLED
V
OUT
1V/div
I
LX
OUTPUT
100mV/div
AC-COUPLED
1A/div
V
PGOOD
5V/div
400ns/div
10µs/div
_______________________________________________________________________________________
5
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Typical Operating Characteristics (continued)
(V = 5V, V
= 1.8V, I
= 2A, Circuit of Figure 5, T = +25NC, unless otherwise noted.)
IN
OUT
LOAD A
SOFT-START WAVEFORMS (PWM)
SOFT-START WAVEFORMS (SKIP MODE)
(I = 2A)
(I
OUT
= 2A)
OUT
MAX15053 toc13a
MAX15053 toc13b
V
V
ENABLE
5V/div
ENABLE
5V/div
V
V
OUT
OUT
1V/div
1V/div
I
LX
I
LX
1A/div
1A/div
V
PGOOD
V
PGOOD
5V/div
5V/div
200µs/div
200µs/div
QUIESCENT CURRENT
vs. INPUT VOLTAGE
SHORT-CIRCUIT HICCUP MODE
MAX15053 toc15
100
V
= 0V
EN
90
80
70
60
50
40
30
20
10
0
I
IN
500mA/div
V
OUT
1V/div
I
OUT
5A/div
2.7
3.2
3.7
4.2
4.7
5.2
200µs/div
INPUT VOLTAGE (V)
RMS INPUT CURRENT
vs. INPUT VOLTAGE
FB VOLTAGE vs. TEMPERATURE
100
90
80
70
60
50
40
30
20
10
0
606
604
602
600
598
596
594
NO LOAD
SHORT CIRCUIT ON OUTPUT
3.2 3.7 4.2
INPUT VOLTAGE (V)
2.7
4.7
5.2
-40 -20
0
20
40
60
80
AMBIENT TEMPERATURE (°C)
6
______________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Typical Operating Characteristics (continued)
(V = 5V, V
= 1.8V, I
= 2A, Circuit of Figure 5, T = +25NC, unless otherwise noted.)
IN
OUT
LOAD A
SOFT-START WAVEFORMS
(EXTERNAL REFIN) (PWM MODE)
SOFT-START WAVEFORMS
(EXTERNAL REFIN) (SKIP MODE)
MAX15053 toc18a
MAX15053 toc18b
V
V
SS/REFIN
500mV/div
SS/REFIN
500mV/div
V
OUT
V
OUT
1V/div
1V/div
NO LOAD
NO LOAD
I
LX
I
LX
1A/div
1A/div
V
V
PGOOD
PGOOD
5V/div
5V/div
200µs/div
200µs/div
STARTING INTO A PREBIASED OUTPUT
(I = 2A)
STARTING INTO A PREBIASED OUTPUT
(NO LOAD)
OUT
MAX15053 toc19
MAX15053 toc20a
V
ENABLE
5V/div
V
ENABLE
5V/div
V
OUT
V
OUT
1V/div
1V/div
I
LX
I
LX
1A/div
1A/div
V
PGOOD
V
PGOOD
PWM MODE
PWM MODE
5V/div
5V/div
200µs/div
200µs/div
STARTING INTO A PREBIASED OUTPUT
STARTING INTO A PREBIASED OUTPUT
HIGHER THAN SET OUTPUT
MAX15053 toc20b
MAX15053 toc21
1.8V
V
OUT
V
ENABLE
5V/div
500mV/div
V
OUT
1V/div
I
L
1A/div
I
LX
1A/div
V
SS/REFIN
500mV/div
V
PGOOD
5V/div
10I LOAD AT OUT
200µs/div
400µs/div
_______________________________________________________________________________________
7
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Typical Operating Characteristics (continued)
(V = 5V, V
= 1.8V, I
= 2A, Circuit of Figure 5, T = +25NC, unless otherwise noted.)
IN
OUT
LOAD A
CASE TEMPERATURE
vs. AMBIENT TEMPERATURE
INPUT CURRENT IN SKIP MODE
vs. OUTPUT VOLTAGE
100
80
60
40
20
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
NO LOAD
V
V
= 5.0V
CC
CC
= 3.3V
2.2
-20
-40
-40
-20
0
20
40
60
80
1.2
1.7
2.7
3.2
AMBIENT TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
8
______________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
MAX15053
GND
A1
LX
A2
IN
A3
COMP
B1
SKIP
B2
EN
B3
FB
C1
SS/REFIN
C2
PGOOD
C3
WLP
Pin Description
BUMP
NAME
FUNCTION
Analog Ground/Low-Side Switch Source Terminal. Connect to the PCB copper plane at one point near
the input bypass capacitor return terminal.
A1
GND
Inductor Connection. Connect LX to the switched side of the inductor. LX is high impedance when the
IC is in shutdown mode.
A2
A3
LX
IN
Input Power Supply. Input supply range is from 2.7V to 5.5V. Bypass with a minimum 10FF ceramic
capacitor to GND. See Figures 5 and 6.
Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to GND. See
the Closing the Loop: Designing the Compensation Circuitry section.
B1
B2
B3
COMP
SKIP
EN
Skip-Mode Input. Connect to EN to select skip mode or leave unconnected for normal operation.
Enable Input. EN is a digital input that turns the regulator on and off. Drive EN high to turn on the regula-
tor. Connect to IN for always-on operation.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to
C1
C2
C3
FB
set the output voltage from 0.6V up to 94% of V
.
IN
Soft-Start/External Voltage Reference Input. Connect a capacitor from SS/REFIN to GND to set the startup
SS/REFIN time. See the Setting the Soft-Start Time section for details on setting the soft-start time. Apply a voltage
reference from 0V to V - 1.5V to drive soft-start externally.
IN
Open-Drain Power-Good Output. PGOOD goes high when FB is above 555mV and pulls low if FB is
below 527mV.
PGOOD
_______________________________________________________________________________________
9
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Block Diagram
SKIP
EN
IN
HIGH-SIDE
CURRENT LIMIT
SHDN
SKPM
BIAS
GENERATOR
EN LOGIC, IN UVLO
THERMAL SHDN
SKIP-MODE
LOGIC
LX
VOLTAGE
REFERENCE
CURRENT-SENSE
AMPLIFIER
LX
IN
IN
STRONG PREBIASED
FORCED START
SKPM
CK
0.58V
LX
CONTROL
LOGIC
SS/REFIN
IN
SS/REFIN BUFFER
0.6V
GND
10µA
LOW-SIDE SOURCE-SINK
CURRENT LIMIT AND ZERO-
CROSSING COMPARATOR
PWM
COMPARATOR
ERROR AMPLIFIER
SINK
SOURCE
FB
ZX
C
COMP
RAMP
CK
SKPM
OSCILLATOR
RAMP GEN
MAX15053
PGOOD
POWER-GOOD
COMPARATOR
0.555V RISING,
0.527V FALLING
10 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
limit is reached. The low-side MOSFET turns on for the
remainder of the oscillation cycle.
Detailed Description
The MAX15053 high-efficiency, current-mode switching
Starting into a Prebiased Output
The MAX15053 can soft-start into a prebiased output
without discharging the output capacitor. In safe pre-
biased startup, both low-side and high-side MOSFETs
remain off to avoid discharging the prebiased output.
PWM operation starts when the voltage on SS/REFIN
crosses the voltage on FB.
regulator can deliver up to 2A of output current. The
MAX15053 provides output voltages from 0.6V to 0.94 x
V
IN
from 2.7V to 5.5V input supplies, making the device
ideal for on-board point-of-load applications.
The MAX15053 delivers current-mode control architec-
ture using a high gain transconductance error amplifier.
The current-mode control architecture facilitates easy
compensation design and ensures cycle-by-cycle cur-
rent limit with fast response to line and load transients.
The MAX15053 can start into a prebiased voltage higher
than the nominal set point without abruptly discharg-
ing the output. Forced PWM operation starts when the
SS/REFIN voltage reaches 0.58V (typ), forcing the
converter to start. In case of prebiased output, below
or above the output nominal set point, if low-side sink
current-limit threshold (set to the reduced value of -0.4A
(typ) for the first 32 clock cycles and then set to -4A typ)
is reached, the low-side switch turns off before the end of
the clock period, and the high-side switch turns on until
one of the following conditions is satisfied:
The MAX15053 features a 1MHz fixed switching frequen-
cy, allowing for all-ceramic capacitor designs and fast
transient responses. The high operating frequency mini-
mizes the size of external components. The MAX15053
is available in a 1.5mm x 1.5mm (3 x 3 array) x 0.5mm
pitch WLP package.
The MAX15053 offers a selectable skip-mode functional-
ity to reduce current consumption and achieve a higher
efficiency at light output loads. The low R
integrat-
DS(ON)
•ꢀ High-sideꢀsourceꢀcurrentꢀhitsꢀtheꢀreducedꢀhigh-sideꢀ
current limit (0.4A, typ); in this case, the high-side
switch is turned off for the remaining time of the clock
period.
ed switches (30mI high-side and 18mI low-side, typ)
ensure high efficiency at heavy loads while minimizing
critical inductances, making the layout design a much
simpler task with respect to discrete solutions. Utilizing
a simple layout and footprint assures first-pass success
in new designs.
•ꢀ Theꢀclockꢀperiodꢀends.ꢀReducedꢀhigh-sideꢀcurrentꢀ
limit is activated to recirculate the current into the
high-side power switch rather than into the internal
high-side body diode, which could be damaged.
Low-side sink current limit is provided to protect the
low-side switch from excessive reverse current dur-
ing prebiased operation.
The MAX15053 features 1MHz Q15%, factory-trimmed,
fixed-frequency PWM mode operation. The MAX15053 also
offers capacitor-programmable, soft-start reducing inrush
current, startup into PREBIAS operation, and a PGOOD
open-drain output for sequencing with other devices.
In skip mode operation, the prebias output needs to be
lower than the set point.
Controller Function–PWM Logic
The controller logic block is the central processor that
determines the duty cycle of the high-side MOSFET
under different line, load, and temperature conditions.
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller
logic block takes the output from the PWM comparator
and generates the driver signals for both high-side and
low-side MOSFETs. The control logic block controls the
break-before-make logic and all the necessary timing.
Enable Input
The MAX15053 features independent device enable
control and power-good signal that allow for flexible
power sequencing. Drive the enable input (EN) high to
enable the regulator, or connect EN to IN for always-on
operation. Power-good (PGOOD) is an open-drain out-
put that asserts when V
is above 555mV (typ), and
FB
deasserts low if V is below 527mV (typ).
FB
The high-side MOSFET turns on at the beginning of
the oscillator cycle and turns off when the COMP volt-
age crosses the internal current-mode ramp waveform,
which is the sum of the slope compensation ramp and
the current-mode ramp derived from inductor current
(current-sense block). The high-side MOSFET also turns
off if the maximum duty cycle is 94%, or when the current
Programmable Soft-Start (SS/REFIN)
The MAX15053 utilizes a soft-start feature to slowly
ramp up the regulated output voltage to reduce input
inrush current during startup. Connect a capacitor from
SS/REFIN to GND to set the startup time (see the Setting
the Soft-Start Time section for capacitor selection details).
______________________________________________________________________________________ 11
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
200mA (typ). The inductor current does not become
negative. If during a clock cycle the inductor current falls
below the 200mA threshold (during off-time), the low side
turns off. At the next clock cycle, if the output voltage is
above set point, the PWM logic keeps both high-side
and low-side MOSFETs off. If instead the output voltage
is below the set point, the PWM logic drives the high-
side on for a minimum fixed on-time (300ns typ). In this
way the system can skip cycles, reducing frequency of
operations, and switches only as needed to service load
at the cost of an increase in output voltage ripple (see
the Skip Mode Frequency and Output Ripple section). In
skip mode, power dissipation is reduced and efficiency
is improved at light loads because power MOSFETs do
not switch at every clock cycle.
Error Amplifier
A high-gain error amplifier provides accuracy for the
voltage-feedback loop regulation. Connect the neces-
sary compensation network between COMP and GND
(see the Compensation Design Guidelines section). The
error-amplifier transconductance is 1.5mS (typ). COMP
clamp low is set to 0.94V (typ), just below the slope ramp
compensation valley, helping COMP to rapidly return to
the correct set point during load and line transients.
PWM Comparator
The PWM comparator compares COMP voltage to the
current-derived ramp waveform (LX current to COMP
voltage transconductance value is 18A/V typ). To avoid
instability due to subharmonic oscillations when the duty
cycle is around 50% or higher, a slope compensation
ramp is added to the current-derived ramp waveform.
The compensation ramp slope (0.3V x 1MHz = 0.3V/Fs)
is equivalent to half the inductor current downslope in the
worst case (load 2A, current ripple 30% and maximum
duty-cycle operation of 94%). The slope compensation
ramp valley is set to 1.15V (typ).
Applications Information
Setting the Output Voltage
The MAX15053 output voltage is adjustable from 0.6V
up to 94% of V by connecting FB to the center tap of a
IN
resistor-divider between the output and GND (Figure 1).
Choose R1 and R2 so that the DC errors due to the FB
input bias current (Q500nA) do not affect the output volt-
age accuracy. With lower value resistors, the DC error
is reduced, but the amount of power consumed in the
resistor-divider increases. A typical value for R2 is 10kI,
but values between 5kIand 50kIare acceptable. Once
R2 is chosen, calculate R1 using:
Overcurrent Protection and Hiccup
When the converter output is shorted or the device is
overloaded, each high-side MOSFET current-limit event
(4A typ) turns off the high-side MOSFET and turns on the
low-side MOSFET. On each current-limit event a 3-bit
counter is incremented. The counter is reset after three
consecutive high-side MOSFETs turn on without reach-
ing current limit. If the current-limit condition persists,
the counter fills up reaching eight events. The control
logic then discharges SS/REFIN, stops both high-side
and low-side MOSFETs, and waits for a hiccup period
(1024 clock cycles typ) before attempting a new soft-
start sequence. The hiccup mode is also enabled during
soft-start time.
VOUT
R1= R2×
−1
V
FB
where the feedback threshold voltage, V = 0.6V (typ).
FB
When regulating for an output of 0.6V in skip mode, short
FB to OUT and keep R2 connected from FB to GND.
Inductor Selection
A high-valued inductor results in reduced inductor ripple
current, leading to a reduced output ripple voltage.
However, a high-valued inductor results in either a larger
physical size or a high series resistance (DCR) and a
lower saturation current rating. Typically, choose an
inductor value to produce a current ripple equal to 30%
of load current. Choose the inductor with the following
formula:
Thermal-Shutdown Protection
The MAX15053 contains an internal thermal sensor that
limits the total power dissipation to protect the device in
the event of an extended thermal fault condition. When
the die temperature exceeds +150NC (typ), the thermal
sensor shuts down the device, turning off the DC-DC
converter to allow the die to cool. After the die tempera-
ture falls by 20NC (typ), the device restarts, following the
soft-start sequence.
V
V
OUT
OUT
L =
× 1−
Skip Mode Operation
The MAX15053 operates in skip mode when SKIP is con-
nected to EN. When in skip mode, LX output becomes
high impedance when the inductor current falls below
f
×LIR×I
V
SW
LOAD
IN
where f
is the internally fixed 1MHz switching frequen-
SW
cy, and LIR is the desired inductor current ratio (typically
12 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
FEEDBACK
DIVIDER
ERROR AMPLIFIER
POWER MODULATOR
OUTPUT FILTER
AND LOAD
SLOPE
COMPENSATION
RAMP
V
IN
V
OUT
g
C
MC
FB
R1
R2
*C
FF
I
L
V
FB
V
OUT
COMP
Q
HS
I
OUT
L
DCR
PWM
CONTROL
LOGIC
V
COMP
ESR
Q
LS
COMPARATOR
R
LOAD
R
C
R
g
MV
OUT
C
OUT
C
C
V
COMP
I
OUT
G
MOD
A
(dB)/20
VEA
/g
MV
R
OUT
= 10
NOTE: THE G
STAGE SHOWN ABOVE MODELS THE AVERAGE CURRENT OF
MOD
REF
THE INDUCTOR, I , INJECTED INTO THE OUTPUT LOAD, I , e.g., I = I
OUT OUT
.
L
L
THIS CAN BE USED TO SIMPLIFY/MODEL THE MODULATION/CONTROL/POWER
STATE CIRCUITRY SHOWN WITHIN THE BOXED AREA.
*NOTE: C IS OPTIONAL AND DESIGNED TO EXTEND THE
REGULATOR’S GAIN BANDWIDTH AND INCREASED PHASE
FF
MARGIN FOR SOME LOW-DUTY CYCLE APPLICATIONS.
Figure 1. Peak Current-Mode Regulator Transfer Model
set to 0.3). In addition, the peak inductor current, I
,
f
is the switching frequency (1MHz), and I is the
LOAD
L_PK
SW
must always be below the minimum high-side current-
output load. The impedance of the input capacitor at
the switching frequency should be less than that of the
input source so high-frequency switching currents do not
pass through the input source, but are instead shunted
through the input capacitor.
limit value, I
rating, I
, and the inductor saturation current
HSCL
.
L_SAT
Ensure that the following relationship is satisfied:
1
I
= I
+
∆I < min I
I
The input capacitor must meet the ripple current require-
ment imposed by the switching currents. The RMS input
ripple current is given by:
(
)
L_PK
LOAD
L
HSCL, L_SAT
2
Input Capacitor Selection
The input capacitor reduces the peak current drawn from
the input power supply and reduces switching noise in
the device. The total input capacitance must be equal to
or greater than the value given by the following equation
to keep the input ripple voltage within the specification
and minimize the high-frequency ripple current being fed
back to the input source:
V
× V − V
(
)
OUT
IN
OUT
I
=
I
RIPPLE
LOAD
V
IN
where I
is the input RMS ripple current.
RIPPLE
Output Capacitor Selection
The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage rating. The
parameters affect the overall stability, output ripple volt-
age, and transient response of the DC-DC converter.
The output ripple occurs due to variations in the charge
stored in the output capacitor, the voltage drop due to
the capacitor’s ESR, and the voltage drop due to the
I
V
OUT
LOAD
C
=
×
IN
f
× ∆V
V
SW
IN_RIPPLE
IN
where DV
is the maximum-allowed input ripple
IN_RIPPLE
voltage across the input capacitors and is recommend-
ed to be less than 2% of the minimum input voltage,
______________________________________________________________________________________ 13
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
capacitor’s ESL. Estimate the output-voltage ripple due
to the output capacitance, ESR, and ESL as follows:
the inductor and output capacitor values. After a short
time, the controller responds by regulating the output
voltage back to the predetermined value.
V
V
OUT
1
× C
OUT
×L
∆V
OUT
=
× 1−
× R
+
ESR_COUT
Use higher C
values for applications that require
OUT
f
V
8 × f
SW
SW
IN
OUT
light load operation or transition between heavy load and
light load, triggering skip mode, causing output under-
shooting or overshooting. When applying the load, limit
For ceramic capacitors, ESR contribution is negligible:
1
the output undershoot by sizing C
according to the
OUT
R
<<
ESR_OUT
following formula:
8× f
× C
OUT
SW
∆I
LOAD
C
≅
For tantalum or electrolytic capacitors, ESR contribution
is dominant:
OUT
3f
x∆V
CO
OUT
where DI
is the total load change, f
is the regula-
CO
LOAD
1
R
>>
tor unity-gain bandwidth (or zero crossover frequency),
and DV is the desired output undershooting. When
ESR_OUT
8× f
× C
OUT
SW
OUT
removing the load and entering skip mode, the device
cannot control output overshooting, since it has no sink
current capability; see the Skip Mode Frequency and
Use these equations for initial output-capacitor selec-
tion. Determine final values by testing a prototype or an
evaluation circuit. A smaller ripple current results in less
output-voltage ripple. Since the inductor ripple current is
a factor of the inductor value, the output-voltage ripple
decreases with larger inductance. Use ceramic capaci-
tors for low ESR and low ESL at the switching frequency
of the converter. The ripple voltage due to ESL is negli-
gible when using ceramic capacitors.
Output Ripple section to properly size C
.
OUT
Skip Mode Frequency and Output Ripple
In skip mode, the switching frequency (f ) and output
SKIP
ripple voltage (V
) shown in Figure 2 are cal-
OUT-RIPPLE
culated as follows:
t
is a fixed time (300ns, typ); the peak inductor current
ON
Load-transient response also depends on the selected
output capacitance. During a load transient, the output
reached is:
instantly changes by ESR x DI
can respond, the output deviates further, depending on
. Before the controller
V
− V
L
LOAD
IN
OUT
I
=
× t
ON
SKIP−LIMIT
I
L
I
SKIP-LIMIT
I
LOAD
t
t
t
= n × t
OFF2 CK
ON
OFF1
V
OUT
V
OUT-RIPPLE
Figure 2. Skip Mode Waveform
14 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
t
is the time needed for inductor current to reach the
the inductor’s pole frequency is shifted beyond the gain
bandwidth of the regulator. System stability is provided
with the addition of a simple series capacitor-resistor from
COMP to GND. This pole-zero combination serves to tailor
the desired response of the closed-loop system. The basic
regulator loop consists of a power modulator (comprising
the regulator’s pulse-width modulator, current sense and
slope compensation ramps, control circuitry, MOSFETs,
and inductor), the capacitive output filter and load, an
output feedback divider, and a voltage-loop error amplifier
with its associated compensation circuitry. See Figure 1.
OFF1
zero-current crossing limit (~ 0A):
L ×I
SKIP−LIMIT
t
=
OFF1
V
OUT
During t
and t
, the output capacitor stores a
ON
OFF1
charge equal to (see Figure 2):
1
− V
1
2
L x I
−I
SKIP−LIMIT LOAD
x
+
(
)
V
V
IN
OUT
OUT
∆Q
=
OUT
2
The average current through the inductor is expressed as:
During t
(= n x t , number of clock cycles skipped),
CK
OFF2
output capacitor loses this charge:
I
= G
× V
MOD COMP
L
∆Q
OUT
LOAD
2
t
=
⇒
where IL is the average inductor current and G
power modulator’s transconductance.
is the
MOD
OFF2
I
1
− V
1
For a buck converter:
L x I
−I
x
+
(
)
SKIP−LIMIT LOAD
V
V
OUT
IN
OUT
t
=
OFF2
V
= R
×I
LOAD L
OUT
2xI
LOAD
where R
is the equivalent load resistor value.
LOAD
Finally, frequency in skip mode is:
1
Combining the above two relationships, the power mod-
ulator’s transfer function in terms of VOUT with respect
to VCOMP is:
f
=
SKIP
t
+ t
+ t
OFF1 OFF2
ON
V
R
×I
LOAD L
OUT
Output ripple in skip mode is:
=
= R
× G
LOAD MOD
V
I
L
COMP
V
= V
+ V
OUT−RIPPLE
COUT−RIPPLE
− I
ESR−RIPPLE
G
MOD
I
x t
(
)
SKIP−LIMIT
LOAD
ON
The peak current-mode controller’s modulator gain
is attenuated by the equivalent divider ratio of the
load resistance and the current-loop gain’s impedance.
=
C
OUT
+ R
x I
(
− I
LOAD
)
ESR,COUT
SKIP−LIMIT
G
becomes:
MOD
L x I
SKIP−LIMIT
1
V
=
+ R
OUT−RIPPLE
ESR,COUT
G
DC = g
×
(
)
C
x V − V
MOD
MC
(
)
)
OUT
IN
OUT
R
f
LOAD
1+
× K × 1− D − 0.5
(
)
S
x I
(
− I
×L
SKIP−LIMIT
LOAD
SW
To limit output ripple in skip mode, size C
based on
where R
= V
I
, f
is the switching
OUT
LOAD
OUT/ OUT(MAX) SW
the above formula. All the above calculations are appli-
cable only in skip mode.
frequency, L is the output inductance, D is the duty cycle
(V /V ), and K is a slope compensation factor cal-
OUT IN
S
culated from the following equation:
Compensation Design Guidelines
The MAX15053 uses a fixed-frequency, peak-current-mode
control scheme to provide easy compensation and fast
transient response. The inductor peak current is monitored
on a cycle-by-cycle basis and compared to the COMP
voltage (output of the voltage error amplifier). The regula-
tor’s duty cycle is modulated based on the inductor’s peak
current value. This cycle-by-cycle control of the inductor
current emulates a controlled current source. As a result,
S
V
× f
×L ×g
MC
SLOPE
SLOPE SW
K
=1+
=1+
S
S
V
− V
(
)
N
IN OUT
where:
V
SLOPE
S
=
= V
× f
SLOPE
SLOPE SW
t
SW
V
(
− V
OUT
)
IN
S
=
N
L ×g
MC
______________________________________________________________________________________ 15
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
1ST ASYMPTOTE
R2 × (R1 + R2) × 10
-1
A
(dB)/20
-1 -1
VEA
× g × R
MC
× {1 + R
× [K × (1 - D) - 0.5] × (L × f
) }
LOAD
LOAD
S
SW
2ND ASYMPTOTE
-1
-1
-1 -1
R2 × (R1 + R2) × g × (2GC ) × g × R
× {1 + R
× [K × (1 - D) - 0.5] × (L × f
) }
MV
C
MC
LOAD
LOAD
S
SW
GAIN
3RD ASYMPTOTE
-1
-1
-1 -1
R2 × (R1 + R2) × g × (2GC ) × g × R
× {1 + R
× [K × (1 - D) - 0.5] × (L × f
) } ×
MV
-1
C
MC
LOAD
LOAD
-1 -1 -1
S
SW
(2GC
× {R
+ [K × (1 - D) - 0.5] × (L × f
) } )
OUT
LOAD
S
SW
4TH ASYMPTOTE
-1
-1 -1
R2 × (R1 + R2) × g × R × g × R
× {1 + R
× [K × (1 - D) - 0.5] × (L × f
) } ×
SW
MV
C
MC
LOAD
LOAD
-1 -1 -1
S
-1
(2πC
× {R
+ [K × (1 - D) - 0.5] × (L × f
) } )
SW
OUT
LOAD
S
3RD POLE (DBL) 2ND ZERO
-1
0.5 × f
(2GC ESR)
SW
OUT
UNITY
FREQUENCY
1ST POLE
VEA
f
CO
A
(dB)/20
-1 -1
[2GC × (10
- g
MV
)]
C
2ND POLE
f
*
PMOD
5TH ASYMPTOTE
-1
-1 -1
R2 × (R1 + R2) × g × R × g × R
× {1 + R
× [K × (1 - D) - 0.5] × (L × f
SW
)
} ×
MV
-1
C
MC
LOAD
LOAD
}
S
1ST ZERO
(2GC R )
-1 -1 -1
2
-2
(2GC
× {R
+ [K × (1 - D) - 0.5] × (L × f
)
)
× (0.5 × f ) × (2Gf)
OUT
LOAD
S
SW
SW
-1
C
C
NOTE:
A
(dB)/20
VEA
-1
R
= 10
× g
MV
OUT
-1
-1 -1 -1
f
= [2GC
× (ESR + {R
+ [K × (1 - D) - 0.5] × (L × f
) } )]
SW
PMOD
OUT
LOAD
S
6TH ASYMPTOTE
-1
-1 -1
R2 × (R1 + R2) × g × R × g × R
× {1 + R
) } × (0.5 × f ) × (2Gf)
SW SW
× [K × (1 - D) - 0.5] × (L × f
) } ×
MV
C
MC
LOAD
LOAD
S
SW
WHICH FOR
ESR << {R
-1
-1 -1
2
-2
ESR × {R
+ [K × (1 - D) - 0.5] × (L × f
LOAD
S
-1
-1 -1
+ [K × (1 - D) - 0.5] × (L × f
S
) }
LOAD
SW
BECOMES
-1
-1
-1 -1 -1
f
f
= [2GC
= (2GC
× {R
+ [K × (1 - D) - 0.5] × (L × f
) } ]
PMOD
PMOD
OUT
OUT
LOAD
)
S
SW
-1
× R
LOAD
+ [K × (1 - D) - 0.5] × (2GC
× L × f
)
S
OUT
SW
Figure 3. Asymptotic Loop Response of Current-Mode Regulator
As previously mentioned, the power modulator’s domi-
nant pole is a function of the parallel effects of the load
resistance and the current-loop gain’s equivalent imped-
ance:
which can be expressed as:
1
K × 1− D − 0.5
(
)
S
f
≈
+
PMOD
2π ×C
×R
2π × f
×L × C
OUT
LOAD
SW
OUT
1
Note: Depending on the application’s specifics, the
amplitude of the slope compensation ramp could have
a significant impact on the modulator’s dominate pole.
For low duty-cycle applications, it provides additional
damping (phase lag) at/near the crossover frequency
(see the Closing the Loop: Designing the Compensation
Circuitry section). There is no equivalent effect on the
f
=
PMOD
−1
K × 1− D − 0.5
(
)
1
S
2π × C
× ESR +
+
OUT
R
f
×L
LOAD
SW
And knowing that the ESR is typically much smaller than
the parallel combination of the load and the current loop:
power modulator zero, f
.
ZMOD
−1
K × 1− D − 0.5
(
)
1
S
ESR <<
+
1
f
= f
=
R
f
×L
ZMOD
ZESR
LOAD
SW
2π × C
×ESR
OUT
1
f
≈
PMOD
−1
K × 1− D − 0.5
(
)
1
S
2π ×C
×
+
OUT
R
f
×L
LOAD
SW
16 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
The effect of the inner current loop at higher frequen-
cies is modeled as a double-pole (complex conjugate)
The dominant poles and zeros of the transfer loop gain
are shown below:
frequency term, G
(s), as shown:
SAMPLING
g
MV
(dB)/20
f
=
P1
A
VEA
1
2π ×10
× C
C
G
s =
( )
2
SAMPLING
1
s
s
f =
P2
+
+1
K × 1−D −0.5
2
(
)
×L
1
π × f
SW
)
× Q
C
S
−1
π × f
(
2π × C
+
SW
OUT
R
f
LOAD
SW
where the sampling effect quality factor, Q , is:
C
1
2
f
=
f
(
)
P3
SW
1
Q
=
1
C
f
=
π × K × 1− D − 0.5
(
)
Z1
S
2π × C R
C
C
1
And the resonant frequency is:
f
=
Z2
2π × C
ESR
OUT
ω
(s) = π × f
SAMPLING SW
The order of pole-zero occurrence is:
< f ≤ f < f ≤ f < f
Z2
or:
f
SW
2
f
f
=
P1 P2
Z1 CO
P3
SAMPLING
Under heavy load, f , approaches f . Figure 3 shows
P2
Z1
Having defined the power modulator’s transfer function,
the total system transfer can be written as follows (see
Figure 3):
a graphical representation of the asymptotic system
closed-loop response, including dominant pole and zero
locations.
Gain(s) = G (s) × G (s) × G
(DC) × G
(s) ×
FILTER
FF
EA
MOD
The loop response’s fourth asymptote (in bold, Figure 3)
is the one of interest in establishing the desired cross-
over frequency (and determining the compensation
component values). A lower crossover frequency pro-
vides for stable closed-loop operation at the expense of
a slower load- and line-transient response. Increasing
the crossover frequency improves the transient response
at the (potential) cost of system instability. A standard
rule of thumb sets the crossover frequency between
1/10 and 1/5 of the switching frequency. First, select
the passive power and decoupling components that
meet the application’s requirements. Then, choose the
small-signal compensation components to achieve the
desired closed-loop frequency response and phase
margin as outlined in the Closing the Loop: Designing
the Compensation Circuitry section.
G
(s)
SAMPLING
where:
sC R1+1
(
)
)
R2
R1+ R2
FF
G
s =
( )
×
FF
sC R1||R2 +1
(
FF
Leaving C empty, G (s) becomes:
FF FF
R2
R1+ R2
G
s =
( )
FF
Also:
G
sC R +1
(
)
A
(dB)/20
C C
A
VEA
s = 10
( )
×
EA
(dB)/20
VEA
10
sC
R
+
+1
C
C
g
MV
which simplifies to:
sC R + 1
(
)
A
(dB)/20
C C
Closing the Loop: Designing the
Compensation Circuitry
VEA
G
s = 10
( )
×
EA
A
(dB)/20
VEA
10
sC
+1
C
1) Select the desired crossover frequency. Choose f
CO
g
MV
approximately 1/10 to 1/5 of the switching frequency
(f ).
SW
A
(dB)/20
VEA
10
when R <<
C
2) Determine R by setting the system transfer’s fourth
C
g
MV
asymptote gain equal to unity (assuming f
> f
,
CO
Z1
f
, and f ) where:
P2
P1
sC
ESR +1
(
)
OUT
G
s = R
( )
×
LOAD
FILTER
−1
K × 1− D − 0.5
(
)
1
S
sC
+
+1
OUT
R
f
× L
LOAD
SW
______________________________________________________________________________________ 17
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
R
K 1− D − 0.5
(
)
LOAD
S
Using C the zero-pole order is adjusted as follows:
FF
1+
L × f
SW
R1+ R2
R2
1
1
R
=
×
×2πf
C
×
C
CO OUT
f
< f ≤ f
<
<
≈
P1 P2 Z1
g
×g
×R
MV
MC
LOAD
2πC R1 2πC (R1||R2)
FF FF
f
≤ f < f
P3 Z2
CO
1
Confirm the desired operation of C empirically. The
FF
phase lead of C diminishes as the output voltage is
a smaller multiple of the reference voltage, e.g., below
about 1V. Do not use C when V
ESR +
K 1− D − 0.5
(
)
1
FF
S
+
R
L × f
LOAD
SW
= V .
FB
FF
OUT
and where the ESR is much smaller than the parallel
combination of the equivalent load resistance and the
current loop impedance, e.g.,:
Setting the Soft-Start Time
The soft-start feature ramps up the output voltage slowly,
reducing input inrush current during startup. Size the
C
using:
capacitor to achieve the desired soft-start time, t
SS
SS,
1
ESR <<
K 1− D − 0.5
(
)
1
S
I
× t
SS
SS
FB
+
C
=
SS
R
L × f
LOAD
SW
V
R
C
becomes:
I
, the soft-start current, is 10FA (typ) and V , the
SS FB
output feedback voltage threshold, is 0.6V (typ). When
using large C capacitance values, the high-side
2πf
g
× C
× g
R1+ R2
R2
CO
MV
OUT
MC
R
=
×
OUT
C
current limit can trigger during the soft-start period. To
ensure the correct soft-start time, t , choose C large
SS
SS
3) Determine C by selecting the desired first sys-
C
enough to satisfy:
tem zero, f , based on the desired phase margin.
Typically, setting f below 1/5 of f
Z1
V
×I
provides suf-
Z1
CO
OUT SS
− I
C
>> C
×
OUT
SS
ficient phase margin.
(I
)× V
OUT FB
HSCL
f
1
I
is the typical high-side MOSFET current-limit
HSCL
CO
5
f
=
≤
Z1
value.
2π × C R
C C
An external tracking reference with steady-state value
between 0V and V - 1.8V can be applied to SS/REFIN.
IN
therefore:
In this case, connect an RC network from external track-
ing reference and SS/REFIN, as shown in Figure 4. The
5
C
≥
C
2π × f
×R
CO
C
recommended value for R
is approximately 1kI.
SS
R
is needed to ensure that, during hiccup period,
SS
4) For low duty-cycle applications, the addition of a
phase-leading capacitor (C in Figure 1) helps
SS/REFIN can be internally pulled down.
FF
mitigate the phase lag of the damped half-frequency
double pole. Adding a second zero near to but below
the desired crossover frequency increases both the
closed-loop phase margin and the regulator’s unity-
gain bandwidth (crossover frequency). Select the
capacitor as follows:
When an external reference is connected to SS/REFIN,
the soft-start must be provided externally.
R
SS
V
REF_EXT
SS/REFIN
1
C
=
FF
C
SS
2π × f
× R1||R2
(
)
CO
MAX15053
This guarantees the additional phase-leading zero
occurs at a frequency lower than f
from:
CO
1
Figure 4. RC Network for External Reference at SS/REFIN
f
=
PHASE_LEAD
2π × C ×R1
FF
18 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
INPUT
2.7V TO 5.5V
L
1µH
OUT
OUTPUT
1.8V AT 2A
IN
LX
C
IN
22µF
1.2I
C
R
OUT
PULL
22µF
20kI
R
C
100pF
1
MAX15053
FF
1nF
8.06kI
PGOOD
EN
GND
ON
FB
ENABLE
OFF
R
2
COMP
4.02kI
SKIP
R
C
2.32kI
SS/REFIN
C
22nF
SS
C
3.3nF
C
Figure 5. Application Circuit for PWM Mode Operation
2) Place capacitors on IN and SS/REFIN as close as
possible to the IC and the corresponding pad using
direct traces.
Power Dissipation
The MAX15053 is available in a 9-bump WLP package
and can dissipate up to 1127mW at T = +70NC. When
A
the die temperature exceeds +150NC, the thermal-shut-
down protection is activated (see the Thermal-Shutdown
Protection section).
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current short
and minimize the loop area formed by LX, the output
capacitors, and the input capacitors.
Layout Procedure
Careful PCB layout is critical to achieve clean and stable
operation. It is highly recommended to duplicate the
MAX15053 Evaluation Kit layout for optimum perfor-
mance. If deviation is necessary, follow these guidelines
for good PCB layout:
4) Connect IN, LX, and GND separately to a large cop-
per area to help cool the IC to further improve effi-
ciency.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors and compensa-
tion components as close as possible to the IC.
1) Connect the signal and ground planes at a single
point immediately adjacent to the GND bump of the
IC.
6) Route high-speed switching nodes (such as LX)
away from sensitive analog areas (such as FB and
COMP).
______________________________________________________________________________________ 19
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
INPUT
2.7V TO 5.5V
L
1µH
OUT
OUTPUT
1.8V AT 2A
IN
LX
C
IN
22µF
1.2I
C
R
OUT
PULL
22µF
20kI
R
C
100pF
1
MAX15053
FF
1nF
8.06kI
PGOOD
EN
GND
ON
FB
ENABLE
OFF
R
2
COMP
4.02kI
SKIP
R
C
2.32kI
SS/REFIN
C
22nF
SS
C
3.3nF
C
Figure 6. Application Circuit for Skip Mode Operation
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE OUTLINE
LAND
PATTERN NO.
CODE
NO.
Refer to
Application
Note 1891
9 WLP
W91E1Z+1
21-0508
20 _____________________________________________________________________________________
High-Efficiency, 2A, Current-Mode
Synchronous, Step-Down Switching Regulator
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
5/10
Initial release
—
—
3/11
Revised Package Information section.
Changed the 1.65mm x 1.65mm, 9-bump package information to 1.5mm x 1.5mm,
9-bump package information. Inserted Typical Operating Circuit on page one.
2
7/11
1, 11
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
21
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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