MAX15301EVKITHP [MAXIM]
Pin-Strap or PMBus Configuration;型号: | MAX15301EVKITHP |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Pin-Strap or PMBus Configuration |
文件: | 总32页 (文件大小:1458K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
General Description
Benefits and Features
● InTune Automatic Compensation Ensures Stability
The MAX15301AA02 is a full-featured, highly efficient,
digital point-of-load (PoL) controller with advanced power
management and telemetry features. Unlike PID-based
digital power regulators, the MAX15301AA02 uses
Maxim’s patented InTune™ automatically compensated,
state-space control algorithm. The InTune control law
is valid for both the small- and large-signal response
and accounts for duty-cycle saturation effects. These
capabilities result in fast loop transient response and
reduce the number of output capacitors compared to com-
peting digital controllers.
While Optimizing Transient Performance
● State-Space Compensation Results in Fast Transient
Response with Reduced Output Capacitance
● Differential Remote Voltage Sensing Enables ±1%
V
OUT
Accuracy over Temperature (-40°C to +85°C)
● PMBus Interface for Configuration, Control, and
Monitoring
● Supports Voltage Positioning
● High Output 2A/4A MOSFET Driver
• Adjustable Nonoverlap Timing
• Variable Gate-Drive Voltage
The MAX15301AA02 includes multiple features to
optimize efficiency. An internal switch BabyBuck™
regulator generates the gate drive and the internal
bias supplies for the controller with low power loss.
An advanced, high-efficiency MOSFET gate driver has
adjustable nonoverlap timing and load-variable gate-drive
voltage to minimize switching losses over the full range of
voltage, current, and temperature.
● Wide Input Range of 4.5V to 14V
● Efficient On-Chip BabyBuck Regulator for Self-Bias
● Output Voltage Range from 0.5V to 5.25V
● Startup into a Prebiased Output
The MAX15301AA02 was designed for end-customer’s
design environment. An on-board PMBus™-compliant
serial bus interface enables communication with a super-
visory controller for monitoring and fault management. A
full suite of power management features eliminates the
need for complicated and expensive sequencing and
monitoring ICs. Basic DC-DC conversion operation can
be set up via pin strapping and does not require user
configuration firmware. This allows for rapid develop-
ment of the power-supply subsystem before board-
level systems engineering is completed. Maxim provides
support hardware and software for configuring the IC.
● Configurable Soft-Start and Soft-Stop Time
● Fixed-Frequency Operation and Synchronization
● Flexible Sequencing and Fault Management
● Pin-Strappable Configuration
• Output Voltage, SMBus Address, Switching
Frequency, Current Limit
● Out-of-the-Box Operation Enables Fast Prototyping
Applications
● Servers
● Storage Systems
● Routers/Switches
● Base-Station Equipment
● Power Modules
The MAX15301AA02 is available in a 32-lead, 5mm x
5mm TQFN package and operates over the -40°C to
+85°C temperature range.
InTune and BabyBuck are trademarks of Maxim Integrated
Products, Inc.
PMBus is a trademark of SMIF, Inc.
Maxim patents apply: 7498781, 7880454, 7696736, 7746048,
7466254, 7986135, 7498781, 8,120,401, 8,014,879.
This product is subject to a license from Power-One, Inc.,
related to digital power technology patents owned by Power-
One, Inc. This license does not extend to merchant market
stand-alone power-supply products.
Ordering Information and Typical Operating Circuit appear
at end of data sheet.
19-7508; Rev 0; 2/15
MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Absolute Maximum Ratings
INSNS to SGND....................................................-0.3V to +14V
LXSNS to SGND......................................................-2V to +14V
LXSNS (pulse < 10ns) to SGND..............................-2V to +20V
OUTP, OUTN, DCRP, DCRN to SGND................-0.3V to +5.5V
PWR to PGND.......................................................-0.3V to +18V
3P3 to SGND................................. -0.3V to the minimum of +4V
1P8 to DGND .......................................................-0.3V to +2.2V
CIO, SET, PG, ADDR0, ADDR1, SYNC, TEMPX,
SALRT to DGND…..............................................-0.3V to +4V
EN, SCL, SDA to DGND .........................................-0.3V to +4V
PGND to SGND....................................................-0.3V to +0.3V
DGND to SGND ...................................................-0.3V to +0.3V
Electrostatic Discharge (ESD) Rating
or (V
+ 0.3V)
GDRV
GDRV to SGND........................... -0.3V to the minimum of +12V
Human Body Model (HBM) .........................................±3500V
Machine Model ..............................................................±200V
Junction Temperature......................................................+125°C
Operating Temperature Range........................... -40°C to +85°C
or (V
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
+ 0.3V)
PWR
LX to PGND........-2V to the minimum of +26V or (V
BST
DL to PGND ......................................... -0.3V to (V
GDRV
LBI to PGND...........................................-0.3V to (V
Continuous Power Dissipation (T = +70°C)
PWR
A
LBO to PGND...........................(V
- 0.3V) to (V
TQFN (derate 34.5mW/°C above +70°C)..................2758mW
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow).......................................+260°C
3P3
GDRV
DH to PGND................................. (V - 0.3V) to (V
LX
BST
BST to LX..............................................................-0.3V to +12V
BST to PGND........................................................-0.3V to +26V
BST to GDRV........................................................-0.3V to +26V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
TQFN
Junction-to-Ambient Thermal Resistance (θ ) ..........29°C/W
Junction-to-Case Thermal Resistance (θ )..................1.7°C/W
JC
JA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(All settings = factory default, V
= V
= 12V, V
= V
= V
= 0V, V
= 1.2V, f
= 600kHz. Specifications are
PWR
INSNS
SGND
DGND
PGND
OUT
SW
for T = T = -40°C to +85°C, typical values are at T = T = +25°C. See the Typical Operating Circuit, unless otherwise noted.)(Note 2)
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLY
Input Voltage Range
V
4.5
14
V
PWR
BabyBuck bias supply, driver not
switching
10
24
Input Supply Current
I
mA
PWR
Linear mode bias supply, driver not
switching
50
Input Overvoltage Lockout
Threshold
V
V
Input rising
14.3
3.8
15.2
16.0
4.4
V
V
OVLO(PWR)
Rising edge
Hysteresis
4.1
Input Undervoltage Lockout
Threshold
UVLO(PWR)
0.24
BIAS REGULATORS
3P3 Output Voltage
1P8 Output Voltage
V
V
I
I
= 0mA
= 0mA
3.3
V
V
3P3
LOAD(3P3)
LOAD(1P8)
1.80
1P8
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Electrical Characteristics (continued)
(All settings = factory default, V
= V
= 12V, V
= V
= V
= 0V, V
= 1.2V, f
= 600kHz. Specifications are
PWR
INSNS
SGND
DGND
PGND
OUT
SW
for T = T = -40°C to +85°C, typical values are at T = T = +25°C. See the Typical Operating Circuit, unless otherwise noted.)(Note 2)
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STARTUP/SHUTDOWN TIMING
Firmware Initialization
From V > V
enable (Figure 2)
, until ready to
IN
UVLO(PWR)
t
t
25
ms
ms
ms
ms
1
2
3
Minimum Programmable
(Figure 2, Note 10)
1
1
t
ON_DELAY
Minimum Programmable
t
(Figure 2, Note 10)
t
ON_RISE
From V
= V
command to assertion
OUT
OUT
Adaptive Tuning Time
OUTPUT VOLTAGE
Output Voltage Range
t
12
4
of power good (PG) (Figure 2)
Measured from OUTP to OUTN
(Notes 5 and 10)
V
0.5
5.25
V
OUT
LX Bias Current
I
Not switching, current out of device pin
(Notes 3 and 4)
200
µA
%
LX
Duty-Cycle Range
5
-0.5
-1
95
+0.5
+1
T
= +25°C, I
≤ 20A (Notes 4, 8, 9)
A
OUT
Regulation Set-Point
Accuracy (Note 4)
%
-40°C ≤ T ≤ +85°C (Notes 4, 8, 9)
A
I
Current flowing into OUTP
Current flowing out of OUTN
50
35
120
4
µA
µA
nA
µA
OUTP
OUTN
DCRP
DCRN
V
Sense Bias Current
OUT
I
I
Current flowing into DCR,
DCR Sense Bias Current
V
- V
= 150mV
DCRP
DCRN
I
PWM CLOCK (Note 4)
Switching Frequency Range
f
(Note 10)
300
-5
1000
+5
kHz
%
SW
Switching Frequency
Set-Point Accuracy
External Clock-to-SYNC
Frequency Range
f
300
1000
kHz
%
SYNC
Minimum Allowable SYNC
Duty-Cycle Range
40
60
Maximum Allowable SYNC
Duty Cycle
%
PROTECTION (Note 4)
Overcurrent Fault Threshold
Accuracy
T
= +25°C, exclusive of sensor error
±3
115
85
%
%
A
Output Overvoltage-Fault
Threshold
Output rising
Output falling
V
V
OUT
%
Output Undervoltage-Fault
Threshold
OUT
Thermal-Shutdown Threshold
Accuracy
±20
°C
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Electrical Characteristics (continued)
(All settings = factory default, V
= V
= 12V, V
= V
= V
= 0V, V
= 1.2V, f
= 600kHz. Specifications are
PWR
INSNS
SGND
DGND
PGND
OUT
SW
for T = T = -40°C to +85°C, typical values are at T = T = +25°C. See the Typical Operating Circuit, unless otherwise noted.)(Note 2)
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Thermal-Shutdown
Hysteresis
20
°C
V
rising
90
85
OUT
%
Power-Good Threshold
V
OUT
V
falling
OUT
STARTUP/SHUTDOWN TIMING
From V > V
enable (Figure 2)
, until ready to
IN
UVLO(PWR)
Firmware Initialization
t
t
25
ms
ms
1
2
Minimum delay (Figure 2, Note 4)
Maximum delay (Figure 2, Note 4)
1
TON_DELAY, TOFF_DELAY
Range
145
TON_DELAY, TOFF DELAY
Resolution
Delay timing step size
0.6
ms
ms
ms
TON_DELAY, TOFF DELAY
Command Accuracy
(Note 10)
Command value sent vs. readback
±0.3
TON_DELAY, TOFF DELAY
Timing Accuracy
Command readback value vs. actual delay
time
±0.8
1
Minimum (Figure 2, Note 4)
Maximum (Figure 2, Note 4)
TON_RISE, TOFF_FALL
Range
t
ms
3
255 x t
RR
TON_RISE, TOFF_FALL
Resolution
Ramp timing step size (varies with VOUT_
COMMAND)
t
0.4 -1.0
ms
ms
µs
RR
TON_RISE, TOFF_FALL
Command Accuracy
(Note 10)
Command value sent vs. readback
±0.5
TON_RISE, TOFF_FALL
Timing Accuracy
Command readback value vs. actual ramp
duration
±10
12
From end of soft-start ramp to PG assertion
(varies with FREQUENCY_SWITCH
(Figure 2)
Adaptive Tuning Time
t
ms
°C
4
External
Internal
±5
±5
Temperature-Measurement
Accuracy
DIGITAL I/O
Power-Good Logic-High
Leakage Current
Open-drain output mode, open-drain
10
µA
connected to 5.5V, V
= 3.3V
3P3
Output Logic-High
Output Logic-Low
Input Bias Current
Rise/Fall Slew Rate
CMOS mode, I
= 4mA
V
- 0.4
V
3P3
V
V
SOURCE
3P3
I
= 4mA
0.4
+1
SINK
-1
µA
ns
C
= 15pF
2
LOAD
EN, SYNC Input Logic-Low
Voltage
Input voltage falling
0.8
V
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Electrical Characteristics (continued)
(All settings = factory default, V
= V
= 12V, V
= V
= V
= 0V, V
= 1.2V, f
= 600kHz. Specifications are
PWR
INSNS
SGND
DGND
PGND
OUT
SW
for T = T = -40°C to +85°C, typical values are at T = T = +25°C. See the Typical Operating Circuit, unless otherwise noted.)(Note 2)
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EN, SYNC Input Logic- High
Voltage
Input voltage rising
2
V
EN, SYNC Input Leakage
Current
-10
+10
0.8
µA
SMBus (Note 4)
SDA, SCL Input Logic-Low
Voltage
Input voltage falling
Input voltage rising
V
V
SDA, SCL Input Logic-High
Voltage
2
SDA, SCL, SALRT Logic-
High Leakage Current
V
, V
= 0V, and V
tested at
SCL SDA
SALRT
10
µA
0V and 3.3V
SDA, SCL, SALRT Logic-Low
Output Voltage
I
= 4mA
0.4
V
SINK
PMBus Operating Frequency
f
400
kHz
µs
SMB
Bus Free Time
(STOP - START)
t
1.3
0.6
0.6
0.6
BUF
START Condition Hold Time
from SCL
t
µs
µs
µs
HD:STA
START Condition Setup Time
from SCL
t
SU:STA
STOP Condition Setup Time
from SCL
t
SU:STO
SDA Hold Time from SCL
SDA Setup Time from SCL
SCL Low Period
t
300
100
1.3
0.6
ns
ns
µs
µs
HD:DAT
t
SU:DAT
t
LOW
SCL High Period
t
HIGH
DRIVER BIAS REGULATOR
GCTRLDAC = 0
GCTRLDAC = 15
5.2
8.7
GDRV Output Voltage Range
V
V
GDRV
GDRV Undervoltage Lockout
LBI, LBO Current Limit
HIGH-SIDE DRIVER
Driver Source Current
Driver Sink Current
V
GDRV falling, 200mV (typ) hysteresis
3.5
3.75
0.7
V
A
GDRVUVLO
I
V
V
= 12V, V
= 12V, V
= 0V, 3.0nF load
= 0V, 3.0nF load
2
4
A
A
DH_SOURCE
PWR
DH
I
DH_SINK
PWR
DH
DH Driver On-Resistance
(Sourcing)
R
V
= 12V, V
- V forced to 5V
1
Ω
Ω
ON(DH)
ON(DH)
PWR
PWR
BST
BST
LX
DH Driver On-Resistance
(Sinking)
R
V
= 12V, V
- V forced to 5V
0.4
LX
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Electrical Characteristics (continued)
(All settings = factory default, V
= V
= 12V, V
= V
= V
= 0V, V
= 1.2V, f
= 600kHz. Specifications are
PWR
INSNS
SGND
DGND
PGND
OUT
SW
for T = T = -40°C to +85°C, typical values are at T = T = +25°C. See the Typical Operating Circuit, unless otherwise noted.)(Note 2)
A
J
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LOW-SIDE DRIVER
Driver Source Current
Driver Sink Current
I
V
= 12V, V = 0V, 5.0nF load
2
4
A
A
DL_SOURCE
PWR
DL
I
V
V
= 12V, V = 5V, 5.0nF load
DL
DL_SINK
PWR
DL Driver On-Resistance
(Sourcing)
R
= 12V, V - V
forced to 5V
forced to 5V
1
Ω
Ω
ON(DL)
ON(DL)
PWR
LX
PGND
DL Driver On-Resistance
(Sinking)
R
V
= 12V, V - V
0.4
PWR
LX
PGND
DRIVER TIMING AND RESISTANCE
t
Falling, 5.0nF load, V
= 5V
= 5V
= 5V
= 5V
10
15
8
F_DL
R_DL
F_DH
R_DH
GDRV
DL Transition Time
ns
ns
t
Rising, 5.0nF load, V
Falling, 3.0nF load, V
GDRV
t
GDRV
GDRV
DH Transition Time
t
Rising, 3.0nF load, V
10
DH Driver Pulldown
Resistance
R
Not switching, V
Not switching, V
= 0V
100
100
300
300
kΩ
kΩ
Ω
PD(DH)
EN
EN
DL Driver Pulldown
Resistance
R
= 0V
= V = V
PGND
PD(DL)
V
= 5V, V
DH
GDRV
LX
Boost On-Resistance
R
1.5
ON(BST)
(pulldown state), I
= 10mA
BST
THERMAL PROTECTION
Gate-Driver Thermal
Shutdown Threshold
T
Hysteresis = 20°C
150
°C
SHDN
Note 2: Limits are 100% production tested at T = +25°C. Maximum and minimum limits over temperature are guaranteed through
A
correlation using statistical quality control (SQC) methods. Typical values are expressed as factory-default values also for
configurable specifications within a range.
Note 3: Can go to 100% during a transient.
Note 4: Design guaranteed by bench characterization. Limits are not production tested.
Note 5: The settable output voltage range is 0.6V to 5.0V. This range expands to 0.5V to 5.25V when the voltage margining
function is enabled.
Note 6: Once the MAX15301AA02 locks onto an external synchronizing clock, the tolerance on the capture range is ±10%.
Note 7: See the Voltage Tracking section.
Note 8: Excluding tracking mode.
Note 9: Voltage regulation accuracy is power-stage dependent; adherence to all data sheet design recommendations is required to
achieve specified accuracy.
Note 10: Customer-programmable parameters.
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Typical Operating Characteristics
(T = +25°C, V = 12V, V
= 1.2V, f
= 600kHz, unless otherwise noted. See the Typical Operating Circuit and Application 1 in
A
IN
OUT
SW
Table 8).
GDRV VOLTAGE
vs. GCTRLDAC SETTING
VARIABLE GATE-DRIVE
EFFICIENCY GAIN
90.0
87.5
85.0
82.5
80.0
77.5
75.0
10
9
VARIABLE GATE DRIVE
8.5V DRIVE
8
7
5.0V DRIVE
6
5
4
0
5
10 15 20 25 30 35 40 45
LOAD CURRENT (A)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
GCTRLDAC VALUE
EFFICIENCY vs. LOAD
(V = 12V, 600kHz)
IN
BABYBUCK EFFICIENCY GAIN
(V = 12V, V = 1.2V, 500kHz)
IN
OUT
100
90
80
70
60
50
40
30
20
10
0
95.0
94.0
93.0
92.0
91.0
90.0
89.0
88.0
87.0
86.0
85.0
84.0
83.0
82.0
81.0
80.0
BABYBUCK
LDO MODE
V
(V)
1.2
2.5
3.3
OUT
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
0
5
10
15
20
25
30
I
(A)
LOAD CURRENT (A)
OUT
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Typical Operating Characteristics (continued)
(T = +25°C, V = 12V, V
= 1.2V, f = 600kHz, unless otherwise noted. See the Typical Operating Circuit and Application 1 in
SW
A
IN
OUT
Table 8).
STARTUP
SHUTDOWN
MAX15301 toc05
MAX15301 toc06
V
OUT
500mV/div
V
500mV/div
5V/div
OUT
PG
EN
5V/div
5V/div
PG
EN
5V/div
V
10V/div
V
10V/div
IN
IN
4ms/div
4ms/div
OUTPUT-VOLTAGE RIPPLE
(VOUT = 3.3V)
OUTPUT-VOLTAGE RIPPLE
(VOUT = 1.2V)
toc08
toc07
20mV/div (AC-
COUPLED)
20mV/div (AC-
COUPLED)
VOUT
VOUT
20µs/div
20µs/div
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
16
15
3P3 25
OUTN 26
LX
DH
14 LXSNS
27
28
29
30
31
32
OUTP
I.C.
INSNS
EN
13
12
MAX15301AA02
I.C.
11 SDA
DCRP
DCRN
PG
EP
SGND
10
9
SCL
+
SALRT
1
2
3
4
5
6
7
8
TQFN
Pin Description
PIN
NAME
FUNCTION
External Switching Frequency Synchronization Input. Connect a resistor between SYNC and SGND to
set the switching frequency of the DC-DC converter (see Table 2). The MAX15301 can also synchronize
with an external clock applied at SYNC.
1
SYNC
2
3
ADDR0
SET
SMBus Address Select Input 0. Used with ADDR1 to assign a unique SMBus address to the device.
Output Voltage Set Input. Connect a resistor between SET and SGND to set the output voltage. Shorting
this pin to ground selects tracking mode (see Table 1).
SMBus Address Select Input 1. Used with ADDR0 to assign a unique SMBus address to the device and
set the current limit for MAX15301.
4
5
ADDR1
DGND
Digital Ground. Connect to DGND and PGND using short, wide PCB traces.
Internal 1.8V Regulator Output. 1P8 is the supply rail for the internal digital circuitry. Bypass 1P8 to
DGND with a 10µF ceramic capacitor. This pin may not be used to power any circuitry external to the
MAX15301.
6
1P8
Connection for the External Temperature Sensor. Connect an npn transistor junction from TEMPX to
SGND to measure the temperature at any point on the PCB. Place a 100pF ceramic capacitor in parallel
with the temperature sense junction.
7
8
TEMPX
CIO
Configurable Input/Output Pin. This is a voltage-tracking input when SET is connected to SGND to select
tracking mode. CIO must be grounded when not in tracking mode.
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Pin Description (continued)
PIN
NAME
FUNCTION
SMBus Alert. Interrupt to the SMBus master. Open-drain output that pulls low when SMBus interaction is
required.
9
SALRT
10
11
SCL
SDA
SMBus Clock Input
SMBus Data Input/Output
Enable Input. Do not leave unconnected. By default, driving EN high enables output regulation, and
driving EN low disables output regulation.
12
13
EN
Powertrain Input Rail Sense. Monitors the input supply of the DC-DC converter. Connect a series 2kΩ
resistor between input rail and INSNS pin.
INSNS
14
15
16
LXSNS
DH
Connect to SGND
High-Side MOSFET Gate Drive
LX
Switching Node. Connect directly to the high-side of the output inductor.
Bootstrap Capacitor Connection. Connect a 0.22µF ceramic capacitor between BST and the switching
node.
17
BST
18
19
20
21
22
23
GDRV
DL
Gate-Driver Supply. Bypass GDRV to PGND with a 2.2µF ceramic capacitor.
Low-Side MOSFET Gate Drive
PGND
LBI
Power Ground. Connect to SGND and DGND using short wide PCB traces.
BabyBuck Switching Node 1. See the BabyBuck Regulator section for configurations.
Power-Supply Input. Connect to a power-supply input. Bypass to ground with a 1µF ceramic capacitor.
BabyBuck Switching Node 2. See the BabyBuck Regulator section for configurations.
PWR
LBO
Internal 3.3V Regulator Output. 3P3 is the supply rail for the internal analog circuitry. Bypass 3P3 to
SGND with a 4.7µF ceramic capacitor. This pin may not be used to power any circuitry external to the
MAX15301.
24, 25
3P3
26
27
OUTN
OUTP
I.C.
Output Voltage Differential Sense Negative Input. Connect to ground at the load.
Output Voltage Differential Sense Positive Input. Connect to the output at the load.
Internally Connected. Connect directly to ground near the MAX15301.
28, 29
Output Current Differential Sense Positive Input. Connect to the inductor or current-sense element
positive side through an appropriate filter network.
30
31
32
DCRP
DCRN
PG
Output Current Differential Sense Negative Input. Connect to the inductor or current-sense element
negative side.
Open-Drain Power-Good Indicator. PG asserts high when soft-start is complete, the voltage has reached
regulation, after a successful InTune calibration is completed.
Exposed Pad and Analog Ground. The EP serves two purposes: it is both the analog ground of
the device and a conduit for heat transfer. Connect to a large ground plane to maximize thermal
performance. See the PCB Layout Guidelines section.
EP
SGND
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Functional Diagram
LXSNS
INSNS
1.8V
REG
1P8
MAX15301AA02
3P3
OSC/
SYNC
THERMAL
PROTECTION
PWR
LBI
ADDR0
ADDR1
SET
SIDO
REG
LX
DETECT
LBO
GDRV
CIO
IO
AUX
ADC
BST
DH
MUX
SYNC
PG
TEMPX
DRIVER
LX
DPWM
DL
HSSP
PGND
NLSS COMPENSATOR
EN
MCU
DCRP
DCRN
ILIM
RAM
FLASH
FAULT
PROCESSOR
OUTP
OUTN
SCL
FB
ADC
SDA
PMBus
SOFT-START
SGND
SALRT
SGND
DGND
EP
BabyBuck bias regulators for biasing the internal circuit
blocks and the MOSFET gate drive.
Detailed Description
The MAX15301AA02 is an innovative, PMBus-
compliant, mixed-signal power-management IC with
a built-in high-performance digital PWM controller
for POL applications. The IC is based on Maxim’s
InTune automatically compensated digital PWM control
loop. The MAX15301AA02 has optimal partitioning of
the digital power-management and the digital power-
conversion domains to minimize startup times and
reduce bias current. The MAX15301AA02 supports
over 80 standard and manufacturer-specific PMBus
commands.
The MAX15301AA02 features integrated power conver-
sion to self-bias its digital, analog, and driver blocks from
a single input supply (V
). The IC relies on mixed-
PWR
signal design techniques to control the power system
efficiently and precisely. It does not require any software
to configure or initialize the device. In addition, functions
can be monitored and configured through the SMBus
interface using standard PMBus commands resulting in
ease of design and flexibility.
The control loop is separated from the housekeeping,
power monitoring, and fault management blocks. Control
loop parameters are stored in an on-chip nonvolatile flash
memory. An internal microcontroller enables monitoring
operating conditions using the SMBus interface. The
DPWM control loop is implemented using dedicated state
machines, there is no DSP or MCU in the control loop.
This partition allows for architecture that minimizes power
consumption while optimizing performance.
The IC uses adaptive compensation techniques to handle
a broad range of timing, voltage, current, temperature,
and external component parameter variations. Efficiency-
optimization techniques further enhance the performance
of the MAX15301AA02, including adjustable nonoverlap
timing, load-variable gate-drive voltage, and switch-mode
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
The Functional Diagram shows the controller implemen-
tation using a digital state space compensator (model
predictive) controller, a microcontroller unit (MCU), a
digital pulse-width modulator (DPWM), a PLL-based
cation. Upon output enable, or in response to a PMBus
command, the IC will perform the InTune calibration.
During this calibration several powertrain parameter
values are measured and the extracted parameters are
used to create the internal model to optimize the band-
width and transient response of the converter.
master timing generator, and
communication port.
a
PMBus serial
The state-space compensator block generates the duty-
cycle command for the DPWM block. The DPWM block
generates the required PWM outputs for the driver. The
state-space controller block also contains a digital-to-
analog converter that adjusts the gate-drive voltage. The
gate-drive voltage can be set using a PMBus command
(manufacturer specific) to a value between 5V and 8.5V
to improve the power-supply efficiency.
State-Space Controller and DPWM
The MAX15301AA02 uses a digital pulse-width modula-
tion (DPWM) control scheme to regulate the output volt-
age. Traditional PWM regulators (both analog and digital)
use classical control methods for DC-DC converters
based on linear models of a discrete time nature and root
locus, Bode and Nyquist plots. These linear time-invariant
approximations work well for small signals. However,
when large transients cause duty-cycle saturation, the
performance of the closed loop can be degraded (larger
overshoots) and the output transients will be “slower”
(large settling times). Tighter regulation performance
during these disturbances is becoming a requirement.
The IC addresses the issue by using model-predictive-
based feedback design to compensate the DPWM.
BabyBuck Regulator
The MAX15301AA02 has an internal BabyBuck bias
regulator circuit to generate both the gate-drive voltage
supply and the internal digital supply to power the control-
ler. The BabyBuck bias regulator is an internal two output
switching regulator that uses a small (1008-size), low-
cost inductor. If the user is not concerned with optimizing
operating efficiency, the inductor can be omitted from the
designs (connect the LBI pin to the PWR pin through a
100kΩ resistor). In this configuration, the bias regulator
operates as a linear regulator (LDO). If an external gate-
drive voltage is available, the LBI pin can be connected
The IC automatically constructs a state-space model
(state estimator) of the control plant (Figure 1). The inter-
nal model gives access to state control variables that are
otherwise unavailable. The state control variables are
used to set the proper control values. For a given input
to output step-down ratio and PWM switching frequency
the IC sets the compensation coefficients for that appli-
to V through a 2kΩ resistor and the GDRV pin can be
IN
connected to the external source.
V
IN
1/x
�
COMPENSATOR
DPWM
DRIVER
LOAD
A/D
STATE ESTIMATOR
Figure 1. State-Space Controller Concept
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
External Temperature Sense
Regulator Parameters
Key operating parameters in the MAX15301AA02, such
as output voltage, switching frequency, and current-sense
resistance, can be configured using resistors. This pro-
vides flexibility for the user while ensuring that the device
has a well-defined “out-of-the-box” operational state. The
pin configurations are only sampled when power is first
applied (the IC ignores changes to resistor settings after
power-up). From this initial operating state, it is possible
for the user to change the parameters using PMBus com-
mands. These changes can be stored in nonvolatile mem-
ory, and the device subsequently powers up in the newly
stored configuration state; however, it is recommended
that the pin-strap or resistor settings always be applied
with values chosen to provide a safe initial behavior prior
to PMBus configuration.
The MAX15301AA02 provides both an internal and
external temperature measurement. Both the internal
and external temperatures are reported to the user
through the PMBus READ_TEMPERATURE_1 and
READ_TEMPERATURE_2 commands, respectively. The
internal temperature is measured directly at the device
silicon junction. The external temperature is measured
through the TEMPX pin using the base-emitter junction
of a standard 2N3904 transistor. This technique is widely
employed because it requires no calibration of the sen-
sor; any PN junction can be used as a temperature sen-
sor. The 2N3904 and 2N2222 transistors and integrated
thermal diodes found in microprocessors, FPGAs, and
ASICs are commonly used temperature sensors. Connect
a 100pF filter capacitor, as shown in Figure 7, to ensure
accurate temperature measurements. When the 2N3904
is connected to the TEMPX pin, the device uses the
external temperature information for temperature-fault
and current-measurement temperature compensation
(tempco). If the external temperature measurement is
not used or measures out of range, the device uses the
internal temperature for temperature compensation and
thermal-fault protection. Disable the external tempera-
ture measurement by connecting TEMPX to ground. The
device’s temperature-fault thresholds are programmed
through the PMBus interface. The default value for
the thermal-shutdown threshold is +115°C. The default
overtemperature response is to shut down and restart
when the fault is no longer present. Note that a rising
temperature faults when it crosses the OT_FAULT_LIMIT
and clears when it falls below the OT_WARN_LIMIT.
The OT_WARN_LIMIT should always be set below the
OT_FAULT_LIMIT. The device shuts down and pulls PG
low when it acts on a temperature fault.
Pin-strap settings are programmed by connecting a
resistor from the appropriate IC pins to SGND. The
IC reads the resistance at startup and sets command
parameters per the tables in the following detail sections.
Note that the external parts count can be reduced in some
cases by unconnecting or grounding the configuration
pins.
Table 1. Output Voltage Setting Using Pin-
Resistor Setting
R
(kΩ)
OUTPUT VOLTAGE (V)
SET
0 to 4.3
5 to 5.2
Track mode
0.6
6.1 to 6.3
0.7
7 to 7.3
0.75
0.8
8.1 to 8.4
9.4 to 9.7
0.85
0.9
Regulation and Monitoring Functions
10.8 to 11.2
12.5 to 12.9
14.5 to 14.9
17.6 to 18
21.2 to 21.8
25.8 to 26.4
31.2 to 32
37.9 to 38.7
43.7 to 44.7
50.5 to 51.7
58.4 to 59.6
67.4 to Open
The MAX15301AA02 improves the reliability of the
system it powers with multiple circuits that protect the
regulator and the load from unexpected system faults.
The IC continuously monitors the input voltage, output
voltage and current, and internal/external temperatures.
The IC can be configured to provide alerts for specific
conditions of the monitored parameters. The thresholds
and responses for these parameters have factory-default
values, but can also be configured through the PMBus
interface. The status of the power supply can be queried
any time by a PMBus master.
0.95
1
1.05
1.1
1.2
1.5
1.8
2.5
3.3
5
0
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Table 2. Interleave Settings
Table 3. Switching Frequency Resistor
Settings (SYNC)
SMBus ADDRESS
xxxx000b
PHASE DELAY (°)
0
R
(kΩ)
SWITCHING FREQUENCY (kHz)
SYNC
xxxx001b
60
0 to 4.3
5 to 5.2
575
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
575
xxxx010b
120
180
240
300
90
xxxx011b
6.1 to 6.3
7 to 7.3
xxxx100b
xxxx101b
8.1 to 8.4
xxxx110b
9.4 to 9.7
xxxx111b
270
10.8 to 11.2
12.5 to 12.9
14.5 to 14.9
17.6 to 18
Output-Voltage Selection
The SET pin is used to establish the initial output voltage;
it can be pin strapped high or low, or connected to SGND
through a resistor to select the output voltage, as shown in
Table 1. Note that the SET pin is read once at power-up
and cannot be used to change the output voltage after that
time.
21.2 to 21.8
25.8 to 26.4
31.2 to 32
If the desired output voltage is not included in Table 1, use
a resistor to set the initial approximate output voltage, and
then send VOUT_COMMAND to set the exact desired
output voltage.
37.9 to 38.7
43.7 to 44.7
50.5 to 51.7
58.4 to Open
The output voltage can be set to any voltage between 0.5V
and 5.25V, including margining, provided the input voltage
to the DC-DC converter (V
voltage by an amount that conforms to the maximum duty-
cycle specification.
) is higher than the output
PWR
Table 3, or by sending the PMBus FREQUENCY_SWITCH
command. Note that the SYNC pin is read once at
power-up and cannot be used to change the switching
frequency after that time. The device considers open
circuit on SYNC to be a fault condition so it sets the switch-
ing frequency to 575kHz in an attempt to pick a switching
frequency typical of most applications; 575kHz is not a
normal pin-strappable frequency, so if the user reads back
a switching frequency of 575kHz, they know the SYNC
resistor is open circuited. The switching frequency can
be changed on-the-fly for frequencies between 300kHz to
475kHz and for frequencies between 476kHz to 1000kHz.
The switching frequency during operation must stay either
above or below 475kHz and should never cross this fre-
quency. Doing so may result in unexpected operation.
The user can cross the 475kHz switching boundary by
disabling the device, changing the switching frequency,
and then reenabling the device. As a guideline, lower fre-
quencies can be used to improve efficiency, while higher
frequencies can be selected to reduce the physical size
and value of the external filter inductor and capacitors.
The device’s output voltage can be dynamically changed
during operation through several PMBus commands. The
output voltage can be decreased during operation without
limit. The output voltage can be increased to 20% above
the upper end of the allowable voltage determined by
the RDIV setting. The RDIV setting is determined by the
programmed output voltage when the output is enabled.
Table 5 shows the voltage ranges that set each RDIV
setting. As an example, if the output voltage is pin
strapped to 1.4V, the RDIV is set to 0.65572 at startup.
The output voltage can be increased to 15% above the
upper end of the 0.65572 RDIV range, or 1.723V. The
output voltage can be programmed higher than 1.723V,
but the actual power-supply output can be clamped to a
lower voltage.
Setting the Switching Frequency
The switching frequency can be adjusted from 300kHz to
1MHz with an external resistor from SYNC to SGND per
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
applying power to the device, but must be applied prior to
enabling the device. The external clock frequency should
External Synchronization
The device can be synchronized with an external clock
to eliminate beat noise on the input- and output-voltage
lines or to minimize input-voltage ripple. Synchronization
is achieved by connecting a clock source to the SYNC
pin. The incoming clock signal must be in the 300kHz
to 1MHz range and must be stable with less than 10%
variation. The device synchronizes to the rising edge of
the clock after the device is enabled. In the event of a loss
of the external clock signal during normal operation after
successful synchronization with the external clock,
the device automatically switches at the frequency
programmed into the PMBus command’s FREQUENCY_
SWITCH variable. If an external clock is present at power-
on when the device is trying to read the SYNC pin-strap
resistance, the device cannot detect the synchronization
frequency and does not write the proper frequency into
FREQUENCY_SWITCH. However, if the clock is still
present at enable, the device reads the proper frequency
and overwrites FREQUENCY_SWITCH with the actual
clock frequency. If a clock is not present at power-on,
the device reads the pin-strap resistor value and writes
the frequency into FREQUENCY_SWITCH per Table 3.
If an external clock is applied to SYNC after power-on
but before enable, the device overwrites FREQUENCY_
SWITCH with the external clock frequency when the
device is enabled. If an external clock is not applied
prior to the device being enabled, the device keeps the
originally programmed FREQUENCY_SWITCH value.
Applying a clock to SYNC after the device is enabled
causes the IC to synchronize to the clock; however, the
FREQUENCY_SWITCH value is not updated. For proper
synchronization, the external clock can be applied prior to
not be changed after the device is enabled. The device
supports interleaving with an external SYNC input. The
default phase delay is pin strappable and is determined
by the 7-bit SMBus address, as shown in Table 2. The
phase delay can also be changed by sending the PMBus
INTERLEAVE command while the output is disabled. The
phase delay should not be changed during operation.
The programmed phase delay is between the rising edge
of the SYNC clock signal and the center of the device’s
PWM pulse. The center of the PWM pulse is used for a
reference point because the device’s PWM pulse is dual-
edge modulated.
IOUT_CAL_GAIN Selection
The device allows the user to set a default pin-strapped
IOUT_CAL_GAIN at startup. IOUT_CAL_GAIN is the
resistance of the current-sense element, which can
be either the power inductor’s DCR or a discrete cur-
rent-sense resistor. The device’s actual overcurrent trip
point is a function of IOUT_CAL_GAIN, the current-
sense element’s actual resistance, and the value of
the IOUT_OC_FAULT_LIMIT. See the output-overcurrent
protection paragraph for more information on setting the
overcurrent trip point. Setting IOUT_CAL_GAIN is accom-
plished by pin strapping, connecting a resistor from
ADDR1 to SGND, as listed in Table 4b. The user can
achieve a more accurate value of IOUT_CAL_GAIN by
setting this parameter through the PMBus. Note that
ADDR1 is used to set both the PMBus address and
IOUT_CAL_GAIN. The user should first determine the
desired PMBus address and then choose the appropriate
ADDR1 resistor per Table 4a and Table 4b.
ENABLED DURING INITIALIZATION
ENABLED AFTER INITIALIZATION
V
V
OUT
PG
EN
OUT
PG
EN
V
V
IN
IN
t1
t3 t4
10ms
t2
2ms
Figure 2. Startup Timing Diagrams
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Table 4a. SMBus Address Set by ADDR0, ADDR1 Resistor Connections
DCR
R
(kΩ)
ADDR1
0 to 4.3
9.4 to 9.7
5 to 5.2
6.1 to 6.3
12.5 to 12.9
31.2 to 32
7 to 7.3
8.1 to 8.4
17.6 to 18
0.4mW ➝
0.8mW ➝
1.2mW ➝
1.6mW ➝
2.0mW ➝
10.8 to 11.2
25.8 to 26.4
58.4 to 59.6
167.3 to 170.7
14.5 to 14.9
37.9 to 38.7
85.7 to 87.5
234.6 to 239.4
21.2 to 21.8
50.5 to 51.7
138.6 to 141.4
43.7 to 44.7
113.8 to 116.2
271.2 to Open
67.4 to 68.8
202.9 to 207.1
R
(kΩ)
SMBus 7-BIT DEVICE ADDRESS
ADDR0
0 to 4.3
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x7F
0x7F
5 to 5.2
6.1 to 6.3
7 to 7.3
8.1 to 8.4
9.4 to 9.7
10.8 to 11.2
12.5 to 12.9
14.5 to 14.9
17.6 to 18
21.2 to 21.8
25.8 to 26.4
31.2 to 32
37.9 to 38.7
43.7 to 44.7
50.5 to 51.7
58.4 to 59.6
67.4 to 68.8
85.7 to 87.5
113.8 to 116.2
138.6 to 141.4
167.3 to 170.7
202.9 to 207.1
234.6 to Open
Note: The SMBus specification recommends against using the shaded addresses.
Table 4b. IOUT_CAL_GAIN Set by ADDR1 Resistor Connection
R
(kΩ)
IOUT_CAL_GAIN (mΩ)
ADDR1
0 to 8.4
0.4
0.8
1.2
1.6
2.0
9.4 to 18
21.2 to 44.7
50.5 to 116.2
138.6 to Open
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Device Initialization
Internal Bias Regulators
The MAX15301AA02 includes power-on reset circuits that
monitor the internal bias supplies and the external supply
voltage. When all supplies are above their UVLO thresh-
olds, the following self-test sequence occurs:
The MAX15301AA02 analog circuitry is powered by an
internal 3.3V regulator (3P3). The IC also has an inter-
nal bias regulator to generate a 1.8V rail (1P8) to power
internal digital circuitry. Bypass the 3P3 pin to SGND with
a 4.7μF ceramic (X5R or better) capacitor. Bypass 1P8
to DGND with a 10μF ceramic (X5R or better) capaci-
tor. These internal regulators are not designed to power
external circuitry.
1) Run self test and CRC check on the memory.
2) Read resistor settings and set command values and
program working memory accordingly.
3) Confirm absence of any faults that would prevent turn-
on.
Input Voltage Feed-Forward
The MAX15301AA02 uses input voltage feed-forward
techniques to provide excellent line regulation. Connect
the INSNS pin to the powertrain input voltage through
a 2kΩ series resistor for input voltage feed-forward and
telemetry. The voltage at INSNS is sampled every 4μs.
4) Begin wait for a valid output enable condition (hard-
ware or PMBus command).
The power-up and initialization process takes approxi-
mately 25ms, depending upon the specific combination of
pin-strap resistor values to be read. The IC will not enable
output regulation until initialization is complete.
The IC does not enable DC-DC conversion if the voltage
at INSNS is below the PMBus VIN_UV_FAULT_LIMIT
threshold (default 4V) or below the VIN_ON, VIN_OFF
limits (default 6V rising and 5.5V falling, respectively.)
The user can read back the measured input voltage value
using the PMBus READ_VIN command.
Output-Voltage Sequencing
In a system with multiple MAX15301AA02 devices or other
PMBus-controlled ICs, output-voltage sequencing can be
achieved by configuring each power supply with different
turn-on/turn-off delays and output rise/fall times. All power
supplies are then commanded to turn on (or off) simultane-
ously using a combined EN signal.
Output On/Off Control
The MAX15301AA02 features both a hardware enable
input (EN pin) and a PMBus enable function. The fac-
tory default for the enable functions is that the IC can be
enabled by either an assertion of the hardware EN pin
to a logic-high level or by issuing a PMBus enable com-
mand. The enable functionality can be changed using the
PMBus ON_OFF_CONFIG PMBus command (see the
PMBus specification for details).
The IC supports soft-start and soft-stop functionality as
shown in Figure 3. The PMBus TON_RISE and TOFF_
FALL commands determine the soft-start and soft-stop
ramp times. The TON_DELAY command sets the time
from a valid enable condition to the beginning of the
output-voltage ramp. Similarly, the TOFF_DELAY
command sets the time between loss of valid enable con-
dition and the beginning of the output ramp down to 0V.
The default setting for TON_DELAY is the minimum value
of 1ms and the default setting for the TON_RISE is 5ms.
The default configuration of the IC allows the output to
be enabled either by driving the EN input to a logic-high
level, or by sending the PMBus OPERATION command.
The enable criteria can be changed using the PMBus
ON_OFF_CONFIG command.
The output-voltage slew-rates for turn-on and turn-off
are given by VOUT_COMMAND ÷ TON_RISE and
VOLTAGE
TOFF_DELAY
TON_DELAY
TON_RISE
SWITCHING
NODE
TOFF_
FALL
VOLTAGE
t
ON_DELAY
V
V
EN
V
OUT
OUT
TIME
TIME
Figure 3. Turn-On/-Off Delays and Soft-Start/-Stop Times
Figure 4. Startup into a Prebiased Output
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
VOUT_COMMAND ÷ TOFF_FALL, respectively. It is rec-
ommended to set TON_RISE and TOFF_FALL to at least
1ms to prevent excessive inrush currents due to high
dV/dt. The output voltage ramp-up rises monotonically
above 300mV regardless of input voltage, output voltage,
or prebias voltage on the output. Note that the IC initiates
the InTune calibration process after the soft-start ramp-up
is complete.
VOUT_OV_FAULT_LIMIT value, the IC does not attempt
soft-start.
If prebias was detected at the time of enable, the IC saves
the prebias voltage level in a register and terminates the
output voltage ramp-down at the prebias voltage when
disabled. This register is not user accessable.
Voltage Tracking
The MAX15301AA02 supports voltage tracking of the out-
put from a reference input. To select the tracking mode,
connect the SET pin to SGND. The IC’s output tracks
Startup with Prebias
The MAX15301AA02 supports soft-start into a prebias
output voltage condition. A prebias condition occurs when
there is already a voltage at the output of the power sup-
ply before it has been enabled. This can be caused by
precharged output capacitors, or a parasitic ESD diode in
the load IC that pulls the output up to another system sup-
ply rail. When EN is asserted, the IC checks the output for
the presence of prebias voltage. If the prebias voltage is
less than 200mV, startup is performed normally assuming
no prebias. If the prebias is greater than 200mV but below
the target set point for the output, the IC ramps up the
output voltage from the prebias voltage to the regulation
set point as shown in Figure 4. If the prebias is above the
the V
voltage with a preset ratio governed by an
TRACK
internal feedback divider (RDIV) and an external resistive
voltage-divider (R1, R2) which is placed from the supply
being tracked to SGND (Figure 5). The center tap of the
external divider should be connected to the CIO input.
In tracking mode, V
is regulated to the lower of:
OUT
V
R1
TRACK
RDIV
V
=
x
OUT
R1+ R2
or the output set-point voltage V
as determined
OUT(SET)
by the VOUT_COMMAND. As seen in the above equa-
V
TRACK
STEP-DOWN
CONVERTER
R2
R1
MAX15301AA02
V
OUT
CIO
SET
Figure 5. Tracking Mode Configuration
RDIV = RR
RDIV ≠ RR
COINCIDENT TRACKING
(TRACK TO TARGET)
RATIOMETRIC MODE
VOLTAGE
VOLTAGE
V
V
V
V
TRACK
OUT
TRACK
OUT
10k
10k
Ω
+ R2
V
x V
TRACK
OUT(SET)
Ω
TIME
TIME
(a)
(b)
Figure 6. Tracking
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
tion, if the resistor-divider ratio RR = R1/(R1 + R2) is
chosen such that it is equal to the operational RDIV, the
output voltage follows the tracking voltage coinciden-
Output-Voltage Margining
The IC supports voltage margining, which can be used to
test the end equipment’s design margin associated with
power-supply variation. The margin set-point commands
VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW are
set to ±5% of VOUT_COMMAND by default, but can be
changed via the PMBus interface. Output voltage margin-
ing is controlled by the OPERATION command.
tally (Figure 6a). For all other cases, the V
follows a
OUT
ratiometric tracking (Figure 6b) depending on the ratio of
RR and RDIV. The IC automatically selects RDIV based
on the output set-point voltage as shown in Table 5.
For example, if V
is set to 1.6V by the VOUT_
OUT(SET)
COMMAND, RDIV is set to 0.54247. For a reliable voltage
tracking, it is recommended that once the IC is powered
up, the VOUT_COMMAND should not be changed so as
to cause a change to the operational RDIV (Table 5). If
such a change in VOUT_COMMAND is required, the user
should save the new VOUT(SET) in the device memory
(using STORE_USER_ALL_COMMAND) and recycle the
input power to set a new RDIV operational value. For
simplicity, fix R1 at 10kΩ and use the following equation
to determine R2:
Output Voltage Ranges and Fault Limits
The MAX15301AA02 features output undervoltage and
overvoltage protection. The PMBus VOUT_OV_FAULT_
LIMIT is set to 115% of VOUT_COMMAND by default,
and VOUT_UV_FAULT_LIMIT is set to 85%. These
thresholds can be changed through PMBus and set
anywhere between 0V and the lower of either the ADC
full-scale value or VOUT_MAX (VOUT_MAX is 110% of
VOUT_COMMAND by default.
The IC continuously monitors the output voltage.
If the voltage exceeds the protection limits, the IC
follows the actions prescribed by the VOUT_OV_
FAULT_RESPONSE or VOUT_UV_FAULT_RESPONSE
commands as appropriate. By default, an overvoltage
fault results in an immediate shutdown with no retry
attempts, whereas undervoltage faults are ignored. The
fault response commands can be changed at any time,
but changes to the fault-response commands only take
effect when the output is disabled.
V
TRACK
× V
OUT
R2 = 10k ×
−1
R
DIV
Table 5. Required Divider Ratio (RDIV) as
a Function of V
OUT
VOUT_COMMAND (V)
< 0.65
RDIV
0.99547
0.88222
0.76897
0.65572
0.54247
0.42922
0.31597
0.20272
0.65 to < 1.12
1.12 to < 1.28
1.28 to < 1.50
1.50 to < 1.82
1.82 to < 2.29
2.29 to < 3.12
3.12 to < 5.25
Output-Overcurrent Protection
The MAX15301AA02 monitors the voltage across the out-
put inductor resistance (or other resistive sense element) to
provide output current monitoring and overload protection.
The voltage signal at the current-sense element is divided
by the IOUT_CAL_GAIN value to yield output current in
Amps. The value of IOUT_CAL_GAIN is initially set by the
ADDR1 resistance according to Table 4b and should be
set as close as possible to the inductor DCR (or the resis-
tive sense element’s resistance.) More accurate output
current measurement can be achieved by calibrating the
IOUT_CAL_GAIN value; contact Maxim for an application
note describing the READ_IOUT calibration process.
For the best voltage regulation, RR should be set
such that the final tracking target volt-
age is slightly higher than the output set-point volt-
age determined by VOUT_COMMAND. The out-
V
OUT
put ramp tracks the V
input as shown in
The overcurrent fault threshold is set by the IOUT_OC_
FAULT_LIMIT command; the default value is 25A. If an
overcurrent condition is detected, the IC shuts down,
delays for 700ms, and then attempts to restart the regula-
tor. This process repeats indefinitely until the fault con-
dition no longer persists. This fault response behavior
can be changed using the PMBus IOUT_OC_FAULT_
RESPONSE command.
TRACK
Figure 6 until reaching the VOUT_COMMAND value. If
the application requires continuous ratiometric tracking,
VOUT_COMMAND should be set higher than the desired
V
tracking target or left at the 5.0V default value. In
OUT
this case, there is a small regulation inaccuracy due to the
tolerance of the external resistors.
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Fault Handling
Table 6. Fault Conditions
The MAX15301AA02 monitors input voltage, out-
put voltage, output current, and both internal and
external temperatures. The fault thresholds and
responses are factory-set, but may be changed using
PMBus commands. Fault detection can be individu-
ally enabled or disabled for the parameters through
PMBus. The default limits are as indicated in Table 6.
The response to a fault condition can be changed through
PMBus. Refer to Maxim’s User Guide 5793: MAX15301
PMBus Command Set User’s Guide for more informa-
tion on setting fault thresholds and fault responses.
FAULT
DEFAULT
RANGE
CONDITION
THRESHOLD
V
V
Overvoltage
14V
0 to 14.7V
0 to 14.7V
IN
Undervoltage
4.2V
IN
VOUT_COMMAND
x 115%
V
V
Overvoltage
0 to 5.5V
0 to 5.5V
OUT
OUT
VOUT_COMMAND
x 85%
Undervoltage
Overcurrent
I
25A
0 to 30A
OUT
Nonvolatile PMBus Memory
Overtemperature
115°C
-40°C to +150°C
The MAX15301AA02 includes three nonvolatile stores for
PMBus configuration values. The first is the MAXIM store,
which contains a read-only copy of all default command
settings. The next is the read/write-accessible DEFAULT
store, which is intended to contain an equipment manu-
facturer’s preferred or suggested settings. Third is the
read/write accessible USER store, which is intended to
store the end-user’s preferred settings.
tor’s configuration on a command-by-command basis.
Contact Maxim for application notes describing these
security features.
Power Good (PG)
PG, power good, is an open-drain output used to indi-
cate when the MAX15301AA02 is ready to provide
regulated output voltage to the load. During startup and
during a fault condition, PG is held low. PG is asserted
high after the output has ramped to a voltage above the
POWER_GOOD_ON (5Eh) threshold and a successful
InTune calibration has completed. If the output regula-
tion voltage falls below the POWER_GOOD_OFF (5Fh)
threshold, PG will be deasserted.
When the device is enabled, a combination of the pin-con-
figurable command values and the contents of the USER
store are loaded into working memory. Any command
values that have been edited and stored to the USER
memory takes precedence over their corresponding pin-
configured values.
Equipment manufacturers should ensure that the
DEFAULT and USER stores are saved with duplicate
copies of the manufacturer’s preferred or suggested com-
mand values. In this manner, an end user can restore
the DEFAULT memory and save to the USER store any
time they wish to return the device to the manufacturer’s
original configuration.
PMBus Digital Interface
The MAX15301AA02 is a PMBus-compatible device
that includes many of the standard PMBus commands.
A PMBus 1.2-compliant device uses the System
Management Bus (SMBus) version 2.0 for transport pro-
tocol and responds to the SMBus slave address. In this
data sheet, the term SMBus is used to refer to the electri-
Special security commands and features are included so
that a manufacturer user can store and lock the regula-
MAX15301AA02 MAX15301AA02
MAX15301AA02
V
LOGIC
SCL
SDA
SCL
SDA
TEMPX
100pF
SGND
R
R
PULLUP
PULLUP
Figure 8. SMBus Multidevice Configuration
Figure 7. Temperature Sensing with a 2N3904 npn Transistor
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Table 7. PMBus Command Summary
SMBus
TRANSFER
# OF
DATA
BYTES
COMMAND
COMMAND NAME
MIN
MAX
DEFAULT VALUE
UNITS
CODE
TYPE
0x01
0x02
0x03
0x10
0x11
0x12
0x15
0x16
0x19
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x33
0x35
0x36
0x37
0x38
0x39
0x40
0x41
0x44
0x45
0x46
0x47
0x4F
0x50
0x51
OPERATION
R/W Byte
R/W Byte
Send Byte
R/W Byte
Send Byte
Send Byte
Send Byte
Send Byte
Read Byte
Read Byte
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
R/W Byte
R/W Word
1
1
0
1
0
0
0
0
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
1
2
1
2
1
2
—
—
—
—
—
—
—
—
—
—
0.5
—
—
—
—
—
—
—
300
4
—
—
—
—
—
—
—
—
—
—
5.25
—
—
—
—
—
—
—
1000
12
12
—
—
—
—
—
—
—
—
—
—
—
—
0x40
—
—
—
—
—
—
—
—
—
—
V
ON_OFF_CONFIG
CLEAR_FAULTS
0x16
—
WRITE_PROTECT
STORE_DEFAULT_ALL
RESTORE_DEFAULT_ALL
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
0
—
—
—
—
0xA0
VOUT_MODE
0x14
VOUT_COMMAND
VOUT_TRIM
SET pin resistor setting
0
V
VOUT_CAL_OFFSET
VOUT_MAX
0
V
VOUT_COMMAND + 10%
V
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VOUT_TRANSITION_RATE
VOUT_DROOP
VOUT_COMMAND + 5%
V
VOUT_COMMAND - 5%
V
0.1
mV/µs
mΩ
kHz
V
0
FREQUENCY_SWITCH
VIN_ON
SYNC pin resistor setting
6
VIN_OFF
4
5.5
V
INTERLEAVE
—
—
—
—
—
—
—
—
—
—
—
—
See Table 2
—
mΩ
A
IOUT_CAL_GAIN
ADDR1 pin resistor setting
IOUT_CAL_OFFSET
VOUT_OV_FAULT_LIMIT
VOUT_OV_FAULT_RESPONSE
VOUT_UV_FAULT_LIMIT
VOUT_UV_FAULT_RESPONSE
IOUT_OC_FAULT_LIMIT
IOUT_OC_FAULT_RESPONSE
OT_FAULT_LIMIT
0
VOUT_COMMAND + 15%
V
0x80
—
V
VOUT_COMMAND - 15%
0x00
25
—
A
0xBF
115
—
°C
—
°C
OT_FAULT_RESPONSE
OT_WARN_LIMIT
0xC0
95
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Table 7. PMBus Command Summary (continued)
SMBus
TRANSFER
TYPE
# OF
DATA
BYTES
COMMAND
CODE
COMMAND NAME
MIN
MAX
DEFAULT VALUE
UNITS
0x55
0x56
0x59
0x5A
0x5E
0x5F
0x60
0x61
0x64
0x65
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x88
0x8B
0x8C
0x8D
0x8E
0x94
0x95
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0xAD
0xAE
VIN_OV_FAULT_LIMIT
VIN_OV_FAULT_RESPONSE
VIN_UV_FAULT_LIMIT
VIN_UV_FAULT_RESPONSE
POWER_GOOD_ON
POWER_GOOD_OFF
TON_DELAY
R/W Word
R/W Byte
2
1
2
1
2
2
2
2
2
2
1
2
1
1
1
1
1
2
2
2
2
2
2
2
1
8
13
7
8
6
13
8
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
14
V
—
V
0xC0
R/W Word
R/W Byte
4.2
0xC0
—
V
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
R/W Word
Read Byte
Read Word
Read Byte
Read Byte
Read Byte
Read Byte
Read Byte
Read Word
Read Word
Read Word
Read Word
Read Word
Read Word
Read Word
Read Byte
R/W Block
R/W Block
R/W Block
R/W Block
R/W Block
R/W Block
Read Block
Read Word
VOUT_COMMAND - 10%
VOUT_COMMAND - 15%
V
5
ms
ms
ms
ms
—
—
—
—
—
—
—
V
TON_RISE
5
TOFF_DELAY
1
TOFF_FALL
5
STATUS_BYTE
—
STATUS_WORD
STATUS_VOUT
—
—
STATUS_IOUT
—
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
—
—
—
READ_VIN
—
READ_VOUT
—
V
READ_IOUT
—
A
READ_TEMPERATURE_1
READ_TEMPERATURE_2
READ_DUTY_CYCLE
READ_FREQUENCY
PMBUS_REVISION
MFR_ID
—
°C
°C
%
—
—
—
kHz
—
—
—
—
—
—
—
—
—
0x22
Null
MFR_MODEL
Null
MFR_REVISION
MFR_LOCATION
MFR_DATE
Null
Null
Null
MFR_SERIAL
Null
IC_DEVICE_ID
“MAX15301AA02”
<firmware revision>
IC_DEVICE_REV
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Table 7. PMBus Command Summary (continued)
SMBus
TRANSFER
TYPE
# OF
DATA
BYTES
COMMAND
CODE
COMMAND NAME
MIN
MAX
DEFAULT VALUE
UNITS
0xD0
0xD3
0xD5
0xDB
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xEA
0xF8
ADAPTIVE_MODE
Write Byte
R/W Word
R/W Word
R/W Block
R/W Block
Write Word
Write Word
R/W Block
Write Word
R/W Word
Read Byte
R/W Block
R/W Word
Send Byte
R/W Block
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x024B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FEEDBACK_EFFORT
LOOP_CONFIG
COMP_MODEL
MANUF_CONF
MANUF_LOCK
0.5
2
0x0100
6
0.03167, 0.5, 0.5
32
2
0
0
MANUF_PASSWD
USER_CONF
2
0
32
2
0
USER_LOCK
0
USER_PASSWD
SECURITY_LEVEL
DEADTIME_GCTRL
ZETAP
2
0
1
0x00
19
2
See PMBus Application Note
1.5
—
RESTORE_MAXIM_ALL
EXT_TEMP_CAL
0
4
1.0391, -8
cal characteristics of the PMBus communication using the
SMBus physical layer. The term PMBus is used to refer to
the PMBus command protocol.
Electrical Characteristics table to determine the value
of the pullup resistors. Refer to Maxim’s User Guide
5793: MAX15301 PMBus Command Set User’s Guide
for more information on setting fault thresholds and fault
responses.
The IC employs six standard SMBus protocols (Write
Byte, Read Byte, Write Word, Read Word, Write Block,
and Read Block) to program output voltage and warn-
ing/faults thresholds, read monitored data, and provide
access to all manufacturer-specific commands.
Design Procedure
Switching Frequency Selection
The first step in selecting a buck controller’s output filter
When the data word is transmitted, the lower order byte
is sent first and the higher order byte is sent last. Within
any byte, the most significant bit (MSB) is sent first and
the least significant bit (LSB) is sent last.
is to select the desired switching frequency (f ) for the
SW
PWM. The MAX15301AA02 will switch at frequencies in
the range of 300kHz ≤ f
≤ 1MHz. Select a low frequency
SW
for higher efficiency. Use a higher frequency to reduce the
size of the external filter components and to improve tran-
sient response. Also consider system frequency require-
Contact the factory for detailed PMBus command support.
Supported PMBus Commands
ments when choosing f , such that the harmonics of
SW
The IC supports the standard PMBus commands given
in Table 7. Contact Maxim for an application note that
describes all MAX15301AA02 PMBus command function-
ality in detail.
the switching frequencies do not interfere with the system
operation. The switching frequency for the IC is set by the
SYNC pin connection per Table 3. The switching frequency
can be changed via the FREQUENCY_SWITCH PMBus
command at anytime the controller is disabled. The selec-
tion of 600kHz provides a good balance of efficiency, small
size, and good transient response.
A single pair of pullup resistors (one each for SCL and
SDA) is required for each shared bus as shown in
Figure 8. Consult the SMBus 2.0 specifications as
well as the guaranteed drive capability of SDA in the
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Inductor Selection
Output Capacitor Selection
Three key inductor parameters must be specified to select
an inductor for operation with the MAX15301AA02: induc-
The MAX15301AA02 has been optimized to operate with
low-ESR output capacitors. These capacitors typically
have X5R and X7R dielectrics. High-ESR capacitors
can be added, but would provide little benefit to system
performance. The output capacitor requirement is
dependent upon two considerations:
tance value (L), inductor saturation current (I
maximum DC resistance (DCR).
), and
SAT
1) Inductor value selection: For automatic compensa-
tion using InTune technology, the inductor is selected
such that the peak-to-peak inductor ripple current
(LIR) is 20% to 40% of the maximum operating cur-
rent (IOUTMAX). Using a low LIR ratio (higher inductor
value) will result in higher DC resistance in the inductor
and will reduce efficiency. Using a high value of LIR
will increase the RMS current which will also decrease
efficiency. Maxim recommends 30% for a peak-to-
peak ripple to maximum operating current ratio (LIR =
0.3).
1) Output-ripple voltage
2) Load current transient envelope
Both requirements are easily achieved with all-ceramic
output capacitors. The total output-voltage ripple is a
function of the output capacitor’s ESR and capacitance
and typically chosen to be ~1% of the output voltage. For
typical applications, the ripple voltage is dominated by the
capacitance. The following equations calculate the mini-
mum output capacitance and maximum allowable ESR:
The nominal inductor value can now be calculated
using LIR, f , V , V
mum DC load current) using the following equation:
, and I
(the maxi-
SW IN OUT
OUTMAX
V
RIPPLE
∆I
ESR
C
=
MAX
∆I
V
(V − V
)
OUT IN
OUT
LIR
=
L =
OUTMIN
V
f
I
8× V
× f
IN SW OUT
RIPPLE
SW
0.2 ≤ LIR ≤ 0.4
where ∆I is:
The exact inductor value in this range is not critical
and can be adjusted to make trade-offs among size,
cost, and efficiency. A higher inductance can increase
efficiency by reducing the RMS current. Lower inductor
values minimize size and cost. Lower inductor values
may also improve transient response but reduce effi-
ciency due to higher peak currents.
V
× V − V
IN OUT
(
)
OUT
V
∆I =
× f
× L
SW
IN
The worst-case output-voltage ripple is:
1
V
=∆I ×
+ ESR
RIPPLE
8× C
× f
SW
2) The selected inductor’s saturation current rating (I
)
OUT
SAT
must exceed the user-defined current limit. I
SAT
An ESR below 10mΩ is typically required. The use of two
or more 100µF ceramic capacitors in parallel is typically
sufficient to achieve a good ripple voltage.
should generally be selected such that it is greater
than I + LIR/2 +10% to provide adequate margin
LIM
in the event of a large load transient. It is important
to select an inductor that has a high enough I to
SAT
When all-ceramic output capacitors are used, load-
current transient envelope is the primary concern for
capacitor selection. Designs with small-load transients
can use fewer capacitors and designs with larger load
transients require more load capacitance to reduce output
“sag” and “soar.” The allowable deviation of the output
voltage during fast-load transient determines the output
capacitance. The following two equations calculate the
satisfy this requirement though this parameter typically
forces a certain dimension of inductor to be used.
3) Finally, the user should select an inductor with minimal
DCR (DC series resistance) to reduce overall losses
in efficiency. See the Current Sense section for more
information on selecting the inductor DCR.
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
minimum capacitance required to meet the voltage sag
Input Capacitor Selection
and soar requirements from a load transient:
To meet load current transient envelope requirements, the
IC compensates for output filters with natural (resonant)
The input filter capacitor reduces peak current drawn from
the power source and reduces noise and voltage ripple
on the input caused by the switching circuitry. The value
of the input capacitor is selected to limit the ripple voltage
(δV) as follows:
frequencies f such that the following is met:
LC
2
L × ∆I
∆I
V
V
V
OUT
O
OUT
I
×
× 1−
C
=
+
OUT
OUT
V
2×∆V
× V
V
2× π ×BW × ∆V
SAG
SAG
IN −
O
(
)
IN
IN
C
≥
IN
f
× DV
2
SW
L × ∆I
2×∆V
∆I
O
C
=
+
OUT
where DV is the input ripple voltage. This calculation
assumes there is measurable inductance back to the
original VIN source thus this calculation provides low
source impedance at the input of the DC-DC converter.
The capacitance requirement is greatest when the duty
cycle is 50% and decreases as duty cycle increases (i.e.
input voltage increases).
×V
2× π ×BW × ∆V
SOAR
O
SOAR
where BW is the power-supply crossover frequency in Hz,
which is approximately f /10 for the device and C
for the out capacitance.
SW
OUT
The total output-voltage ripple also includes a voltage
ripple due to quantization noise. This quantization noise
is inherent to the digital control loop and is not affected by
adding or removing output capacitors. The noise appears
as random noise on the output voltage at a frequency
between 10kHz and 60kHz. The amplitude is approxi-
= 1.2V and 12mV at V
See the Typical Operating Characteristics for the typical
waveforms.
The input capacitor must meet the ripple current require-
ment (I
) imposed by the switching currents as defined
RMS
by the following equation:
V
(V − V
)
OUT
OUT IN
mately 4mV at V
= 3.3V.
I
RMS
= I
OUT
OUT
LOAD(MAX)
V
IN
I
attains a maximum value when the input volt-
RMS
age equals twice the output voltage (V
= 2V
),
IN
OUT
Compensating the Power Supply
so I
= I
/2. For most applications,
RMS(MAX)
LOAD(MAX)
Unlike most power-supply designs, the device does not
require designing and testing a compensation circuit.
The device automatically measures the output filter’s
resonant frequency and uses this information to set the
appropriate compensation parameters. The device is
stable if the output-filter corner frequency meets the
following requirements:
nontantalum capacitors (ceramic, aluminum, polymer, or
OS-CON) are preferred at the inputs due to the robustness
of non-tantalum capacitors to accommodate high inrush
currents of systems being powered from very low imped-
ance sources. Additionally, two (or more) smaller-value
low-ESR capacitors should be connected in parallel to
reduce high-frequency noise.
25 ≤ f /f ≤ 70
SW LC
MOSFET Selection
where:
The following guidelines address the challenge of
selecting the appropriate MOSFETs for high-current appli-
fLC = 1 2π LC
cation. The high-side MOSFET (Q ) must be able to
H
dissipate the resistive losses plus the switching losses at
Therefore:
both V
Ideally, the losses at V
and V
. Calculate both these sums.
should be roughly equal to
IN(MIN)
IN(MAX)
IN(MIN)
2
2
1
25
1
70
losses at V
with lower losses in between. If the
≤ C ≤
IN(MAX),
L 2πfSW
L 2πfSW
losses at V
are significantly higher than the losses
IN(MIN)
at V
, consider increasing the size of QH (reducing
IN(MAX)
Most 600kHz PoL designs (10A to 25A) are satisfied using
between 200µF and 1000µF of ceramic output capaci-
tance and no additional electrolytic capacitors. The InTune
adaptive compensation permits a large range of output
inductors and capacitors.
R
but increasing C ). Conversely, if the losses at
GATE
DS(ON)
V
are significantly higher than the losses at V
,
IN(MAX)
IN(MIN)
consider reducing the size of QH (increasing R
reducing C
range, the minimum power dissipation occurs where the
but
DS(ON)
). If input voltage does not vary over a wide
GATE
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
resistive losses equal the switching losses. Choose a low-
side MOSFET that has the lowest possible on-resistance
tion above. If the high-side MOSFET chosen for adequate
at low input voltages becomes extraordinarily hot
R
DS(ON)
when biased from V
(R ), comes in a moderate-sized package, and is
DS(ON)
, consider choosing another
IN(MAX)
reasonably priced. Ensure that the DL gate driver can sup-
ply sufficient current to support the gate charge and the
current injected into the parasitic gate-to-drain capacitor
caused by the high-side MOSFET turning on; otherwise,
cross-conduction problems can occur.
MOSFET with lower parasitic capacitance.
For the low-side MOSFET (QL), the worst-case power dis-
sipation always occurs at the maximum input voltage and
is due primarily to conduction losses. Switching losses in
the low-side FET are minimal because it is turned on and
off when the body diode is conducting and hence under
zero-voltage conditions.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty cycle
extremes. For the high-side MOSFET (QH), the worst-case
conduction losses occur at the minimum input voltage:
V
2
OUT
P
= 1−
×I
×R
OUT DS(ON)
Q −COND
L
V
IN(MAX)
V
2
OUT
P
=
×I
× R
OUT DS(ON)
Q
−COND
H
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
V
IN(MIN)
Generally, a small high-side MOSFET is desired to reduce
switching losses at high input voltages. However, the
I
, but are not quite high enough to exceed
OUT(MAX)
the current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle the
overload power dissipation. The heatsink can be a large
copper field on the PCB or an externally mounted device.
R
required to stay within package-power dissipa-
DS(ON)
tion often limits how small the MOSFETs can be. Again,
the optimum occurs when the switching losses equal the
conduction (R
) losses.
DS(ON)
Avoiding dV/dt Turn-On of the Low-Side MOSFET
Calculating the power dissipation in high-side MOSFETs
(NH) due to switching losses is difficult since it must allow
for difficult quantifying factors that influence the turn-on
and turn-off times. These factors include the internal gate
resistance, gate charge, threshold voltage, source induc-
tance, and PCB layout characteristics.
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the low-side
MOSFET. The high dV/dt causes a current flow through
the Miller capacitance (C
) and the input capacitance
RSS
(C ) of the low-side MOSFET. Improper selection of the
ISS
low-side MOSFET that results in a high ratio of C
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a ther-
mocouple mounted on QH:
/
RSS
makes the problem more severe. To avoid this prob-
C
ISS
lem, minimize the ratio of C
/C
when selecting the
RSS ISS
low-side MOSFET. Adding a 1Ω to 4.7Ω resistor in series
with the high-side MOSFET gate can slow the high-side
MOSFET turn-on. Similarly, adding a small capacitor from
the gate to the source of the high-side MOSFET has the
same effect. However, both methods work at the expense
of increased switching losses (lower efficiency).
V
I
f
Q
1
2
IN(MAX) LOAD SW G
P
=
−SW
×
Q
H
I
SWH-SOURCE
V
I
f
Q
1
2
IN(MAX) LOAD SW G(SW)
+
×
I
SWH-SINK
2
Boost Capacitor
+
C
V
f
OSS IN(MAX) SW
2
The MAX15301AA02 uses a bootstrap circuit to gener-
ate the necessary gate-to-source voltage to turn on the
high-side MOSFET. The selected n-channel high-side
MOSFET determines the appropriate boost capacitance
where C
is the QH MOSFET’s output capacitance,
OSS
value (C
in the Typical Operating Circuit) according to
BST
Q
G(SW)
is the charge needed to turn on the high-side
the following equation:
MOSFET, I
is the peak gate-drive source
DH-SOURCE
current (2A typ), and I
current (4A typ).
is the peak gate-drive sink
DH-SINK
QG
∆V
C
=
BST
BST
Switching losses in the high-side MOSFET can become an
insidious heat problem when the maximum input voltage is
applied due to the squared term in the switching-loss equa-
where Q is the total gate charge of the high-side
G
MOSFET and DV
is the voltage variation allowed
BST
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
on the high-side MOSFET driver after turn-on. Choose
DV such that the available gate-drive voltage is not
More accurate current sensing can be achieved by sensing
across a current-sense resistor placed between the induc-
tor and the output capacitors. A dedicated current-sense
resistor provides a more accurate resistance and lower
tempco than sensing across the inductor. If using a current-
sense resistor, connect DCRP to the node between the
inductor and the current-sense resistor. Connect DCRN
to the node between the current-sense resistor and
the output capacitors. Be sure to use Kelvin sensing
across the resistor. For accurate current sensing, pro-
gram the device’s IOUT_CAL_GAIN to be equal to the
current-sense element’s resistance. Note that the default
IOUT_CAL_ GAIN is set by the pin-strap resistor con-
nected between ADDR1 and SGND. This default
IOUT_CAL_GAIN can be change through the PMBus.
If IOUT_CAL_GAIN is not configured to match the
actual current-sense resistance, the actual load
current is scaled from the measured current by the ratio
of IOUT_CAL_GAIN to DCR. In this case, the actual load
current is: ILOAD = READ_IOUT x IOUT_CAL_GAIN/
DCR As an example, if IOUT_CAL_GAIN is pin strapped
to 0.8mΩ, the actual inductor DCR is 1.6mΩ, and a
PMBus READ_IOUT command returns 20A; the actual
load current is 10A.
BST
significantly degraded (e.g. DV
= 100mV to 300mV)
BST
when determining C
.
BST
For most applications, a 0.22µF low-ESR ceramic capaci-
tor will suffice.
Current Sense
The MAX15301AA02 uses lossless DCR current
sensing to reduce the overall power dissipation and
improve efficiency. Lossless sensing is configured by con-
necting a series RC circuit across the inductor as shown in
Figure 9. Select the resistor and capacitor such that their
time constant is equal to that of the inductor and its DCR:
L
R C
=
L
L
DCR
Use the typical inductance and DCR values provided
by the inductor manufacturer. The resistor value should
be set to 2kΩ. Use high-accuracy and low-tempco C0G
ceramic capacitors for C . The maximum sense voltage
L
produced using lossless sensing is:
V
− V
= DCR×I
DCRP
DCRN OUT(MAX)
Current Limit
Choose the DCR so the maximum current-sense voltage
is between 10mV and 150mV. A higher current-sense
voltage improves the measurement signal-to-noise ratio,
but increases power dissipation. Carefully observe the
PCB layout guidelines provided in the data sheet to
ensure the noise and DC errors do not corrupt the differ-
ential current-sense signals seen by DCRP and DCRN.
Place the RC network close to the inductor and Kelvin
sense the voltage across the capacitor.
The MAX15301AA02 provides current protection
utilizing inductor DCR current sense or a current-sense
resistor. The details for selecting the current-sense
element are described in the previous paragraph. When
the measured current equals the IOUT_FAULT_LIMIT, the
device acts on the current faults, as defined by the PMBus
IOUT_OC_FAULT_RESPONSE setting. For the most
accurate current sensing, configure IOUT_CAL_GAIN
through the PMBus to equal the current-sense element.
If only the pin-strapped values of IOUT_CAL_GAIN are
used, select the R
resistor such that:
ADDR1
IOUT_CAL_GAIN ≥ DCR×I
25A
OUT(MAX)
DH
N
N
L
Output-Voltage Remote Sensing
MAX15301AA02
The MAX15301AA02 uses two dedicated inputs (OUTP
and OUTN) for the output differential voltage sensing to
reduce the common-mode noise sensitivity. This sensing
circuitry is part of the feedback loop. The output voltage
is connected to the IC directly through these two inputs
without the need for an external resistive divider. The PCB
traces to the OUTP and OUTN pins should be routed as
a differential pair to the desired regulation sense point to
minimize noise induced in the sensed signal. A 100pF to
1000pF capacitor can be placed directly across OUTP to
OUTN to minimize noise.
C
L
C
OUT
R
L
DL
DCRP
DCRN
Figure 9. Lossless DCR Current Sensing
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
For applications where efficiency is not critical, the
inductor can be omitted and the BabyBuck automatically
BabyBuck Component Selection
The MAX15301AA02 features an internal DC-DC switch-
ing regulator to power internal circuitry and provide the
gate-drive voltage for the external MOSFETs. Competing
parts with internal driver circuits use linear regulators to
provide these voltages which leads to significant efficien-
cy loss when operating from an input voltage above ~6V.
The patent-pending BabyBuck circuit improves overall
efficiency in a typical application by more than 1% at full
load and more than 10% in lightly loaded conditions.
operates as a linear regulator (Figure 11). In this con-
figuration, bypass GDRV to PGND with a 2.2µF ceramic
capacitor and connect LBI to PWR through a 100kΩ
resistor. The linear regulator can be bypassed altogether
with an external power source. An external 5V to 9V sup-
ply can also be applied directly to the GDRV pin to power
the gate drivers (Figure 12). Pull LBI up to PWR with a
2kΩ resistor and leave LBO unconnected to allow exter-
nal gate drive supply.
The BabyBuck uses a tiny (1008-size) low current
inductor connected across LBI and LBO (Figure 10).
A 10µH inductor with a saturation rating of at least
200mA and a 2.2µF ceramic capacitor at GDRV pin is
recommended.
V
IN
100kΩ
PWR
LBI
LBO
In addition to the efficiency improvement from using a
DC-DC regulator to power the MOSFETs, the BabyBuck
can vary the gate-drive voltage to improve the efficiency
over different load current conditions. The variable gate-
drive function can be disabled and the gate-drive voltage
GDRV
LDO
2.2µF
FB
MAX15301AA02
5V TO 8.5V
GDRV COMMAND
V
IN
BST
DH
10µH
PWR LBI
LBO
LX
DL
DPWM
GDRV
BABYBUCK
2.2µF
FB
5V TO 8.5V
GDRV COMMAND
BST
Figure 11. Gate Drivers Powered by Linear Regulator
DH
LX
DL
DPWM
MAX15301AA02
V
IN
2kΩ
PWR
LBI
LBO
GDRV
V
EXT
5V TO 9V
Figure 10. Gate Drivers Powered by Switching Regulator
levels can be modified using PMBus commands.
2.2µF
MAX15301AA02
BST
DH
LX
DL
DPWM
Figure 12. Gate Drivers Powered Externally
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
3) Bypass GDRV to PGND, 3P3 to SGND, and 1P8 to
DGND with ceramic decoupling capacitors. Place the
Design Examples
See Table 8 for the component values in the Typical
Operating Circuit. For additional examples and detailed
layout information, refer to the MAX15301 evaluation kit.
capacitors as close as possible to the pins.
4) Minimize the length of the high-current loop from the
input capacitor, the high-side switching MOSFET, and
the low-side MOSFET back to the input-capacitor
negative terminal.
Applications Information
PCB Layout Guidelines
5) Provide enough copper area at and around the switch-
ing MOSFETs and inductors to aid in thermal dissipa-
tion. Maintain a good balance between the LX copper
area for thermal performance and electromagnetic
radiation.
Careful PCB layout is critical to achieve clean and stable
operation. The switching power stage requires particular
attention. Follow these guidelines for best thermal perfor-
mance and signal integrity:
1) When using a resistor to set a command value, con-
nect its return terminal to SGND.
6) Route high-speed switching nodes (BST, LX, DH, and
DL) away from sensitive sense inputs (OUTP, OUTN,
DCRP, and DCRN).
2) Connect the power ground plane (connected to
PGND), digital return (connected to DGND), and ana-
log ground plane (SGND) at one point near the device.
7) Route the DCRP, DCRN and OUTP, OUTN traces as
differential pairs.
8) Connect PGND of the IC as close as possible to the
source of the low-side MOSFET.
Table 8. Typical Component Values
COMPONENT
Input Supply
Output Voltage
APPLICATION 1
APPLICATION 2
APPLICATION 3
12V
1.0V
12V
3.3V
12V
1.0V
R
14.7kΩ
20A
51.1kΩ
12A
14.7kΩ
35A
SET
Output Current
2.15, 5.11, 6.19, 7.15, or
21.5, 26.1, 31.6, 38.3, or
2.15, 5.11, 6.19, 7.15, or
R
R
ADDR1
8.25kΩ
44.2kΩ
8.25kΩ
User defined (see Table 4a)
User defined (see Table 4a)
User defined (see Table 4a)
ADDR0
Switching Frequency
750kHz
600kHz
850kHz
R
SYNC
21.5kΩ
12.7kΩ
31.6kΩ
Würth 744308033, 330nH,
Würth 744332082, 820nH,
Inductor L1
Inductor L2
Coilcraft SLC1049-125
370μΩ
1.17mΩ
TDK NLCV25T-100K-PF, 10μH TDK NLCV25T-100K-PF, 10μH TDK NLCV25T-100K-PF, 10μH
R
C
665Ω
634Ω
2.10kΩ
FILTER
1μF
1μF
0.22μF
FILTER
CSD86350Q5D,
(5mm x 6mm)
Infineon BSC032NE2LS,
3.2mΩ (5mm x 6mm)
High-Side MOSFET
Low-Side MOSFET
FDPC8011S, 7.3mΩ
as above (MOSFET pair),
Infineon BSC010NE2LS,
1.0mΩ (5mm x 6mm)
as above (MOSFET pair)
2.1mΩ
Output Capacitance
Input Capacitance
5 x 100μF, X5R, 1206, 6.3V
3 x 47μF, X5R, 1210, 16V
3 x 100μF, X5R, 1206, 6.3V
1 x 47μF, X5R, 1210, 16V
10 x 100μF, X5R, 1206, 6.3V
4 x 47μF, X5R, 1210, 16V
Maxim Integrated
│ 29
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
to approximately 40°C/W. The IC will shut down if its tem-
perature increases beyond +115°C. (This threshold can
be changed using a PMBus command). An evaluation kit
is available that demonstrates the recommended layout
practices for the MAX15301AA02.
Thermal Layout
The MAX15301AA02 is available in a small 5mm x 5mm
TQFN package with exposed pad to remove heat from
the internal semiconductor junctions. The exposed pad
must be soldered to the copper on the PCB directly
underneath the device package reducing the θ down
JA
Typical Operating Circuit
V
IN
2kΩ
1FF
2.2FF
L2
10FH
13
14
22
18
GDRV
C
IN
INSNS
LXSNS
PWR
21
23
LBI
17
LBO
3P3
BST
24, 25
6
Q
0.22FF
H
L
1P8
4.7FF
15
16
DH
LX
L1
10FF
V
OUT
MAX15301AA02
C
OUT
CL
R
LO
Q
L
7
2
19
20
TEMPX
ADDR0
DL
PGND
4
3
8
ADDR1
SET
30
31
DCRP
DCRN
2N3904
CIO
R
R
R
R
CIO
ADDR0
ADDR1
SET
100pF
27
26
OUTP
OUTN
12
1
ENABLE
EXT CLK
EN
SYNC
3.3V LOGIC
POWER GROUND
SIGNAL GROUND
10kΩ
3kΩ
3kΩ
10kΩ
32
10
PG
SCL
11
9
SMBus
INTERFACE
SDA
SALRT
5
DGND
EP
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFN-EP*
32 TQFN-EP*
FIRMWARE
4328
MAX15301AA02+CJK
MAX15301AA02+TCJK
4328
Note: Refer to User Guide 5793: MAX15301 PMBus Command Set User’s Guide for more information on the differences between
MAX15301 IC firmware options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 TQFN-EP
T3255M+5
21-0140
90-0013
Maxim Integrated
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MAX15301AA02
InTune Automatically Compensated Digital PoL
Controller with Driver and PMBus Telemetry
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
2/15
Initial release
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2015 Maxim Integrated Products, Inc.
│ 32
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