MAX16031ETM+T [MAXIM]
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| 型号： | MAX16031ETM+T |
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MAXIM INTEGRATED PRODUCTS |
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19-0870; Rev 1; 10/07
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
General Description
Features
o Supply Voltage Operating Range of 2.85V to 14V
o Monitors Up to Eight Voltages (Single-Ended or
Pseudo-Differential) with 1% Accuracy
o EEPROM-Configurable Limits
The MAX16031/MAX16032 EEPROM-configurable sys-
tem monitors feature an integrated 10-bit analog-to-
digital converter (ADC) designed to monitor voltages,
temperatures, and current in complex systems. These
EEPROM-configurable devices allow enormous flexibility
in selecting operating ranges, upper and lower limits,
fault output configuration, and operating modes with
the capability of storing these values within the device.
Two Undervoltage and Two Overvoltage
Two Overtemperature
Two Overcurrent
o High-Side Current-Sense Amplifier with
Overcurrent Output (MAX16031 Only)
o Monitors Up to Three Temperatures
(1 Internal/2 Remote)
The MAX16031 monitors up to eight voltages, three
temperatures (one internal/two external remote temper-
ature diodes), and a single current. The MAX16032
monitors up to six voltages and two temperatures (one
internal/one remote temperature diode). Each of these
monitored parameters is muxed into the ADC and writ-
ten to its respective register that can be read back
through the SMBus™ and JTAG interface.
o Nonvolatile Fault Memory Stores Fault Conditions
for Later Retrieval
o Two Additional Configurable Fault Outputs
o Two Configurable GPIOs
o SMBus/I C-Compatible Interface with ALERT
2
Output and Bus Timeout Function
o JTAG Interface
o 7mm x 7mm, 48-Pin TQFN Package
Measured values are compared to the user-config-
urable upper and lower limits. For voltage measure-
ments, there are two undervoltage and two overvoltage
limits. For current and temperature, there are two sets
of upper limits. Whenever the measured value is out-
side its limits, an alert signal is generated to notify the
processor. Independent outputs are available for over-
current, overtemperature, and undervoltage/overvolt-
age that are configured to assert on assigned
channels. There are also undedicated fault outputs that
are configured to offer a secondary limit for tempera-
ture, current, or voltage fault or provide a separate
overvoltage output.
Ordering Information
PIN-
PKG
PART
TEMP RANGE
PACKAGE
CODE
MAX16031ETM+
MAX16032ETM+
-40°C to +85°C 48 TQFN-EP* T4877-6
-40°C to +85°C 48 TQFN-EP* T4877-6
+Denotes a lead-free package.
*EP = Exposed paddle.
Pin Configuration
During a major fault event, such as a system shutdown,
the MAX16031/MAX16032 automatically copy the inter-
nal ADC registers into the nonvolatile EEPROM registers
that then are read back for diagnostic purposes.
48 47 46 45 44 43 42 41 40 39 38 37
IN2
IN3
1
2
3
4
5
6
7
8
9
36 ABP
35 GND
34 DBP
33 TDO
32 N.C.
31 N.C.
30 N.C.
29 TDI
The MAX16031/MAX16032 offer additional GPIOs that
are used for voltage sequencing, additional fault out-
puts, a manual reset input, or read/write logic levels. A
separate current-sense amplifier with an independent
output allows for fast shutoff during overcurrent condi-
tions. The MAX16031/MAX16032 are available in a
7mm x 7mm TQFN package and are fully specified
from -40°C to +85°C.
+
IN4
N.C.
N.C.
N.C.
N.C.
GND
IN5
MAX16031
MAX16032
Applications
28 TCK
27 TMS
26 RESET
25 FAULT1
IN6 10
N.C. (IN7) 11
N.C. (IN8) 12
Servers
Workstations
Storage Systems
Telecom
Networking
13 14 15 16 17 18 19 20 21 22 23 24
( ) MAX16031 ONLY
TQFN
(7mm x 7mm)
SMBus is a trademark of Intel Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Selector Guide
VOLTAGE MONITORS
SINGLE ENDED DIFFERENTIAL
TEMPERATURE SENSORS
CURRENT-
SENSE AMPS OUTPUTS
FAULT
PART
GPIOs
INT
1
EXT
2
MAX16031ETM+
MAX16032ETM+
8
4
1
4
4
2
2
6
3
1
1
—
Typical Application Circuit
5V
1.5V
3.3V
1.2V
2.5V
0.9V
1.8V
5V DC-DC
EN
1.5V
DC-DC
3.3V DC-DC
EN
1.2V
DC-DC
12V BUS
2.5V DC-DC
EN
/MAX16032
0.9V
LINEAR
1.8V DC-DC
EN
3.3V AUX
CS+
CS-
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
V
CC
INT
ALERT
1µF
SCL
SDA
SCL
µC
SDA
RESET
GPIO1
DXP1
RESET
FAULT1
FAULT2
SYSTEM RESET
MAX16031
DXN1
DXP2
OVERT
OVERC
TO FAN CONTROL
WARNING INDICATORS
DXN2
GPIO2
ABP
DBP
RBP
GND
A0
A1
TMS TCK TDI TDO
1µF
1µF
2.2µF
MANUAL
RESET
SWITCH
TMS
TCK
SYSTEM JTAG
HEADER
TO OTHER
JTAG DEVICES
TDI
TDO
2
_______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND............................................................-0.3V to +15V
Input/Output Current
IN_, FAULT_, SCL, SDA, OVERT to GND.................-0.3V to +6V
A0, A1, TCK, TMS, TDI to GND................................-0.3V to +6V
OVERC, RESET, GPIO_, ALERT to GND..................-0.3V to +6V
(all except DXN1, DXN2, SDA, and ALERT)..................20mA
Continuous Power Dissipation (T = +70°C)
A
48-Pin, 7mm x 7mm TQFN
RBP, ABP, DBP to GND ...-0.3V to lower of (6V and V
+ 0.3V)
+ 0.3V
(derate 27.8mW/°C above +70°C) ........................2222.2mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+250°C
CC
TDO, DXP1, DXP2 to GND..........................-0.3V to V
DBP
CS+, CS- to GND ...................................................-0.3V to +30V
(CS+ - CS-) ............................................................................ 5V
DXN1, DXN2 to GND.............................................-0.3V to +0.8V
SDA, ALERT Current...........................................-1mA to +50mA
DXN1, DXN2 Current ............................................................1mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 2.9V to 14V, T = -40°C to +85°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range
V
2.90
14.00
V
CC
Minimum voltage at V
to access the digital interfaces
CC
Undervoltage Lockout
V
2.8
V
UVLO
Undervoltage Lockout Hysteresis
Supply Current
V
100
3
mV
mA
UVLOHYS
I
Static (EEPROM not accessed)
5
CC
ADC DC ACCURACY
Resolution
10
Bits
% FSR
LSB
Total Unadjusted Error
Integral Nonlinearity
Differential Nonlinearity
T
= -40°C to +85°C
0.9
A
1
1
LSB
Eight supply inputs, three temperatures,
and current sense
ADC Total Monitoring Cycle Time
t
80
5.6
2.8
100
µs
CYCLE
Register map bit set to 00
(LSB = 5.46mV)
Register map bit set to 01
(LSB = 2.73mV)
ADC IN_ Voltage Ranges
V
V
Register map bit set to 10
(LSB = 1.36mV)
1.4
1.4
Reference Voltage
V
1.306
1.414
RBP
IN_ ANALOG INPUT
Absolute Input Voltage Range
(Referenced to GND)
0
5.6
80
V
Input Impedance
30
50
kΩ
_______________________________________________________________________________________
3
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.9V to 14V, T = -40°C to +85°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
Percent of programmed
threshold
MIN
TYP
0.78
1.17
MAX
UNITS
r5Ch[5] = 0
r5Ch[5] = 1
Input Hysteresis
%
RESET OUTPUT
r20h[5:3] = 000; from MR going high
r20h[5:3]= 001
22.5
2.25
9
25
2.5
27.5
2.75
11
µs
r20h[5:3]= 010
10
r20h[5:3]= 011
36
40
44
Reset Timeout Period
t
RP
ms
r20h[5:3]= 100
144
576
1152
2304
160
640
1280
2560
176
704
1408
2816
r20h[5:3]= 101
r20h[5:3]= 110
r20h[5:3]= 111
TEMPERATURE MEASUREMENTS
Internal Sensor Measurement
Error
(Note 2)
(Note 2)
3
5
°C
°C
°C
/MAX16032
External Remote Diode
Temperature Measurement Error
Temperature Measurement
Resolution
0.5
Temperature Measurement Noise
External Diode Drive High
External Diode Drive Low
Diode Drive Current Ratio
DXN_ Impedance to GND
Power-Supply Rejection
CURRENT SENSE
Internal sensor
0.1
84
6
°C
µA
µA
14
1.8
0.1
kΩ
PSR
Internal sensor, DC condition
°C/V
CS+ Input Voltage Range
V
3
28
25
V
CS+
I
V
V
= V
14
3
CS+
CS+
CS-
CS-
Input Bias Current
µA
I
= V
8
CS-
CS+
A = 48
A = 24
A = 12
A = 6
21.5
45
25
50
100
200
0.5
50
4
28.5
55
Primary Current-Sense
Differential Thresholds
V
V
- V
mV
CSTH
CS+
CS-
92
108
210
190
Primary Current-Sense Threshold
CS
Percent of V
%
HYS
CSTH
r5Ch[1:0] = 00
r5Ch[1:0] = 01
r5Ch[1:0] = 10
r5Ch[1:0] = 11
µs
3.6
4.4
Secondary Overcurrent
Threshold Timeout
14.4
57.6
16
64
17.6
70.4
ms
4
_______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.9V to 14V, T = -40°C to +85°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
A = 6
232
A = 12
A = 24
A = 48
116
58
29
0.2
1.2
2
Current-Sense Analog Input
Range
V
- V
mV
CS+
CS-
V
V
V
V
= 150mV, (A = 6 only)
= 50mV, (A = 6, 12 only)
= 25mV
-4
+4
SENSE
SENSE
SENSE
SENSE
-10
+10
ADC Current-Sense
Measurement Accuracy
%
%
= 10mV
10
V
V
= 20mV to 100mV,
SENSE
Gain Accuracy
-3
+3
= 12V, A = 6
CS+
Common-Mode Rejection Ratio
Power-Supply Rejection Ratio
OVERC Output Leakage Current
OVERC Output Low Voltage
OVERC Propagation Delay
SMBus INTERFACE (SCL, SDA)
Logic-Input Low Voltage
Logic-Input High Voltage
Input Leakage Current
CMRR
V
> 4V
80
80
dB
dB
µA
V
CS
CS+
PSRR
CS
I
1
0.4
5
OVERCLKG
V
I
= 3mA
OLOVERC
OUT
t
V
- V
> 10% x V
CSTH
µs
OVERC
SENSE
CSTH
V
Input voltage falling
Input voltage rising
0.8
V
V
IL
V
2.0
-1
IH
GND or 5.5V (V
= 5.5V) V
, V
SCL SDA
+1
µA
V
CC
Output Low Voltage
V
I
= 3mA
0.4
OL
SINK
Input Capacitance
C
5
pF
IN
ALERT, FAULT_, AND GPIO_ OUTPUTS
ALERT, FAULT_, and GPIO_
Output Low Voltage
I
= 3mA
0.4
+1
V
SINK
ALERT, FAULT_, and GPIO_
Leakage Current
V
, V
, V
= 5.5V or GND
-1
µA
ALERT FAULT GPIO_
GPIO_ (INPUT)
Logic-Low Voltage
GPIO_ voltage falling
GPIO_ voltage rising
0.8
0.4
V
V
Logic-High Voltage
SMBus ADDRESS (A0 and A1)
Address Logic-Low
Address Logic-High
2.0
V
V
1.4
-1
High-Impedance Leakage
Current
Maximum current to achieve high-
impedance logic level
+1
µA
µA
Input Leakage Current
0 to 3V, V
= 3V
-12
+12
CC
_______________________________________________________________________________________
5
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.9V to 14V, T = -40°C to +85°C, unless otherwise specified. Typical values are at V
= 3.3V, T = +25°C.) (Note 1)
CC A
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SMBus TIMING (see Figure 1)
Serial-Clock Frequency
f
400
kHz
µs
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
BUF
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
t
0.6
0.6
0.6
1.3
0.6
100
µs
µs
µs
µs
µs
ns
ns
µs
ns
ms
SU:STA
HD:STA
SU:STO
t
t
t
LOW
Clock High Period
t
HIGH
Data Setup Time
t
SU:DAT
Output Fall Time
t
C
= 10pF to 400pF
BUS
250
0.9
OF
HD:DAT
Data Hold Time
t
From 50% SCL falling to SDA change
0.3
25
Minimum Pulse Width Ignored
SMBus Timeout
30
0
t
SCL time low for reset
35
TIMEOUT
JTAG INTERFACE (see Figure 2)
TDI, TMS, TCK Logic-Low Input
Voltage
V
Input voltage falling
Input voltage rising
0.4
V
V
IL
TDI, TMS, TCK Logic-High Input
Voltage
V
2.2
IH
TDO Logic-Output Low Voltage
TDO Logic-Output High Voltage
TDO Leakage Current
TDI, TMS Pullup Resistors
I/O Capacitance
V
I
I
= 4mA
0.4
V
OL
SINK
V
= 1mA
2.2
-10
6.5
V
OH
SOURCE
TDO high impedance
+10
16
µA
kΩ
pF
ns
ns
ns
ns
ns
R
Pullup to V
10
50
JPU
DBP
C
I/O
TCK Clock Period
t
1000
1
TCK High/Low Time
t
t
(Note 3)
60
15
35
500
2, 3
TCK to TMS, TDI Setup Time
TCK to TMS, TDI Hold Time
TCK to TDO Delay
t
t
t
4
5
6
500
500
TCK to TDO High-Impedance
Delay
t
ns
7
MISCELLANEOUS
Power-On Delay
t
4
ms
ms
D-PO
Single-Byte EEPROM Write Cycle
Delay
(Note 4)
11
Note 1: Limits to -40°C are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: TCK stops either high or low.
Note 4: An additional cycle is required when writing to configuration memory for the first time.
6
_______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
SDA
t
BUF
t
SU:DAT
t
SU:STA
t
t
SU:STO
HD:DAT
t
t
LOW
HD:STA
SCL
t
HIGH
t
HD:STA
t
t
F
R
START
CONDITION
STOP
CONDITION
START
CONDITION
REPEATED START
CONDITION
Figure 1. SMBus Interface Timing Diagram
t
1
t
t
2
3
TCK
t
t
4
5
TDI, TMS
t
6
t
7
TDO
TRI-STATE ONLY
Figure 2. JTAG Interface Timing Diagram
_______________________________________________________________________________________
7
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Typical Operating Characteristics
(Typical values are at V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
NORMALIZED IN_ THRESHOLD
vs. TEMPERATURE
V
SUPPLY CURRENT
CC
NORMALIZED RESET TIMEOUT PERIOD
vs. TEMPERATURE
CC
vs. V SUPPLY VOLTAGE
1.03
1.02
1.01
1.00
0.99
0.98
0.97
3.0
2.5
2.0
1.5
1.0
0.5
0
1.05
1.04
1.03
1.02
1.01
1.00
0.99
0.98
0.97
0.96
0.95
T
= +85°C
A
T
= +25°C
A
T
= -40°C
A
-40
-15
10
35
60
85
0
2
4
6
8
10
12
14
-40
-15
10
35
60
85
TEMPERATURE (°C)
V
(V)
TEMPERATURE (°C)
CC
/MAX16032
OUTPUT VOLTAGE LOW
vs. SINK CURRENT
ADC DIFFERENTIAL NONLINEARITY
vs. INPUT VOLTAGE
ADC INTEGRAL NONLINEARITY
vs. INPUT VOLTAGE
400
350
300
250
200
150
100
50
0.15
0.10
0.05
0
0.50
0.40
0.30
0.20
0.10
0
-0.05
-0.10
-0.15
-0.20
-0.10
-0.20
-0.30
-0.40
-0.50
0
0
1
2
3
4
5
6
7
0
128 256 384 512 640 768 896 1024
INPUT VOLTAGE (DIGITAL CODE)
0
128 256 384 512 640 768 896 1024
INPUT VOLTAGE (DIGITAL CODE)
SINK CURRENT (mA)
REFERENCE VOLTAGE
vs. TEMPERATURE
NOISE HISTOGRAM
1000
900
800
700
600
500
400
300
200
100
0
1.50
1.48
1.46
1.44
1.42
1.40
1.38
1.36
1.34
1.32
ADC HALF-SCALE
VOLTAGE INPUT
1.30
-40
507 508 509 510 511 512 513
ADC OUTPUT CODE
-15
10
35
60
85
TEMPERATURE (°C)
8
_______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Typical Operating Characteristics (continued)
(Typical values are at V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
INTERNAL TEMPERATURE SENSOR
ACCURACY vs. TEMPERATURE
TEMPERATURE ERROR
vs. LEAKAGE RESISTANCE
TEMPERATURE ERROR
vs. REMOTE DIODE TEMPERATURE
3
2
15
10
5
5
4
PATH = DXP TO GND
3
0
-5
2
1
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
1
PATH = DXP TO V (+5V)
CC
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-35
-10
15
40
65
90
1
10
100
-30 -15
0
15 30 45 60 75 90 105
TEMPERATURE (°C)
LEAKAGE RESISTANCE (MΩ)
REMOTE DIODE TEMPERATURE (°C)
CURRENT-SENSE ACCURACY
TEMPERATURE ERROR
vs. DXP-DXN CAPACITANCE
CURRENT-SENSE PRIMARY THRESHOLD
vs. V
vs. V
OVERDRIVE
SENSE
SENSE
8
6
0
-1
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-2
-3
4
-4
2
-5
-6
0
-7
-8
-2
-4
-9
-10
0
23 46 69 92 115 138 161 184 207 230
0
1
2
3
4
5
6
7
8
9
0
20
40
60
80
100
V
(mV)
DXP-DXN CAPACITANCE (nF)
SENSE
V
OVERDRIVE (mV)
SENSE
_______________________________________________________________________________________
9
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Pin Description
PIN
NAME
FUNCTION
MAX16031 MAX16032
Supply Monitor Input 2. IN2 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
1
2
1
2
IN2
Supply Monitor Input 3. IN3 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
IN3
IN4
Supply Monitor Input 4. IN4 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
3
3
4–7, 11, 12,
23, 30, 31,
32, 39,
4–7, 30, 31,
32, 39, 40,
47
N.C.
No Connection. Leave unconnected. Do not use.
Ground. Connect all GND pins together.
/MAX16032
40–44, 47
8, 13, 35
9
8, 13, 35
9
GND
IN5
Supply Monitor Input 5. IN5 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
Supply Monitor Input 6. IN6 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
10
11
12
10
—
—
IN6
IN7
IN8
Supply Monitor Input 7. IN7 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
Supply Monitor Input 8. IN8 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
14
15
14
15
GPIO1 Configurable General-Purpose Input/Output 1
GPIO2 Configurable General-Purpose Input/Output 2
ADC Reference Bypass. RBP is an internally generated 1.4V reference for the ADC. Bypass
RBP to GND with a 2.2µF capacitor. Do not use RBP to power any additional circuitry.
16
16
RBP
17
18
17
18
SDA
SCL
SMBus Serial-Data, Open-Drain Input/Output
SMBus Serial-Clock Input
SMBus Address Input 0. Connect to DBP, GND, or leave unconnected to select the desired
device address.
19
20
19
20
A0
A1
SMBus Address Input 1. Connect to DBP, GND, or leave unconnected to select the desired
device address.
10 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Pin Description (continued)
PIN
NAME
FUNCTION
MAX16031 MAX16032
SMBus Alert Open-Drain Output. ALERT follows the SMBALERT# signal functionality
described in Appendix A of the SMBus 2.0 Specification. ALERT asserts when the device
detects a fault, thereby interrupting the host processor to query which device on the serial
bus detected faults.
21
21
ALERT
Overtemperature, Open-Drain Output. OVERT asserts when an overtemperature condition is
detected.
22
23
22
—
OVERT
OVERC
Overcurrent, Open-Drain Output. OVERC asserts when the primary overcurrent threshold is
exceeded.
24
25
26
27
28
29
33
24
25
26
27
28
29
33
FAULT2 Configurable Open-Drain Fault Output 2
FAULT1 Configurable Open-Drain Fault Output 1
RESET Configurable Open-Drain Reset Output
TMS
TCK
TDI
JTAG Test Mode Select Input. Internally pulled up to V
JTAG Test Clock Input
with a 10kΩ resistor.
DBP
JTAG Test Data Input. Internally pulled up to V
JTAG Test Data Output
with a 10kΩ resistor.
DBP
TDO
Internal Digital Voltage Regulator Output. Connect a 1µF bypass capacitor from DBP to
GND. Do not use DBP to power external circuitry.
34
36
34
36
DBP
ABP
Internal Analog Voltage Regulator Output. Connect a 1µF bypass capacitor from ABP to
GND. Do not use ABP to power external circuitry.
37, 38
41
37, 38
41
V
Device Power Supply. Bypass V to GND with a 1µF capacitor.
CC
CC
CS-
Current-Sense Negative Input. Must be biased between 3V to 28V for proper operation.
Current-Sense Positive Input. Must be biased between 3V to 28V for proper operation.
42
42
CS+
43
—
DXN2 Remote Diode 2 Negative Input. If remote sensing is not used, connect DXP2 to DXN2.
DXP2 Remote Diode 2 Positive Input. If remote sensing is not used, connect DXP2 to DXN2.
DXN1 Remote Diode 1 Negative Input. If remote sensing is not used, connect DXP1 to DXN1.
44
—
45
45
46
46
DXP1
Remote Diode 1 Positive Input. If remote sensing is not used, connect DXP1 to DXN1.
Supply Monitor Input 1. IN1 is internally sampled by the ADC. It is configurable for unipolar/
bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form
the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage
range.
48
—
48
—
IN1
Exposed Paddle. Connect EP to ground. EP is internally connected to GND. Do not use as
the main ground connection.
EP
______________________________________________________________________________________ 11
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Functional Diagram
V
CC
INTERNAL
TEMPERATURE SENSOR
CIRCUITRY
ANALOG
ABP
OSCILLATOR
REGULATOR
DIGITAL
DBP
REGULATOR
IN1
10-BIT
ADC
1.4V INTERNAL
RBP
REFERENCE
INPUT RANGE
SELECTION
FAULT1
/MAX16032
FAULT2
OVERT
RESET
FAULT
COMPARATORS
REGISTERS
INPUT RANGE
SELECTION
IN2
IN3
INPUT RANGE
SELECTION
MULTIPLEXER
GPIO1
GPIO2
INPUT RANGE
SELECTION
IN4
INPUT RANGE
SELECTION
IN5
SDA
SCL
ALERT
A0
INPUT RANGE
SELECTION
IN6
SMBus
SERIAL
INTERFACE
EEPROM
INPUT RANGE
SELECTION
*IN7
*IN8
INPUT RANGE
SELECTION
A1
DXP1
DXN1
EXTERNAL
TEMPERATURE
SENSOR
TMS
TCK
TDI
*DXP2
*DXN2
CIRCUITRY
JTAG
SERIAL
INTERFACE
MAX16031/
MAX16032
CURRENT-SENSE
AMPLIFIER/
COMPARATOR
*CS+
*CS-
TDO
OVERC
*MAX16031 ONLY
12 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 1. Address Map
EEPROM
REGISTER
READ/
WRITE
MEMORY
DESCRIPTION
ADDRESS
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
—
—
R
R
IN1 ADC Result Register (MSB)
IN1 ADC Result Register (LSB)
—
R
IN2 ADC Result Register (MSB)
—
R
IN2 ADC Result Register (LSB)
—
R
IN3 ADC Result Register (MSB)
—
R
IN3 ADC Result Register (LSB)
—
R
IN4 ADC Result Register (MSB)
—
R
IN4 ADC Result Register (LSB)
—
R
IN5 ADC Result Register (MSB)
—
R
IN5 ADC Result Register (LSB)
—
R
IN6 ADC Result Register (MSB)
—
R
IN6 ADC Result Register (LSB)
—
R
IN7 ADC Result Register (MSB)*
—
R
IN7 ADC Result Register (LSB)*
—
R
IN8 ADC Result Register (MSB)*
—
R
IN8 ADC Result Register (LSB)*
—
R
Internal Temperature Sensor ADC Result Register (MSB)
Internal Temperature Sensor ADC Result Register (LSB)
Remote Temperature Sensor 1 ADC Result Register (MSB)
Remote Temperature Sensor 1 ADC Result Register (LSB)
Remote Temperature Sensor 2 ADC Result Register (MSB)
Remote Temperature Sensor 2 ADC Result Register (LSB)
Current-Sense ADC Result Register
—
R
—
R
—
R
—
R
—
R
—
R
97h
98h
99h
9Ah
R/W
R/W
R/W
R/W
Voltage Monitoring Input ADC Range Selection (IN1–IN4)
Voltage Monitoring Input ADC Range Selection (IN5–IN8)
Current-Sense Gain/Primary Threshold and Remote Temperature Sensor 1 Gain Trim
Voltage Monitoring Input Enable
Internal/Remote Temperature Sensor, Current Sense, and ALERT Enables and
Remote Temperature Sensor 1 Offset Trim
1Bh
9Bh
R/W
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
9Ch
9Dh
9Eh
9Fh
A0h
A1h
A2h
A3h
A4h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Voltage Monitoring Input Single-Ended/Differential and Unipolar/Bipolar Selection
FAULT1 Dependency Selection
FAULT2 Dependency Selection
OVERT Dependency Selection
RESET Dependency and Timeout Selection
RESET IN1–IN8 Dependency Selection
GPIO1 Configuration
GPIO1 Dependency Selection
GPIO2 Configuration
______________________________________________________________________________________ 13
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 1. Address Map (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPIO2 Dependency Selection
IN1 Primary Undervoltage Threshold
IN1 Primary Overvoltage Threshold
IN1 Secondary Undervoltage Threshold
IN1 Secondary Overvoltage Threshold
IN2 Primary Undervoltage Threshold
IN2 Primary Overvoltage Threshold
IN2 Secondary Undervoltage Threshold
IN2 Secondary Overvoltage Threshold
IN3 Primary Undervoltage Threshold
IN3 Primary Overvoltage Threshold
IN3 Secondary Undervoltage Threshold
IN3 Secondary Overvoltage Threshold
IN4 Primary Undervoltage Threshold
/MAX16032
IN4 Primary Overvoltage Threshold
IN4 Secondary Undervoltage Threshold
IN4 Secondary Overvoltage Threshold
IN5 Primary Undervoltage Threshold
IN5 Primary Overvoltage Threshold
IN5 Secondary Undervoltage Threshold
IN5 Secondary Overvoltage Threshold
IN6 Primary Undervoltage Threshold
IN6 Primary Overvoltage Threshold
IN6 Secondary Undervoltage Threshold
IN6 Secondary Overvoltage Threshold
IN7 Primary Undervoltage Threshold*
IN7 Primary Overvoltage Threshold*
IN7 Secondary Undervoltage Threshold*
IN7 Secondary Overvoltage Threshold*
IN8 Primary Undervoltage Threshold*
IN8 Primary Overvoltage Threshold*
IN8 Secondary Undervoltage Threshold*
IN8 Secondary Overvoltage Threshold*
Internal Temperature Sensor Primary Overtemperature Threshold (MSB)
Internal Temperature Sensor Secondary Overtemperature Threshold (MSB)
Remote Temperature Sensor 1 Primary Overtemperature Threshold
Remote Temperature Sensor 1 Secondary Overtemperature Threshold
Remote Temperature Sensor 2 Primary Overtemperature Threshold
14 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 1. Address Map (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
READ/
WRITE
DESCRIPTION
4Bh
4Ch
CBh
CCh
R/W
R/W
Remote Temperature Sensor 2 Secondary Overtemperature Threshold
Overcurrent Secondary Threshold
Remote Temperature Sensor Primary/Secondary Overtemperature Threshold (LSBs).
External Temperature Sensor 2 Offset Trim
4Dh
CDh
R/W
4Eh
4Fh
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
60h–7Fh
—
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
D6h
D7h
D8h
D9h
DAh
DBh
DCh
DDh
DEh
DFh
E0h–FFh
80h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Remote Temperature Sensor 1/2 Primary/Secondary Overtemperature Threshold (LSBs)
Remote Temperature Sensor 2 Gain Trim
Remote Temperature Sensor Short/Open Status
IN1–IN8 Primary Threshold Fault Status
IN1–IN8 Secondary Threshold Fault Status
Temperature/Current Threshold Fault Status
Remote Temperature Sensor Short/Open Fault Mask
IN1–IN8 Primary Threshold Fault Mask
IN1–IN8 Secondary Threshold Fault Mask
Temperature/Current Threshold Fault Mask
IN1–IN8 Primary Undervoltage Faults Triggering Fault EEPROM
IN1–IN8 Primary Overvoltage Faults Triggering Fault EEPROM
Temperature/Current Faults Triggering Fault EEPROM
Temperature Filter Selection and Postboot Fault Mask Time
Threshold Fault Options and Overcurrent Fault Timeout
Reserved
R/W
R/W
—
Customer Firmware Version
EEPROM and Configuration Lock
Reserved
R
IN1–IN8 Primary Threshold Fault Status at Time of Fault
IN1–IN8 Secondary Threshold Fault Status at Time of Fault
Temperature/Current Threshold Fault Status at Time of Fault
IN1 Conversion Result at Time of Fault
—
81h
R
—
82h
R
—
83h
R
—
84h
R
IN2 Conversion Result at Time of Fault
—
85h
R
IN3 Conversion Result at Time of Fault
—
86h
R
IN4 Conversion Result at Time of Fault
—
87h
R
IN5 Conversion Result at Time of Fault
—
88h
R
IN6 Conversion Result at Time of Fault
—
89h
R
IN7 Conversion Result at Time of Fault*
—
8Ah
8Bh
8Ch
8Dh
8Eh
R
IN8 Conversion Result at Time of Fault*
—
R
Internal Temperature Sensor Conversion Result at Time of Fault
Remote Temperature Sensor 1 Conversion Result at Time of Fault
Remote Temperature Sensor 2 Conversion Result at Time of Fault*
Current-Sense Conversion Result at Time of Fault*
—
R
—
R
—
R
*MAX16031 only.
______________________________________________________________________________________ 15
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
lates a programmed threshold, the conversion is config-
Detailed Description
ured to generate a fault. Logic outputs are programmed
to depend on many combinations of faults. Additionally,
faults are programmed to trigger a fault log, whereby all
fault information is automatically written to EEPROM.
Getting Started
The MAX16031/MAX16032 contain both I2C/SMBus and
JTAG serial interfaces for accessing registers and
EEPROM. Use only one interface at any given time. For
more information on how to access the internal memory
through these interfaces, see the I2C/SMBus-Compatible
Serial Interface and JTAG Serial Interface sections. This
data sheet uses a specific convention for referring to bits
within a particular address location. As an example,
r15h[3:0] refers to bits 3 through 0 in register with
address 15 hexadecimal.
Voltage Monitoring
The MAX16031 provides eight inputs, IN1–IN8, for volt-
age monitoring. The MAX16032 provides six inputs,
IN1–IN6, for voltage monitoring. Each input voltage
range is programmable through r17h[7:0] and r18h[7:0]
(see Table 2). Voltage monitoring for each input is
enabled through r1Ah[7:0] (see Table 2). There are four
programmable thresholds per voltage monitor input: pri-
mary undervoltage, secondary undervoltage, primary
overvoltage, and secondary overvoltage. All voltage
thresholds are 8 bits wide. Only the 8 most significant
bits of the conversion result are compared to the
thresholds. See the Miscellaneous Settings section to
set the amount of hysteresis for the thresholds. See
Table 1 for an address map of all voltage monitor input
threshold registers.
The factory-default values at power-on reset (POR) for all
EEPROM locations are zeros. POR occurs when V
CC
reaches the undervoltage lockout (UVLO) of 2.8V. At
POR, the device begins a boot-up sequence. During the
boot-up sequence, all monitored inputs are masked from
initiating faults and EEPROM contents are copied to the
respective register locations. The boot-up sequence
takes up to 1.81ms. Monitoring is disabled for up to 16s
past the boot-up sequence by programming r5Bh[3:0]
(see the Miscellaneous Settings section). RESET is low
during boot-up and remains low after boot-up for its pro-
grammed timeout period after all monitored channels are
within their respective thresholds.
/MAX16032
ADC inputs are configurable for two different modes:
pseudo-differential and single-ended (see Table 3). In
pseudo-differential mode, two inputs make up a differ-
ential pair. Psuedo-differential conversions are per-
formed by taking a single-ended conversion at each
input of a differential pair and then subtracting the
results. The pseudo-differential mode is selectable for
unipolar or bipolar operation. Unipolar differential oper-
ation allows only positive polarities of differential volt-
ages. Bipolar differential operation allows negative and
positive polarities of differential voltages. Bipolar con-
versions are in two’s complement format. For example,
The MAX16031/MAX16032 monitor up to eight voltages,
up to one current, and up to three temperatures. After
boot-up, an internal multiplexer cycles through each
input. At each multiplexer stop, the 10-bit ADC converts
the analog parameter to a digital result and stores the
result in a register. Each time the multiplexer completes a
cycle, internal logic compares the conversion results to
the thresholds stored in memory. When a conversion vio-
Table 2. Input Monitor Ranges and Enables
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
IN1 Voltage Range Selection:
[1:0]
[3:2]
[5:4]
[7:6]
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
IN2 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
17h
97h
IN3 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
IN4 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
16 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 2. Input Monitor Ranges and Enables (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
[1:0]
[3:2]
[5:4]
[7:6]
[0]
DESCRIPTION
IN5 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
IN6 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
18h
98h
IN7 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
IN8 Voltage Range Selection:
00 = 5.6V, 01 = 2.8V
10 = 1.4V, 11 = Reserved
IN1 Monitoring Enable:
0 = IN1 monitoring disabled
1 = IN1 monitoring enabled
IN2 Monitoring Enable:
0 = IN2 monitoring disabled
1 = IN2 monitoring enabled
[1]
IN3 Monitoring Enable:
0 = IN3 monitoring disabled
1 = IN3 monitoring enabled
[2]
IN4 Monitoring Enable:
0 = IN4 monitoring disabled
1 = IN4 monitoring enabled
[3]
1Ah
9Ah
IN5 Monitoring Enable:
0 = IN5 monitoring disabled
1 = IN5 monitoring enabled
[4]
IN6 Monitoring Enable:
0 = IN6 monitoring disabled
1 = IN6 monitoring enabled
[5]
IN7 Monitoring Enable:
0 = IN7 monitoring disabled
1 = IN7 monitoring enabled
[6]
IN8 Monitoring Enable:
0 = IN8 monitoring disabled
1 = IN8 monitoring enabled
[7]
______________________________________________________________________________________ 17
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
a -1V differential input (range of 5.6V) gives a decimal
code of -183, which is 1101001001 in two’s comple-
ment binary form. In single-ended mode, conversions
are performed between a single input and ground.
When single-ended mode is selected, conversions are
always unipolar regardless of r1Ch[7:4]. The single-
ended and pseudo-differential ADC mode equations
are shown below.
where X
is the resulting code in decimal, V is the
ADC IN
voltage at a voltage monitoring input, and V
is
RANGE
the selected range programmed in r17h and r18h.
Bipolar/unipolar pseudo-differential mode:
⎛
⎞
⎛
⎞
V
V
IN−
V
REF
IN+
X
=INT
× 1024 − INT
× 1024
ADC
⎜
⎟
⎜
⎟
V
⎝
⎠
⎝
⎠
REF
Unipolar single-ended mode:
where X
is the resulting code in decimal, V
is the
ADC
IN+
⎛
⎞
V
voltage at a positive input of a differential voltage moni-
toring input pair, V is the voltage at a negative input of
IN−
X
=INT
× 1024
ADC
⎜
⎟
IN-
V
⎝
⎠
REF
a differential voltage monitoring input pair, and V
is the selected range programmed in r17h and r18h.
RANGE
Table 3. IN1–IN8 ADC Input Mode Selection
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
/MAX16032
IN1/IN2 Single-Ended/Pseudo-Differential:
0 = IN1 and IN2 conversions are single-ended.
1 = IN1 and IN2 conversions are pseudo-differential (IN1 to IN2).
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
IN3/IN4 Single-Ended/Pseudo-Differential:
0 = IN3 and IN4 conversions are single-ended.
1 = IN3 and IN4 conversions are pseudo-differential (IN3 to IN4).
IN5/IN6 Single-Ended/Pseudo-Differential:
0 = IN5 and IN6 conversions are single-ended.
1 = IN5 and IN6 conversions are pseudo-differential (IN5 to IN6).
IN7/IN8 Single-Ended/Pseudo-Differential:
0 = IN7 and IN8 conversions are single-ended.
1 = IN7 and IN8 conversions are pseudo-differential (IN7 to IN8).
1Ch
9Ch
IN1/IN2 Unipolar/Bipolar:
0 = IN1 and IN2 conversions are unipolar.
1 = IN1 and IN2 conversions are bipolar (two’s complement).
IN3/IN4 Unipolar/Bipolar:
0 = IN3 and IN4 conversions are unipolar.
1 = IN3 and IN4 conversions are bipolar (two’s complement).
IN5/IN6 Unipolar/Bipolar:
0 = IN5 and IN6 conversions are unipolar.
1 = IN5 and IN6 conversions are bipolar (two’s complement).
IN7/IN8 Unipolar/Bipolar:
0 = IN7 and IN8 conversions are unipolar.
1 = IN7 and IN8 conversions are bipolar (two’s complement).
18 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
of the sense resistor. See Table 4 for a description of
r19h. The ADC output for a current-sense conversion is:
Current Monitoring
The MAX16031 provides current-sense inputs CS+/CS-
and a current-sense amplifier for current monitoring
(see Figure 3). There are two programmable current-
sense thresholds: primary overcurrent and secondary
overcurrent. For fast fault detection, the primary over-
current threshold is implemented with an analog com-
parator connected to the OVERC output. The primary
threshold equation is:
V
× A
V
8
SENSE
X
=
× 2 − 1
ADC
(
)
V
RBP
where X
CS+
by r19h[1:0], and V
(1.4V typical).
is the 8-bit decimal ADC result, V
is
ADC
SENSE
V
- V , A is the current-sense voltage gain set
CS- V
is the reference voltage at RBP
RBP
V
CSTH
I
=
TH
R
OVERC is latched when the primary overcurrent thresh-
old is exceeded by programming r5Ch[4]. The latch is
cleared by writing a ‘1’ to r53h[6]. OVERC depends
only on the primary overcurrent threshold. Other fault
outputs are programmed to depend on the secondary
overcurrent threshold. The secondary overcurrent
threshold is implemented through ADC conversions
and digital comparisons. The secondary overcurrent
threshold contains programmable time delay options
located in r5Ch[1:0]. Primary and secondary current-
sense faults are enabled/disabled through r1Bh[3].
SENSE
where I
is the current threshold to be set, V
is
TH
CSTH
is the value
the threshold set by r19h[1:0], and R
SENSE
V
MON
CS+
CS-
-
TO ADC MUX
*A
V
+
R
SENSE
Temperature Monitoring
The MAX16031 provides two sets of remote diode inputs,
DXP1/DXN1 and DXP2/DXN2, and one internal tempera-
ture sensor. The MAX16032 provides one set,
DXP1/DXN1, and one internal temperature sensor.
Calibration registers provide adjustments for gain and off-
set to accommodate different types of remote diodes.
The internal temperature sensor circuitry is factory
trimmed. In addition to offset/gain trimming, a program-
mable lowpass filter is provided. See Figure 4 for the
block diagram of the temperature sensor circuitry. The
remote diode is actually a diode-connected transistor.
See Application Notes AN1057 and AN1944 for informa-
tion on error budget and several transistor manufacturers.
V
L
MAX16031
LOAD
-
+
OVERC
+
-
*V
CSTH
*ADJUSTABLE BY r19h [1:0]
Figure 3. Current-Sense Block Diagram
Table 4. Overcurrent Primary Threshold and Remote Temperature Sense Gain Trim
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
Overcurrent Primary Threshold and Current-Sense Gain Setting:
00 = 200mV threshold, A = 6V/V
V
[1:0]
01 = 100mV threshold, A = 12V/V
V
19h
4Fh
99h
CFh
10 = 50mV threshold, A = 24V/V
V
11 = 25mV threshold, A = 48V/V
V
[7:2]
[5:0]
[7:6]
Remote Temperature Sensor 1 Gain Trim. Note bit 6 is inverted.
Remote Temperature Sensor 1 Gain Trim
Not used
______________________________________________________________________________________ 19
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 5. Temperature Data Format
ABP
TEMPERATURE (°C)
DIGITAL CODE
1100000000
1011111010
1011010000
1000110011
1000000000
0111101100
0101101010
0100111000
0100000000
0000000000
+128
+125
+100
+25.5
0
I
I
HIGH
LOW
DXP_
DXN_
-
TO ADC MUX
-10
+
V
~ 100mV
BIAS
-75
-100
I
BIAS
-128
Diode fault
ABP
Reading ADC Results
Figure 4. Remote Temperature Sensor Amplifier Circuitry
ADC conversion results are read from the ADC conver-
sion registers through the I2C/SMBus-compatible or
JTAG interfaces (see Table 7). These registers are also
used for fault threshold comparison. Voltage monitoring
thresholds are compared with only the first 8 MSBs of
the conversion results.
The ADC converts the internal sensor and remote sen-
sor amplifier outputs. Each time the ADC converts all
enabled parameters, the temperature conversions are
compared to the temperature threshold registers (r46h
to r4Bh and r4Dh). Unlike the voltage input compara-
tors, the temperature threshold comparators are 10 bits
wide. OVERT is the designated output for temperature
faults, although other outputs are programmed to
depend on temperature faults as well. See the
Programmable Inputs/Outputs section for more informa-
tion on programming output dependencies. See the
Faults section for more information on setting tempera-
ture fault thresholds.
/MAX16032
Programmable Inputs/Outputs
The MAX16031 provides two general fault outputs,
FAULT1 and FAULT2, one reset output RESET, one
temperature fault output OVERT, one current fault out-
put OVERC, two general-purpose inputs/outputs GPIO1
and GPIO2, and one SMBALERT#-compatible output
ALERT. The MAX16032 provides the same except
OVERC. All outputs are open drain and require pullup
resistors. Fault outputs do not latch except for OVERC,
which either latches or does not latch depending on the
configuration bit in r5Ch. Individual fault flag bits, how-
ever, latch (see the Faults section) and must be cleared
one bit at a time by writing a byte containing all zeros
except for a single ‘1’ in the bit to be cleared.
The remote temperature sensor amplifier detects a
short or open between DXP_ and DXN_. The detection
of these events is programmed to cause a fault.
Temperature thresholds and conversions are in a two’s
complement temperature format, where 1 LSB corre-
sponds to 0.5°C. The data format for temperature con-
versions is illustrated in Table 5.
The general outputs, FAULT1 and FAULT2, are identi-
cal in functionality and are programmed to depend on
overvoltage, undervoltage, overtemperature, and over-
current parameters. See r1Dh and r1Eh in Table 8 for
more detailed information regarding the general fault
output dependencies.
Offset and gain errors for remote temperature sensor
measurements are user-trimmed through gain registers
r19h[7:2]/r4Fh[5:0] and offset registers r1Bh[7:5]/r4D[6:4],
as shown in Tables 4 and 6. The gain value trims the
high (56µA) drive current source to compensate for the
n-factor of the remote diode. The offset value is multi-
plied by 4 and added to the conversion result numeri-
cally. The MAX16031/MAX16032 contain an internal
lowpass filter at DXN_ and DXP_ to reduce noise. See
the Miscellaneous Settings section for more information
on programming the filter cutoff frequency.
The reset output RESET provides many programmable
output dependencies as well as reset timeouts. See
r20h and r21h in Table 8 for detailed information on
RESET output dependencies and timeouts.
The temperature fault output OVERT indicates tempera-
ture-related faults. OVERT is programmed to depend
on any primary temperature threshold and/or the
remote diode open/short flags. OVERT latches low dur-
20 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 6. Temperature Sensor Fault Enable, Current-Sense Fault Enable, SMBALERT#
Enable, and Temperature Offset Trim
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
Internal Temperature Sensor Faults Enable:
0 = Internal temperature sensor faults disabled
1 = Internal temperature sensor faults enabled
[0]
[1]
[2]
[3]
[4]
Remote Temperature Sensor 1 Faults Enable:
0 = Remote temperature sensor 1 faults disabled
1 = Internal temperature sensor 1 faults enabled
Remote Temperature Sensor 2 Faults Enable:
0 = Remote temperature sensor 2 faults disabled
1 = Remote temperature sensor 2 faults enabled
1Bh
9Bh
Current-Sense Fault Enable:
0 = Current-sense faults disabled
1 = Current-sense faults enabled
SMBALERT# Enable (ALERT):
0 = SMBALERT# disabled
1 = SMBALERT# enabled
Remote Temperature Sensor 1 Offset Trim:
Offset = 4 × X, where X is the two’s-complement 3-bit temperature code
(1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C,
allowing a total offset adjustment of 6°C.
[7:5]
[1:0]
[3:2]
Internal Temperature Sensor Primary Overtemperature Threshold LSB
Internal Temperature Sensor Secondary Overtemperature Threshold LSB
Remote Temperature Sensor 2 Offset Trim:
4Dh
CDh
Offset = 4 × X, where X is the two’s-complement 3-bit temperature code
(1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C,
allowing a total offset adjustment of 6°C.
[6:4]
[7]
Not used.
ing diode open/short fault conditions, and the corre-
sponding diode open/short flags must be cleared to
release the latch. See r1Fh in Table 8 for more informa-
tion on OVERT output dependencies.
outputs. See r22h–r25h in Table 8 for more detailed
information on GPIO1/GPIO2 functionality. GPIO1 and
GPIO2 assert low when configured as a fault output.
ALERT is an SMBALERT#-compatible fault interrupt
output. When enabled, it is logically ANDed with out-
puts RESET, FAULT1, FAULT2, OVERT, OVERC, and
GPIO1/GPIO2 (only if enabled as fault outputs). When
any fault output is asserted, ALERT also asserts, inter-
rupting the SMBus master to query the fault. The mas-
ter needs to answer MAX16031/MAX16032 with a
specific SMBus command (ARA) to retrieve the slave
address of the interrupting device. See the I2C/SMBus-
Compatible Serial Interface section for more details.
The current fault output OVERC indicates overcurrent
events. OVERC only depends on the primary analog
overcurrent threshold. See the Current Monitoring sec-
tion for more information about the current-sense amplifi-
er and the primary threshold. The secondary overcurrent
threshold is set digitally and is used by other outputs.
The secondary threshold also has a programmable time-
out option (see Miscellaneous Settings section).
GPIO1 and GPIO2 are programmable as logic inputs,
manual reset inputs, logic outputs, or fault dependent
______________________________________________________________________________________ 21
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 7. ADC Conversion Registers
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
[1:0]
[7:2]
[7:0]
IN1 ADC Conversion Result (MSB)
IN1 ADC Conversion Result (LSB)
Reserved
IN2 ADC Conversion Result (MSB)
IN2 ADC Conversion Result (LSB)
Reserved
IN3 ADC Conversion Result (MSB)
IN3 ADC Conversion Result (LSB)
Reserved
IN4 ADC Conversion Result (MSB)
IN4 ADC Conversion Result (LSB)
Reserved
IN5 ADC Conversion Result (MSB)
IN5 ADC Conversion Result (LSB)
Reserved
/MAX16032
IN6 ADC Conversion Result (MSB)
IN6 ADC Conversion Result (LSB)
Reserved
IN7 ADC Conversion Result (MSB)
IN7 ADC Conversion Result (LSB)
Reserved
IN8 ADC Conversion Result (MSB)
IN8 ADC Conversion Result (LSB)
Reserved
Internal Temperature Sensor ADC Conversion Result (MSB)
Internal Temperature Sensor ADC Conversion Result (LSB)
Reserved
Remote Temperature Sensor 1 ADC Conversion Result (MSB)
Remote Temperature Sensor 1 ADC Conversion Result (LSB)
Reserved
Remote Temperature Sensor 2 ADC Conversion Result (MSB)
Remote Temperature Sensor 2 ADC Conversion Result (LSB)
Reserved
Current-Sense ADC Conversion Result
22 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 8. Output Dependencies
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
[0]
[1]
[2]
1 = FAULT1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8.
1 = FAULT1 depends on the primary overvoltage thresholds of all enabled IN1–IN8.
1 = FAULT1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8.
1 = FAULT1 depends on the secondary overtemperature threshold of the internal
temperature sensor.
[3]
[4]
[5]
1Dh
9Dh
1 = FAULT1 depends on the secondary overtemperature threshold of remote
temperature sensor 1.
1 = FAULT1 depends on the secondary overtemperature threshold of remote
temperature sensor 2.
[6]
[7]
[0]
[1]
[2]
1 = FAULT1 depends on the secondary overcurrent threshold.
Reserved
1 = FAULT2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8.
1 = FAULT2 depends on the primary overvoltage thresholds of all enabled IN1–IN8.
1 = FAULT2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8.
1 = FAULT2 depends on the secondary overtemperature threshold of the internal
temperature sensor.
[3]
[4]
[5]
1Eh
9Eh
1 = FAULT2 depends on the secondary overtemperature threshold of remote
temperature sensor 1.
1 = FAULT2 depends on the secondary overtemperature threshold of remote
temperature sensor 2.
[6]
[7]
1 = FAULT2 depends on the secondary overcurrent threshold.
Reserved
1 = OVERT depends on the primary overtemperature threshold of the internal
temperature sensor.
[0]
[1]
[2]
1 = OVERT depends on the primary overtemperature threshold of the remote
temperature sensor 1.
1Fh
9Fh
1 = OVERT depends on the primary overtemperature threshold of the remote
temperature sensor 2.
______________________________________________________________________________________ 23
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 8. Output Dependencies (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT RANGE
DESCRIPTION
1 = OVERT depends on the diode short flag of remote temperature sensor 1. OVERT
latches when the diode is shorted. Clear the latch by writing to r50h.
[3]
[4]
[5]
1 = OVERT depends on the diode open flag of remote temperature sensor 1. OVERT
latches when the diode is open. Clear the latch by writing to r50h.
1Fh
9Fh
1 = OVERT depends on the diode short flag of remote temperature sensor 2. OVERT
latches when the diode is shorted. Clear the latch by writing to r50h.
1 = OVERT depends on the diode open flag of remote temperature sensor 2. OVERT
latches when the diode is open. Clear the latch by writing to r50h.
[6]
[7]
Reserved
RESET Configuration:
000 = RESET has no dependencies; asserts during boot and boot-up timeout and then
deasserts indefinitely.
001 = RESET depends on the primary undervoltage thresholds at inputs that are
selected by r21h[7:0].
/MAX16032
010 = RESET depends on the primary overvoltage thresholds at inputs that are selected
by r21h[7:0].
011 = RESET depends on both the primary undervoltage and overvoltage thresholds at
those inputs that are selected by r21h[7:0].
100 = RESET depends on the primary undervoltage thresholds at inputs that are
selected by r21h[7:0] and the internal temperature sensor primary overtemperature
threshold.
[2:0]
101 = RESET depends on both the primary undervoltage and overvoltage thresholds at
those inputs that are selected by r21h[7:0] and the internal temperature sensor primary
overtemperature threshold.
110 = RESET depends on the primary undervoltage thresholds at inputs that are
selected by r21h[7:0] and each internal/remote temperature sensor primary
overtemperature threshold.
20h
A0h
111 = RESET depends on both the primary undervoltage and overvoltage thresholds at
those inputs that are selected by r21h[7:0] and each internal/remote temperature sensor
primary overtemperature threshold.
RESET Timeout:
000 = 25µs
001 = 2.5ms
010 = 10ms
[5:3]
[7:6]
011 = 40ms
100 = 160ms
101 = 640ms
110 = 1280ms
111 = 2560ms
Reserved
24 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 8. Output Dependencies (continued)
EEPROM
MEMORY BIT RANGE
ADDRESS
REGISTER
ADDRESS
DESCRIPTION
[0]
[1]
[2]
1 = RESET depends on IN1 with thresholds defined by r20h[2:0].
1 = RESET depends on IN2 with thresholds defined by r20h[2:0].
1 = RESET depends on IN3 with thresholds defined by r20h[2:0].
1 = RESET depends on IN4 with thresholds defined by r20h[2:0].
1 = RESET depends on IN5 with thresholds defined by r20h[2:0].
1 = RESET depends on IN6 with thresholds defined by r20h[2:0].
1 = RESET depends on IN7 with thresholds defined by r20h[2:0].
1 = RESET depends on IN8 with thresholds defined by r20h[2:0].
[3]
21h
A1h
[4]
[5]
[6]
[7]
GPIO1 Output Dependencies:
000 = GPIO1 is a digital input that is read from r22h[7].
001 = GPIO1 is a digital manual reset input that asserts RESET when asserted. The state
of GPIO1 is read from r22h[7].
010 = GPIO1 is a digital output that is written to through r22h[6].
011 = GPIO1 is a digital fault output that depends on conditions selected by r23h[6:0].
100 = GPIO1 is a digital output that depends on primary thresholds at the input selected
by r22h[5:3].
[2:0]
101 =GPIO1 is a digital output that depends on primary thresholds at the input selected
by r22h[5:3] and on conditions selected by r23h[6:0].
110 = Reserved
111 = Reserved
GPIO1 Single-Input Primary Threshold Voltage Monitor (r22h[2:0] = 100 or 101 only).
GPIO1 asserts low when any primary threshold of this input is exceeded:
22h
A2h
000 = IN1
001 = IN2
010 = IN3
011 = IN4
100 = IN5
101 = IN6
110 = IN7
111 = IN8
[5:3]
GPIO1 Output (write to this bit):
[6]
[7]
1 = GPIO1 is set high if GPIO1 is configured as an output.
0 = GPIO1 is set low if GPIO1 is configured as an output.
GPIO1 Input State (read from this bit):
1 = Indicates that GPIO1 is high regardless if GPIO1 is set as an output or input.
0 = Indicates that GPIO1 is low regardless if GPIO1 is set as an output or input.
______________________________________________________________________________________ 25
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 8. Output Dependencies (continued)
EEPROM
MEMORY BIT RANGE
ADDRESS
REGISTER
ADDRESS
DESCRIPTION
[0]
[1]
[2]
1 = GPIO1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8.
1 = GPIO1 depends on the primary overvoltage thresholds of all enabled IN1–IN8.
1 = GPIO1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8.
1 = GPIO1 depends on the secondary overtemperature threshold of the internal
temperature sensor.
[3]
23h
A3h
[4]
1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature
sensor 1.
1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature
sensor 2.
[5]
[6]
[7]
1 = GPIO1 depends on the secondary overcurrent threshold.
Reserved
GPIO2 Output Dependencies:
000 = GPIO2 is a digital input that is read from r24h[7].
001 = GPIO2 is a digital manual reset input that asserts RESET when asserted. The state
of GPIO2 is read from r24h[7].
/MAX16032
010 = GPIO2 is a digital output that is written to through r24h[6].
011 = GPIO2 is a digital fault output that depends on conditions selected by r25h[6:0].
100 = GPIO2 is a digital output that depends on primary thresholds at the input selected
by r24h[5:3].
[2:0]
101 = GPIO2 is a digital output that depends on primary thresholds at the input selected
by r24h[5:3] and on conditions selected by r25h[6:0].
110 = Reserved
111 = Reserved
GPIO2 Single-Input Primary Threshold Voltage Monitor (r24h[2:0] = 100 or 101 only).
GPIO2 asserts low when the primary threshold of this input is exceeded:
24h
A4h
000 = IN1
001 = IN2
010 = IN3
011 = IN4
100 = IN5
101 = IN6
110 = IN7
111 = IN8
[5:3]
GPIO2 Output (write to this bit):
[6]
[7]
1 = GPIO2 is set high if GPIO2 is configured as an output.
0 = GPIO2 is set low if GPIO2 is configured as an output.
GPIO2 Input (read from this bit):
1 = Indicates that GPIO2 is high regardless if GPIO2 is set as an output or input.
0 = Indicates that GPIO2 is low regardless if GPIO2 is set as an output or input.
26 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 8. Output Dependencies (continued)
EEPROM
MEMORY BIT RANGE
ADDRESS
REGISTER
ADDRESS
DESCRIPTION
[0]
[1]
[2]
1 = GPIO2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8.
1 = GPIO2 depends on the primary overvoltage thresholds of all enabled IN1–IN8.
1 = GPIO2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8.
1 = GPIO2 depends on the secondary overtemperature threshold of the internal
temperature sensor.
[3]
25h
A5h
[4]
1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature
sensor 1.
1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature
sensor 2.
[5]
[6]
[7]
1 = GPIO2 depends on the secondary overcurrent threshold.
Reserved
in r54h–r57h, as shown in Table 10. Fault flags indicate
the fault status of a particular input. The fault flag of any
monitored input in the device can be read at any time
from r50h–r53h, as shown in Table 11. Clear a fault flag
by writing a ‘1’ to the appropriate bit in the flag register.
Faults
The MAX16031/MAX16032 offer many configurable
options for detecting and managing system faults. Fault
thresholds are set in r26h–r4Eh, as shown in Table 9.
Any threshold that is configured to cause a fault can be
masked at any time from causing a fault by setting bits
Table 9. Fault Thresholds
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
IN1 Primary Undervoltage Threshold
IN1 Primary Overvoltage Threshold
IN1 Secondary Undervoltage Threshold
IN1 Secondary Overvoltage Threshold
IN2 Primary Undervoltage Threshold
IN2 Primary Overvoltage Threshold
IN2 Secondary Undervoltage Threshold
IN2 Secondary Overvoltage Threshold
IN3 Primary Undervoltage Threshold
IN3 Primary Overvoltage Threshold
IN3 Secondary Undervoltage Threshold
IN3 Secondary Overvoltage Threshold
IN4 Primary Undervoltage Threshold
IN4 Primary Overvoltage Threshold
______________________________________________________________________________________ 27
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 9. Fault Thresholds (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
41h
42h
43h
44h
45h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C0h
C1h
C2h
C3h
C4h
C5h
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
IN4 Secondary Undervoltage Threshold
IN4 Secondary Overvoltage Threshold
IN5 Primary Undervoltage Threshold
IN5 Primary Overvoltage Threshold
IN5 Secondary Undervoltage Threshold
IN5 Secondary Overvoltage Threshold
IN6 Primary Undervoltage Threshold
IN6 Primary Overvoltage Threshold
IN6 Secondary Undervoltage Threshold
IN6 Secondary Overvoltage Threshold
IN7 Primary Undervoltage Threshold
IN7 Primary Overvoltage Threshold
IN7 Secondary Undervoltage Threshold
IN7 Secondary Overvoltage Threshold
IN8 Primary Undervoltage Threshold
IN8 Primary Overvoltage Threshold
IN8 Secondary Undervoltage Threshold
IN8 Secondary Overvoltage Threshold
/MAX16032
Internal Temperature Sensor Primary Overtemperature Threshold MSB (2 LSBs are in
r4Dh[1:0]).
46h
47h
48h
49h
4Ah
C6h
C7h
C8h
C9h
CAh
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Internal Temperature Sensor Secondary Overtemperature Threshold MSB (2 LSBs are
in r4Dh[3:2]).
Remote Temperature Sensor 1 Primary Overtemperature Threshold MSB (2 LSBs are
in r4Eh[1:0]).
Remote Temperature Sensor 1 Secondary Overtemperature Threshold MSB (2 LSBs
are in r4Eh[3:2]).
Remote Temperature Sensor 2 Primary Overtemperature Threshold MSB (2 LSBs are
in r4Eh[5:4]).
Remote Temperature Sensor 2 Secondary Overtemperature Threshold MSB (2 LSBs
are in r4Eh[7:6]).
4Bh
4Ch
CBh
CCh
[7:0]
[1:0]
[3:2]
[6:4]
[7]
Current-Sense Secondary Threshold
Internal Temperature Sensor Primary Overtemperature Threshold LSB
Internal Temperature Sensor Secondary Overtemperature Threshold LSB
Remote Temperature Sensor 2, Offset Trim
4Dh
4Eh
CDh
CEh
Not used
[1:0]
[3:2]
[5:3]
[7:6]
Remote Temperature Sensor 1 Primary Overtemperature Threshold LSB
Remote Temperature Sensor 1 Secondary Overtemperature Threshold LSB
Remote Temperature Sensor 2 Primary Overtemperature Threshold LSB
Remote Temperature Sensor 2 Secondary Overtemperature Threshold LSB
28 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 10. Fault Masks
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
1 = Short-circuit detection at remote temperature sensor 1 is masked.
1 = Open-circuit detection at remote temperature sensor 1 is masked.
1 = Short-circuit detection at remote temperature sensor 2 is masked.
1 = Open-circuit detection at remote temperature sensor 2 is masked.
Not used.
54h
55h
D4h
D5h
1 = IN1 primary overvoltage and undervoltage faults are masked.
1 = IN2 primary overvoltage and undervoltage faults are masked.
1 = IN3 primary overvoltage and undervoltage faults are masked.
1 = IN4 primary overvoltage and undervoltage faults are masked.
1 = IN5 primary overvoltage and undervoltage faults are masked.
1 = IN6 primary overvoltage and undervoltage faults are masked.
1 = IN7 primary overvoltage and undervoltage faults are masked.
1 = IN8 primary overvoltage and undervoltage faults are masked.
1 = IN1 secondary overvoltage and undervoltage faults are masked.
1 = IN2 secondary overvoltage and undervoltage faults are masked.
1 = IN3 secondary overvoltage and undervoltage faults are masked.
1 = IN4 secondary overvoltage and undervoltage faults are masked.
1 = IN5 secondary overvoltage and undervoltage faults are masked.
1 = IN6 secondary overvoltage and undervoltage faults are masked.
1 = IN7 secondary overvoltage and undervoltage faults are masked.
1 = IN1 secondary overvoltage and undervoltage faults are masked.
1 = Internal temperature sensor primary overtemperature fault masked.
1 = Remote temperature sensor 1 primary overtemperature fault masked.
1 = Remote temperature sensor 2 primary overtemperature fault masked.
1 = Internal temperature sensor secondary overtemperature fault masked.
1 = Remote temperature sensor 1 secondary overtemperature fault masked.
1 = Remote temperature sensor 2 secondary overtemperature fault masked.
1 = Current-sense primary overcurrent fault masked.
56h
D6h
57h
D7h
1 = Current-sense secondary overcurrent fault masked.
______________________________________________________________________________________ 29
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 11. Fault Flags
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[7:4]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
1 = Short circuit detected at remote temperature sensor 1.
1 = Open circuit detected at remote temperature sensor 1.
50h
51h
D0h
D1h
1 = Short circuit detected at remote temperature sensor 2.
1 = Open circuit detected at remote temperature sensor 2.
Not used.
1 = IN1 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN2 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN3 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN4 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN5 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN6 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN7 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN8 conversion result exceeds primary overvoltage or undervoltage thresholds.
1 = IN1 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN2 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN3 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN4 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN5 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN6 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN7 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = IN8 conversion result exceeds secondary overvoltage or undervoltage thresholds.
1 = Internal temperature sensor conversion exceeds its primary overtemperature threshold.
1 = Remote temperature sensor 1 conversion exceeds its primary overtemperature threshold.
1 = Remote temperature sensor 2 conversion exceeds its primary overtemperature threshold.
1 = Internal temperature sensor conversion exceeds its secondary overtemperature threshold.
/MAX16032
52h
D2h
1 = Remote temperature sensor 1 conversion exceeds its secondary overtemperature
threshold.
[4]
[5]
53h
D3h
1 = Remote temperature sensor 2 conversion exceeds its secondary overtemperature
threshold.
[6]
[7]
1 = Current-sense conversion exceeds its primary overcurrent threshold.
1 = Current-sense conversion exceeds its secondary overcurrent threshold.
30 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 12. Fault Log Dependency
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[7:4]
1 = Fault log triggered when IN1 is below its primary undervoltage threshold.
1 = Fault log triggered when IN2 is below its primary undervoltage threshold.
1 = Fault log triggered when IN3 is below its primary undervoltage threshold.
1 = Fault log triggered when IN4 is below its primary undervoltage threshold.
1 = Fault log triggered when IN5 is below its primary undervoltage threshold.
1 = Fault log triggered when IN6 is below its primary undervoltage threshold.
1 = Fault log triggered when IN7 is below its primary undervoltage threshold.
1 = Fault log triggered when IN8 is below its primary undervoltage threshold.
1 = Fault log triggered when IN1 is above its primary overvoltage threshold.
1 = Fault log triggered when IN2 is above its primary overvoltage threshold.
1 = Fault log triggered when IN3 is above its primary overvoltage threshold.
1 = Fault log triggered when IN4 is above its primary overvoltage threshold.
1 = Fault log triggered when IN5 is above its primary overvoltage threshold.
1 = Fault log triggered when IN6 is above its primary overvoltage threshold.
1 = Fault log triggered when IN7 is above its primary overvoltage threshold.
1 = Fault log triggered when IN8 is above its primary overvoltage threshold.
1 = Fault log triggered when current sense is above its primary overcurrent threshold.
1 = Fault log triggered when internal temperature sensor is above its overtemperature threshold.
1 = Fault log triggered when remote temperature sensor 1 is above its overtemperature threshold.
1 = Fault log triggered when remote temperature sensor 2 is above its overtemperature threshold.
Not used.
58h
D8h
59h
D9h
DAh
5Ah
Fault Logging
remote temperature sensor filter cutoff settings.
Register r5Ch[1:0] sets the secondary overcurrent
threshold timeout, which is the amount of delay after an
overcurrent condition before the overcurrent condition
becomes a fault. All voltage thresholds include two
selectable hysteresis options programmed by r5Ch[5].
When r5Ch[6] = 1, the conditions programmed to
cause a fault log event must happen for two consecu-
tive ADC cycles rather than just one to provide an
improvement in noise immunity. Register r5Ch[7] con-
trols whether the ADC result registers are stored in
EEPROM after a fault log. Register r5Eh provides stor-
age space for a user-defined configuration or firmware
version number. Register r5Fh[0] locks and unlocks the
EEPROM and register set. Register r5Fh[1] indicates
whether a fault log event occurred and the correspond-
ing fault information is locked in EEPROM. Further fault
log conditions will not write new fault information to the
fault EEPROM until a ‘1’ is written to r5Fh[1].
If a specific input threshold is critical to the operation of
the system, an automatic fault log is configured to trig-
ger a transfer of fault information to EEPROM. The fault
log dependencies are configured through r58h–r5Ah,
as shown in Table 12. Logged fault information is read
from EEPROM locations r80h–r8Eh, as shown in Table
13. Once a fault log event occurs, the fault log feature
is locked and must be reset to enable a new fault log to
be stored. Write a ‘1’ to r5Fh[1] to reset the fault log.
Fault information always contains the fault flag registers
and is configured to also include the ADC result regis-
ters through r5Ch[7] (see the Miscellaneous Settings
section). All stored ADC results are the 8 MSBs of the
result.
Miscellaneous Settings
Table 14 shows several miscellaneous programmable
items. Register r5Bh contains boot-up timeout and
______________________________________________________________________________________ 31
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 13. Fault Log EEPROM
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
—
—
—
—
—
—
—
—
—
—
—
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Copy of r51h[7:0] at the time the fault log was triggered.
Copy of r52h[7:0] at the time the fault log was triggered.
Copy of r53h[7:0] at the time the fault log was triggered.
IN1 conversion result at the time the fault log was triggered.
IN2 conversion result at the time the fault log was triggered. 8 MSBs only.
IN3 conversion result at the time the fault log was triggered. 8 MSBs only.
IN4 conversion result at the time the fault log was triggered. 8 MSBs only.
IN5 conversion result at the time the fault log was triggered. 8 MSBs only.
IN6 conversion result at the time the fault log was triggered. 8 MSBs only.
IN7 conversion result at the time the fault log was triggered. 8 MSBs only.
IN8 conversion result at the time the fault log was triggered. 8 MSBs only.
Internal temperature sensor conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
—
—
8Bh
8Ch
[7:0]
[7:0]
/MAX16032
Remote temperature sensor 1 conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
Remote temperature sensor 2 conversion result at the time the fault log was triggered.
8 MSBs from 10-bit ADC conversion.
—
—
8Dh
8Eh
[7:0]
[7:0]
Current-sense conversion result at the time the fault log was triggered.
I2C/SMBus-Compatible Serial Interface
The MAX16031/MAX16032 feature an I2C/SMBus-com-
patible 2-wire (SDA and SCL) serial interface for com-
munication with a master device. All possible
communication formats are shown in Figure 5. The
slave address and SMBALERT# are described further
in the following subsections. Figure 1 shows a detailed
2-wire interface timing diagram. For descriptions of the
I2C and SMBus protocol and terminology, refer to the
I2C-Bus Specification Version 2.1 and the System
Management Bus (SMBus) Specification Version 2.0.
The MAX16031/MAX16032 allow 2-wire communication
up to 400kHz. SDA and SCL require external pullup
resistors.
SMBALERT#
SMBALERT# is an optional interrupt signal defined in
Appendix A of the SMBus Specification. The
MAX16031/MAX16032 provide output ALERT as this
interrupt signal. If enabled, ALERT asserts if any one of
the following outputs asserts: FAULT1, FAULT2,
RESET, OVERT, or OVERC. Additionally, if a GPIO_ is
configured for a fault output, a fault at this output also
causes ALERT to assert. ALERT deasserts when all
fault conditions are removed (i.e., when all fault outputs
are high).
Typically ALERT is connected to all other SMBALERT#
open-drain signals in the system, creating a wired-OR
function with all SMBALERT# outputs. When the master
is interrupted by its SMBALERT# input, it stops or fin-
ishes the current bus transfer and places an alert
response address (ARA) on the bus. The slave that
pulled the SMBALERT# signal low acknowledges the
ARA and places its own address on the bus, identifying
itself to the master as the slave that caused the inter-
rupt. The 7-bit ARA is ‘0001100’ and the R/W bit is a
don’t care.
Slave Address
The slave address inputs, A0 and A1, are each capa-
ble of detecting three different states, allowing nine
identical devices to share the same serial bus. Connect
A0 and A1 to GND, DBP, or leave as not connected
(N.C.). See Table 15 for a listing of all possible 7-bit
address input connections and their corresponding
serial-bus addresses.
32 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Send Byte Format
ADDRESS R/W ACK COMMAND ACK
Receive Byte Format
S
P
S
ADDRESS R/W ACK
7 bits
DATA
8 bits
NACK
P
7 bits
0
8 bits
1
Slave Address: Address
of the slave on the serial
interface bus.
Data Byte: Presets the internal
address pointer or represents
a command.
Slave Address: Address
of the slave on the serial
interface bus.
Data Byte: Data is read from
the location pointed to by the
internal address pointer.
Write Byte Format
ADDRESS R/W ACK COMMAND ACK
SMBALERT#
S
DATA
8 bits
ACK
P
S
ADDRESS R/W ACK
0001100 D.C.
DATA
NACK
P
7 bits
0
8 bits
8 bits
Slave Address: Address
of the slave on the serial
interface bus.
Command Byte:
Sets the internal
address pointer.
Data Byte: Data is written to
the locations set by the
internal address pointer.
Alert Response Address:
Only the device that
interrupted the master
responds to this address.
Slave Address: Slave places
its own address on the
serial bus.
Read Byte Format
SLAVE
S
SLAVE
ADDRESS
R/W ACK COMMAND ACK SR
R/W ACK DATA BYTE NACK
8 bits
P
ADDRESS
7 bits
0
8 bits
7 bits
1
Slave Address: Address
of the slave on the serial
interface bus.
Command Byte:
Sets the internal
address pointer.
Data Byte: Data is written to
the locations set by the
internal address pointer.
Block Write Format
ADDRESS
BYTE
COUNT = N
Slave to master
Master to slave
S
WR ACK COMMAND ACK
ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N ACK
8 bits 8 bits 8 bits
P
7 bits
0
8 bits
8 bits
Slave Address: Address
of the slave on the
Command Byte:
FAh
Data Byte: Data is written to the locations
set by the internal address pointer.
serial interface bus.
Block Read Format
BYTE
COUNT = N
S
ADDRESS
7 bits
WR ACK COMMAND ACK SR
ADDRESS
7 bits
WR ACK
1
ACK DATA BYTE N ACK DATA BYTE … ACK DATA BYTE N NACK
P
0
8 bits
8 bits
8 bits
8 bits
8 bits
Slave Address: Address
of the slave on the
Command Byte:
FBh
Slave Address: Address
of the slave on the
Data Byte: Data is read from the locations
set by the internal address pointer.
serial interface bus.
serial interface bus.
S = START Condition
P = STOP Condition
Sr = Repeated START Condition
D.C. = Don’t Care
ACK = Acknowledge, SDA pulled low during rising edge of SCL.
NACK = Not acknowledge, SDA left high during rising edge of SCL.
= SDA transitions from high to low during period of SCL.
= SDA transitions from low to high during period of SCL.
All data is clocked in/out of the device on rising edges of SCL.
Figure 5. Communication Formats
______________________________________________________________________________________ 33
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 14. Miscellaneous Settings
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
Postboot Timeout (all faults and outputs masked):
0h = No timeout
1h = 0.974ms
2h = 2.030ms
3h = 3.978ms
4h = 8.038ms
5h = 15.99ms
6h = 31.99ms
[3:0]
7h = 63.99ms
8h = 128ms
9h = 256.0ms
Ah = 512ms
Bh = 1024ms
Ch = 2048ms
Dh = 4096ms
5Bh
DBh
Eh = 8192ms
/MAX16032
Fh = 16384ms
Temperature Sensor Lowpass Filter Cutoff:
000 = No filter
001 = 2.53Hz
010 = 5.06Hz
[6:4]
011 = 10.1Hz
100 = 20.2Hz
101 = 40.5Hz
110 = 81Hz
111 = 162Hz
[7]
Not used.
Overcurrent Secondary Threshold Timeout:
00 = No delay
01 = 3.98ms
10 = 16ms
[1:0]
11 = 64ms
Latch OVERC:
5Ch
DCh
0 = No latch
1 = Latched after assertion
[2]
[4:3]
[5]
Not used.
Threshold Hysteresis (all thresholds):
0 = 0.78%
1 = 1.17%
34 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 14. Miscellaneous Settings (continued)
EEPROM
MEMORY
ADDRESS
REGISTER
ADDRESS
BIT
RANGE
DESCRIPTION
Consecutive Faults on Primary Thresholds:
[6]
[7]
0 = Fault occurs after primary threshold is exceeded one time (normal operation).
1 = Fault occurs after primary threshold is exceeded twice.
5Ch
5Eh
DCh
DEh
Fault Log ADC Conversions Option:
0 = When a fault log is triggered, only fault flags are saved in EEPROM.
1 = When a fault log is triggered, fault flags and ADC conversion results (8 MSBs) are
saved in EEPROM.
[7:0]
[0]
Firmware Version. 8 bits of memory for user-defined firmware version number.
Configuration Lock:
Write a ‘1’ to r5Fh[0] to toggle this register bit.
0 = Register and EEPROM configuration unlocked.
1 = Register and EEPROM configuration locked.
Fault Log EEPROM Lock Flag (set automatically after fault log is triggered):
Write a ‘1’ to r5Fh[1] to toggle this register bit.
5Fh
DFh
[1]
0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM.
1 = A fault log has been triggered. Write a ‘1’ to this bit to clear the flag and allow a
new fault log to be triggered.
[7:2]
Not used.
2
JTAG Serial Interface
Table 15. Setting the I C/SMBus Slave
Address
The MAX16031/MAX16032 contain an IEEE 1149.1- com-
pliant JTAG port in addition to the I2C/SMBus-compatible
serial bus. Either interface may be used to access internal
memory; however, only one interface is allowed to run at
a time. All digital I/Os on the MAX16031/MAX16032 are
IEEE 1149.1 boundary-scan compliant, and contain the
typical JTAG boundary scan cells that allow the
inputs/outputs to be polled or forced high/low using stan-
dard JTAG instructions. The MAX16031/MAX16032 con-
tain extra JTAG instructions and registers not included in
the JTAG specification that provide access to internal
memory. The extra instructions are: LOAD ADDRESS,
WRITE, READ, REBOOT, SAVE, and USERCODE. The
extra registers are: memory address, memory write,
memory read, and user-code data. See Figure 6 for a
block diagram of the JTAG interface.
A1
A0
BUS ADDRESS
0011000
0011001
0011010
0101001
0101010
0101011
1001100
1001111
1001110
GND
GND
GND
N.C.
N.C.
N.C.
DBP
DBP
DBP
GND
N.C.
DBP
GND
N.C.
DBP
GND
N.C.
DBP
Special Commands
The MAX16031/MAX16032 provide software reboot and
fault log commands. A software reboot initiates the
boot-up sequence, which normally occurs at POR.
During boot-up, EEPROM configuration data is copied
to registers. To initiate a software reboot, send 0xFC
using the send byte format. A software-initiated fault log
is functionally the same as a hardware-initiated fault
log. During a fault log, ADC registers and fault informa-
tion are logged in EEPROM. To trigger a software initi-
ated fault log, send 0xFD using the send byte format.
Test Access Port (TAP) Controller State Machine
The TAP controller is a finite state machine that
responds to the logic level at TMS on the rising edge of
TCK. See Figure 7 for a diagram of the finite state
machine.
Test-Logic-Reset: At power-up, the TAP controller is in
the test-logic-reset state. The instruction register con-
tains the IDCODE instruction. All system logic of the
device operates normally.
______________________________________________________________________________________ 35
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
REGISTERS
AND EEPROM
01101
01100
MEMORY WRITE REGISTER
01010
[LENGTH = 8 BITS]
MEMORY READ REGISTER
01001
[LENGTH = 8 BITS]
MEMORY ADDRESS REGISTER
01000
[LENGTH = 8 BITS]
MUX 1
00001
00010
BOUNDARY SCAN REGISTER
[LENGTH = 198 BITS]
USER CODE REGISTER
[LENGTH = 32 BITS]
00100
00000
11111
COMMAND
DECODER
SAVE
01101
01100
/MAX16032
IDENTIFICATION REGISTER
[LENGTH = 32 BITS]
REBOOT
BYPASS REGISTER
[LENGTH = 1 BIT]
V
DBP
INSTRUCTION REGISTER
[LENGTH = 5 BITS]
R
PU
MUX 2
TDO
TDI
TMS
TCK
TEST ACCESS PORT
(TAP) CONTROLLER
Figure 6. JTAG Block Diagram
Run-Test/Idle: The run-test/idle state is used between
scan operations or during specific tests. The instruction
register and test data registers remain idle.
Shift-DR: The test data register selected by the current
instruction is connected between TDI and TDO and
shifts data one stage toward its serial output on each
rising edge of TCK while TMS is low. On the rising edge
of TCK, the controller goes to the exit1-DR state if TMS
is high.
Select-DR-Scan: All test data registers retain their pre-
vious state. With TMS low, a rising edge of TCK moves
the controller into the capture-DR state and initiates a
scan sequence. TMS high during a rising edge on TCK
moves the controller to the select-IR-scan state.
Exit1-DR: While in this state, a rising edge on TCK puts
the controller in the update-DR state. A rising edge on
TCK with TMS low puts the controller in the pause-DR
state.
Capture-DR: Data are parallel-loaded into the test data
registers selected by the current instruction. If the instruc-
tion does not call for a parallel load or the selected test
data register does not allow parallel loads, the test data
register remains at its current value. On the rising edge of
TCK, the controller goes to the shift-DR state if TMS is low
or it goes to the exit1-DR state if TMS is high.
Pause-DR: Shifting of the test data registers is halted
while in this state. All test data registers retain their pre-
vious state. The controller remains in this state while
TMS is low. A rising edge on TCK with TMS high puts
the controller in the exit2-DR state.
36 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
TEST-LOGIC-RESET
1
0
0
1
1
1
SELECT-DR-SCAN
SELECT-IR-SCAN
RUN-TEST/IDLE
0
CAPTURE-DR
0
0
CAPTURE-IR
0
1
1
0
SHIFT-DR
0
SHIFT-IR
1
1
1
0
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
PAUSE-IR
0
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Figure 7. TAP Controller State Diagram
Exit2-DR: A rising edge on TCK with TMS high while in
this state puts the controller in the update-DR state. A
rising edge on TCK with TMS low enters the Shift-DR
state.
Capture-IR: Use the capture-IR state to load the shift
register in the instruction register with a fixed value.
This value is loaded on the rising edge of TCK. If TMS
is high on the rising edge of TCK, the controller enters
the exit1-IR state. If TMS is low on the rising edge of
TCK, the controller enters the shift-IR state.
Update-DR: A falling edge on TCK while in the update-
DR state latches the data from the shift register path of
the test data registers into a set of output latches. This
prevents changes at the parallel output because of
changes in the shift register. On the rising edge of TCK,
the controller goes to the run-test/idle state if TMS is
low or it goes to the select-DR-scan state if TMS is high.
Shift-IR: In this state, the shift register in the instruction
register is connected between TDI and TDO and shifts
data one stage for every rising edge of TCK toward the
TDO serial output while TMS is low. The parallel outputs
of the instruction register as well as all test data regis-
ters remain at their previous states. A rising edge on
TCK with TMS high moves the controller to the exit1-IR
state. A rising edge on TCK with TMS low keeps the
controller in the shift-IR state while moving data one
stage through the instruction shift register.
Select-IR-Scan: All test data registers retain their previ-
ous state. The instruction register remains unchanged
during this state. With TMS low, a rising edge on TCK
moves the controller into the capture-IR state. TMS high
during a rising edge on TCK puts the controller back
into the test-logic-reset state.
______________________________________________________________________________________ 37
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Exit1-IR: A rising edge on TCK with TMS low puts the
controller in the pause-IR state. If TMS is high on the ris-
ing edge of TCK, the controller enters the update-IR state.
SAMPLE/PRELOAD: This is a mandatory instruction
for the IEEE 1149.1 specification that supports two
functions. The digital I/Os of the device are sampled at
the boundary scan test data register without interfering
with the normal operation of the device by using the
capture-DR state. SAMPLE/PRELOAD also allows the
device to shift data into the boundary scan test data
register through TDI using the shift-DR state.
Pause-IR: Shifting of the instruction shift register is halt-
ed temporarily. With TMS high, a rising edge on TCK
puts the controller in the exit2-IR state. The controller
remains in the pause-IR state if TMS is low during a ris-
ing edge on TCK.
BYPASS: When the BYPASS instruction is latched into
the instruction register, TDI connects to TDO through
the 1-bit bypass test data register. This allows data to
pass from DTDI to TDO without affecting the device’s
normal operation.
Exit2-IR: A rising edge on TCK with TMS high puts the
controller in the update-IR state. The controller loops
back to shift-IR if TMS is low during a rising edge of
TCK in this state.
Update-IR: The instruction code that has been shifted
into the instruction shift register is latched to the parallel
outputs of the instruction register on the falling edge of
TCK as the controller enters this state. Once latched,
this instruction becomes the current instruction. A rising
edge on TCK with TMS low puts the controller in the
run-test/idle state. With TMS high, the controller enters
the select-DR-scan state.
EXTEST: This instruction allows testing of all intercon-
nections to the device. When the EXTEST instruction is
latched in the instruction register, the following actions
occur. Once enabled through the update-IR state, the
parallel outputs of all digital outputs are driven. The
boundary scan test data register is connected between
TDI and TDO. The capture-DR samples all digital inputs
into the boundary scan test data register.
/MAX16032
Instruction Register
The instruction register contains a shift register as well
as a latched parallel output and is 5 bits in length.
When the TAP controller enters the shift-IR state, the
instruction shift register is connected between TDI and
TDO. While in the shift-IR state, a rising edge on TCK with
TMS low shifts the data one stage toward the serial output
at TDO. A rising edge on TCK in the exit1-IR state or the
exit2-IR state with TMS high moves the controller to the
update-IR state. The falling edge of that same TCK latch-
es the data in the instruction shift register to the instruc-
tion register parallel output. Instructions supported by the
MAX16031/MAX16032 and their respective operational
binary codes are shown in Table 16.
IDCODE: When the IDCODE instruction is latched into
the parallel instruction register, the identification test
data register is selected. The device identification code
is loaded into the identification test data register on the
rising edge of TCK following entry into the capture-DR
state. Shift-DR is used to shift the identification code
out serially through TDO. During test-logic-reset, the
identification code is forced into the instruction register.
The ID code always has a 1 in the LSB position. The
next 11 bits identify the manufacturer’s JEDEC number
and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version. See Table 17.
Table 16. JTAG Instruction Set
INSTRUCTION
BYPASS
BINARY CODE
11111
SELECTED REGISTER/ACTION
Bypass
IDCODE
00000
Identification
SAMPLE/PRELOAD
EXTEST
00001
Boundary scan
00010
Boundary scan
USERCODE
LOAD ADDRESS
READ DATA
WRITE DATA
REBOOT
00100
User-code data
01000
Memory address
01001
Memory read
01010
Memory write
01100
Resets the device
Stores current fault information in EEPROM
SAVE
01101
38 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Table 17. 32-Bit Identification Code
MSB
LSB
Version (4 bits)
0000
Device ID (16 bits)
0000000000000001
Manufacturer ID (11 bits)
00011001011
Fixed value (1 bit)
1
SAVE: This is an extension to the standard IEEE 1149.1
instruction set that triggers a fault log. When the SAVE
instruction is latched into the instruction register, the
MAX16031/MAX16032 copy fault information from reg-
isters to EEPROM.
Table 18. 32-Bit User-Code Data
MSB
2
I C/SMBus
User identification
(firmware version)
D.C. (don’t cares)
Slave Address
00000000000000000
See Table 15
r5Eh[7:0] contents
Boundary Scan
The boundary scan feature allows access to all the dig-
ital I/O connections of the MAX16031/MAX16032. If the
sample/preload or the EXTEST instruction is loaded into
the instruction register, TDI connects to TDO through
the 198-bit boundary scan register. Each digital I/O pin
corresponds to 1 bit (or 2 bits, in the case of the A0
and A1 pins) of the boundary scan register. The rest of
the boundary scan bits are reserved and are loaded
with zeros.
USERCODE: When the USERCODE instruction is
latched into the parallel instruction register, the user-
code data register is selected. The device user code is
loaded into the user-code data register on the rising
edge of TCK following entry into the capture-DR state.
Shift-DR is used to shift the user code out serially
through TDO. See Table 18.
LOAD ADDRESS: This is an extension to the standard
IEEE 1149.1 instruction set to support access to the
memory in the MAX16031/MAX16032. When the LOAD
ADDRESS instruction is latched into the instruction reg-
ister, TDI connects to TDO through the 8-bit memory
address test data register during the shift-DR state.
When the sample/preload instruction is executed, the
current state of the digital outputs is latched into the
boundary scan register and is shifted out through TDO.
This instruction may be executed without interrupting
normal operation of the part. When the EXTEST instruc-
tion is executed, the boundary scan register bits super-
sede the normal functionality of the I/O pins: an output
mirrors the state of the corresponding boundary scan
register bit.
READ: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16031/MAX16032. When the READ instruc-
tion is latched into the instruction register, TDI connects
to TDO through the 8-bit memory read test data register
during the shift-DR state.
Table 19 lists the function of each boundary scan regis-
ter bit. Since the I2C address select pins have three
possible states, 2 boundary scan register bits are
required to represent them. These bits are defined in
Table 20.
WRITE: This is an extension to the standard IEEE
1149.1 instruction set to support access to the memory
in the MAX16031/MAX16032. When the WRITE instruc-
tion is latched into the instruction register, TDI connects
to TDO through the 8-bit memory write test data regis-
ter during the shift-DR state.
Applications Information
Layout and Bypassing
Bypass V , DBP, and ABP each with a 1µF capacitor
CC
to GND. Bypass RBP with a 2.2µF capacitor to GND.
Avoid routing digital return currents through a sensitive
analog area, such as an analog supply input return
path or ABP’s bypass capacitor ground connection.
Use dedicated analog and digital ground planes.
REBOOT: This is an extension to the standard IEEE
1149.1 instruction set to initiate a software-controlled
reset to the MAX16031/MAX16032. When the REBOOT
instruction is latched into the instruction register, the
MAX16031/MAX16032 reset and immediately begin
their boot-up sequence.
______________________________________________________________________________________ 39
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Table 20. Address Pin State Decode
Table 19. Boundary Cell Order
BOUNDARY CELL NO.
DESCRIPTION/PIN
A0A A0B
0 0
A0 PIN STATE
High impedance
Low
0–147
148
Reserved
GPIO1 (output)
GPIO2 (output)
SDA (output)
ALERT
0 1
149
1 0
High
150
1 1
Not defined
151
152
FAULT2
153
FAULT1
154
OVERT
155
RESET
156
OVERC
157–182
183
Reserved
GPIO2 (input)
GPIO1 (input)
SDA (input)
A0b
184
185
/MAX16032
186
187
A0a
188
A1b
189
A1a
190
SCL
191–197
Reserved
Chip Information
PROCESS: BiCMOS
40 ______________________________________________________________________________________
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
/MAX16032
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
E
DETAIL A
(NE-1) X
e
E/2
k
e
e
D/2
C
(ND-1) X
D
D2
L
D2/2
b
L
E2/2
C
L
k
E2
C
C
L
L
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
F
21-0144
2
______________________________________________________________________________________ 41
EEPROM-Based System Monitors
with Nonvolatile Fault Memory
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
/MAX16032
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
F
21-0144
2
Revision History
Pages changed at Rev 1: 1, 41, 42
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
42 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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