MAX1631A_技术文档

19-3518; Rev 1; 8/05

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

________________General Description

____________________________Features

♦ 96% Efficiency

♦ +4.2V to +30V Input Range

The MAX1630A–MAX1635A are buck-topology, step-

down, switch-mode, power-supply controllers that gener-

ate logic-supply voltages in battery-powered systems.

These high-performance, dual-/triple-output devices

include on-board power-up sequencing, power-good

signaling with delay, digital soft-start, secondary winding

control, low-dropout circuitry, internal frequency-com-

pensation networks, and automatic bootstrapping.

♦ 2.5V to 5.5V Dual Adjustable Outputs

♦ Selectable 3.3V and 5V Fixed or Adjustable

Outputs (Dual Mode™)

♦ 12V Linear Regulator

♦ Adjustable Secondary Feedback

(MAX1631A/MAX1634A)

Up to 96% efficiency is achieved through synchronous

rectification and Maxim’s proprietary Idle Mode™ control

scheme. Efficiency is greater than 80% over a 1000:1

load-current range, which extends battery life in system-

suspend or standby mode. Excellent dynamic response

corrects output load transients caused by the latest

dynamic-clock CPUs within five 300kHz clock cycles.

Strong 1A on-board gate drivers ensure fast external

n-channel MOSFET switching.

♦ 5V/50mA Linear Regulator Output

♦ Precision 2.5V Reference Output

♦ Programmable Power-Up Sequencing

♦ Power-Good (RESET) Output

♦ Output Overvoltage Protection

(MAX1630A/MAX1631A/MAX1632A)

♦ Output Undervoltage Shutdown

(MAX1630A/MAX1631A/MAX1632A)

These devices feature a logic-controlled and synchroniz-

able, fixed-frequency, pulse-width-modulation (PWM)

operating mode. This reduces noise and RF interference

in sensitive mobile communications and pen-entry appli-

cations. Asserting the SKIP pin enables fixed-frequency

mode for lowest noise under all load conditions.

♦ 200kHz/300kHz Low-Noise, Fixed-Frequency

Operation

♦ Low-Dropout, 99% Duty-Factor Operation

♦ 2.5mW Typical Quiescent Power (+12V Input,

Both SMPSs On)

♦ 4µA Typical Shutdown Current

♦ 28-Pin SSOP Package

The MAX1630A–MAX1635A include two PWM regulators,

adjustable from 2.5V to 5.5V with fixed 5.0V and 3.3V

modes. All these devices include secondary feedback

regulation, and the MAX1630A/MAX1632A/MAX1633A/

MAX1635A each contain 12V/120mA linear regulators.

The MAX1631A/MAX1634A include a secondary feed-

back input (SECFB), plus a control pin (STEER) that

selects which PWM (3.3V or 5V) receives the secondary

feedback signal. SECFB provides a method for adjusting

the secondary winding voltage regulation point with an

external resistor-divider, and is intended to aid in creating

auxiliary voltages other than fixed 12V.

_______________Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

MAX1630AEAI

-40°C to +85°C

28 SSOP

+Denotes lead-free package.

Ordering Information continued at end of data sheet.

________________Functional Diagram

INPUT

The MAX1630A/MAX1631A/MAX1632A contain internal

output overvoltage and undervoltage protection features.

The MAX1630A family has improved RF immunity over

the MAX1630 family.

+12V

+5V (RTC)

5V

12V

LINEAR

________________________Applications

Notebook and Subnotebook Computers

+3.3V

+5V

3.3V

5V

SMPS

PDAs and Mobile Communicators

Desktop CPU Local DC-DC Converters

Pin Configurations and Selector Guide appear at end of data

sheet.

POWER-UP

SEQUENCE

POWER-

GOOD

ON/OFF

RESET

Idle Mode and Dual Mode are trademarks of Maxim Integrated

Products, Inc.

________________________________________________________________ Maxim Integrated Products

1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

ABSOLUTE MAXIMUM RATINGS

V+ to GND..............................................................-0.3V to +36V

PGND to GND..................................................................... 0.3V

VL to GND ................................................................-0.3V to +6V

BST3, BST5 to GND ...............................................-0.3V to +36V

LX3 to BST3..............................................................-6V to +0.3V

LX5 to BST5..............................................................-6V to +0.3V

REF, SYNC, SEQ, STEER, SKIP, TIME/ON5,

VL, REF Short to GND ................................................Momentary

12OUT Short to GND..................................................Continuous

REF Current...........................................................+5mA to -1mA

VL Current.........................................................................+50mA

12OUT Current ...............................................................+200mA

V

Shunt Current............................................................+15mA

DD

Operating Temperature Ranges

SECFB, RESET to GND .......................................-0.3V to +6V

MAX163_ACAI ....................................................0°C to +70°C

MAX163_AEAI .................................................-40°C to +85°C

Storage Temperature Range.............................-65°C to +160°C

V

to GND............................................................-0.3V to +20V

DD

RUN/ON3, SHDN to GND.............................-0.3V to (V+ + 0.3V)

12OUT to GND ...........................................-0.3V to (V + 0.3V)

Continuous Power Dissipation (T = +70°C)

DD

A

DL3, DL5 to PGND........................................-0.3V to (VL + 0.3V)

DH3 to LX3 ...............................................-0.3V to (BST3 + 0.3V)

DH5 to LX5 ...............................................-0.3V to (BST5 + 0.3V)

SSOP (derate 9.52mW/°C above +70°C) ....................762mW

Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, T = T

to T

, unless otherwise noted.

MAX

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

MAIN SMPS CONTROLLERS

Input Voltage Range

CONDITIONS

MIN

TYP

MAX

UNITS

4.2

30.0

2.58

V

3V Output Voltage in

Adjustable Mode

V+ = 4.2V to 30V, CSH3–CSL3 = 0V,

CSL3 tied to FB3

2.42

2.5

3.39

2.5

V+ = 4.2V to 30V, 0mV < CSH3–CSL3 < 80mV,

FB3 = 0V

3V Output Voltage in Fixed Mode

3.20

2.42

4.85

3.47

2.58

5.25

V

5V Output Voltage in

Adjustable Mode

V+ = 4.2V to 30V, CSH5–CSL5 = 0V,

CSL5 tied to FB5

V+ = 5.2V to 30V, 0mV < CSH–CSL5 < 80mV,

FB5 = 0V

5V Output Voltage in Fixed Mode

5.13

Output Voltage Adjust Range

Adjustable-Mode Threshold Voltage

Load Regulation

Either SMPS

REF

0.5

5.5

1.1

V

Dual Mode comparator

Either SMPS, 0V < CSH_- CSL_ < 80mV

Either SMPS, 5.2V < V+ < 30V

CSH3–CSL3 or CSH5–CSL5

-2

%

Line Regulation

0.03

100

-100

%/V

80

-50

10

120

-150

40

Current-Limit Threshold

Idle Mode Threshold

Soft-Start Ramp Time

mV

SKIP = VL or V

< 13V or SECFB < 2.44V

DD

25

SKIP = 0V, not tested

From enable to 95% full current limit with respect to

512

Clks

f

(Note 1)

OSC

SYNC = VL

270

170

97

300

200

98

330

230

Oscillator Frequency

Maximum Duty Factor

kHz

%

SYNC = 0V

SYNC = VL

SYNC = 0V (Note 2)

98

99

2

_______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, T = T

to T

, unless otherwise noted.

MAX

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

SYNC Input High Pulse Width

SYNC Input Low Pulse Width

SYNC Rise/Fall Time

CONDITIONS

MIN

TYP

MAX

UNITS

ns

Not tested

200

ns

200

350

ns

SYNC Input Frequency Range

240

kHz

V+ = VL = 0V,

CSL3 = CSH3 = CSL5 = CSH5 = 5.5V

Current-Sense Input Leakage Current

0.01

10

µA

FLYBACK CONTROLLER

V

Regulation Threshold

Falling edge (Note 3)

13

14

V

DD

SECFB Regulation Threshold

DL Pulse Width

Falling edge (MAX1631A/MAX1634A)

2.44

2.60

V

< 13V or SECFB < 2.44V

1

µs

V

DD

V

Shunt Threshold

Shunt Sink Current

Leakage Current

Rising edge, hysteresis = 1% (Note 3)

18

10

20

30

DD

V

= 20V (Note 3)

mA

µA

DD

= 5V, off mode (Notes 3, 4)

12V LINEAR REGULATOR (Note 3)

12OUT Output Voltage

13V < V

< 18V, 0mA < I

< 120mA

11.65

12.1

150

50

12.50

100

V

DD

LOAD

12OUT Current Limit

12OUT forced to 11V, V

= 13V

mA

µA

DD

Quiescent V

Current

V

= 18V, run mode, no 12OUT load

DD

INTERNAL REGULATOR AND REFERENCE

SHDN = V+, RUN/ON3 = TIME/ON5 = 0V,

5.3V < V+ < 30V, 0mA < I < 50mA

VL Output Voltage

4.7

3.5

5.1

3.7

V

LOAD

VL Undervoltage Lockout

Fault Threshold

Falling edge, hysteresis = 1%

3.6

VL Switchover Threshold

REF Output Voltage

Rising edge of CSL5, hysteresis = 1%

No external load (Note 5)

4.2

4.5

2.5

4.7

2.55

12.5

100.0

V

2.45

0µA < I

< 50µA

< 5mA

LOAD

REF Load Regulation

mV

0mA < I

LOAD

REF Sink Current

10

µA

V

REF Fault Lockout Voltage

V+ Operating Supply Current

Falling edge

1.8

2.4

50

VL switched over to CSL5, 5V SMPS on

5

µA

V+ = 5.5V to 30V, both SMPSs off,

includes current into SHDN

V+ Standby Supply Current

30

60

µA

V+ Standby Supply Current

in Dropout

V+ = 4.2V to 5.5V, both SMPSs off,

includes current into SHDN

50

200

µA

V+ Shutdown Supply Current

4

10

4

V+ = 4V to 24V, SHDN = 0V

(Note 3)

2.5

Both SMPSs enabled, FB3 = FB5 = 0V,

CSL3 = CSH3 = 3.5V,

CSL5 = CSH5 = 5.3V

Quiescent Power Consumption

mW

MAX1631A/

MAX1634A

1.5

4

_______________________________________________________________________________________

3

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

ELECTRICAL CHARACTERISTICS (continued)

(V+ = 15V, both PWMs on, SYNC = VL, VL load = 0mA, REF load = 0mA, SKIP = 0V, T = T

to T

, unless otherwise noted.

MAX

A

MIN

Typical values are at T = +25°C.)

A

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

FAULT DETECTION (MAX1630A/MAX1631A/MAX1632A)

Overvoltage Trip Threshold

Overvoltage-Fault Propagation Delay

Output Undervoltage Threshold

Output Undervoltage Lockout Time

Thermal Shutdown Threshold

RESET

With respect to unloaded output voltage

CSL_ driven 2% above overvoltage trip threshold

With respect to unloaded output voltage

4

7

10

%

µs

1.5

60

70

80

%

From each SMPS enabled, with respect to f

Typical hysteresis = +10°C

5000

6144

150

7000

Clks

°C

OSC

With respect to unloaded output voltage,

falling edge; typical hysteresis = 1%

-7

-5.5

1.5

-4

%

RESET Trip Threshold

Falling edge, CSL_ driven 2%

below RESET trip threshold

µs

RESET Propagation Delay

With respect to f

OSC

27,000 32,000 37,000

Clks

RESET Delay Time

INPUTS AND OUTPUTS

Feedback Input Leakage Current

FB3, FB5; SECFB = 2.6V

1

50

nA

V

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

SHDN, STEER, SYNC

Logic Input Low Voltage

Logic Input High Voltage

0.6

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

SHDN, STEER, SYNC

2.4

V

RUN/ON3, SKIP, TIME/ON5 (SEQ = REF),

Input Leakage Current

1

µA

V

SHDN, STEER, SYNC, SEQ; V

= 0V or 3.3V

Logic Output Low Voltage

0.4

RESET, I

= 4mA

SINK

Logic Output High Current

TIME/ON5 Input Trip Level

TIME/ON5 Source Current

TIME/ON5 On-Resistance

Gate Driver Sink/Source Current

Gate Driver On-Resistance

1

mA

V

RESET = 3.5V

SEQ = 0V or VL

2.4

2.5

2.6

3.5

80

TIME/ON5 = 0V, SEQ = 0V or VL

3

15

1

µA

Ω

A

TIME/ON5; RUN/ON3 = 0V, SEQ = 0V or VL

DL3, DH3, DL5, DH5; forced to 2V

High or low

1.5

7

Ω

Note 1: Each of the four digital soft-start levels is tested for functionality; the steps are typically in 20mV increments.

Note 2: High duty-factor operation supports low input-to-output differential voltages, and is achieved at a lowered operating

frequency (see Overload and Dropout Operation section).

Note 3: MAX1630A/MAX1632A/MAX1633A/MAX1635A only.

Note 4: Off mode for the 12V linear regulator occurs when the SMPS that has flyback feedback (V ) steered to it is disabled. In

DD

situations where the main outputs are being held up by external keep-alive supplies, turning off the 12OUT regulator pre-

vents a leakage path from the output-referred flyback winding, through the rectifier, and into V

.

DD

Note 5: Since the reference uses VL as its supply, the reference’s V+ line-regulation error is insignificant.

4

_______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

__________________________________________Typical Operating Characteristics

(Circuit of Figure 1, 3A Table 1 components, T = +25°C, unless otherwise noted.)

A

MAX1632A/MAX1635A

MAXIMUM 15V V OUTPUT

CURRENT vs. SUPPLY VOLTAGE

DD

EFFICIENCY vs. 5V OUTPUT CURRENT

EFFICIENCY vs. 3.3V OUTPUT CURRENT

100

800

100

V+ = 6V

V

> 13V

5V REGULATING

DD

V+ = 6V

90

80

70

60

90

80

70

60

600

400

200

0

5V LOAD = 0A

V+ = 15V

5V LOAD = 3A

ON5 = 5V

ON3 = 0V

f = 300kHz

MAX1631A/MAX1634A

ON3 = ON5 = 5V

f = 300kHz

MAX1631A/MAX1634A

50

0.001

0.01

0.1

1

10

0

5

10

15

20

0.001

0.01

0.1

1

10

5V OUTPUT CURRENT (A)

SUPPLY VOLTAGE (V)

3.3V OUTPUT CURRENT (A)

MAX1630A/MAX1633A

PWM MODE INPUT CURRENT

vs. INPUT VOLTAGE

MAXIMUM 15V V OUTPUT

IDLE MODE INPUT CURRENT

vs. INPUT VOLTAGE

DD

CURRENT vs. SUPPLY VOLTAGE

30

10

1

500

400

300

200

100

ON3 = ON5 = 5V

SKIP = 0V

NO LOAD

ON3 = ON5 = 5V

SKIP = VL

NO LOAD

V

> 13V

DD

3.3V REGULATING

25

20

15

10

3.3V LOAD = 0A

0.1

0.01

3.3V LOAD = 3A

5

0

5

10

15

20

25

30

0

5

10

15

20

25

30

0

5

10

SUPPLY VOLTAGE (V)

15

20

INPUT VOLTAGE (V)

MINIMUM V TO V

DIFFERENTIAL

SHUTDOWN INPUT CURRENT

vs. INPUT VOLTAGE

IN

OUT

STANDBY INPUT CURRENT

vs. INPUT VOLTAGE

vs. 5V OUTPUT CURRENT

1000

10

8

10,000

1000

100

10

ON3 = ON5 = 0V

NO LOAD

SHDN = 0V

100

10

6

4

2

5V, 3A CIRCUIT

> 4.8V

V

OUT

f = 300kHz

1

0

1

0.001

0.01

0.1

1

10

0

5

10

15

20

25

30

0

5

10

15

20

25

30

5V OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

_______________________________________________________________________________________

5

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

____________________________________Typical Operating Characteristics (continued)

(Circuit of Figure 1, 3A Table 1 components, T = +25°C, unless otherwise noted.)

A

SWITCHING FREQUENCY

vs. LOAD CURRENT

VL REGULATOR OUTPUT VOLTAGE

vs. OUTPUT CURRENT

1000

5.00

4.98

4.96

4.94

4.92

100

+5V, V = 15V

IN

10

1

+3.3V, V = 15V

IN

+3.3V, V = 6V

IN

+5V, V = 6V

V

= 15V

IN

ON3 = ON5 = 0V

0.1

4.90

0.1

1

10

100

1000

0

10 20

30

40

50

60

LOAD CURRENT (mA)

OUTPUT CURRENT (mA)

REF OUTPUT VOLTAGE

vs. OUTPUT CURRENT

STARTUP WAVEFORMS

2.510

2.505

RUN

5V/div

2.500

2.495

2.490

3.3V OUTPUT

2V/div

TIME

5V/div

5V OUTPUT

5V/div

2.485

2.480

V

= 15V

IN

ON3 = ON5 = 0V

2ms/div

0

1

2

3

4

5

6

SEQ = VL, 0.015μF CAPACITOR ON-TIME

OUTPUT CURRENT (mA)

__________________________________________________________________________Pin Description

1

NAME

CSH3

CSL3

FUNCTION

Current-Sense Input for the 3.3V SMPS. Current-limit level is 100mV referred to CSL3.

Current-Sense Input. Also serves as the feedback input in fixed-output mode.

2

Feedback Input for the 3.3V SMPS; regulates at FB3 = REF (approx. 2.5V) in adjustable mode. FB3 is a

Dual Mode input that also selects the 3.3V fixed output voltage setting when tied to GND. Connect FB3

to a resistor-divider for adjustable-output mode.

3

4

FB3

12OUT

(MAX1630A/

32A/33A/35A)

12V/120mA Linear Regulator Output. Input supply comes from V . Bypass 12OUT to GND with

DD

1µF minimum.

Logic-Control Input for secondary feedback. Selects the PWM that uses a transformer and secondary

feedback signal (SECFB):

STEER

(MAX1631A/

MAX1634A)

STEER = GND: 3.3V SMPS uses transformer

STEER = VL: 5V SMPS uses transformer

6

_______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_________________________________________________Pin Description (continued)

NAME

FUNCTION

V

DD

Supply Voltage Input for the 12OUT Linear Regulator. Also connects to an internal resistor-divider for

secondary winding feedback, and to an 18V overvoltage shunt regulator clamp.

(MAX1630A/

32A/33A/35A)

5

SECFB

Secondary Winding Feedback Input. Normally connected to a resistor-divider from an auxiliary output.

(MAX1631A/

MAX1634A)

SECFB regulates at V

used.

= 2.5V (see Secondary Feedback Regulation Loop section). Tie to VL if not

SECFB

Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz

operation. Can be driven at 240kHz to 350kHz for external synchronization.

6

7

SYNC

Dual-Purpose Timing Capacitor Pin and ON/OFF Control Input. See Power-Up Sequencing and

ON/OFF Controls section.

TIME/ON5

8

9

GND

REF

Low-Noise Analog Ground and Feedback Reference Point

2.5V Reference Voltage Output. Bypass to GND with 1µF minimum.

Logic-Control Input that Disables Idle Mode when High. Connect to GND for normal use.

10

SKIP

Active-Low Timed Reset Output. RESET swings GND to VL. Goes high after a fixed 32,000 clock-cycle

delay following power-up.

11

RESET

Feedback Input for the 5V SMPS; regulates at FB5 = REF (approximately 2.5V) in adjustable mode. FB5

is a Dual Mode input that also selects the 5V fixed output voltage setting when tied to GND. Connect

FB5 to a resistor-divider for adjustable-output mode.

12

FB5

Current-Sense Input for the 5V SMPS. Also serves as the feedback input in fixed-output mode, and as

the bootstrap supply input when the voltage on CSL5/VL is > 4.5V.

13

14

CSL5

CSH5

Current-Sense Input for the 5V SMPS. Current-limit level is 100mV referred to CSL5.

Pin-Strap Input that Selects the SMPS Power-Up Sequence:

SEQ = GND: 5V before 3.3V, RESET output determined by both outputs

SEQ = REF: Separate ON3/ON5 controls, RESET output determined by 3.3V output

SEQ = VL: 3.3V before 5V, RESET output determined by both outputs

15

SEQ

Gate-Drive Output for the 5V, High-Side n-Channel Switch. DH5 is a floating driver output that swings

from LX5 to BST5, riding on the LX5 switching node voltage.

16

DH5

17

18

19

20

LX5

BST5

DL5

Switching Node (Inductor) Connection. Can swing 2V below ground without hazard.

Boost Capacitor Connection for High-Side Gate Drive (0.1µF)

Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0V to VL.

Power Ground

PGND

5V Internal Linear-Regulator Output. VL is also the supply voltage rail for the chip. After the 5V SMPS

output has reached +4.5V (typical), VL automatically switches to the output voltage through CSL5 for

bootstrapping. Bypass to GND with 4.7µF. VL supplies up to 25mA for external loads.

21

VL

Battery Voltage Input, +4.2V to +30V. Bypass V+ to PGND close to the IC with a 0.22µF capacitor.

Connects to a linear regulator that powers VL.

22

23

V+

Shutdown Control Input, Active Low. Logic threshold is set at approximately 1V. For automatic startup,

connect SHDN to V+ through a 220kΩ resistor and bypass SHDN to GND with a 0.01µF capacitor.

SHDN

24

25

26

DL3

BST3

LX3

Gate-Drive Output for the Low-Side Synchronous-Rectifier MOSFET. Swings 0V to VL.

Boost Capacitor Connection for High-Side Gate Drive (0.1µF)

Switching Node (Inductor) Connection. Can swing 2V below ground without hazard.

Gate-Drive Output for the 3.3V, High-Side n-Channel Switch. DH3 is a floating driver output that swings

from LX3 to BST3, riding on the LX3 switching node voltage.

27

28

DH3

RUN/ON3

ON/OFF Control Input. See Power-Up Sequencing and ON/OFF Controls section.

_______________________________________________________________________________________

7

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

ON/OFF

INPUT

C3

+5V ALWAYS ON

4.7μF

10Ω

0.1μF

V+ SHDN SECFB VL

0.1μF

SYNC

BST3

4.7μF

0.1μF

BST5

DH5

Q3

Q4

Q1

Q2

DH3

0.1μF

L1

0.1μF

L2

R1

+5V OUTPUT

C1

R2

+3.3V OUTPUT

LX5

DL5

LX3

MAX1631A

MAX1634A

C2

*

DL3

PGND

CSH3

CSL3

FB3

CSH5

CSL5

FB5

RESET OUTPUT

RESET

TIME/ON5

RUN/ON3

5V ON/OFF

SKIP

3.3V ON/OFF

STEER

GND

REF

SEQ

+2.5V ALWAYS ON

1μF

*1A SCHOTTKY DIODE REQUIRED

FOR THE MAX1631A (SEE OUTPUT

OVERVOLTAGE PROTECTION SECTION).

Figure 1. Standard 3.3V/5V Application Circuit (MAX1631A/MAX1634A)

cy of these circuits without first recalculating compo-

nent values (particularly inductance value at maximum

battery voltage). Adding a Schottky rectifier across

each synchronous rectifier improves the efficiency of

these circuits by approximately 1%, but this rectifier is

otherwise not needed because the MOSFETs required

for these circuits typically incorporate a high-speed sili-

con diode from drain to source. Use a Schottky rectifier

rated at a DC current equal to at least 1/3 of the load

current.

_______Standard Application Circuit

The basic MAX1631A/MAX1634A dual-output 3.3V/5V

buck converter (Figure 1) is easily adapted to meet a

wide range of applications with inputs up to 28V by

substituting components from Table 1. These circuits

represent a good set of tradeoffs between cost, size,

and efficiency, while staying within the worst-case

specification limits for stress-related parameters, such

as capacitor ripple current. Do not change the frequen-

8

_______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Table 1. Component Selection for Standard 3.3V/5V Application

LOAD CURRENT

3A

COMPONENT

2A

4A

Input Range

4.75V to 18V

PDA

4.75V to 28V

4.75V to 24V

Workstation

200kHz

Application

Frequency

Notebook

300kHz

1/2 IR IRF7301;

IR IRF7403 or IRF7401 (18V

max); Siliconix Si4412DY; or

Motorola MMSF5N03HD or

MMSF5N02HD (18V max)

Q1, Q3 High-Side

MOSFETs

1/2 Siliconix Si9925DQ; or

1/2 Motorola MMDF3N03HD or

MMDF4N01HD (10V max)

IR IRF7413 or

Siliconix Si4410DY

1/2 IR IRF7301;

IR IRF7403 or IRF7401 (18V

max); Siliconix Si4412DY; or

Motorola MMSF5N03HD or

MMSF5N02HD (18V max)

Q2, Q4 Low-Side

MOSFETs

1/2 Siliconix Si9925DQ; or

1/2 Motorola MMDF3N03HD or

MMDF4N01HD (10V max)

IR IRF7413 or

Siliconix Si4410DY

10µF, 30V Sanyo OS-CON;

22µF, 35V AVX TPS; or

Sprague 594D

2 x 10µF, 30V Sanyo OS-CON;

2 x 22µF, 35V AVX TPS; or

Sprague 594D

3 x 10µF, 30V Sanyo OS-CON;

4 x 22µF, 35V AVX TPS; or

Sprague 595D

C3 Input Capacitor

C1, C2 Output Capacitors

R1, R2 Resistors

220µF, 10V AVX TPS or

Sprague 595D

2 x 220µF, 10V AVX TPS or

Sprague 595D

4 x 220µF, 10V AVX TPS or

Sprague 595D

0.033Ω IRC LR2010-01-R033 or

Dale WSL2010-R033-F

0.02Ω IRC LR2010-01-R020 or

Dale WSL2010-R020-F

0.012Ω Dale WSL2512-R012-F

15µH, 2.4A Ferrite

10µH, 4A Ferrite

4.7µH, 5.5A Ferrite

Coilcraft DO3316P-153 or

Sumida CDRH125-150

Coilcraft DO3316P-103 or

Sumida CDRH125-100

Coilcraft DO3316-472 or

5.2µH, 6.5A Ferrite Sumida

CDRH127-5R2MC

L1, L2 Inductors

Table 2. Component Suppliers

FACTORY FAX

COMPANY

FACTORY FAX

(COUNTRY CODE)

USA PHONE

COMPANY

USA PHONE

(COUNTRY CODE)

AVX

(1) 803-626-3123

(1) 516-435-1824

803-946-0690

516-435-1110

Motorola

Murata-Erie

NIEC

(1) 602-994-6430

(1) 814-238-0490

(81) 3-3494-7414

(81) 7-2070-1174

(1) 408-970-3950

(1) 603-224-1430

(81) 3-3607-5144

(1) 847-390-4428

602-303-5454

814-237-1431

805-867-2555*

619-661-6835

408-988-8000

603-224-1961

847-956-0666

847-390-4373

Central

Semiconductor

Coilcraft

Coiltronics

Dale

(1) 847-639-1469

(1) 561-241-9339

(1) 605-665-1627

847-639-6400

561-241-7876

605-668-4131

Sanyo

Siliconix

Sprague

Sumida

TDK

International

Rectifier (IR)

(1) 310-322-3332

310-322-3331

IRC

(1) 512-992-3377

(1) 714-960-6492

512-992-7900

714-969-2491

Transpower

Technologies

(1) 702-831-3521

702-831-0140

Matsuo

*Distributor

_______________________________________________________________________________________

9

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

VL/CSL5 bootstrap switch connected to the +5V PWM,

_______________Detailed Description

and SECFB. The heart of each current-mode PWM con-

troller is a multi-input, open-loop comparator that sums

three signals: the output voltage error signal with

respect to the reference voltage, the current-sense sig-

nal, and the slope compensation ramp (Figure 3). The

PWM controller is a direct-summing type, lacking a tra-

ditional error amplifier and the phase shift associated

with it. This direct-summing configuration approaches

ideal cycle-by-cycle control over the output voltage.

The MAX1630A is a dual, BiCMOS, switch-mode power-

supply controller designed primarily for buck-topology

regulators in battery-powered applications where high effi-

ciency and low quiescent supply current are critical. Light-

load efficiency is enhanced by automatic Idle Mode

operation, a variable-frequency pulse-skipping mode that

reduces transition and gate-charge losses. Each step-

down, power-switching circuit consists of two n-channel

MOSFETs, a rectifier, and an LC output filter. The output

voltage is the average AC voltage at the switching node,

which is regulated by changing the duty cycle of the

MOSFET switches. The gate-drive signal to the n-channel

high-side MOSFET must exceed the battery voltage, and

is provided by a flying-capacitor boost circuit that uses a

100nF capacitor connected to BST_.

When SKIP = low, Idle Mode circuitry automatically

optimizes efficiency throughout the load current range.

Idle Mode dramatically improves light-load efficiency

by reducing the effective frequency, which reduces

switching losses. It keeps the peak inductor current

above 25% of the full current limit in an active cycle,

allowing subsequent cycles to be skipped. Idle Mode

transitions seamlessly to fixed-frequency PWM opera-

tion as load current increases.

Devices in the MAX1630A family contain 10 major circuit

blocks (Figure 2).

The two PWM controllers each consist of a Dual Mode

feedback network and multiplexer, a multi-input PWM

comparator, high-side and low-side gate drivers, and

logic. The MAX1630A/MAX1631A/MAX1632A contain

fault-protection circuits that monitor the main PWM out-

puts for undervoltage and overvoltage. A power-on

sequence block controls the power-up timing of the

main PWMs and determines whether one or both of the

outputs are monitored for undervoltage faults. The

MAX1630A/MAX1632A/MAX1633A/MAX1635A include

a secondary feedback network and 12V linear regulator

to generate a 12V output from a coupled-inductor fly-

back winding. The MAX1631A/MAX1634A have an

SECFB instead, which allows a quasi-regulated,

adjustable-output, coupled-inductor flyback winding to

be attached to either the 3.3V or the 5V main inductor.

Bias generator blocks include the 5V IC internal rail (VL)

linear regulator, 2.5V precision reference, and automatic

bootstrap switchover circuit. The PWMs share a com-

mon 200kHz/300kHz synchronizable oscillator.

With SKIP = high, the controller always operates in

fixed-frequency PWM mode for lowest noise. Each

pulse from the oscillator sets the main PWM latch that

turns on the high-side switch for a period determined

by the duty factor (approximately V

/V ). As the

OUT IN

high-side switch turns off, the synchronous rectifier

latch sets; 60ns later, the low-side switch turns on. The

low-side switch stays on until the beginning of the next

clock cycle.

In PWM mode, the controller operates as a fixed-

frequency current-mode controller where the duty ratio

is set by the input/output voltage ratio. The current-

mode feedback system regulates the peak inductor

Table 3. SKIP PWM Table

LOAD

CURRENT

SKIP

MODE

DESCRIPTION

Pulse-skipping, supply cur-

rent = 250µA at V = 12V,

discontinuous inductor

current

IN

These internal IC blocks are not powered directly from

the battery. Instead, the 5V VL linear regulator steps

down the battery voltage to supply both VL and the

gate drivers. The synchronous-switch gate drivers are

directly powered from VL, while the high-side switch

gate drivers are indirectly powered from VL through an

external diode-capacitor boost circuit. An automatic

bootstrap circuit turns off the +5V linear regulator and

powers the IC from the 5V PWM output voltage if the

output is above 4.5V.

Low

Light

Idle

Constant-frequency PWM,

continuous inductor current

Low

High

Heavy

Light

PWM

Constant-frequency PWM,

continuous inductor current

Constant-frequency PWM,

continuous inductor current

Heavy

PWM Controller Block

The two PWM controllers are nearly identical. The only

differences are fixed output settings (3.3V vs. 5V), the

10 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

INPUT

SHDN

V+

SYNC

CSL5

-

MAX1632A

+

4.5V

ON/OFF

5V

LINEAR

REG

12OUT

+12V

12V

LINEAR

REG

+5V ALWAYS ON

VL

IN

V

DD

REF

SECFB

+

-

2.5V

REF

13V

RAW +15V

BST3

BST5

DH3

LX3

DH5

LX5

3.3V

PWM

LOGIC

5V

PWM

LOGIC

200kHz

TO

300kHz

OSC

+5V

+3.3V

VL

DL3

DL5

PGND

OV/UV

FAULT

CSH3

CSL3

+

-

CSH5

CSL5

REF

-

+

LPF

60kHz

LPF

60kHz

1.75V

2.68V

2.388V

-

R1

R2

-

R3

FB3

FB5

OUTPUTS

UP

-

R4

+

0.6V

RESET

SEQ

VL

TIMER

2.6V

-

TIME/ON5

+

POWER-ON

SEQUENCE

LOGIC

REF

-

+

1V

-

RUN/ON3

GND

Figure 2. MAX1632A Block Diagram

______________________________________________________________________________________ 11

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

CSH_

CSL_

1X

REF

FROM

FEEDBACK

DIVIDER

MAIN PWM

COMPARATOR

BST_

DH_

LX_

R

Q

LEVEL

SHIFT

S

SLOPE COMP

OSC

30mV

SKIP

CURRENT

LIMIT

DAC

SHOOT-

THROUGH

CONTROL

CK

COUNTER

SHDN

SOFT-START

SYNCHRONOUS

RECTIFIER CONTROL

VL

R

S

Q

LEVEL

SHIFT

DL_

-100mV

PGND

REF

1μs

SINGLE-SHOT

SECFB

Figure 3. PWM Controller Detailed Block Diagram

12 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

current value as a function of the output-voltage error

(ESR) (see the Design Procedure section). A 60kHz

pole-zero cancellation filter provides additional rolloff

above the unity-gain crossover. This internal 60kHz low-

pass compensation filter cancels the zero due to filter

capacitor ESR. The 60kHz filter is included in the loop in

both fixed-output and adjustable-output modes.

signal. In continuous-conduction mode, the average

inductor current is nearly the same as the peak current,

so the circuit acts as a switch-mode transconductance

amplifier. This pushes the second output LC filter pole,

normally found in a duty-factor-controlled (voltage-

mode) PWM, to a higher frequency. To preserve inner-

loop stability and eliminate regenerative inductor

current “staircasing,” a slope compensation ramp is

summed into the main PWM comparator to make the

apparent duty factor less than 50%.

Synchronous Rectifier Driver (DL)

Synchronous rectification reduces conduction losses in

the rectifier by shunting the normal Schottky catch diode

with a low-resistance MOSFET switch. Also, the synchro-

nous rectifier ensures proper startup of the boost gate-

driver circuit. If the synchronous power MOSFETs are

omitted for cost or other reasons, replace them with a

small-signal MOSFET, such as a 2N7002.

The MAX1630A family uses a relatively low loop gain,

allowing the use of lower cost output capacitors. The rel-

ative gains of the voltage-sense and current-sense

inputs are weighted by the values of current sources

that bias three differential input stages in the main PWM

comparator (Figure 4). The relative gain of the voltage

comparator to the current comparator is internally fixed

at K = 2:1. The low loop gain results in the 2% typical

load-regulation error. The low value of loop gain helps

reduce output filter capacitor size and cost by shifting

the unity-gain crossover frequency to a lower level.

If the circuit is operating in continuous-conduction mode,

the DL drive waveform is the complement of the DH high-

side drive waveform (with controlled dead time to prevent

cross-conduction or “shoot-through”). In discontinuous

(light-load) mode, the synchronous switch is turned off as

the inductor current falls through zero. The synchronous

rectifier works under all operating conditions, including

Idle Mode. The SECFB signal further controls the syn-

chronous switch timing to improve multiple-output cross-

regulation (see the Secondary Feedback Regulation

Loop section).

The output filter capacitors (Figure 1, C1 and C2) set a

dominant pole in the feedback loop that must roll off the

loop gain to unity before encountering the zero intro-

duced by the output capacitor’s parasitic resistance

VL

R1

R2

TO PWM

LOGIC

UNCOMPENSATED

HIGH-SPEED

FB_

LEVEL TRANSLATOR

AND BUFFER

OUTPUT DRIVER

I1

I2

I3

V

BIAS

REF

CSH_

CSL_

SLOPE COMPENSATION

Figure 4. Main PWM Comparator Block Diagram

______________________________________________________________________________________ 13

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

switch, an action that “boosts” the 5V gate-drive signal

Internal VL and REF Supplies

An internal regulator produces the +5V supply (VL) that

powers the PWM controller, logic, reference, and other

blocks within the IC. This 5V low-dropout linear regula-

tor supplies up to 25mA for external loads, with a

reserve of 25mA for supplying gate-drive power.

Bypass VL to GND with 4.7µF.

above the battery voltage.

Ringing at the high-side MOSFET gate (DH3 and DH5)

in discontinuous-conduction mode (light loads) is a nat-

ural operating condition. It is caused by residual ener-

gy in the tank circuit, formed by the inductor and stray

capacitance at the switching node, LX. The gate-drive

negative rail is referred to LX, so any ringing there is

directly coupled to the gate-drive output.

Important: Ensure that VL does not exceed 6V.

Measure VL with the main output fully loaded. If it is

pumped above 5.5V, either excessive boost diode

capacitance or excessive ripple at V+ is the probable

cause. Use only small-signal diodes for the boost cir-

cuit (10mA to 100mA Schottky or 1N4148 are pre-

ferred), and bypass V+ to PGND with 4.7µF directly at

the package pins.

Current-Limiting and Current-Sense

Inputs (CSH and CSL)

The current-limit circuit resets the main PWM latch and

turns off the high-side MOSFET switch whenever the

voltage difference between CSH and CSL exceeds

100mV. This limiting is effective for both current flow

directions, putting the threshold limit at 100mV. The

tolerance on the positive current limit is 20%, so the

external low-value sense resistor (R1) must be sized for

The 2.5V reference (REF) is accurate to 2% over tem-

perature, making REF useful as a precision system ref-

erence. Bypass REF to GND with 1µF minimum. REF

can supply up to 5mA for external loads. (Bypass REF

with a minimum 1µF/mA reference load current.)

However, if extremely accurate specifications for both

the main output voltages and REF are essential, avoid

loading REF more than 100µA. Loading REF reduces

the main output voltage slightly, because of the refer-

ence load-regulation error.

80mV/I

, where I

is the required peak inductor

PEAK

current to support the full load current, while compo-

nents must be designed to withstand continuous cur-

rent stresses of 120mV/R1.

For breadboarding or for very-high-current applications,

it may be useful to wire the current-sense inputs with a

twisted pair, rather than PC traces. (This twisted pair

need not be anything special; two pieces of wire-wrap

wire twisted together are sufficient.) This reduces the

possible noise picked up at CSH_ and CSL_, which can

cause unstable switching and reduced output current.

When the 5V main output voltage is above 4.5V, an

internal p-channel MOSFET switch connects CSL5 to

VL, while simultaneously shutting down the VL linear

regulator. This action bootstraps the IC, powering the

internal circuitry from the output voltage, rather than

through a linear regulator from the battery. Boot-

strapping reduces power dissipation due to gate

charge and quiescent losses by providing that power

from a 90%-efficient switch-mode source, rather than

from a much less efficient linear regulator.

The CSL5 input also serves as the IC’s bootstrap sup-

ply input. Whenever V

connects CSL5 to VL.

> 4.5V, an internal switch

CSL5

Oscillator Frequency and

Synchronization (SYNC)

The SYNC input controls the oscillator frequency. Low

selects 200kHz; high selects 300kHz. SYNC can also

be used to synchronize with an external 5V CMOS or

TTL clock generator. SYNC has a guaranteed 240kHz

to 350kHz capture range. A high-to-low transition on

SYNC initiates a new cycle.

Boost High-Side Gate-Drive Supply

(BST3 and BST5)

Gate-drive voltage for the high-side n-channel switches

is generated by a flying-capacitor boost circuit

(Figure 2). The capacitor between BST_ and LX_ is

alternately charged from the VL supply and placed par-

allel to the high-side MOSFET’s gate-source terminals.

300kHz operation optimizes the application circuit for

component size and cost. 200kHz operation provides

increased efficiency, lower dropout, and improved

load-transient response at low input-output voltage dif-

ferences (see the Low-Voltage Operation section).

On startup, the synchronous rectifier (low-side

MOSFET) forces LX_ to 0V and charges the boost

capacitors to 5V. On the second half-cycle, the SMPS

turns on the high-side MOSFET by closing an internal

switch between BST_ and DH_. This provides the nec-

essary enhancement voltage to turn on the high-side

14 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Shutdown Mode

Holding SHDN low puts the IC into its 4µA shutdown

mode. SHDN is logic input with a threshold of about 1V

Output Undervoltage Shutdown Protection

(MAX1630A/MAX1631A/MAX1632A)

The output undervoltage lockout circuit is similar to

foldback current limiting, but employs a timer rather

than a variable current limit. Each SMPS has an under-

voltage protection circuit that is activated 6144 clock

cycles after the SMPS is enabled. If either SMPS output

is under 70% of the nominal value, both SMPSs are

latched off and their outputs are clamped to ground by

the synchronous rectifier MOSFETs (see the Output

Overvoltage Protection section). They do not restart

until SHDN or RUN/ON3 is toggled, or until V+ power is

cycled below 1V. Note that undervoltage protection can

make prototype troubleshooting difficult, since you

have only 20ms or 30ms to figure out what might be

wrong with the circuit before both SMPSs are latched

off. In extreme cases, it may be useful to substitute the

MAX1633A/MAX1634A/MAX1635A into the prototype

breadboard until the prototype is working properly.

(the V

of an internal n-channel MOSFET). For auto-

TH

matic startup, bypass SHDN to GND with a 0.01µF

capacitor and connect it to V+ through a 220kΩ resistor.

Power-Up Sequencing

and ON/OFF Controls

Startup is controlled by RUN/ON3 and TIME/ON5 in

conjunction with SEQ. With SEQ tied to REF, the two

control inputs act as separate ON/OFF controls for

each supply. With SEQ tied to VL or GND, RUN/ON3

becomes the master ON/OFF control input and

TIME/ON5 becomes a timing pin, with the delay

between the two supplies determined by an external

capacitor. The delay is approximately 800µs/nF. The

+3.3V supply powers up first if SEQ is tied to VL, and

the +5V supply is first if SEQ is tied to GND. When driv-

ing TIME/ON5 as a control input with external logic,

always place a resistor (>1kΩ) in series with the input.

This prevents possible crowbar current due to the inter-

nal discharge pulldown transistor, which turns on in

standby mode and momentarily at the first power-up or

in shutdown mode.

Output Overvoltage Protection

(MAX1630A/MAX1631A/MAX1632A)

Both SMPS outputs are monitored for overvoltage. If

either output is more than 7% above the nominal regu-

lation point, both low-side gate drivers (DL_) are

latched high until SHDN or RUN/ON3 is toggled, or until

V+ power is cycled below 1V. This action turns on the

synchronous rectifiers with 100% duty, in turn rapidly

discharging the output capacitors and forcing both

SMPS outputs to ground. The DL outputs are also kept

high whenever the corresponding SMPS is disabled,

and in shutdown if VL is sustained.

RESET Power-Good Voltage Monitor

The power-good monitor generates a system RESET sig-

nal. At first power-up, RESET is held low until both the

3.3V and 5V SMPS outputs are in regulation. At this point,

an internal timer begins counting oscillator pulses, and

RESET continues to be held low until 32,000 cycles have

elapsed. After this timeout period (107ms at 300kHz or

160ms at 200kHz), RESET is actively pulled up to VL. If

SEQ is tied to REF (for separate ON3/ON5 controls), only

the 3.3V SMPS is monitored—the 5V SMPS is ignored.

Table 4. Operating Modes

SEQ

RUN/ON3

TIME/ON5

X

MODE

DESCRIPTION

SHDN

Low

X

Shutdown

Standby

Run

All circuit blocks turned off. Supply current = 4µA.

Both SMPSs off. Supply current = 30µA.

3.3V SMPS enabled/5V off.

High

Ref

GND

VL

Low

High

Low

High

Run

5V SMPS enabled/3.3V off.

High

Low

High

Run

Both SMPSs enabled.

Timing capacitor

Standby

Run

Both SMPSs off. Supply current = 30µA.

Both SMPSs enabled. 5V enabled before 3.3V.

Both SMPSs off. Supply current = 30µA.

Both SMPSs enabled. 3.3V enabled before 5V.

High

Low

Standby

Run

VL

High

X = Don’t care.

______________________________________________________________________________________ 15

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Discharging the output capacitor through the main

inductor causes the output to momentarily go below

GND. Clamp this negative pulse with a back-biased 1A

Schottky diode across the output capacitor (Figure 1).

Internal Digital Soft-Start Circuit

Soft-start allows a gradual increase of the internal cur-

rent-limit level at startup to reduce input surge currents.

Both SMPSs contain internal digital soft-start circuits,

each controlled by a counter, a digital-to-analog con-

verter (DAC), and a current-limit comparator. In shut-

down or standby mode, the soft-start counter is reset to

zero. When an SMPS is enabled, its counter starts

counting oscillator pulses, and the DAC begins incre-

menting the comparison voltage applied to the current-

limit comparator. The DAC output increases from 0mV to

100mV in five equal steps as the count increases to 512

clocks. As a result, the main output capacitor charges

up relatively slowly. The exact time of the output rise

depends on output capacitance and load current, and

is typically 1ms with a 300kHz oscillator.

To ensure overvoltage protection on initial power-up,

connect signal diodes from both output voltages to VL

(cathodes to VL) to eliminate the VL power-up delay.

This circuitry protects the load from accidental overvolt-

age caused by a short-circuit across the high-side

power MOSFETs. This scheme relies on the presence

of a fuse, in series with the battery, which is blown by

the resulting crowbar current. Note that the overvoltage

circuitry will interfere with external keep-alive supplies

that hold up the outputs (such as lithium backup or hot-

swap power supplies); in such cases, the MAX1633A,

MAX1634A, or MAX1635A should be used.

Dropout Operation

Dropout (low input-output differential operation) is

enhanced by stretching the clock pulse width to

increase the maximum duty factor. The algorithm fol-

Low-Noise Operation (PWM Mode)

PWM mode (SKIP = high) minimizes RF and audio

interference in noise-sensitive applications (such as hi-

fi multimedia-equipped systems), cellular phones, RF

communicating computers, and electromagnetic pen-

entry systems. See the summary of operating modes in

Table 2. SKIP can be driven from an external logic

signal.

lows: If the output voltage (V

) drops out of regula-

OUT

tion without the current limit having been reached, the

SMPS skips an off-time period (extending the on-time).

At the end of the cycle, if the output is still out of regula-

tion, the SMPS skips another off-time period. This

action can continue until three off-time periods are

skipped, effectively dividing the clock frequency by as

much as four.

Interference due to switching noise is reduced in PWM

mode by ensuring a constant switching frequency, thus

concentrating the emissions at a known frequency out-

side the system audio or IF bands. Choose an oscillator

frequency for which switching frequency harmonics do

not overlap a sensitive frequency band. If necessary,

synchronize the oscillator to a tight-tolerance external

clock generator. To extend the output-voltage-regula-

tion range, constant operating frequency is not main-

tained under overload or dropout conditions (see the

Overload and Dropout Operation section.)

The typical PWM minimum off-time is 300ns, regardless

of the operating frequency. Lowering the operating fre-

quency raises the maximum duty factor above 98%.

Adjustable-Output Feedback

(Dual Mode FB)

Fixed, preset output voltages are selected when FB_ is

connected to ground. Adjusting the main output volt-

age with external resistors is simple for any of the

MAX1630A family ICs, through resistor-dividers con-

nected to FB3 and FB5 (Figure 2). Calculate the output

voltage with the following formula:

PWM mode (SKIP = high) forces two changes upon the

PWM controllers. First, it disables the minimum-current

comparator, ensuring fixed-frequency operation.

Second, it changes the detection threshold for reverse-

current limit from 0mV to -100mV, allowing the inductor

current to reverse at light loads. This results in fixed-

frequency operation and continuous inductor-current

flow. This eliminates discontinuous-mode inductor ring-

ing and improves cross regulation of transformer-

coupled multiple-output supplies, particularly in circuits

that do not use additional secondary regulation through

V

OUT

= V

(1 + R1 / R2)

REF

where V

= 2.5V nominal.

REF

The nominal output should be set approximately 1% or

2% high to make up for the MAX1630A’s -2% typical

load-regulation error. For example, if designing for a

3.0V output, use a resistor ratio that results in a nominal

output voltage of 3.05V. This slight offsetting gives the

best possible accuracy. Recommended normal values

for R2 range from 5kΩ to 100kΩ. To achieve a 2.5V

nominal output, connect FB_ directly to CSL_.

SECFB or V

.

DD

In most applications, tie SKIP to GND to minimize qui-

escent supply current. VL supply current with SKIP high

is typically 20mA, depending on external MOSFET gate

capacitance and switching losses.

16 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Remote output-voltage sensing, while not possible in

fixed-output mode due to the combined nature of the

voltage-sense and current-sense inputs (CSL3 and

CSL5), is easy to do in adjustable mode by using the top

of the external resistor-divider as the remote sense point.

R2

SECFB

1-SHOT

TRIG

R1

When using adjustable mode, it is a good idea to

always set the “3.3V output” to a lower voltage than the

“5V output.” The 3.3V output must always be less than

VL, so that the voltage on CSH3 and CSL3 is within the

common-mode range of the current-sense inputs. While

VL is nominally 5V, it can be as low as 4.7V when lin-

early regulating, and as low as 4.2V when automatically

bootstrapped to CSH5.

POSITIVE

SECONDARY

OUTPUT

V+

2.5V REF

DH_

MAIN

OUTPUT

MAX1631A

MAX1634A

DL_

Secondary Feedback Regulation Loop

(SECFB or V

)

DD

A flyback-winding control loop regulates a secondary

winding output, improving cross-regulation when the

primary output is lightly loaded or when there is a low

R1

+V = V_REF(1 + –––)

WHERE V (NOMINAL) = 2.5V

REF

TRIP

R2

input-output differential voltage. If V

or SECFB falls

DD

below its regulation threshold, the low-side switch is

turned on for an extra 1µs. This reverses the inductor

(primary) current, pulling current from the output filter

capacitor and causing the flyback transformer to oper-

ate in forward mode. The low impedance presented by

the transformer secondary in forward mode dumps cur-

rent into the secondary output, charging up the sec-

Figure 5. Adjusting the Secondary Output Voltage with SECFB

+12V OUTPUT

200mA

12OUT

0.1μF

10μF

V

DD

2N3906

ondary capacitor and bringing V

or SECFB back into

DD

regulation. The secondary feedback loop does not

improve secondary output accuracy in normal flyback

mode, where the main (primary) output is heavily

loaded. In this condition, secondary output accuracy is

determined by the secondary rectifier drop, transformer

turns ratio, and accuracy of the main output voltage. A

linear postregulator may still be needed to meet strict

output-accuracy specifications.

0.1μF

10Ω

0.1μF

MAX1630A

MAX1632A

MAX1633A

MAX1635A

V+

V

OUTPUT

DD

2.2μF

DH_

DL_

Devices with a 12OUT linear regulator have a V

DD

MAIN

OUTPUT

that regulates at a fixed 13.5V, set by an internal

resistor-divider. The MAX1631A/MAX1634A have an

adjustable secondary output voltage set by an external-

resistor-divider on SECFB (Figure 5). Ordinarily, the

secondary regulation point is set 5% to 10% below the

voltage normally produced by the flyback effect. For

example, if the output voltage as determined by turns

ratio is 15V, set the feedback resistor ratio to produce

13.5V. Otherwise, the SECFB one-shot might be trig-

gered unintentionally, unnecessarily increasing supply

current and output noise.

Figure 6. Increased 12V Linear Regulator Output Current

12V Linear Regulator Output

(MAX1630A/MAX1632A/

MAX1633A/MAX1635A)

The MAX1630A/MAX1632A/MAX1633A/MAX1635A

include a 12V linear regulator output capable of deliver-

ing 120mA of output current. Typically, greater current is

available at the expense of output accuracy. If an accu-

______________________________________________________________________________________ 17

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

rate output of more than 120mA is needed, an external

pass transistor can be added. Figure 6’s circuit delivers

more than 200mA. Total output current is constrained

by the V+ input voltage and the transformer primary

intended mainly for high-efficiency, battery-powered

applications. Refer to Appendix A in Maxim’s Battery

Management and DC-DC Converter Circuit Collection

for crossover-point and discontinuous-mode equations.

Discontinuous conduction doesn’t affect normal Idle

Mode operation.

load (see Maximum 15V V

Output Current vs.

DD

Supply Voltage graphs in the Typical Operating

Characteristics).

Three key inductor parameters must be specified:

inductance value (L), peak current (I

), and DC

PEAK

__________________Design Procedure

resistance (R ). The following equation includes a

DC

The three predesigned 3V/5V standard application cir-

cuits (Figure 1 and Table 1) contain ready-to-use solu-

tions for common application needs. Also, two standard

flyback transformer circuits support the 12OUT linear

regulator in the Applications Information section. Use

the following design procedure to optimize these basic

schematics for different voltage or current require-

ments. Before beginning a design, firmly establish the

following:

constant, LIR, which is the ratio of inductor peak-to-

peak AC current to DC load current. A higher LIR value

allows smaller inductance, but results in higher losses

and higher ripple. A good compromise between size

and losses is found at a 30% ripple-current to load-

current ratio (LIR = 0.3), which corresponds to a peak

inductor current 1.15 times higher than the DC load

current:

V

(V

- V

)

OUT IN(MAX)

x f x I

OUT

•

Maximum input (battery) voltage, V

. This

IN(MAX)

L =

V

x LIR

OUT

value should include the worst-case conditions,

such as no-load operation when a battery charger

or AC adapter is connected but no battery is

IN(MAX)

where:

installed. V

must not exceed 30V.

IN(MAX)

f = switching frequency, normally 200kHz or

300kHz

•

Minimum input (battery) voltage, V

. This

IN(MIN)

should be taken at full load under the lowest battery

conditions. If V is less than 4.2V, use an

I

= maximum DC load current

OUT

IN(MIN)

LIR = ratio of AC to DC inductor current, typi-

cally 0.3; should be selected for >0.15

external circuit to externally hold VL above the VL

undervoltage lockout threshold. If the minimum

input-output difference is less than 1.5V, the filter

capacitance required to maintain good AC load

regulation increases (see Low-Voltage Operation

section).

The nominal peak inductor current at full load is 1.15 x

I

if the above equation is used; otherwise, the peak

OUT

current can be calculated by:

V

(V

- V

)

OUT IN(MAX)

2 x f x L x V

OUT

I

= I

+

PEAK

LOAD

Inductor Value

IN(MAX)

The exact inductor value is not critical and can be

freely adjusted to make trade-offs between size, cost,

and efficiency. Lower inductor values minimize size

and cost, but reduce efficiency due to higher peak-cur-

rent levels. The smallest inductor is achieved by lower-

ing the inductance until the circuit operates at the

border between continuous and discontinuous mode.

Further reducing the inductor value below this

crossover point results in discontinuous-conduction

operation even at full load. This helps lower output filter

capacitance requirements, but efficiency suffers due to

high I²R losses. On the other hand, higher inductor val-

ues mean greater efficiency, but resistive losses due to

extra wire turns will eventually exceed the benefit

gained from lower peak-current levels. Also, high

inductor values can affect load-transient response (see

The inductor’s DC resistance should be low enough that

x I < 100mV, as it is a key parameter for effi-

R

DC

PEAK

ciency performance. If a standard off-the-shelf inductor

is not available, choose a core with an LI²rating greater

than L x I

2 and wind it with the largest diameter

PEAK

wire that fits the winding area. For 300kHz applications,

ferrite core material is strongly preferred; for 200kHz

applications, Kool-Mµ (aluminum alloy) or even pow-

®

dered iron is acceptable. If light-load efficiency is unim-

portant (in desktop PC applications, for example), then

low-permeability iron-powder cores, such as the

Micrometals type found in Pulse Engineering’s 2.1µH

PE-53680, may be acceptable even at 300kHz. For

high-current applications, shielded-core geometries,

such as toroidal or pot core, help keep noise, EMI, and

switching-waveform jitter low.

the V

equation in the Low-Voltage Operation sec-

SAG

tion). The equations that follow are for continuous-con-

duction operation, since the MAX1630A family is

Kool-Mµ is a registered trademark of Magnetics Div., Spang & Co.

18 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Current-Sense Resistor Value

The current-sense resistor value is calculated according

to the worst-case-low current-limit threshold voltage

(from the Electrical Characteristics table) and the peak

inductor current:

Output Filter Capacitor Value

The output filter capacitor values are generally deter-

mined by the ESR and voltage rating requirements, rather

than actual capacitance requirements for loop stability. In

other words, the low-ESR electrolytic capacitor that meets

the ESR requirement usually has more output capaci-

tance than is required for AC stability. Use only special-

ized low-ESR capacitors intended for switching-regulator

applications, such as AVX TPS, Sprague 595D, Sanyo

OS-CON, or Nichicon PL series. To ensure stability, the

capacitor must meet both minimum capacitance and

maximum ESR values as given in the following equations:

80mV

R

=

SENSE

I

PEAK

Use I

from the second equation in the Inductor

PEAK

Value section

Use the calculated value of R

to size the MOSFET

SENSE

switches and specify inductor saturation-current ratings

according to the worst-case high-current-limit threshold

voltage:

V

(1 + V

/ V

)

REF

OUT

IN(MIN)

C

>

OUT

V

x R

x f

OUT

R

SENSE

x V

120mV

SENSE

OUT

R

<

I

=

ESR

PEAK(MAX)

V

R

REF

SENSE

Low-inductance resistors, such as surface-mount

metal-film, are recommended.

(can be multiplied by 1.5; see text below)

These equations are worst case, with 45 degrees of

phase margin to ensure jitter-free, fixed-frequency

operation and provide a nicely damped output

response for zero to full-load step changes. Some cost-

conscious designers may wish to bend these rules with

less-expensive capacitors, particularly if the load lacks

large step changes. This practice is tolerable if some

bench testing over temperature is done to verify

acceptable noise and transient response.

Input Capacitor Value

Connect low-ESR bulk capacitors and small ceramic

capacitors (0.1µF) directly to the drains on the high-side

MOSFETs. The bulk input filter capacitor is usually

selected according to input ripple current requirements

and voltage rating, rather than capacitor value.

Electrolytic capacitors with low enough effective series

resistance (ESR) to meet the ripple current requirement

invariably have sufficient capacitance values. Aluminum

No well-defined boundary exists between stable and

unstable operation. As phase margin is reduced, the

first symptom is a bit of timing jitter, which shows up as

blurred edges in the switching waveforms where the

scope does not quite sync up. Technically speaking,

this jitter (usually harmless) is unstable operation, since

the duty factor varies slightly. As capacitors with higher

ESRs are used, the jitter becomes more pronounced,

and the load-transient output voltage waveform starts

looking ragged at the edges. Eventually, the load-tran-

sient waveform has enough ringing on it that the peak

noise levels exceed the allowable output voltage toler-

ance. Note that even with zero phase margin and gross

instability present, the output voltage noise never gets

electrolytic

capacitors,

such

as

Sanyo

OS-CON or Nichicon PL, are superior to tantalum types,

which carry the risk of power-up surge-current failure,

especially when connecting to robust AC adapters or

low-impedance batteries. RMS input ripple current

(I

) is determined by the input voltage and load cur-

RMS

rent, with the worst case occurring at V = 2 x V

:

IN

OUT

V

(V -V

)

OUT IN OUT

I

= I

x

RMS

LOAD

V

IN

Therefore, when V is 2 X V

IN

:

OUT

I

LOAD

2

I

=

RMS

much worse than I

x R

(under constant loads).

PEAK

ESR

Designers of RF communicators or other noise-sensi-

tive analog equipment should be conservative and stay

within the guidelines. Designers of notebook computers

and similar commercial-temperature-range digital

Bypassing V+

Bypass the V+ input with a 4.7µF tantalum capacitor

paralleled with a 0.1µF ceramic capacitor, close to the

IC. A 10Ω series resistor to V is also recommended.

IN

systems can multiply the R

value by a factor of 1.5

ESR

without hurting stability or transient response.

Bypassing VL

Bypass the VL output with a 4.7µF tantalum capacitor

paralleled with a 0.1µF ceramic capacitor, close to the

device.

The output voltage ripple is usually dominated by the

filter capacitor’s ESR, and can be approximated as

I

x R

. There is also a capacitive term, so the

ESR

RIPPLE

______________________________________________________________________________________ 19

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

full equation for ripple in continuous-conduction mode

is V = I x [R + 1/(2 x π x f x

VOUT(MIN) = the minimum value of the main output

voltage (from the Electrical Characteristics)

= the on-state voltage drop across the synchro-

NOISE (P-P)

RIPPLE

ESR

C

)]. In Idle Mode, the inductor current becomes

OUT

V

RECT

discontinuous, with high peaks and widely spaced

pulses, so the noise can actually be higher at light load

(compared to full load). In Idle Mode, calculate the out-

put ripple as follows:

nous rectifier MOSFET

V

= the voltage drop across the sense resistor

SENSE

In positive-output applications, the transformer sec-

ondary return is often referred to the main output volt-

age, rather than to ground, to reduce the needed turns

ratio. In this case, the main output voltage must first be

0.02 x R

ESR

V

=

+

NOISE(P-P)

R

SENSE

subtracted from the secondary voltage to obtain V

.

SEC

0.0003 x Lx 1 / V

+1 / (V - V

)

]

[

OUT

2

IN OUT

) x C

OUT

Selecting Other Components

(R

SENSE

MOSFET Switches

The high-current n-channel MOSFETs must be logic-level

types with guaranteed on-resistance specifications at

Transformer Design

(for Auxiliary Outputs Only)

V

= 4.5V. Lower gate threshold specifications are bet-

GS

Buck-plus-flyback applications, sometimes called “cou-

pled-inductor” topologies, need a transformer to gener-

ate multiple output voltages. Performing the basic

electrical design is a simple task of calculating turns

ratios and adding the power delivered to the secondary

to calculate the current-sense resistor and primary

inductance. However, extremes of low input-output dif-

ferentials, widely different output loading levels, and

high turns ratios can complicate the design due to par-

asitic transformer parameters such as interwinding

capacitance, secondary resistance, and leakage

inductance. For examples of what is possible with real-

world transformers, see the Maximum Secondary

Current vs. Input Voltage graph in the Typical

Operating Characteristics section.

ter (i.e., 2V max rather than 3V max). Drain-source break-

down voltage ratings must at least equal the maximum

input voltage, preferably with a 20% derating factor. The

best MOSFETs have the lowest on-resistance per

nanocoulomb of gate charge. Multiplying R

x Q

G

DS(ON)

provides a good figure for comparing various MOSFETs.

Newer MOSFET process technologies with dense cell

structures generally perform best. The internal gate dri-

vers tolerate >100nC total gate charge, but 70nC is a

more practical upper limit to maintain best switching

times.

In high-current applications, MOSFET package power

dissipation often becomes a dominant design factor. I²R

power losses are the greatest heat contributor for both

high-side and low-side MOSFETs. I²R losses are distrib-

uted between Q1 and Q2 according to duty factor (see

the following equations). Generally, switching losses

affect only the upper MOSFET, since the Schottky rectifier

clamps the switching node in most cases before the syn-

chronous rectifier turns on. Gate-charge losses are dissi-

pated by the driver and do not heat the MOSFET.

Calculate the temperature rise according to package

thermal-resistance specifications to ensure that both

MOSFETs are within their maximum junction temperature

at high ambient temperature. The worst-case dissipation

for the high-side MOSFET occurs at both extremes of

input voltage, and the worst-case dissipation for the low-

side MOSFET occurs at maximum input voltage:

Power from the main and secondary outputs is combined

to get an equivalent current referred to the main output

voltage (see the Inductor Value section for parameter def-

initions). Set the current-sense resistor resistor value at

80mV / I

.

TOTAL

P

= The sum of the output power from all outputs

TOTAL

I

= P

/ V

= The equivalent output cur-

OUT

TOTAL

rent referred to V

:

OUT

V

(V

- V

)

OUT IN(MAX)

OUT

L(primary) =

V

x f x I

x LIR

TOTAL

IN(MAX)

V

+ V

FWD

SEC

Turns Ratio N =

V

+V

OUT(MIN)

RECT SENSE

2

PD(upper FET)= (I

)

x R

x DUTY

DS(ON)

LOAD

⎛

⎞

V

x C

RSS

IN

I

+V x I

x f x

+ 20ns

⎟

IN

LOAD

⎜

where:

⎝

⎠

GATE

V

= the minimum required rectified secondary out-

SEC

put voltage

2

PD(lower FET) = (I

)

x R

x (1 - DUTY)

LOAD

DS(ON)

)

DUTY = (V

+V ) / (V - V

V

= the forward drop across the secondary

OUT

Q2

IN Q1

FWD

rectifier

20 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

where:

on-state voltage drop V = I

Common silicon rectifiers, such as the 1N4001, are also

prohibited because they are too slow. This often makes

fast silicon rectifiers such as the MURS120 the only

choice. The flyback voltage across the rectifier is relat-

x R

DS(ON)

Q_

LOAD

C

= MOSFET reverse transfer capacitance

RSS

I

=DH driver peak output current capability

ed to the V - V

difference, according to the trans-

OUT

GATE

(1A typical)

IN

former turns ratio:

20ns = DH driver inherent rise/fall time

V

= V

+ (V - V

) x N

FLYBACK

SEC

IN OUT

Under output short circuit, the MAX1633A/MAX1634A/

MAX1635As’ synchronous rectifier MOSFET suffers

extra stress because its duty factor can increase to

greater than 0.9. It may need to be oversized to tolerate

a continuous DC short circuit. During short circuit, the

MAX1630A/MAX1631A/MAX1632As’ output undervolt-

age shutdown protects the synchronous rectifier under

output short-circuit conditions.

where:

N = the transformer turns ratio SEC/PRI

V

= the maximum secondary DC output voltage

= the primary (main) output voltage

SEC

OUT

Subtract the main output voltage (V

) from V

FLYBACK

OUT

in this equation if the secondary winding is returned to

V and not to ground. The diode reverse breakdown

OUT

To reduce EMI, add a 0.1µF ceramic capacitor from the

high-side switch drain to the low-side switch source.

rating must also accommodate any ringing due to leak-

age inductance. D3’s current rating should be at least

twice the DC load current on the secondary output.

Rectifier Clamp Diode

The rectifier is a clamp across the low-side MOSFET

that catches the negative inductor swing during the

60ns dead time between turning one MOSFET off and

each low-side MOSFET on. The latest generations of

MOSFETs incorporate a high-speed silicon body diode,

which serves as an adequate clamp diode if efficiency

is not of primary importance. A Schottky diode can be

placed in parallel with the body diode to reduce the for-

ward voltage drop, typically improving efficiency 1% to

2%. Use a diode with a DC current rating equal to one-

third of the load current; for example, use an MBR0530

(500mA-rated) type for loads up to 1.5A, a 1N5819 type

for loads up to 3A, or a 1N5822 type for loads up to

10A. The rectifier’s rated reverse breakdown voltage

must be at least equal to the maximum input voltage,

preferably with a 20% derating factor.

Low-Voltage Operation

Low input voltages and low input-output differential

voltages each require extra care in their design. Low

absolute input voltages can cause the VL linear regula-

tor to enter dropout and eventually shut itself off. Low

input voltages relative to the output (low V -V

dif-

IN OUT

ferential) can cause bad load regulation in multi-output

flyback applications (see the design equations in the

Transformer Design section). Also, low V -V

differ-

IN OUT

entials can also cause the output voltage to sag when

the load current changes abruptly. The amplitude of the

sag is a function of inductor value and maximum duty

factor (an Electrical Characteristics parameter, 98%

guaranteed over temperature at f = 200kHz), as follows:

2

(I

x (V

) x L

x D

STEP

Boost-Supply Diode D2

A signal diode such as a 1N4148 works well in most

applications. If the input voltage can go below +6V, use

a small (20mA) Schottky diode for slightly improved

efficiency and dropout characteristics. Do not use large

power diodes, such as 1N5817 or 1N4001, since high

junction capacitance can pump up VL to excessive

voltages.

V

=

SAG

2 x C

- V

)

OUT

IN(MAX)

MAX

OUT

The cure for low-voltage sag is to increase the output

capacitor’s value. For example, at V = +5.5V, V

=

OUT

IN

+5V, L = 10µH, f = 200kHz, I

= 3A, a total capaci-

STEP

tance of 660µF keeps the sag less than 200mV. Note

that only the capacitance requirement increases, and

the ESR requirements do not change. Therefore, the

added capacitance can be supplied by a low-cost bulk

capacitor in parallel with the normal low-ESR capacitor.

Rectifier Diode D3

(Transformer Secondary Diode)

The secondary diode in coupled-inductor applications

must withstand flyback voltages greater than 60V,

which usually rules out most Schottky rectifiers.

______________________________________________________________________________________ 21

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Table 5. Low-Voltage Troubleshooting Chart

SYMPTOM

CONDITION

ROOT CAUSE

SOLUTION

Increase bulk output capacitance

per formula (see the Low-Voltage

Operation section). Reduce inductor

value.

Sag or droop in V

step-load change

under

Low V -V

differential, <1.5V

Limited inductor-current

slew rate per cycle.

OUT

IN OUT

Dropout voltage is too high

(V follows V as V

decreases)

Reduce operation to 200kHz.

Reduce MOSFET on-resistance and

coil DCR.

Low V -V

differential, <1V

Maximum duty-cycle limits

exceeded.

IN OUT

OUT

IN

Unstable—jitters between

different duty factors and

frequencies

Low V -V

differential, <0.5V

Normal function of internal

low-dropout circuitry.

Increase the minimum input voltage

or ignore.

IN OUT

Not enough duty cycle left to

initiate forward-mode opera-

tion. Small AC current in

primary cannot store energy

for flyback operation.

Reduce operation to 200kHz.

Reduce secondary impedances;

use a Schottky diode, if possible.

Stack secondary winding on the

main output.

Low V -V

IN OUT

Secondary output won’t

support a load

differential,

< 1.3 x V

V

IN

(main)

OUT

VL linear regulator is going

into dropout and is not pro-

viding good gate-drive levels.

Use a small 20mA Schottky diode

for boost diode D2. Supply VL from

an external source.

Poor efficiency

Low input voltage, <5V

Low input voltage, <4.5V

Does not start under load or

quits before battery is

completely dead

Supply VL from an external source

VL output is so low that it hits

the VL UVLO threshold.

other than V , such as the system

IN

+5V supply.

where R

is the DC resistance of the coil, R

is

DC

DS(ON)

is the current-

________________Applications Information

Heavy-Load Efficiency Considerations

The major efficiency-loss mechanisms under loads are,

in the usual order of importance:

the MOSFET on-resistance, and R

SENSE

sense resistor value. The R

term assumes identi-

DS(ON)

cal MOSFETs for the high-side and low-side switches,

because they time-share the inductor current. If the

MOSFETs are not identical, their losses can be estimat-

ed by averaging the losses according to duty factor:

3

•

P(I²R) = I²R losses

P(tran) = transition losses

P(gate) = gate-charge losses

P(diode) = diode-conduction losses

P(cap) = capacitor ESR losses

PD(tran)= transition loss = V x I

x f x

x

IN LOAD

2

(V x C

/ I

) + 20ns

[

]

IN

RSS GATE

where C

is the reverse transfer capacitance of the

RSS

P(IC) = losses due to the IC’s operating supply

current

high-side MOSFET (a data-sheet parameter), I

is the

GATE

DH gate-driver peak output current (1.5A typ), and 20ns

is the rise/fall time of the DH driver (20ns typ):

Inductor core losses are fairly low at heavy loads

because the inductor’s AC current component is small.

Therefore, they are not accounted for in this analysis.

Ferrite cores are preferred, especially at 300kHz, but

powdered cores, such as Kool-Mu, can work well:

P(gate) = qG x f x VL

where VL is the internal-logic-supply voltage (+5V), and qG

is the sum of the gate-charge values for low-side and high-

side switches. For matched MOSFETs, qG is twice the

data-sheet value of an individual MOSFET. If V

less than 4.5V, replace VL in this equation with V

this case, efficiency can be improved by connecting VL to

an efficient 5V source, such as the system +5V supply:

Efficiency = P

/ P x 100%

IN

is set to

OUT

. In

BATT

= P

/ (P

+ P

) x 100%

OUT

TOTAL

2

P

= P(I R) + P(tran) + P(gate) +

TOTAL

P(diode) + P(cap) + P(IC)

P(diode)= diode- conduction losses

2

P = (I R)= (I

) x (R

+ R

)

= I

x V

x t x f

LOAD

DC

DS(ON)

SENSE

LOAD

FWD D

22 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

where t is the diode-conduction time (120ns typ) and

FWD

Rectifier diode cathode to low-side

MOSFET: 5mm max length.

D

V

is the forward voltage of the diode.

LX node (MOSFETs, rectifier cathode,

inductor): 15mm max length.

This power is dissipated in the MOSFET body diode if

no external Schottky diode is used:

Ideally, surface-mount power components are butted

up to one another with their ground terminals almost

touching. These high-current grounds are then con-

nected to each other with a wide filled zone of top-layer

copper so they do not go through vias. The resulting

top-layer “subground-plane” is connected to the normal

inner-layer ground plane at the output ground termi-

nals, which ensures that the IC’s analog ground is

sensing at the supply’s output terminals without interfer-

ence from IR drops and ground noise. Other high-

current paths should also be minimized, but focusing

primarily on short ground and current-sense con-

nections eliminates about 90% of all PC board lay-

out problems (refer to the PC board layouts in the

MAX1630A Evaluation Kit manual for examples).

2

P(cap) = input capacitor ESR loss = (I

)

x R

ESR

RMS

where I

is the input ripple current as calculated in the

Design Procedure and Input Capacitor Value sections.

RMS

Light-Load Efficiency Considerations

Under light loads, the PWM operates in discontinuous

mode, where the inductor current discharges to zero at

some point during the switching cycle. This makes the

inductor current’s AC component high compared to the

load current, which increases core losses and I²R loss-

es in the output filter capacitors. For best light-load effi-

ciency, use MOSFETs with moderate gate-charge

levels, and use ferrite, MPP, or other low-loss core

material. Avoid powdered-iron cores; even Kool-Mu

(aluminum alloy) is not as good as ferrite.

2) Place the IC and signal components. Keep the main

switching nodes (LX nodes) away from sensitive

analog components (current-sense traces and REF

capacitor). Place the IC and analog components on

the opposite side of the board from the power-

switching node. Important: The IC must be no far-

ther than 10mm from the current-sense resistors.

Keep the gate-drive traces (DH_, DL_, and BST_)

shorter than 20mm and route them away from CSH_,

CSL_, and REF.

PC Board Layout Considerations

Good PC board layout is required in order to achieve

specified noise, efficiency, and stability performance.

The PC board layout artist must be given explicit

instructions, preferably a pencil sketch showing the

placement of power-switching components and high-

current routing. Refer to the PC board layout in the

MAX1630A Evaluation Kit manual for examples. A

ground plane is essential for optimum performance. In

most applications, the circuit will be located on a

multilayer board, and full use of the four or more cop-

per layers is recommended. Use the top layer for high-

current connections, the bottom layer for quiet

connections (REF, SS, GND), and the inner layers for

an uninterrupted ground plane. Use the following step-

by-step guide:

3) Use a single-point star ground where the input

ground trace, power ground (subground-plane),

and normal ground plane meet at the supply’s out-

put ground terminal. Connect both IC ground pins

and all IC bypass capacitors to the normal ground

plane.

HIGH-CURRENT PATH

1) Place the high-power components (Figure 1, C1,

C3, Q1, Q2, D1, L1, and R1) first, with any grounded

connections adjacent:

Priority 1: Minimize current-sense resistor trace

lengths and ensure accurate current

sensing with Kelvin connections (Figure 7).

SENSE RESISTOR

Priority 2: Minimize ground trace lengths in the

high-current paths (discussed below).

Priority 3: Minimize other trace lengths in the high-

current paths.

MAX1630A

Use > 5mm-wide traces.

C

to high-side MOSFET drain: 10mm

IN

max length.

Figure 7. Kelvin Connections for the Current-Sense Resistors

______________________________________________________________________________________ 23

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_______________________________________________________________________________Application Circuits

*

TO +3.3V OUTPUT

TO +5V OUTPUT

C4

INPUT

+5.2V TO +24V

C3

10Ω

0.1μF

4.7μF

+5V

ALWAYS ON

ON/OFF

4.7μF

0.1μF

23 22

6

21

VL

V+

SHDN

SYNC

5

4

+12V

AT 120mA

12OUT

V

DD

2.2μF

25

27

18

16

2.7μF

BST3

DH3

BST5

DH5

Q3

Q1

C1

L2

R2

+5V OUTPUT (3A)

C2

+3.3V

OUTPUT

(3A)

0.1μF

Q4

26

24

17

19

T1

1:4

LX5

DL5

R1

LX3

DL3

MAX1630A

MAX1633A

0.1μF

*

Q2

20

14

PGND

1N5819

1

CSH3

CSL3

FB3

CSH5

CSL5

FB5

13

12

2

3

15

9

28

7

3V ON/OFF

5V ON/OFF

SEQ

REF

RUN/ON3

TIME/ON5

+2.5V REF

1μF

11

RESET

POWER-GOOD

SKIP

10

GND

8

R1 = R2 = 20mΩ

L2 = 10μH SUMIDA CDRH125-100

T1 = 10μH 1:4 TRANSFORMER

TRANSPOWER TECHNOLOGIES TTI-5902

Q1–Q4 = Si4410DY or IRF7413

C1 = 3 x 220μF 10V SPRAGUE 594D227X0010D2T

C2 = 2 x 220μF 10V SPRAGUE 594D227X0010D2T

C3 = C4 = 2 x 10μF 30V SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1630A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

Figure 8. Triple-Output Application for Low-Voltage Batteries (MAX1630A/MAX1633A)

24 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_____________________________________________________________Application Circuits (continued)

*

TO +3.3V OUTPUT

TO +5V OUTPUT

C4

INPUT

+6.5V TO +28V

C3

10Ω

0.1μF

4.7μF

+5V ALWAYS ON

ON/OFF

0.1μF

4.7μF

23

22

V+

6

21

VL

SHDN

SYNC

+12V AT 120mA

4

5

12OUT

2.2μF

V

DD

D2

D1

2.2μF

D5

25

18

16

BST3

DH3

BST5

DH5

Q1

Q3

27

L1

0.1μF

+3.3V OUTPUT (3A)

C1

R2

+5V OUTPUT (3A)

C2

*

0.1μF

26

24

17

19

20

T2

1:2.2

LX5

R1

LX3

DL3

MAX1632A

MAX1635A

0.1μF

*

DL5

Q2

Q4

PGND

1N5819

1

14

13

12

CSH3

CSL3

FB3

CSH5

CSL5

FB5

2

3

15

9

28

7

3V ON/OFF

5V ON/OFF

SEQ

REF

RUN/ON3

TIME/ON5

+2.5V REF

1μF

11

RESET

POWER-GOOD

SKIP

10

GND

8

R1 = R2 = 20mΩ

L1 = 10μH SUMIDA CDRH125-100

T2 = 10μH 1:2.2 TRANSFORMER

TRANSPOWER TECHNOLOGIES TTI-5870

Q1–Q4 = Si4410DY or IRF7413

C1 = 3 x 220μF 10V SPRAGUE 594D227X0010D2T

C2 = 2 x 220μF 10V SPRAGUE 594D227X0010D2T

C3 = C4 = 2 x 10μF 30V SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1632A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

Figure 9. Triple-Output Application for High-Voltage Batteries (MAX1632A/MAX1635A)

______________________________________________________________________________________ 25

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

_____________________________________________________________Application Circuits (continued)

ON/OFF

*

INPUT

+6V TO +24V

5V ALWAYS ON

C3

10Ω

0.1μF

22 23

5

21

4.7μF

V+ SHDN SECFB VL

4.7μF

18

16

25

27

BST5

BST3

0.1μF

Q1

DH5

DH3

Q3

0.1μF

L1

R1

0.1μF

2.5V OUTPUT

26

24

17

19

L2

R2

LX5

DL5

LX3

DL3

+3.3V OUTPUT

C2

Q2

*

Q4

MAX1631A

MAX1634A

C1

*

20

14

1N5819

PGND

CSH5

1

2

CSH3

CSL3

13

CSL5

0Ω

OPEN

12

3

FB3

FB5

RESET OUTPUT

11

10

0Ω

OPEN

RESET

SKIP

7

TIME/ON5

RUN/ON3

GND

ON/OFF

28

4

STEER

8

REF SYNC SEQ

15

9

6

1μF

R1 = R2 = 15mΩ

L1 = L2 = 6.8μH SUMIDA CDRH 127-6R8MC

Q1 = Q4 = Si4410DY or 1RF7413

C1 = C2 = 2X SANYO OS-CON 10 SA220M

C3 = 4X SANYO OS-CON 30SC10M

*VL DIODES AND OUTPUT SCHOTTKY DIODES REQUIRED

FOR THE MAX1631A ONLY (SEE OUTPUT OVERVOLTAGE PROTECTION

AND OUTPUT UNDERVOLTAGE SHUTDOWN PROTECTION SECTIONS).

Figure 10. Dual, 4A, Notebook Computer Power Supply

26 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

________________________________________________________________________________Pin Configurations

TOP VIEW

CSH3

CSL3

CSH3

CSL3

FB3

28

27

26

25

24

28

27

26

25

1

2

1

2

RUN/ON3

DH3

RUN/ON3

DH3

LX3

FB3

STEER

SECFB

SYNC

3

BST3

DL3

BST3

4

12OUT

4

V

24 DL3

5

DD

MAX1631A

MAX1634A

MAX1630A

MAX1632A

MAX1633A

MAX1635A

6

SHDN

SYNC

6

23 SHDN

23

22

21

20

19

18

17

TIME/ON5

V+

VL

TIME/ON5

GND

7

22

21

20

19

18

17

16

15

V+

VL

8

GND

REF

8

9

REF

PGND

DL5

PGND

DL5

10

SKIP

RESET 11

BST5

LX5

BST5

LX5

12

13

14

12

13

14

FB5

16

15

CSL5

CSH5

DH5

SEQ

CSL5

CSH5

DH5

SEQ

SSOP

_______________________________________________________________Selector Guide

OVER/UNDERVOLTAGE

DEVICE

AUXILIARY OUTPUT

SECONDARY FEEDBACK

PROTECTION

MAX1630A

MAX1631A

MAX1632A

MAX1633A

MAX1634A

MAX1635A

12V linear regulator

None (SECFB input)

12V linear regulator

None (SECFB input)

12V linear regulator

Feeds into the 3.3V SMPS

Selectable (STEER pin)

Feeds into the 5V SMPS

Feeds into the 3.3V SMPS

Selectable (STEER pin)

Feeds into the 5V SMPS

Yes

No

______________________________________________________________________________________ 27

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

__Ordering Information (continued)

PART

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

28 SSOP

MAX1630AEAI+

MAX1631AEAI

MAX1631AEAI+

MAX1632AEAI

MAX1632AEAI+

MAX1633AEAI

MAX1633AEAI+

MAX1634AEAI

MAX1634AEAI+

MAX1635AEAI

MAX1635AEAI+

+Denotes lead-free package.

28 ______________________________________________________________________________________

Multi-Output, Low-Noise Power-Supply

Controllers for Notebook Computers

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information

go to www.maxim-ic.com/packages.)

2

1

INCHES

MILLIMETERS

MAX

1.99

0.21

0.38

0.20

DIM

A

MIN

0.068

MIN

1.73

0.05

0.25

0.09

INCHES

MAX

MILLIMETERS

MAX

6.33

7.33

MIN

6.07

7.07

8.07

N

0.078

14L

16L

20L

A1

B

D

0.239 0.249

0.278 0.289

0.317 0.328

0.002 0.008

0.010 0.015

0.004 0.008

C

8.33 24L

E

H

SEE VARIATIONS

0.205 0.212 5.20

0.0256 BSC

D

0.397 0.407 10.07 10.33

28L

E

5.38

e

0.65 BSC

H

0.301 0.311 7.65

0.025 0.037 0.63

7.90

0.95

8∞

L

0∞

8∞

0∞

N

A

C

B

L

e

A1

D

NOTES:

1. D&E DO NOT INCLUDE MOLD FLASH.

2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").

3. CONTROLLING DIMENSION: MILLIMETERS.

4. MEETS JEDEC MO150.

PROPRIETARY INFORMATION

TITLE:

PACKAGE OUTLINE, SSOP, 5.3 MM

APPROVAL

DOCUMENT CONTROL NO.

REV.

5. LEADS TO BE COPLANAR WITHIN 0.10 MM.

1

21-0056

C

1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

29 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products, Inc.


型号：	MAX1631A
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers
文件：	总29页 (文件大小：288K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1631A [MAXIM]

相关型号：

MAX1631AEAI

MAX1631AEAI+

MAX1631AEAI+T

MAX1631AEAI-T

MAX1631CAI

MAX1631CAI+

MAX1631CAI+T

MAX1631EAI

MAX1631EAI-T

MAX1632

MAX1632A

MAX1632AEAI